1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved. 4 * 5 * Authors: Shlomi Gridish <gridish@freescale.com> 6 * Li Yang <leoli@freescale.com> 7 * 8 * Description: 9 * QUICC Engine (QE) external definitions and structure. 10 */ 11 #ifndef _ASM_POWERPC_QE_H 12 #define _ASM_POWERPC_QE_H 13 #ifdef __KERNEL__ 14 15 #include <linux/compiler.h> 16 #include <linux/genalloc.h> 17 #include <linux/spinlock.h> 18 #include <linux/errno.h> 19 #include <linux/err.h> 20 #include <soc/fsl/cpm.h> 21 #include <soc/fsl/qe/immap_qe.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/types.h> 25 26 struct device; 27 struct gpio_desc; 28 29 #define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ 30 #define QE_NUM_OF_BRGS 16 31 #define QE_NUM_OF_PORTS 1024 32 33 /* Clocks and BRGs */ 34 enum qe_clock { 35 QE_CLK_NONE = 0, 36 QE_BRG1, /* Baud Rate Generator 1 */ 37 QE_BRG2, /* Baud Rate Generator 2 */ 38 QE_BRG3, /* Baud Rate Generator 3 */ 39 QE_BRG4, /* Baud Rate Generator 4 */ 40 QE_BRG5, /* Baud Rate Generator 5 */ 41 QE_BRG6, /* Baud Rate Generator 6 */ 42 QE_BRG7, /* Baud Rate Generator 7 */ 43 QE_BRG8, /* Baud Rate Generator 8 */ 44 QE_BRG9, /* Baud Rate Generator 9 */ 45 QE_BRG10, /* Baud Rate Generator 10 */ 46 QE_BRG11, /* Baud Rate Generator 11 */ 47 QE_BRG12, /* Baud Rate Generator 12 */ 48 QE_BRG13, /* Baud Rate Generator 13 */ 49 QE_BRG14, /* Baud Rate Generator 14 */ 50 QE_BRG15, /* Baud Rate Generator 15 */ 51 QE_BRG16, /* Baud Rate Generator 16 */ 52 QE_CLK1, /* Clock 1 */ 53 QE_CLK2, /* Clock 2 */ 54 QE_CLK3, /* Clock 3 */ 55 QE_CLK4, /* Clock 4 */ 56 QE_CLK5, /* Clock 5 */ 57 QE_CLK6, /* Clock 6 */ 58 QE_CLK7, /* Clock 7 */ 59 QE_CLK8, /* Clock 8 */ 60 QE_CLK9, /* Clock 9 */ 61 QE_CLK10, /* Clock 10 */ 62 QE_CLK11, /* Clock 11 */ 63 QE_CLK12, /* Clock 12 */ 64 QE_CLK13, /* Clock 13 */ 65 QE_CLK14, /* Clock 14 */ 66 QE_CLK15, /* Clock 15 */ 67 QE_CLK16, /* Clock 16 */ 68 QE_CLK17, /* Clock 17 */ 69 QE_CLK18, /* Clock 18 */ 70 QE_CLK19, /* Clock 19 */ 71 QE_CLK20, /* Clock 20 */ 72 QE_CLK21, /* Clock 21 */ 73 QE_CLK22, /* Clock 22 */ 74 QE_CLK23, /* Clock 23 */ 75 QE_CLK24, /* Clock 24 */ 76 QE_RSYNC_PIN, /* RSYNC from pin */ 77 QE_TSYNC_PIN, /* TSYNC from pin */ 78 QE_CLK_DUMMY 79 }; 80 81 static inline bool qe_clock_is_brg(enum qe_clock clk) 82 { 83 return clk >= QE_BRG1 && clk <= QE_BRG16; 84 } 85 86 extern spinlock_t cmxgcr_lock; 87 88 /* Export QE common operations */ 89 #ifdef CONFIG_QUICC_ENGINE 90 extern void qe_reset(void); 91 #else 92 static inline void qe_reset(void) {} 93 #endif 94 95 int cpm_muram_init(void); 96 97 #if defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) 98 s32 cpm_muram_alloc(unsigned long size, unsigned long align); 99 s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size, 100 unsigned long align); 101 void cpm_muram_free(s32 offset); 102 s32 cpm_muram_alloc_fixed(unsigned long offset, unsigned long size); 103 s32 devm_cpm_muram_alloc_fixed(struct device *dev, unsigned long offset, 104 unsigned long size); 105 void __iomem *cpm_muram_addr(unsigned long offset); 106 unsigned long cpm_muram_offset(const void __iomem *addr); 107 dma_addr_t cpm_muram_dma(void __iomem *addr); 108 void cpm_muram_free_addr(const void __iomem *addr); 109 #else 110 static inline s32 cpm_muram_alloc(unsigned long size, 111 unsigned long align) 112 { 113 return -ENOSYS; 114 } 115 116 static inline s32 devm_cpm_muram_alloc(struct device *dev, unsigned long size, 117 unsigned long align) 118 { 119 return -ENOSYS; 120 } 121 122 static inline void cpm_muram_free(s32 offset) 123 { 124 } 125 126 static inline s32 cpm_muram_alloc_fixed(unsigned long offset, 127 unsigned long size) 128 { 129 return -ENOSYS; 130 } 131 132 static inline s32 devm_cpm_muram_alloc_fixed(struct device *dev, 133 unsigned long offset, 134 unsigned long size) 135 { 136 return -ENOSYS; 137 } 138 139 static inline void __iomem *cpm_muram_addr(unsigned long offset) 140 { 141 return NULL; 142 } 143 144 static inline unsigned long cpm_muram_offset(const void __iomem *addr) 145 { 146 return -ENOSYS; 147 } 148 149 static inline dma_addr_t cpm_muram_dma(void __iomem *addr) 150 { 151 return 0; 152 } 153 static inline void cpm_muram_free_addr(const void __iomem *addr) 154 { 155 } 156 #endif /* defined(CONFIG_CPM) || defined(CONFIG_QUICC_ENGINE) */ 157 158 /* QE PIO */ 159 #define QE_PIO_PINS 32 160 161 struct qe_pio_regs { 162 __be32 cpodr; /* Open drain register */ 163 __be32 cpdata; /* Data register */ 164 __be32 cpdir1; /* Direction register */ 165 __be32 cpdir2; /* Direction register */ 166 __be32 cppar1; /* Pin assignment register */ 167 __be32 cppar2; /* Pin assignment register */ 168 #ifdef CONFIG_PPC_85xx 169 u8 pad[8]; 170 #endif 171 }; 172 173 #define QE_PIO_DIR_IN 2 174 #define QE_PIO_DIR_OUT 1 175 extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, 176 int dir, int open_drain, int assignment, 177 int has_irq); 178 #ifdef CONFIG_QUICC_ENGINE 179 extern int par_io_init(struct device_node *np); 180 extern int par_io_of_config(struct device_node *np); 181 extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 182 int assignment, int has_irq); 183 extern int par_io_data_set(u8 port, u8 pin, u8 val); 184 #else 185 static inline int par_io_init(struct device_node *np) { return -ENOSYS; } 186 static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } 187 static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, 188 int assignment, int has_irq) { return -ENOSYS; } 189 static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } 190 #endif /* CONFIG_QUICC_ENGINE */ 191 192 /* 193 * Pin multiplexing functions. 194 */ 195 struct qe_pin; 196 #ifdef CONFIG_QE_GPIO 197 extern struct qe_pin *qe_pin_request(struct device *dev, struct gpio_desc *gpiod); 198 extern void qe_pin_free(struct qe_pin *qe_pin); 199 extern void qe_pin_set_gpio(struct qe_pin *qe_pin); 200 extern void qe_pin_set_dedicated(struct qe_pin *pin); 201 #else 202 static inline struct qe_pin * 203 qe_pin_request(struct device *dev, struct gpio_desc *gpiod) 204 { 205 return ERR_PTR(-ENOSYS); 206 } 207 static inline void qe_pin_free(struct qe_pin *qe_pin) {} 208 static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} 209 static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} 210 #endif /* CONFIG_QE_GPIO */ 211 212 #ifdef CONFIG_QUICC_ENGINE 213 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); 214 #else 215 static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, 216 u32 cmd_input) 217 { 218 return -ENOSYS; 219 } 220 #endif /* CONFIG_QUICC_ENGINE */ 221 222 /* QE internal API */ 223 enum qe_clock qe_clock_source(const char *source); 224 unsigned int qe_get_brg_clk(void); 225 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); 226 int qe_get_snum(void); 227 void qe_put_snum(u8 snum); 228 unsigned int qe_get_num_of_risc(void); 229 unsigned int qe_get_num_of_snums(void); 230 231 static inline int qe_alive_during_sleep(void) 232 { 233 /* 234 * MPC8568E reference manual says: 235 * 236 * "...power down sequence waits for all I/O interfaces to become idle. 237 * In some applications this may happen eventually without actively 238 * shutting down interfaces, but most likely, software will have to 239 * take steps to shut down the eTSEC, QUICC Engine Block, and PCI 240 * interfaces before issuing the command (either the write to the core 241 * MSR[WE] as described above or writing to POWMGTCSR) to put the 242 * device into sleep state." 243 * 244 * MPC8569E reference manual has a similar paragraph. 245 */ 246 #ifdef CONFIG_PPC_85xx 247 return 0; 248 #else 249 return 1; 250 #endif 251 } 252 253 /* we actually use cpm_muram implementation, define this for convenience */ 254 #define qe_muram_init cpm_muram_init 255 #define qe_muram_alloc cpm_muram_alloc 256 #define devm_qe_muram_alloc devm_cpm_muram_alloc 257 #define qe_muram_alloc_fixed cpm_muram_alloc_fixed 258 #define devm_qe_muram_alloc_fixed devm_cpm_muram_alloc_fixed 259 #define qe_muram_free cpm_muram_free 260 #define qe_muram_addr cpm_muram_addr 261 #define qe_muram_offset cpm_muram_offset 262 #define qe_muram_dma cpm_muram_dma 263 #define qe_muram_free_addr cpm_muram_free_addr 264 265 #define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr)) 266 #define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr)) 267 268 #define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr)) 269 #define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr)) 270 271 #define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr)) 272 #define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr)) 273 274 #define qe_clrsetbits_be32(addr, clear, set) \ 275 iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr)) 276 #define qe_clrsetbits_be16(addr, clear, set) \ 277 iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr)) 278 #define qe_clrsetbits_8(addr, clear, set) \ 279 iowrite8((ioread8(addr) & ~(clear)) | (set), (addr)) 280 281 /* Structure that defines QE firmware binary files. 282 * 283 * See Documentation/arch/powerpc/qe_firmware.rst for a description of these 284 * fields. 285 */ 286 struct qe_firmware { 287 struct qe_header { 288 __be32 length; /* Length of the entire structure, in bytes */ 289 u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ 290 u8 version; /* Version of this layout. First ver is '1' */ 291 } header; 292 u8 id[62]; /* Null-terminated identifier string */ 293 u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ 294 u8 count; /* Number of microcode[] structures */ 295 struct { 296 __be16 model; /* The SOC model */ 297 u8 major; /* The SOC revision major */ 298 u8 minor; /* The SOC revision minor */ 299 } __attribute__ ((packed)) soc; 300 u8 padding[4]; /* Reserved, for alignment */ 301 __be64 extended_modes; /* Extended modes */ 302 __be32 vtraps[8]; /* Virtual trap addresses */ 303 u8 reserved[4]; /* Reserved, for future expansion */ 304 struct qe_microcode { 305 u8 id[32]; /* Null-terminated identifier */ 306 __be32 traps[16]; /* Trap addresses, 0 == ignore */ 307 __be32 eccr; /* The value for the ECCR register */ 308 __be32 iram_offset; /* Offset into I-RAM for the code */ 309 __be32 count; /* Number of 32-bit words of the code */ 310 __be32 code_offset; /* Offset of the actual microcode */ 311 u8 major; /* The microcode version major */ 312 u8 minor; /* The microcode version minor */ 313 u8 revision; /* The microcode version revision */ 314 u8 padding; /* Reserved, for alignment */ 315 u8 reserved[4]; /* Reserved, for future expansion */ 316 } __packed microcode[]; 317 /* All microcode binaries should be located here */ 318 /* CRC32 should be located here, after the microcode binaries */ 319 } __attribute__ ((packed)); 320 321 struct qe_firmware_info { 322 char id[64]; /* Firmware name */ 323 u32 vtraps[8]; /* Virtual trap addresses */ 324 u64 extended_modes; /* Extended modes */ 325 }; 326 327 #ifdef CONFIG_QUICC_ENGINE 328 /* Upload a firmware to the QE */ 329 int qe_upload_firmware(const struct qe_firmware *firmware); 330 #else 331 static inline int qe_upload_firmware(const struct qe_firmware *firmware) 332 { 333 return -ENOSYS; 334 } 335 #endif /* CONFIG_QUICC_ENGINE */ 336 337 /* Obtain information on the uploaded firmware */ 338 struct qe_firmware_info *qe_get_firmware_info(void); 339 340 /* QE USB */ 341 int qe_usb_clock_set(enum qe_clock clk, int rate); 342 343 /* Buffer descriptors */ 344 struct qe_bd { 345 __be16 status; 346 __be16 length; 347 __be32 buf; 348 } __attribute__ ((packed)); 349 350 #define BD_STATUS_MASK 0xffff0000 351 #define BD_LENGTH_MASK 0x0000ffff 352 353 /* Alignment */ 354 #define QE_INTR_TABLE_ALIGN 16 /* ??? */ 355 #define QE_ALIGNMENT_OF_BD 8 356 #define QE_ALIGNMENT_OF_PRAM 64 357 358 /* RISC allocation */ 359 #define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ 360 #define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ 361 #define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ 362 #define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ 363 #define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ 364 QE_RISC_ALLOCATION_RISC2) 365 #define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ 366 QE_RISC_ALLOCATION_RISC2 | \ 367 QE_RISC_ALLOCATION_RISC3 | \ 368 QE_RISC_ALLOCATION_RISC4) 369 370 /* QE extended filtering Table Lookup Key Size */ 371 enum qe_fltr_tbl_lookup_key_size { 372 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES 373 = 0x3f, /* LookupKey parsed by the Generate LookupKey 374 CMD is truncated to 8 bytes */ 375 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES 376 = 0x5f, /* LookupKey parsed by the Generate LookupKey 377 CMD is truncated to 16 bytes */ 378 }; 379 380 /* QE FLTR extended filtering Largest External Table Lookup Key Size */ 381 enum qe_fltr_largest_external_tbl_lookup_key_size { 382 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE 383 = 0x0,/* not used */ 384 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES 385 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ 386 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES 387 = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ 388 }; 389 390 /* structure representing QE parameter RAM */ 391 struct qe_timer_tables { 392 u16 tm_base; /* QE timer table base adr */ 393 u16 tm_ptr; /* QE timer table pointer */ 394 u16 r_tmr; /* QE timer mode register */ 395 u16 r_tmv; /* QE timer valid register */ 396 u32 tm_cmd; /* QE timer cmd register */ 397 u32 tm_cnt; /* QE timer internal cnt */ 398 } __attribute__ ((packed)); 399 400 #define QE_FLTR_TAD_SIZE 8 401 402 /* QE extended filtering Termination Action Descriptor (TAD) */ 403 struct qe_fltr_tad { 404 u8 serialized[QE_FLTR_TAD_SIZE]; 405 } __attribute__ ((packed)); 406 407 /* Communication Direction */ 408 enum comm_dir { 409 COMM_DIR_NONE = 0, 410 COMM_DIR_RX = 1, 411 COMM_DIR_TX = 2, 412 COMM_DIR_RX_AND_TX = 3 413 }; 414 415 /* QE CMXUCR Registers. 416 * There are two UCCs represented in each of the four CMXUCR registers. 417 * These values are for the UCC in the LSBs 418 */ 419 #define QE_CMXUCR_MII_ENET_MNG 0x00007000 420 #define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 421 #define QE_CMXUCR_GRANT 0x00008000 422 #define QE_CMXUCR_TSA 0x00004000 423 #define QE_CMXUCR_BKPT 0x00000100 424 #define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F 425 426 /* QE CMXGCR Registers. 427 */ 428 #define QE_CMXGCR_MII_ENET_MNG 0x00007000 429 #define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 430 #define QE_CMXGCR_USBCS 0x0000000f 431 #define QE_CMXGCR_USBCS_CLK3 0x1 432 #define QE_CMXGCR_USBCS_CLK5 0x2 433 #define QE_CMXGCR_USBCS_CLK7 0x3 434 #define QE_CMXGCR_USBCS_CLK9 0x4 435 #define QE_CMXGCR_USBCS_CLK13 0x5 436 #define QE_CMXGCR_USBCS_CLK17 0x6 437 #define QE_CMXGCR_USBCS_CLK19 0x7 438 #define QE_CMXGCR_USBCS_CLK21 0x8 439 #define QE_CMXGCR_USBCS_BRG9 0x9 440 #define QE_CMXGCR_USBCS_BRG10 0xa 441 442 /* QE CECR Commands. 443 */ 444 #define QE_CR_FLG 0x00010000 445 #define QE_RESET 0x80000000 446 #define QE_INIT_TX_RX 0x00000000 447 #define QE_INIT_RX 0x00000001 448 #define QE_INIT_TX 0x00000002 449 #define QE_ENTER_HUNT_MODE 0x00000003 450 #define QE_STOP_TX 0x00000004 451 #define QE_GRACEFUL_STOP_TX 0x00000005 452 #define QE_RESTART_TX 0x00000006 453 #define QE_CLOSE_RX_BD 0x00000007 454 #define QE_SWITCH_COMMAND 0x00000007 455 #define QE_SET_GROUP_ADDRESS 0x00000008 456 #define QE_START_IDMA 0x00000009 457 #define QE_MCC_STOP_RX 0x00000009 458 #define QE_ATM_TRANSMIT 0x0000000a 459 #define QE_HPAC_CLEAR_ALL 0x0000000b 460 #define QE_GRACEFUL_STOP_RX 0x0000001a 461 #define QE_RESTART_RX 0x0000001b 462 #define QE_HPAC_SET_PRIORITY 0x0000010b 463 #define QE_HPAC_STOP_TX 0x0000020b 464 #define QE_HPAC_STOP_RX 0x0000030b 465 #define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b 466 #define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b 467 #define QE_HPAC_START_TX 0x0000060b 468 #define QE_HPAC_START_RX 0x0000070b 469 #define QE_USB_STOP_TX 0x0000000a 470 #define QE_USB_RESTART_TX 0x0000000c 471 #define QE_QMC_STOP_TX 0x0000000c 472 #define QE_QMC_STOP_RX 0x0000000d 473 #define QE_SS7_SU_FIL_RESET 0x0000000e 474 #define QE_PUSHSCHED 0x0000000f 475 /* jonathbr added from here down for 83xx */ 476 #define QE_RESET_BCS 0x0000000a 477 #define QE_MCC_INIT_TX_RX_16 0x00000003 478 #define QE_MCC_STOP_TX 0x00000004 479 #define QE_MCC_INIT_TX_1 0x00000005 480 #define QE_MCC_INIT_RX_1 0x00000006 481 #define QE_MCC_RESET 0x00000007 482 #define QE_SET_TIMER 0x00000008 483 #define QE_RANDOM_NUMBER 0x0000000c 484 #define QE_ATM_MULTI_THREAD_INIT 0x00000011 485 #define QE_ASSIGN_PAGE 0x00000012 486 #define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 487 #define QE_START_FLOW_CONTROL 0x00000014 488 #define QE_STOP_FLOW_CONTROL 0x00000015 489 #define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 490 491 #define QE_ASSIGN_RISC 0x00000010 492 #define QE_CR_MCN_NORMAL_SHIFT 6 493 #define QE_CR_MCN_USB_SHIFT 4 494 #define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 495 #define QE_CR_SNUM_SHIFT 17 496 497 /* QE CECR Sub Block - sub block of QE command. 498 */ 499 #define QE_CR_SUBBLOCK_INVALID 0x00000000 500 #define QE_CR_SUBBLOCK_USB 0x03200000 501 #define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 502 #define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 503 #define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 504 #define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 505 #define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 506 #define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 507 #define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 508 #define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 509 #define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 510 #define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 511 #define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 512 #define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 513 #define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 514 #define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 515 #define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 516 #define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 517 #define QE_CR_SUBBLOCK_MCC1 0x03800000 518 #define QE_CR_SUBBLOCK_MCC2 0x03a00000 519 #define QE_CR_SUBBLOCK_MCC3 0x03000000 520 #define QE_CR_SUBBLOCK_IDMA1 0x02800000 521 #define QE_CR_SUBBLOCK_IDMA2 0x02a00000 522 #define QE_CR_SUBBLOCK_IDMA3 0x02c00000 523 #define QE_CR_SUBBLOCK_IDMA4 0x02e00000 524 #define QE_CR_SUBBLOCK_HPAC 0x01e00000 525 #define QE_CR_SUBBLOCK_SPI1 0x01400000 526 #define QE_CR_SUBBLOCK_SPI2 0x01600000 527 #define QE_CR_SUBBLOCK_RAND 0x01c00000 528 #define QE_CR_SUBBLOCK_TIMER 0x01e00000 529 #define QE_CR_SUBBLOCK_GENERAL 0x03c00000 530 531 /* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ 532 #define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ 533 #define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 534 #define QE_CR_PROTOCOL_QMC 0x02 535 #define QE_CR_PROTOCOL_UART 0x04 536 #define QE_CR_PROTOCOL_ATM_POS 0x0A 537 #define QE_CR_PROTOCOL_ETHERNET 0x0C 538 #define QE_CR_PROTOCOL_L2_SWITCH 0x0D 539 540 /* BRG configuration register */ 541 #define QE_BRGC_ENABLE 0x00010000 542 #define QE_BRGC_DIVISOR_SHIFT 1 543 #define QE_BRGC_DIVISOR_MAX 0xFFF 544 #define QE_BRGC_DIV16 1 545 546 /* QE Timers registers */ 547 #define QE_GTCFR1_PCAS 0x80 548 #define QE_GTCFR1_STP2 0x20 549 #define QE_GTCFR1_RST2 0x10 550 #define QE_GTCFR1_GM2 0x08 551 #define QE_GTCFR1_GM1 0x04 552 #define QE_GTCFR1_STP1 0x02 553 #define QE_GTCFR1_RST1 0x01 554 555 /* SDMA registers */ 556 #define QE_SDSR_BER1 0x02000000 557 #define QE_SDSR_BER2 0x01000000 558 559 #define QE_SDMR_GLB_1_MSK 0x80000000 560 #define QE_SDMR_ADR_SEL 0x20000000 561 #define QE_SDMR_BER1_MSK 0x02000000 562 #define QE_SDMR_BER2_MSK 0x01000000 563 #define QE_SDMR_EB1_MSK 0x00800000 564 #define QE_SDMR_ER1_MSK 0x00080000 565 #define QE_SDMR_ER2_MSK 0x00040000 566 #define QE_SDMR_CEN_MASK 0x0000E000 567 #define QE_SDMR_SBER_1 0x00000200 568 #define QE_SDMR_SBER_2 0x00000200 569 #define QE_SDMR_EB1_PR_MASK 0x000000C0 570 #define QE_SDMR_ER1_PR 0x00000008 571 572 #define QE_SDMR_CEN_SHIFT 13 573 #define QE_SDMR_EB1_PR_SHIFT 6 574 575 #define QE_SDTM_MSNUM_SHIFT 24 576 577 #define QE_SDEBCR_BA_MASK 0x01FFFFFF 578 579 /* Communication Processor */ 580 #define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ 581 #define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ 582 #define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ 583 584 /* I-RAM */ 585 #define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ 586 #define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ 587 #define QE_IRAM_READY 0x80000000 /* Ready */ 588 589 /* UPC */ 590 #define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ 591 #define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ 592 #define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ 593 #define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ 594 #define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ 595 596 /* UCC GUEMR register */ 597 #define UCC_GUEMR_MODE_MASK_RX 0x02 598 #define UCC_GUEMR_MODE_FAST_RX 0x02 599 #define UCC_GUEMR_MODE_SLOW_RX 0x00 600 #define UCC_GUEMR_MODE_MASK_TX 0x01 601 #define UCC_GUEMR_MODE_FAST_TX 0x01 602 #define UCC_GUEMR_MODE_SLOW_TX 0x00 603 #define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) 604 #define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but 605 must be set 1 */ 606 607 /* structure representing UCC SLOW parameter RAM */ 608 struct ucc_slow_pram { 609 __be16 rbase; /* RX BD base address */ 610 __be16 tbase; /* TX BD base address */ 611 u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ 612 u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ 613 __be16 mrblr; /* Rx buffer length */ 614 __be32 rstate; /* Rx internal state */ 615 __be32 rptr; /* Rx internal data pointer */ 616 __be16 rbptr; /* rb BD Pointer */ 617 __be16 rcount; /* Rx internal byte count */ 618 __be32 rtemp; /* Rx temp */ 619 __be32 tstate; /* Tx internal state */ 620 __be32 tptr; /* Tx internal data pointer */ 621 __be16 tbptr; /* Tx BD pointer */ 622 __be16 tcount; /* Tx byte count */ 623 __be32 ttemp; /* Tx temp */ 624 __be32 rcrc; /* temp receive CRC */ 625 __be32 tcrc; /* temp transmit CRC */ 626 } __attribute__ ((packed)); 627 628 /* General UCC SLOW Mode Register (GUMRH & GUMRL) */ 629 #define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 630 #define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 631 #define UCC_SLOW_GUMR_H_REVD 0x00002000 632 #define UCC_SLOW_GUMR_H_TRX 0x00001000 633 #define UCC_SLOW_GUMR_H_TTX 0x00000800 634 #define UCC_SLOW_GUMR_H_CDP 0x00000400 635 #define UCC_SLOW_GUMR_H_CTSP 0x00000200 636 #define UCC_SLOW_GUMR_H_CDS 0x00000100 637 #define UCC_SLOW_GUMR_H_CTSS 0x00000080 638 #define UCC_SLOW_GUMR_H_TFL 0x00000040 639 #define UCC_SLOW_GUMR_H_RFW 0x00000020 640 #define UCC_SLOW_GUMR_H_TXSY 0x00000010 641 #define UCC_SLOW_GUMR_H_4SYNC 0x00000004 642 #define UCC_SLOW_GUMR_H_8SYNC 0x00000008 643 #define UCC_SLOW_GUMR_H_16SYNC 0x0000000c 644 #define UCC_SLOW_GUMR_H_RTSM 0x00000002 645 #define UCC_SLOW_GUMR_H_RSYN 0x00000001 646 647 #define UCC_SLOW_GUMR_L_TCI 0x10000000 648 #define UCC_SLOW_GUMR_L_RINV 0x02000000 649 #define UCC_SLOW_GUMR_L_TINV 0x01000000 650 #define UCC_SLOW_GUMR_L_TEND 0x00040000 651 #define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 652 #define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 653 #define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 654 #define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 655 #define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 656 #define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 657 #define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 658 #define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 659 #define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 660 #define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 661 #define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 662 #define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 663 #define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 664 #define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 665 #define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 666 #define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 667 #define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 668 #define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 669 #define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 670 #define UCC_SLOW_GUMR_L_ENR 0x00000020 671 #define UCC_SLOW_GUMR_L_ENT 0x00000010 672 #define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F 673 #define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 674 #define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 675 #define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 676 #define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 677 678 /* General UCC FAST Mode Register */ 679 #define UCC_FAST_GUMR_LOOPBACK 0x40000000 680 #define UCC_FAST_GUMR_TCI 0x20000000 681 #define UCC_FAST_GUMR_TRX 0x10000000 682 #define UCC_FAST_GUMR_TTX 0x08000000 683 #define UCC_FAST_GUMR_CDP 0x04000000 684 #define UCC_FAST_GUMR_CTSP 0x02000000 685 #define UCC_FAST_GUMR_CDS 0x01000000 686 #define UCC_FAST_GUMR_CTSS 0x00800000 687 #define UCC_FAST_GUMR_TXSY 0x00020000 688 #define UCC_FAST_GUMR_RSYN 0x00010000 689 #define UCC_FAST_GUMR_SYNL_MASK 0x0000C000 690 #define UCC_FAST_GUMR_SYNL_16 0x0000C000 691 #define UCC_FAST_GUMR_SYNL_8 0x00008000 692 #define UCC_FAST_GUMR_SYNL_AUTO 0x00004000 693 #define UCC_FAST_GUMR_RTSM 0x00002000 694 #define UCC_FAST_GUMR_REVD 0x00000400 695 #define UCC_FAST_GUMR_ENR 0x00000020 696 #define UCC_FAST_GUMR_ENT 0x00000010 697 698 /* UART Slow UCC Event Register (UCCE) */ 699 #define UCC_UART_UCCE_AB 0x0200 700 #define UCC_UART_UCCE_IDLE 0x0100 701 #define UCC_UART_UCCE_GRA 0x0080 702 #define UCC_UART_UCCE_BRKE 0x0040 703 #define UCC_UART_UCCE_BRKS 0x0020 704 #define UCC_UART_UCCE_CCR 0x0008 705 #define UCC_UART_UCCE_BSY 0x0004 706 #define UCC_UART_UCCE_TX 0x0002 707 #define UCC_UART_UCCE_RX 0x0001 708 709 /* HDLC Slow UCC Event Register (UCCE) */ 710 #define UCC_HDLC_UCCE_GLR 0x1000 711 #define UCC_HDLC_UCCE_GLT 0x0800 712 #define UCC_HDLC_UCCE_IDLE 0x0100 713 #define UCC_HDLC_UCCE_BRKE 0x0040 714 #define UCC_HDLC_UCCE_BRKS 0x0020 715 #define UCC_HDLC_UCCE_TXE 0x0010 716 #define UCC_HDLC_UCCE_RXF 0x0008 717 #define UCC_HDLC_UCCE_BSY 0x0004 718 #define UCC_HDLC_UCCE_TXB 0x0002 719 #define UCC_HDLC_UCCE_RXB 0x0001 720 721 /* BISYNC Slow UCC Event Register (UCCE) */ 722 #define UCC_BISYNC_UCCE_GRA 0x0080 723 #define UCC_BISYNC_UCCE_TXE 0x0010 724 #define UCC_BISYNC_UCCE_RCH 0x0008 725 #define UCC_BISYNC_UCCE_BSY 0x0004 726 #define UCC_BISYNC_UCCE_TXB 0x0002 727 #define UCC_BISYNC_UCCE_RXB 0x0001 728 729 /* Gigabit Ethernet Fast UCC Event Register (UCCE) */ 730 #define UCC_GETH_UCCE_MPD 0x80000000 731 #define UCC_GETH_UCCE_SCAR 0x40000000 732 #define UCC_GETH_UCCE_GRA 0x20000000 733 #define UCC_GETH_UCCE_CBPR 0x10000000 734 #define UCC_GETH_UCCE_BSY 0x08000000 735 #define UCC_GETH_UCCE_RXC 0x04000000 736 #define UCC_GETH_UCCE_TXC 0x02000000 737 #define UCC_GETH_UCCE_TXE 0x01000000 738 #define UCC_GETH_UCCE_TXB7 0x00800000 739 #define UCC_GETH_UCCE_TXB6 0x00400000 740 #define UCC_GETH_UCCE_TXB5 0x00200000 741 #define UCC_GETH_UCCE_TXB4 0x00100000 742 #define UCC_GETH_UCCE_TXB3 0x00080000 743 #define UCC_GETH_UCCE_TXB2 0x00040000 744 #define UCC_GETH_UCCE_TXB1 0x00020000 745 #define UCC_GETH_UCCE_TXB0 0x00010000 746 #define UCC_GETH_UCCE_RXB7 0x00008000 747 #define UCC_GETH_UCCE_RXB6 0x00004000 748 #define UCC_GETH_UCCE_RXB5 0x00002000 749 #define UCC_GETH_UCCE_RXB4 0x00001000 750 #define UCC_GETH_UCCE_RXB3 0x00000800 751 #define UCC_GETH_UCCE_RXB2 0x00000400 752 #define UCC_GETH_UCCE_RXB1 0x00000200 753 #define UCC_GETH_UCCE_RXB0 0x00000100 754 #define UCC_GETH_UCCE_RXF7 0x00000080 755 #define UCC_GETH_UCCE_RXF6 0x00000040 756 #define UCC_GETH_UCCE_RXF5 0x00000020 757 #define UCC_GETH_UCCE_RXF4 0x00000010 758 #define UCC_GETH_UCCE_RXF3 0x00000008 759 #define UCC_GETH_UCCE_RXF2 0x00000004 760 #define UCC_GETH_UCCE_RXF1 0x00000002 761 #define UCC_GETH_UCCE_RXF0 0x00000001 762 763 /* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ 764 #define UCC_UART_UPSMR_FLC 0x8000 765 #define UCC_UART_UPSMR_SL 0x4000 766 #define UCC_UART_UPSMR_CL_MASK 0x3000 767 #define UCC_UART_UPSMR_CL_8 0x3000 768 #define UCC_UART_UPSMR_CL_7 0x2000 769 #define UCC_UART_UPSMR_CL_6 0x1000 770 #define UCC_UART_UPSMR_CL_5 0x0000 771 #define UCC_UART_UPSMR_UM_MASK 0x0c00 772 #define UCC_UART_UPSMR_UM_NORMAL 0x0000 773 #define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 774 #define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 775 #define UCC_UART_UPSMR_FRZ 0x0200 776 #define UCC_UART_UPSMR_RZS 0x0100 777 #define UCC_UART_UPSMR_SYN 0x0080 778 #define UCC_UART_UPSMR_DRT 0x0040 779 #define UCC_UART_UPSMR_PEN 0x0010 780 #define UCC_UART_UPSMR_RPM_MASK 0x000c 781 #define UCC_UART_UPSMR_RPM_ODD 0x0000 782 #define UCC_UART_UPSMR_RPM_LOW 0x0004 783 #define UCC_UART_UPSMR_RPM_EVEN 0x0008 784 #define UCC_UART_UPSMR_RPM_HIGH 0x000C 785 #define UCC_UART_UPSMR_TPM_MASK 0x0003 786 #define UCC_UART_UPSMR_TPM_ODD 0x0000 787 #define UCC_UART_UPSMR_TPM_LOW 0x0001 788 #define UCC_UART_UPSMR_TPM_EVEN 0x0002 789 #define UCC_UART_UPSMR_TPM_HIGH 0x0003 790 791 /* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ 792 #define UCC_GETH_UPSMR_FTFE 0x80000000 793 #define UCC_GETH_UPSMR_PTPE 0x40000000 794 #define UCC_GETH_UPSMR_ECM 0x04000000 795 #define UCC_GETH_UPSMR_HSE 0x02000000 796 #define UCC_GETH_UPSMR_PRO 0x00400000 797 #define UCC_GETH_UPSMR_CAP 0x00200000 798 #define UCC_GETH_UPSMR_RSH 0x00100000 799 #define UCC_GETH_UPSMR_RPM 0x00080000 800 #define UCC_GETH_UPSMR_R10M 0x00040000 801 #define UCC_GETH_UPSMR_RLPB 0x00020000 802 #define UCC_GETH_UPSMR_TBIM 0x00010000 803 #define UCC_GETH_UPSMR_RES1 0x00002000 804 #define UCC_GETH_UPSMR_RMM 0x00001000 805 #define UCC_GETH_UPSMR_CAM 0x00000400 806 #define UCC_GETH_UPSMR_BRO 0x00000200 807 #define UCC_GETH_UPSMR_SMM 0x00000080 808 #define UCC_GETH_UPSMR_SGMM 0x00000020 809 810 /* UCC Protocol Specific Mode Register (UPSMR), when used for HDLC */ 811 #define UCC_HDLC_UPSMR_RTE 0x02000000 812 #define UCC_HDLC_UPSMR_BUS 0x00200000 813 #define UCC_HDLC_UPSMR_CW8 0x00007000 814 815 /* UCC Transmit On Demand Register (UTODR) */ 816 #define UCC_SLOW_TOD 0x8000 817 #define UCC_FAST_TOD 0x8000 818 819 /* UCC Bus Mode Register masks */ 820 /* Not to be confused with the Bundle Mode Register */ 821 #define UCC_BMR_GBL 0x20 822 #define UCC_BMR_BO_BE 0x10 823 #define UCC_BMR_CETM 0x04 824 #define UCC_BMR_DTB 0x02 825 #define UCC_BMR_BDB 0x01 826 827 /* Function code masks */ 828 #define FC_GBL 0x20 829 #define FC_DTB_LCL 0x02 830 #define UCC_FAST_FUNCTION_CODE_GBL 0x20 831 #define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 832 #define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 833 834 #endif /* __KERNEL__ */ 835 #endif /* _ASM_POWERPC_QE_H */ 836