1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2023 Linaro Ltd.
4 * Author: Peter Griffin <peter.griffin@linaro.org>
5 *
6 * Common Clock Framework support for GS101.
7 */
8
9 #include <linux/clk-provider.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12
13 #include <dt-bindings/clock/google,gs101.h>
14
15 #include "clk.h"
16 #include "clk-exynos-arm64.h"
17 #include "clk-pll.h"
18
19 /* NOTE: Must be equal to the last clock ID increased by one */
20 #define CLKS_NR_TOP (CLK_GOUT_CMU_TPU_UART + 1)
21 #define CLKS_NR_APM (CLK_APM_PLL_DIV16_APM + 1)
22 #define CLKS_NR_DPU (CLK_GOUT_DPU_SYSREG_DPU_PCLK + 1)
23 #define CLKS_NR_HSI0 (CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1)
24 #define CLKS_NR_HSI2 (CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)
25 #define CLKS_NR_MISC (CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
26 #define CLKS_NR_PERIC0 (CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK + 1)
27 #define CLKS_NR_PERIC1 (CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK + 1)
28
29 #define GS101_GATE_DBG_OFFSET 0x4000
30 #define GS101_DRCG_EN_OFFSET 0x104
31 #define GS101_MEMCLK_OFFSET 0x108
32
33 /* ---- CMU_TOP ------------------------------------------------------------- */
34
35 /* Register Offset definitions for CMU_TOP (0x1e080000) */
36 #define PLL_LOCKTIME_PLL_SHARED0 0x0000
37 #define PLL_LOCKTIME_PLL_SHARED1 0x0004
38 #define PLL_LOCKTIME_PLL_SHARED2 0x0008
39 #define PLL_LOCKTIME_PLL_SHARED3 0x000c
40 #define PLL_LOCKTIME_PLL_SPARE 0x0010
41 #define PLL_CON0_PLL_SHARED0 0x0100
42 #define PLL_CON1_PLL_SHARED0 0x0104
43 #define PLL_CON2_PLL_SHARED0 0x0108
44 #define PLL_CON3_PLL_SHARED0 0x010c
45 #define PLL_CON4_PLL_SHARED0 0x0110
46 #define PLL_CON0_PLL_SHARED1 0x0140
47 #define PLL_CON1_PLL_SHARED1 0x0144
48 #define PLL_CON2_PLL_SHARED1 0x0148
49 #define PLL_CON3_PLL_SHARED1 0x014c
50 #define PLL_CON4_PLL_SHARED1 0x0150
51 #define PLL_CON0_PLL_SHARED2 0x0180
52 #define PLL_CON1_PLL_SHARED2 0x0184
53 #define PLL_CON2_PLL_SHARED2 0x0188
54 #define PLL_CON3_PLL_SHARED2 0x018c
55 #define PLL_CON4_PLL_SHARED2 0x0190
56 #define PLL_CON0_PLL_SHARED3 0x01c0
57 #define PLL_CON1_PLL_SHARED3 0x01c4
58 #define PLL_CON2_PLL_SHARED3 0x01c8
59 #define PLL_CON3_PLL_SHARED3 0x01cc
60 #define PLL_CON4_PLL_SHARED3 0x01d0
61 #define PLL_CON0_PLL_SPARE 0x0200
62 #define PLL_CON1_PLL_SPARE 0x0204
63 #define PLL_CON2_PLL_SPARE 0x0208
64 #define PLL_CON3_PLL_SPARE 0x020c
65 #define PLL_CON4_PLL_SPARE 0x0210
66 #define CMU_CMU_TOP_CONTROLLER_OPTION 0x0800
67 #define CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0 0x0810
68 #define CMU_HCHGEN_CLKMUX_CMU_BOOST 0x0840
69 #define CMU_HCHGEN_CLKMUX_TOP_BOOST 0x0844
70 #define CMU_HCHGEN_CLKMUX 0x0850
71 #define POWER_FAIL_DETECT_PLL 0x0864
72 #define EARLY_WAKEUP_FORCED_0_ENABLE 0x0870
73 #define EARLY_WAKEUP_FORCED_1_ENABLE 0x0874
74 #define EARLY_WAKEUP_APM_CTRL 0x0878
75 #define EARLY_WAKEUP_CLUSTER0_CTRL 0x087c
76 #define EARLY_WAKEUP_DPU_CTRL 0x0880
77 #define EARLY_WAKEUP_CSIS_CTRL 0x0884
78 #define EARLY_WAKEUP_APM_DEST 0x0890
79 #define EARLY_WAKEUP_CLUSTER0_DEST 0x0894
80 #define EARLY_WAKEUP_DPU_DEST 0x0898
81 #define EARLY_WAKEUP_CSIS_DEST 0x089c
82 #define EARLY_WAKEUP_SW_TRIG_APM 0x08c0
83 #define EARLY_WAKEUP_SW_TRIG_APM_SET 0x08c4
84 #define EARLY_WAKEUP_SW_TRIG_APM_CLEAR 0x08c8
85 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0 0x08d0
86 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_SET 0x08d4
87 #define EARLY_WAKEUP_SW_TRIG_CLUSTER0_CLEAR 0x08d8
88 #define EARLY_WAKEUP_SW_TRIG_DPU 0x08e0
89 #define EARLY_WAKEUP_SW_TRIG_DPU_SET 0x08e4
90 #define EARLY_WAKEUP_SW_TRIG_DPU_CLEAR 0x08e8
91 #define EARLY_WAKEUP_SW_TRIG_CSIS 0x08f0
92 #define EARLY_WAKEUP_SW_TRIG_CSIS_SET 0x08f4
93 #define EARLY_WAKEUP_SW_TRIG_CSIS_CLEAR 0x08f8
94 #define CLK_CON_MUX_MUX_CLKCMU_BO_BUS 0x1000
95 #define CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS 0x1004
96 #define CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS 0x1008
97 #define CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS 0x100c
98 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0 0x1010
99 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1 0x1014
100 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2 0x1018
101 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3 0x101c
102 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4 0x1020
103 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5 0x1024
104 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6 0x1028
105 #define CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7 0x102c
106 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST 0x1030
107 #define CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1 0x1034
108 #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1038
109 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG 0x103c
110 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH 0x1040
111 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH 0x1044
112 #define CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH 0x1048
113 #define CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS 0x104c
114 #define CLK_CON_MUX_MUX_CLKCMU_DISP_BUS 0x1050
115 #define CLK_CON_MUX_MUX_CLKCMU_DNS_BUS 0x1054
116 #define CLK_CON_MUX_MUX_CLKCMU_DPU_BUS 0x1058
117 #define CLK_CON_MUX_MUX_CLKCMU_EH_BUS 0x105c
118 #define CLK_CON_MUX_MUX_CLKCMU_G2D_G2D 0x1060
119 #define CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL 0x1064
120 #define CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA 0x1068
121 #define CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD 0x106c
122 #define CLK_CON_MUX_MUX_CLKCMU_G3D_GLB 0x1070
123 #define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1074
124 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0 0x1078
125 #define CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1 0x107c
126 #define CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC 0x1080
127 #define CLK_CON_MUX_MUX_CLKCMU_HPM 0x1084
128 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS 0x1088
129 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC 0x108c
130 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD 0x1090
131 #define CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG 0x1094
132 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS 0x1098
133 #define CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE 0x109c
134 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS 0x10a0
135 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD 0x10a4
136 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE 0x10a8
137 #define CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD 0x10ac
138 #define CLK_CON_MUX_MUX_CLKCMU_IPP_BUS 0x10b0
139 #define CLK_CON_MUX_MUX_CLKCMU_ITP_BUS 0x10b4
140 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC 0x10b8
141 #define CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC 0x10bc
142 #define CLK_CON_MUX_MUX_CLKCMU_MFC_MFC 0x10c0
143 #define CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP 0x10c4
144 #define CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH 0x10c8
145 #define CLK_CON_MUX_MUX_CLKCMU_MISC_BUS 0x10cc
146 #define CLK_CON_MUX_MUX_CLKCMU_MISC_SSS 0x10d0
147 #define CLK_CON_MUX_MUX_CLKCMU_PDP_BUS 0x10d4
148 #define CLK_CON_MUX_MUX_CLKCMU_PDP_VRA 0x10d8
149 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS 0x10dc
150 #define CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP 0x10e0
151 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS 0x10e4
152 #define CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP 0x10e8
153 #define CLK_CON_MUX_MUX_CLKCMU_TNR_BUS 0x10ec
154 #define CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1 0x10f0
155 #define CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF 0x10f4
156 #define CLK_CON_MUX_MUX_CLKCMU_TPU_BUS 0x10f8
157 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPU 0x10fc
158 #define CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL 0x1100
159 #define CLK_CON_MUX_MUX_CLKCMU_TPU_UART 0x1104
160 #define CLK_CON_MUX_MUX_CMU_CMUREF 0x1108
161 #define CLK_CON_DIV_CLKCMU_BO_BUS 0x1800
162 #define CLK_CON_DIV_CLKCMU_BUS0_BUS 0x1804
163 #define CLK_CON_DIV_CLKCMU_BUS1_BUS 0x1808
164 #define CLK_CON_DIV_CLKCMU_BUS2_BUS 0x180c
165 #define CLK_CON_DIV_CLKCMU_CIS_CLK0 0x1810
166 #define CLK_CON_DIV_CLKCMU_CIS_CLK1 0x1814
167 #define CLK_CON_DIV_CLKCMU_CIS_CLK2 0x1818
168 #define CLK_CON_DIV_CLKCMU_CIS_CLK3 0x181c
169 #define CLK_CON_DIV_CLKCMU_CIS_CLK4 0x1820
170 #define CLK_CON_DIV_CLKCMU_CIS_CLK5 0x1824
171 #define CLK_CON_DIV_CLKCMU_CIS_CLK6 0x1828
172 #define CLK_CON_DIV_CLKCMU_CIS_CLK7 0x182c
173 #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1830
174 #define CLK_CON_DIV_CLKCMU_CPUCL0_DBG 0x1834
175 #define CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH 0x1838
176 #define CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH 0x183c
177 #define CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH 0x1840
178 #define CLK_CON_DIV_CLKCMU_CSIS_BUS 0x1844
179 #define CLK_CON_DIV_CLKCMU_DISP_BUS 0x1848
180 #define CLK_CON_DIV_CLKCMU_DNS_BUS 0x184c
181 #define CLK_CON_DIV_CLKCMU_DPU_BUS 0x1850
182 #define CLK_CON_DIV_CLKCMU_EH_BUS 0x1854
183 #define CLK_CON_DIV_CLKCMU_G2D_G2D 0x1858
184 #define CLK_CON_DIV_CLKCMU_G2D_MSCL 0x185c
185 #define CLK_CON_DIV_CLKCMU_G3AA_G3AA 0x1860
186 #define CLK_CON_DIV_CLKCMU_G3D_BUSD 0x1864
187 #define CLK_CON_DIV_CLKCMU_G3D_GLB 0x1868
188 #define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x186c
189 #define CLK_CON_DIV_CLKCMU_GDC_GDC0 0x1870
190 #define CLK_CON_DIV_CLKCMU_GDC_GDC1 0x1874
191 #define CLK_CON_DIV_CLKCMU_GDC_SCSC 0x1878
192 #define CLK_CON_DIV_CLKCMU_HPM 0x187c
193 #define CLK_CON_DIV_CLKCMU_HSI0_BUS 0x1880
194 #define CLK_CON_DIV_CLKCMU_HSI0_DPGTC 0x1884
195 #define CLK_CON_DIV_CLKCMU_HSI0_USB31DRD 0x1888
196 #define CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG 0x188c
197 #define CLK_CON_DIV_CLKCMU_HSI1_BUS 0x1890
198 #define CLK_CON_DIV_CLKCMU_HSI1_PCIE 0x1894
199 #define CLK_CON_DIV_CLKCMU_HSI2_BUS 0x1898
200 #define CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD 0x189c
201 #define CLK_CON_DIV_CLKCMU_HSI2_PCIE 0x18a0
202 #define CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD 0x18a4
203 #define CLK_CON_DIV_CLKCMU_IPP_BUS 0x18a8
204 #define CLK_CON_DIV_CLKCMU_ITP_BUS 0x18ac
205 #define CLK_CON_DIV_CLKCMU_MCSC_ITSC 0x18b0
206 #define CLK_CON_DIV_CLKCMU_MCSC_MCSC 0x18b4
207 #define CLK_CON_DIV_CLKCMU_MFC_MFC 0x18b8
208 #define CLK_CON_DIV_CLKCMU_MIF_BUSP 0x18bc
209 #define CLK_CON_DIV_CLKCMU_MISC_BUS 0x18c0
210 #define CLK_CON_DIV_CLKCMU_MISC_SSS 0x18c4
211 #define CLK_CON_DIV_CLKCMU_OTP 0x18c8
212 #define CLK_CON_DIV_CLKCMU_PDP_BUS 0x18cc
213 #define CLK_CON_DIV_CLKCMU_PDP_VRA 0x18d0
214 #define CLK_CON_DIV_CLKCMU_PERIC0_BUS 0x18d4
215 #define CLK_CON_DIV_CLKCMU_PERIC0_IP 0x18d8
216 #define CLK_CON_DIV_CLKCMU_PERIC1_BUS 0x18dc
217 #define CLK_CON_DIV_CLKCMU_PERIC1_IP 0x18e0
218 #define CLK_CON_DIV_CLKCMU_TNR_BUS 0x18e4
219 #define CLK_CON_DIV_CLKCMU_TPU_BUS 0x18e8
220 #define CLK_CON_DIV_CLKCMU_TPU_TPU 0x18ec
221 #define CLK_CON_DIV_CLKCMU_TPU_TPUCTL 0x18f0
222 #define CLK_CON_DIV_CLKCMU_TPU_UART 0x18f4
223 #define CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST 0x18f8
224 #define CLK_CON_DIV_DIV_CLK_CMU_CMUREF 0x18fc
225 #define CLK_CON_DIV_PLL_SHARED0_DIV2 0x1900
226 #define CLK_CON_DIV_PLL_SHARED0_DIV3 0x1904
227 #define CLK_CON_DIV_PLL_SHARED0_DIV4 0x1908
228 #define CLK_CON_DIV_PLL_SHARED0_DIV5 0x190c
229 #define CLK_CON_DIV_PLL_SHARED1_DIV2 0x1910
230 #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x1914
231 #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x1918
232 #define CLK_CON_DIV_PLL_SHARED2_DIV2 0x191c
233 #define CLK_CON_DIV_PLL_SHARED3_DIV2 0x1920
234 #define CLK_CON_GAT_CLKCMU_BUS0_BOOST 0x2000
235 #define CLK_CON_GAT_CLKCMU_BUS1_BOOST 0x2004
236 #define CLK_CON_GAT_CLKCMU_BUS2_BOOST 0x2008
237 #define CLK_CON_GAT_CLKCMU_CORE_BOOST 0x200c
238 #define CLK_CON_GAT_CLKCMU_CPUCL0_BOOST 0x2010
239 #define CLK_CON_GAT_CLKCMU_CPUCL1_BOOST 0x2014
240 #define CLK_CON_GAT_CLKCMU_CPUCL2_BOOST 0x2018
241 #define CLK_CON_GAT_CLKCMU_MIF_BOOST 0x201c
242 #define CLK_CON_GAT_CLKCMU_MIF_SWITCH 0x2020
243 #define CLK_CON_GAT_GATE_CLKCMU_BO_BUS 0x2024
244 #define CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS 0x2028
245 #define CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS 0x202c
246 #define CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS 0x2030
247 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0 0x2034
248 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1 0x2038
249 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2 0x203c
250 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3 0x2040
251 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4 0x2044
252 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5 0x2048
253 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6 0x204c
254 #define CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7 0x2050
255 #define CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST 0x2054
256 #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x2058
257 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS 0x205c
258 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH 0x2060
259 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH 0x2064
260 #define CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH 0x2068
261 #define CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS 0x206c
262 #define CLK_CON_GAT_GATE_CLKCMU_DISP_BUS 0x2070
263 #define CLK_CON_GAT_GATE_CLKCMU_DNS_BUS 0x2074
264 #define CLK_CON_GAT_GATE_CLKCMU_DPU_BUS 0x2078
265 #define CLK_CON_GAT_GATE_CLKCMU_EH_BUS 0x207c
266 #define CLK_CON_GAT_GATE_CLKCMU_G2D_G2D 0x2080
267 #define CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL 0x2084
268 #define CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA 0x2088
269 #define CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD 0x208c
270 #define CLK_CON_GAT_GATE_CLKCMU_G3D_GLB 0x2090
271 #define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2094
272 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0 0x2098
273 #define CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1 0x209c
274 #define CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC 0x20a0
275 #define CLK_CON_GAT_GATE_CLKCMU_HPM 0x20a4
276 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS 0x20a8
277 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC 0x20ac
278 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD 0x20b0
279 #define CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG 0x20b4
280 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS 0x20b8
281 #define CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE 0x20bc
282 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS 0x20c0
283 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD 0x20c4
284 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE 0x20c8
285 #define CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD 0x20cc
286 #define CLK_CON_GAT_GATE_CLKCMU_IPP_BUS 0x20d0
287 #define CLK_CON_GAT_GATE_CLKCMU_ITP_BUS 0x20d4
288 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC 0x20d8
289 #define CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC 0x20dc
290 #define CLK_CON_GAT_GATE_CLKCMU_MFC_MFC 0x20e0
291 #define CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP 0x20e4
292 #define CLK_CON_GAT_GATE_CLKCMU_MISC_BUS 0x20e8
293 #define CLK_CON_GAT_GATE_CLKCMU_MISC_SSS 0x20ec
294 #define CLK_CON_GAT_GATE_CLKCMU_PDP_BUS 0x20f0
295 #define CLK_CON_GAT_GATE_CLKCMU_PDP_VRA 0x20f4
296 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS 0x20f8
297 #define CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP 0x20fc
298 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS 0x2100
299 #define CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP 0x2104
300 #define CLK_CON_GAT_GATE_CLKCMU_TNR_BUS 0x2108
301 #define CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF 0x210c
302 #define CLK_CON_GAT_GATE_CLKCMU_TPU_BUS 0x2110
303 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPU 0x2114
304 #define CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL 0x2118
305 #define CLK_CON_GAT_GATE_CLKCMU_TPU_UART 0x211c
306 #define DMYQCH_CON_CMU_TOP_CMUREF_QCH 0x3000
307 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0 0x3004
308 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1 0x3008
309 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2 0x300c
310 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3 0x3010
311 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4 0x3014
312 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5 0x3018
313 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6 0x301c
314 #define DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7 0x3020
315 #define DMYQCH_CON_OTP_QCH 0x3024
316 #define QUEUE_CTRL_REG_BLK_CMU_CMU_TOP 0x3c00
317 #define QUEUE_ENTRY0_BLK_CMU_CMU_TOP 0x3c10
318 #define QUEUE_ENTRY1_BLK_CMU_CMU_TOP 0x3c14
319 #define QUEUE_ENTRY2_BLK_CMU_CMU_TOP 0x3c18
320 #define QUEUE_ENTRY3_BLK_CMU_CMU_TOP 0x3c1c
321 #define QUEUE_ENTRY4_BLK_CMU_CMU_TOP 0x3c20
322 #define QUEUE_ENTRY5_BLK_CMU_CMU_TOP 0x3c24
323 #define QUEUE_ENTRY6_BLK_CMU_CMU_TOP 0x3c28
324 #define QUEUE_ENTRY7_BLK_CMU_CMU_TOP 0x3c2c
325 #define MIFMIRROR_QUEUE_CTRL_REG 0x3e00
326 #define MIFMIRROR_QUEUE_ENTRY0 0x3e10
327 #define MIFMIRROR_QUEUE_ENTRY1 0x3e14
328 #define MIFMIRROR_QUEUE_ENTRY2 0x3e18
329 #define MIFMIRROR_QUEUE_ENTRY3 0x3e1c
330 #define MIFMIRROR_QUEUE_ENTRY4 0x3e20
331 #define MIFMIRROR_QUEUE_ENTRY5 0x3e24
332 #define MIFMIRROR_QUEUE_ENTRY6 0x3e28
333 #define MIFMIRROR_QUEUE_ENTRY7 0x3e2c
334 #define MIFMIRROR_QUEUE_BUSY 0x3e30
335 #define GENERALIO_ACD_CHANNEL_0 0x3f00
336 #define GENERALIO_ACD_CHANNEL_1 0x3f04
337 #define GENERALIO_ACD_CHANNEL_2 0x3f08
338 #define GENERALIO_ACD_CHANNEL_3 0x3f0c
339 #define GENERALIO_ACD_MASK 0x3f14
340
341 static const unsigned long top_clk_regs[] __initconst = {
342 PLL_LOCKTIME_PLL_SHARED0,
343 PLL_LOCKTIME_PLL_SHARED1,
344 PLL_LOCKTIME_PLL_SHARED2,
345 PLL_LOCKTIME_PLL_SHARED3,
346 PLL_LOCKTIME_PLL_SPARE,
347 PLL_CON0_PLL_SHARED0,
348 PLL_CON1_PLL_SHARED0,
349 PLL_CON2_PLL_SHARED0,
350 PLL_CON3_PLL_SHARED0,
351 PLL_CON4_PLL_SHARED0,
352 PLL_CON0_PLL_SHARED1,
353 PLL_CON1_PLL_SHARED1,
354 PLL_CON2_PLL_SHARED1,
355 PLL_CON3_PLL_SHARED1,
356 PLL_CON4_PLL_SHARED1,
357 PLL_CON0_PLL_SHARED2,
358 PLL_CON1_PLL_SHARED2,
359 PLL_CON2_PLL_SHARED2,
360 PLL_CON3_PLL_SHARED2,
361 PLL_CON4_PLL_SHARED2,
362 PLL_CON0_PLL_SHARED3,
363 PLL_CON1_PLL_SHARED3,
364 PLL_CON2_PLL_SHARED3,
365 PLL_CON3_PLL_SHARED3,
366 PLL_CON4_PLL_SHARED3,
367 PLL_CON0_PLL_SPARE,
368 PLL_CON1_PLL_SPARE,
369 PLL_CON2_PLL_SPARE,
370 PLL_CON3_PLL_SPARE,
371 PLL_CON4_PLL_SPARE,
372 CMU_CMU_TOP_CONTROLLER_OPTION,
373 CLKOUT_CON_BLK_CMU_CMU_TOP_CLKOUT0,
374 CMU_HCHGEN_CLKMUX_CMU_BOOST,
375 CMU_HCHGEN_CLKMUX_TOP_BOOST,
376 CMU_HCHGEN_CLKMUX,
377 POWER_FAIL_DETECT_PLL,
378 EARLY_WAKEUP_FORCED_0_ENABLE,
379 EARLY_WAKEUP_FORCED_1_ENABLE,
380 EARLY_WAKEUP_APM_CTRL,
381 EARLY_WAKEUP_CLUSTER0_CTRL,
382 EARLY_WAKEUP_DPU_CTRL,
383 EARLY_WAKEUP_CSIS_CTRL,
384 EARLY_WAKEUP_APM_DEST,
385 EARLY_WAKEUP_CLUSTER0_DEST,
386 EARLY_WAKEUP_DPU_DEST,
387 EARLY_WAKEUP_CSIS_DEST,
388 EARLY_WAKEUP_SW_TRIG_APM,
389 EARLY_WAKEUP_SW_TRIG_CLUSTER0,
390 EARLY_WAKEUP_SW_TRIG_DPU,
391 EARLY_WAKEUP_SW_TRIG_CSIS,
392 CLK_CON_MUX_MUX_CLKCMU_BO_BUS,
393 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS,
394 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS,
395 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS,
396 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0,
397 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1,
398 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2,
399 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3,
400 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4,
401 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5,
402 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6,
403 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7,
404 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST,
405 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1,
406 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
407 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_DBG,
408 CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
409 CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
410 CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
411 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS,
412 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS,
413 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS,
414 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS,
415 CLK_CON_MUX_MUX_CLKCMU_EH_BUS,
416 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D,
417 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL,
418 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA,
419 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD,
420 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB,
421 CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH,
422 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0,
423 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1,
424 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC,
425 CLK_CON_MUX_MUX_CLKCMU_HPM,
426 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS,
427 CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC,
428 CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
429 CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
430 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS,
431 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE,
432 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS,
433 CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
434 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE,
435 CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
436 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS,
437 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS,
438 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC,
439 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC,
440 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC,
441 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP,
442 CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH,
443 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS,
444 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS,
445 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS,
446 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA,
447 CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS,
448 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP,
449 CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS,
450 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP,
451 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS,
452 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1,
453 CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF,
454 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS,
455 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU,
456 CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL,
457 CLK_CON_MUX_MUX_CLKCMU_TPU_UART,
458 CLK_CON_MUX_MUX_CMU_CMUREF,
459 CLK_CON_DIV_CLKCMU_BO_BUS,
460 CLK_CON_DIV_CLKCMU_BUS0_BUS,
461 CLK_CON_DIV_CLKCMU_BUS1_BUS,
462 CLK_CON_DIV_CLKCMU_BUS2_BUS,
463 CLK_CON_DIV_CLKCMU_CIS_CLK0,
464 CLK_CON_DIV_CLKCMU_CIS_CLK1,
465 CLK_CON_DIV_CLKCMU_CIS_CLK2,
466 CLK_CON_DIV_CLKCMU_CIS_CLK3,
467 CLK_CON_DIV_CLKCMU_CIS_CLK4,
468 CLK_CON_DIV_CLKCMU_CIS_CLK5,
469 CLK_CON_DIV_CLKCMU_CIS_CLK6,
470 CLK_CON_DIV_CLKCMU_CIS_CLK7,
471 CLK_CON_DIV_CLKCMU_CORE_BUS,
472 CLK_CON_DIV_CLKCMU_CPUCL0_DBG,
473 CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH,
474 CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH,
475 CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH,
476 CLK_CON_DIV_CLKCMU_CSIS_BUS,
477 CLK_CON_DIV_CLKCMU_DISP_BUS,
478 CLK_CON_DIV_CLKCMU_DNS_BUS,
479 CLK_CON_DIV_CLKCMU_DPU_BUS,
480 CLK_CON_DIV_CLKCMU_EH_BUS,
481 CLK_CON_DIV_CLKCMU_G2D_G2D,
482 CLK_CON_DIV_CLKCMU_G2D_MSCL,
483 CLK_CON_DIV_CLKCMU_G3AA_G3AA,
484 CLK_CON_DIV_CLKCMU_G3D_BUSD,
485 CLK_CON_DIV_CLKCMU_G3D_GLB,
486 CLK_CON_DIV_CLKCMU_G3D_SWITCH,
487 CLK_CON_DIV_CLKCMU_GDC_GDC0,
488 CLK_CON_DIV_CLKCMU_GDC_GDC1,
489 CLK_CON_DIV_CLKCMU_GDC_SCSC,
490 CLK_CON_DIV_CLKCMU_HPM,
491 CLK_CON_DIV_CLKCMU_HSI0_BUS,
492 CLK_CON_DIV_CLKCMU_HSI0_DPGTC,
493 CLK_CON_DIV_CLKCMU_HSI0_USB31DRD,
494 CLK_CON_DIV_CLKCMU_HSI0_USBDPDBG,
495 CLK_CON_DIV_CLKCMU_HSI1_BUS,
496 CLK_CON_DIV_CLKCMU_HSI1_PCIE,
497 CLK_CON_DIV_CLKCMU_HSI2_BUS,
498 CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD,
499 CLK_CON_DIV_CLKCMU_HSI2_PCIE,
500 CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD,
501 CLK_CON_DIV_CLKCMU_IPP_BUS,
502 CLK_CON_DIV_CLKCMU_ITP_BUS,
503 CLK_CON_DIV_CLKCMU_MCSC_ITSC,
504 CLK_CON_DIV_CLKCMU_MCSC_MCSC,
505 CLK_CON_DIV_CLKCMU_MFC_MFC,
506 CLK_CON_DIV_CLKCMU_MIF_BUSP,
507 CLK_CON_DIV_CLKCMU_MISC_BUS,
508 CLK_CON_DIV_CLKCMU_MISC_SSS,
509 CLK_CON_DIV_CLKCMU_OTP,
510 CLK_CON_DIV_CLKCMU_PDP_BUS,
511 CLK_CON_DIV_CLKCMU_PDP_VRA,
512 CLK_CON_DIV_CLKCMU_PERIC0_BUS,
513 CLK_CON_DIV_CLKCMU_PERIC0_IP,
514 CLK_CON_DIV_CLKCMU_PERIC1_BUS,
515 CLK_CON_DIV_CLKCMU_PERIC1_IP,
516 CLK_CON_DIV_CLKCMU_TNR_BUS,
517 CLK_CON_DIV_CLKCMU_TPU_BUS,
518 CLK_CON_DIV_CLKCMU_TPU_TPU,
519 CLK_CON_DIV_CLKCMU_TPU_TPUCTL,
520 CLK_CON_DIV_CLKCMU_TPU_UART,
521 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST,
522 CLK_CON_DIV_DIV_CLK_CMU_CMUREF,
523 CLK_CON_DIV_PLL_SHARED0_DIV2,
524 CLK_CON_DIV_PLL_SHARED0_DIV3,
525 CLK_CON_DIV_PLL_SHARED0_DIV4,
526 CLK_CON_DIV_PLL_SHARED0_DIV5,
527 CLK_CON_DIV_PLL_SHARED1_DIV2,
528 CLK_CON_DIV_PLL_SHARED1_DIV3,
529 CLK_CON_DIV_PLL_SHARED1_DIV4,
530 CLK_CON_DIV_PLL_SHARED2_DIV2,
531 CLK_CON_DIV_PLL_SHARED3_DIV2,
532 CLK_CON_GAT_CLKCMU_BUS0_BOOST,
533 CLK_CON_GAT_CLKCMU_BUS1_BOOST,
534 CLK_CON_GAT_CLKCMU_BUS2_BOOST,
535 CLK_CON_GAT_CLKCMU_CORE_BOOST,
536 CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
537 CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
538 CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
539 CLK_CON_GAT_CLKCMU_MIF_BOOST,
540 CLK_CON_GAT_CLKCMU_MIF_SWITCH,
541 CLK_CON_GAT_GATE_CLKCMU_BO_BUS,
542 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS,
543 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS,
544 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS,
545 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0,
546 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1,
547 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2,
548 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3,
549 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4,
550 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5,
551 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6,
552 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7,
553 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST,
554 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
555 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
556 CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
557 CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
558 CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
559 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS,
560 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS,
561 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS,
562 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS,
563 CLK_CON_GAT_GATE_CLKCMU_EH_BUS,
564 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D,
565 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL,
566 CLK_CON_GAT_GATE_CLKCMU_G3AA_G3AA,
567 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD,
568 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB,
569 CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
570 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0,
571 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1,
572 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC,
573 CLK_CON_GAT_GATE_CLKCMU_HPM,
574 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS,
575 CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
576 CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
577 CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
578 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS,
579 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE,
580 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS,
581 CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
582 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE,
583 CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
584 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS,
585 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS,
586 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC,
587 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC,
588 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC,
589 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP,
590 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS,
591 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS,
592 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS,
593 CLK_CON_GAT_GATE_CLKCMU_PDP_VRA,
594 CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
595 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP,
596 CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
597 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP,
598 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS,
599 CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
600 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS,
601 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU,
602 CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
603 CLK_CON_GAT_GATE_CLKCMU_TPU_UART,
604 DMYQCH_CON_CMU_TOP_CMUREF_QCH,
605 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK0,
606 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK1,
607 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK2,
608 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK3,
609 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK4,
610 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK5,
611 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK6,
612 DMYQCH_CON_DFTMUX_CMU_QCH_CIS_CLK7,
613 DMYQCH_CON_OTP_QCH,
614 QUEUE_CTRL_REG_BLK_CMU_CMU_TOP,
615 QUEUE_ENTRY0_BLK_CMU_CMU_TOP,
616 QUEUE_ENTRY1_BLK_CMU_CMU_TOP,
617 QUEUE_ENTRY2_BLK_CMU_CMU_TOP,
618 QUEUE_ENTRY3_BLK_CMU_CMU_TOP,
619 QUEUE_ENTRY4_BLK_CMU_CMU_TOP,
620 QUEUE_ENTRY5_BLK_CMU_CMU_TOP,
621 QUEUE_ENTRY6_BLK_CMU_CMU_TOP,
622 QUEUE_ENTRY7_BLK_CMU_CMU_TOP,
623 MIFMIRROR_QUEUE_CTRL_REG,
624 MIFMIRROR_QUEUE_ENTRY0,
625 MIFMIRROR_QUEUE_ENTRY1,
626 MIFMIRROR_QUEUE_ENTRY2,
627 MIFMIRROR_QUEUE_ENTRY3,
628 MIFMIRROR_QUEUE_ENTRY4,
629 MIFMIRROR_QUEUE_ENTRY5,
630 MIFMIRROR_QUEUE_ENTRY6,
631 MIFMIRROR_QUEUE_ENTRY7,
632 MIFMIRROR_QUEUE_BUSY,
633 GENERALIO_ACD_CHANNEL_0,
634 GENERALIO_ACD_CHANNEL_1,
635 GENERALIO_ACD_CHANNEL_2,
636 GENERALIO_ACD_CHANNEL_3,
637 GENERALIO_ACD_MASK,
638 };
639
640 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
641 /* CMU_TOP_PURECLKCOMP */
642 PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk",
643 PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0,
644 NULL),
645 PLL(pll_0517x, CLK_FOUT_SHARED1_PLL, "fout_shared1_pll", "oscclk",
646 PLL_LOCKTIME_PLL_SHARED1, PLL_CON3_PLL_SHARED1,
647 NULL),
648 PLL(pll_0518x, CLK_FOUT_SHARED2_PLL, "fout_shared2_pll", "oscclk",
649 PLL_LOCKTIME_PLL_SHARED2, PLL_CON3_PLL_SHARED2,
650 NULL),
651 PLL(pll_0518x, CLK_FOUT_SHARED3_PLL, "fout_shared3_pll", "oscclk",
652 PLL_LOCKTIME_PLL_SHARED3, PLL_CON3_PLL_SHARED3,
653 NULL),
654 PLL(pll_0518x, CLK_FOUT_SPARE_PLL, "fout_spare_pll", "oscclk",
655 PLL_LOCKTIME_PLL_SPARE, PLL_CON3_PLL_SPARE,
656 NULL),
657 };
658
659 /* List of parent clocks for Muxes in CMU_TOP */
660 PNAME(mout_pll_shared0_p) = { "oscclk", "fout_shared0_pll" };
661 PNAME(mout_pll_shared1_p) = { "oscclk", "fout_shared1_pll" };
662 PNAME(mout_pll_shared2_p) = { "oscclk", "fout_shared2_pll" };
663 PNAME(mout_pll_shared3_p) = { "oscclk", "fout_shared3_pll" };
664 PNAME(mout_pll_spare_p) = { "oscclk", "fout_spare_pll" };
665 PNAME(mout_cmu_bo_bus_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
666 "fout_shared3_pll", "dout_cmu_shared1_div3",
667 "dout_cmu_shared0_div4",
668 "dout_cmu_shared1_div4",
669 "fout_spare_pll", "oscclk" };
670 PNAME(mout_cmu_bus0_bus_p) = { "dout_cmu_shared0_div4",
671 "dout_cmu_shared1_div4",
672 "dout_cmu_shared2_div2",
673 "dout_cmu_shared3_div2",
674 "fout_spare_pll", "oscclk",
675 "oscclk", "oscclk" };
676 PNAME(mout_cmu_bus1_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
677 "dout_cmu_shared1_div3",
678 "dout_cmu_shared0_div4",
679 "dout_cmu_shared1_div4",
680 "dout_cmu_shared2_div2",
681 "fout_spare_pll", "oscclk" };
682 PNAME(mout_cmu_bus2_bus_p) = { "dout_cmu_shared0_div2",
683 "dout_cmu_shared1_div2",
684 "fout_shared2_pll", "fout_shared3_pll",
685 "dout_cmu_shared0_div3",
686 "dout_cmu_shared1_div3",
687 "dout_cmu_shared0_div5", "fout_spare_pll" };
688 PNAME(mout_cmu_cis_clk0_7_p) = { "oscclk", "dout_cmu_shared0_div3",
689 "dout_cmu_shared1_div3",
690 "dout_cmu_shared2_div2",
691 "dout_cmu_shared3_div2", "fout_spare_pll",
692 "oscclk", "oscclk" };
693 PNAME(mout_cmu_cmu_boost_p) = { "dout_cmu_shared0_div4",
694 "dout_cmu_shared1_div4",
695 "dout_cmu_shared2_div2",
696 "dout_cmu_shared3_div2" };
697 PNAME(mout_cmu_cmu_boost_option1_p) = { "dout_cmu_cmu_boost",
698 "gout_cmu_boost_option1" };
699 PNAME(mout_cmu_core_bus_p) = { "dout_cmu_shared0_div2",
700 "dout_cmu_shared1_div2",
701 "fout_shared2_pll", "fout_shared3_pll",
702 "dout_cmu_shared0_div3",
703 "dout_cmu_shared1_div3",
704 "dout_cmu_shared0_div5", "fout_spare_pll" };
705 PNAME(mout_cmu_cpucl0_dbg_p) = { "fout_shared2_pll", "fout_shared3_pll",
706 "dout_cmu_shared0_div4",
707 "dout_cmu_shared1_div4",
708 "dout_cmu_shared2_div2", "fout_spare_pll",
709 "oscclk", "oscclk" };
710 PNAME(mout_cmu_cpucl0_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
711 "dout_cmu_shared1_div2", "fout_shared2_pll",
712 "fout_shared3_pll", "dout_cmu_shared0_div3",
713 "dout_cmu_shared1_div3", "fout_spare_pll" };
714 PNAME(mout_cmu_cpucl1_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
715 "dout_cmu_shared1_div2", "fout_shared2_pll",
716 "fout_shared3_pll", "dout_cmu_shared0_div3",
717 "dout_cmu_shared1_div3", "fout_spare_pll" };
718 PNAME(mout_cmu_cpucl2_switch_p) = { "fout_shared1_pll", "dout_cmu_shared0_div2",
719 "dout_cmu_shared1_div2", "fout_shared2_pll",
720 "fout_shared3_pll", "dout_cmu_shared0_div3",
721 "dout_cmu_shared1_div3", "fout_spare_pll" };
722 PNAME(mout_cmu_csis_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
723 "dout_cmu_shared1_div3",
724 "dout_cmu_shared0_div4",
725 "dout_cmu_shared1_div4",
726 "dout_cmu_shared2_div2",
727 "fout_spare_pll", "oscclk" };
728 PNAME(mout_cmu_disp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
729 "dout_cmu_shared1_div3",
730 "dout_cmu_shared0_div4",
731 "dout_cmu_shared1_div4",
732 "dout_cmu_shared2_div2",
733 "fout_spare_pll", "oscclk" };
734 PNAME(mout_cmu_dns_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
735 "dout_cmu_shared1_div3",
736 "dout_cmu_shared0_div4",
737 "dout_cmu_shared1_div4",
738 "dout_cmu_shared2_div2",
739 "fout_spare_pll", "oscclk" };
740 PNAME(mout_cmu_dpu_p) = { "dout_cmu_shared0_div3",
741 "fout_shared3_pll",
742 "dout_cmu_shared1_div3",
743 "dout_cmu_shared0_div4",
744 "dout_cmu_shared1_div4",
745 "dout_cmu_shared2_div2",
746 "fout_spare_pll", "oscclk" };
747 PNAME(mout_cmu_eh_bus_p) = { "dout_cmu_shared0_div2",
748 "dout_cmu_shared1_div2",
749 "fout_shared2_pll", "fout_shared3_pll",
750 "dout_cmu_shared0_div3",
751 "dout_cmu_shared1_div3",
752 "dout_cmu_shared0_div5", "fout_spare_pll" };
753 PNAME(mout_cmu_g2d_g2d_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
754 "dout_cmu_shared1_div3",
755 "dout_cmu_shared0_div4",
756 "dout_cmu_shared1_div4",
757 "dout_cmu_shared2_div2",
758 "fout_spare_pll", "oscclk" };
759 PNAME(mout_cmu_g2d_mscl_p) = { "dout_cmu_shared0_div4",
760 "dout_cmu_shared1_div4",
761 "dout_cmu_shared2_div2",
762 "dout_cmu_shared3_div2",
763 "fout_spare_pll", "oscclk",
764 "oscclk", "oscclk" };
765 PNAME(mout_cmu_g3aa_g3aa_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
766 "dout_cmu_shared1_div3",
767 "dout_cmu_shared0_div4",
768 "dout_cmu_shared1_div4",
769 "dout_cmu_shared2_div2",
770 "fout_spare_pll", "oscclk" };
771 PNAME(mout_cmu_g3d_busd_p) = { "dout_cmu_shared0_div2",
772 "dout_cmu_shared1_div2",
773 "fout_shared2_pll", "fout_shared3_pll",
774 "dout_cmu_shared0_div3",
775 "dout_cmu_shared1_div3",
776 "dout_cmu_shared0_div4", "fout_spare_pll" };
777 PNAME(mout_cmu_g3d_glb_p) = { "dout_cmu_shared0_div2",
778 "dout_cmu_shared1_div2",
779 "fout_shared2_pll", "fout_shared3_pll",
780 "dout_cmu_shared0_div3",
781 "dout_cmu_shared1_div3",
782 "dout_cmu_shared0_div4", "fout_spare_pll" };
783 PNAME(mout_cmu_g3d_switch_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
784 "fout_shared3_pll", "dout_cmu_shared1_div3",
785 "dout_cmu_shared0_div4",
786 "dout_cmu_shared1_div4",
787 "fout_spare_pll", "fout_spare_pll"};
788 PNAME(mout_cmu_gdc_gdc0_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
789 "dout_cmu_shared1_div3",
790 "dout_cmu_shared0_div4",
791 "dout_cmu_shared1_div4",
792 "dout_cmu_shared2_div2",
793 "fout_spare_pll", "oscclk" };
794 PNAME(mout_cmu_gdc_gdc1_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
795 "dout_cmu_shared1_div3",
796 "dout_cmu_shared0_div4",
797 "dout_cmu_shared1_div4",
798 "dout_cmu_shared2_div2",
799 "fout_spare_pll", "oscclk" };
800 PNAME(mout_cmu_gdc_scsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
801 "dout_cmu_shared1_div3",
802 "dout_cmu_shared0_div4",
803 "dout_cmu_shared1_div4",
804 "dout_cmu_shared2_div2",
805 "fout_spare_pll", "oscclk" };
806 PNAME(mout_cmu_hpm_p) = { "oscclk", "dout_cmu_shared1_div3",
807 "dout_cmu_shared0_div4",
808 "dout_cmu_shared2_div2" };
809 PNAME(mout_cmu_hsi0_bus_p) = { "dout_cmu_shared0_div4",
810 "dout_cmu_shared1_div4",
811 "dout_cmu_shared2_div2",
812 "dout_cmu_shared3_div2",
813 "fout_spare_pll", "oscclk",
814 "oscclk", "oscclk" };
815 PNAME(mout_cmu_hsi0_dpgtc_p) = { "oscclk", "dout_cmu_shared0_div4",
816 "dout_cmu_shared2_div2", "fout_spare_pll" };
817 PNAME(mout_cmu_hsi0_usb31drd_p) = { "oscclk", "dout_cmu_shared2_div2" };
818 PNAME(mout_cmu_hsi0_usbdpdbg_p) = { "oscclk", "dout_cmu_shared2_div2" };
819 PNAME(mout_cmu_hsi1_bus_p) = { "dout_cmu_shared0_div4",
820 "dout_cmu_shared1_div4",
821 "dout_cmu_shared2_div2",
822 "dout_cmu_shared3_div2",
823 "fout_spare_pll" };
824 PNAME(mout_cmu_hsi1_pcie_p) = { "oscclk", "dout_cmu_shared2_div2" };
825 PNAME(mout_cmu_hsi2_bus_p) = { "dout_cmu_shared0_div4",
826 "dout_cmu_shared1_div4",
827 "dout_cmu_shared2_div2",
828 "dout_cmu_shared3_div2",
829 "fout_spare_pll", "oscclk",
830 "oscclk", "oscclk" };
831 PNAME(mout_cmu_hsi2_mmc_card_p) = { "fout_shared2_pll", "fout_shared3_pll",
832 "dout_cmu_shared0_div4", "fout_spare_pll" };
833 PNAME(mout_cmu_hsi2_pcie0_p) = { "oscclk", "dout_cmu_shared2_div2" };
834 PNAME(mout_cmu_hsi2_ufs_embd_p) = { "oscclk", "dout_cmu_shared0_div4",
835 "dout_cmu_shared2_div2", "fout_spare_pll" };
836 PNAME(mout_cmu_ipp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
837 "dout_cmu_shared1_div3",
838 "dout_cmu_shared0_div4",
839 "dout_cmu_shared1_div4",
840 "dout_cmu_shared2_div2",
841 "fout_spare_pll", "oscclk" };
842 PNAME(mout_cmu_itp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
843 "dout_cmu_shared1_div3",
844 "dout_cmu_shared0_div4",
845 "dout_cmu_shared1_div4",
846 "dout_cmu_shared2_div2",
847 "fout_spare_pll", "oscclk" };
848 PNAME(mout_cmu_mcsc_itsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
849 "dout_cmu_shared1_div3",
850 "dout_cmu_shared0_div4",
851 "dout_cmu_shared1_div4",
852 "dout_cmu_shared2_div2",
853 "fout_spare_pll", "oscclk" };
854 PNAME(mout_cmu_mcsc_mcsc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
855 "dout_cmu_shared1_div3",
856 "dout_cmu_shared0_div4",
857 "dout_cmu_shared1_div4",
858 "dout_cmu_shared2_div2",
859 "fout_spare_pll", "oscclk" };
860 PNAME(mout_cmu_mfc_mfc_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
861 "dout_cmu_shared0_div4",
862 "dout_cmu_shared1_div4",
863 "dout_cmu_shared2_div2", "fout_spare_pll",
864 "oscclk", "oscclk" };
865 PNAME(mout_cmu_mif_busp_p) = { "dout_cmu_shared0_div4",
866 "dout_cmu_shared1_div4",
867 "dout_cmu_shared0_div5", "fout_spare_pll" };
868 PNAME(mout_cmu_mif_switch_p) = { "fout_shared0_pll", "fout_shared1_pll",
869 "dout_cmu_shared0_div2",
870 "dout_cmu_shared1_div2",
871 "fout_shared2_pll", "dout_cmu_shared0_div3",
872 "fout_shared3_pll", "fout_spare_pll" };
873 PNAME(mout_cmu_misc_bus_p) = { "dout_cmu_shared0_div4",
874 "dout_cmu_shared2_div2",
875 "dout_cmu_shared3_div2", "fout_spare_pll" };
876 PNAME(mout_cmu_misc_sss_p) = { "dout_cmu_shared0_div4",
877 "dout_cmu_shared2_div2",
878 "dout_cmu_shared3_div2", "fout_spare_pll" };
879 PNAME(mout_cmu_pdp_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
880 "dout_cmu_shared1_div3",
881 "dout_cmu_shared0_div4",
882 "dout_cmu_shared1_div4",
883 "dout_cmu_shared2_div2",
884 "fout_spare_pll", "oscclk" };
885 PNAME(mout_cmu_pdp_vra_p) = { "fout_shared2_pll", "dout_cmu_shared0_div3",
886 "fout_shared3_pll", "dout_cmu_shared1_div3",
887 "dout_cmu_shared0_div4",
888 "dout_cmu_shared1_div4",
889 "fout_spare_pll", "oscclk" };
890 PNAME(mout_cmu_peric0_bus_p) = { "dout_cmu_shared0_div4",
891 "dout_cmu_shared2_div2",
892 "dout_cmu_shared3_div2", "fout_spare_pll" };
893 PNAME(mout_cmu_peric0_ip_p) = { "dout_cmu_shared0_div4",
894 "dout_cmu_shared2_div2",
895 "dout_cmu_shared3_div2", "fout_spare_pll" };
896 PNAME(mout_cmu_peric1_bus_p) = { "dout_cmu_shared0_div4",
897 "dout_cmu_shared2_div2",
898 "dout_cmu_shared3_div2", "fout_spare_pll" };
899 PNAME(mout_cmu_peric1_ip_p) = { "dout_cmu_shared0_div4",
900 "dout_cmu_shared2_div2",
901 "dout_cmu_shared3_div2", "fout_spare_pll" };
902 PNAME(mout_cmu_tnr_bus_p) = { "dout_cmu_shared0_div3", "fout_shared3_pll",
903 "dout_cmu_shared1_div3",
904 "dout_cmu_shared0_div4",
905 "dout_cmu_shared1_div4",
906 "dout_cmu_shared2_div2",
907 "fout_spare_pll", "oscclk" };
908 PNAME(mout_cmu_top_boost_option1_p) = { "oscclk",
909 "gout_cmu_boost_option1" };
910 PNAME(mout_cmu_top_cmuref_p) = { "dout_cmu_shared0_div4",
911 "dout_cmu_shared1_div4",
912 "dout_cmu_shared2_div2",
913 "dout_cmu_shared3_div2" };
914 PNAME(mout_cmu_tpu_bus_p) = { "dout_cmu_shared0_div2",
915 "dout_cmu_shared1_div2",
916 "fout_shared2_pll",
917 "fout_shared3_pll",
918 "dout_cmu_shared0_div3",
919 "dout_cmu_shared1_div3",
920 "dout_cmu_shared0_div4",
921 "fout_spare_pll" };
922 PNAME(mout_cmu_tpu_tpu_p) = { "dout_cmu_shared0_div2",
923 "dout_cmu_shared1_div2",
924 "fout_shared2_pll",
925 "fout_shared3_pll",
926 "dout_cmu_shared0_div3",
927 "dout_cmu_shared1_div3",
928 "dout_cmu_shared0_div4", "fout_spare_pll" };
929 PNAME(mout_cmu_tpu_tpuctl_p) = { "dout_cmu_shared0_div2",
930 "dout_cmu_shared1_div2",
931 "fout_shared2_pll", "fout_shared3_pll",
932 "dout_cmu_shared0_div3",
933 "dout_cmu_shared1_div3",
934 "dout_cmu_shared0_div4", "fout_spare_pll" };
935 PNAME(mout_cmu_tpu_uart_p) = { "dout_cmu_shared0_div4",
936 "dout_cmu_shared2_div2",
937 "dout_cmu_shared3_div2", "fout_spare_pll" };
938 PNAME(mout_cmu_cmuref_p) = { "mout_cmu_top_boost_option1",
939 "dout_cmu_cmuref" };
940
941 /*
942 * Register name to clock name mangling strategy used in this file
943 *
944 * Replace PLL_CON0_PLL with CLK_MOUT_PLL and mout_pll
945 * Replace CLK_CON_MUX_MUX_CLKCMU with CLK_MOUT_CMU and mout_cmu
946 * Replace CLK_CON_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
947 * Replace CLK_CON_DIV_DIV_CLKCMU with CLK_DOUT_CMU and dout_cmu
948 * Replace CLK_CON_GAT_CLKCMU with CLK_GOUT_CMU and gout_cmu
949 * Replace CLK_CON_GAT_GATE_CLKCMU with CLK_GOUT_CMU and gout_cmu
950 *
951 * For gates remove _UID _BLK _IPCLKPORT and _RSTNSYNC
952 */
953
954 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
955 MUX(CLK_MOUT_PLL_SHARED0, "mout_pll_shared0", mout_pll_shared0_p,
956 PLL_CON0_PLL_SHARED0, 4, 1),
957 MUX(CLK_MOUT_PLL_SHARED1, "mout_pll_shared1", mout_pll_shared1_p,
958 PLL_CON0_PLL_SHARED1, 4, 1),
959 MUX(CLK_MOUT_PLL_SHARED2, "mout_pll_shared2", mout_pll_shared2_p,
960 PLL_CON0_PLL_SHARED2, 4, 1),
961 MUX(CLK_MOUT_PLL_SHARED3, "mout_pll_shared3", mout_pll_shared3_p,
962 PLL_CON0_PLL_SHARED3, 4, 1),
963 MUX(CLK_MOUT_PLL_SPARE, "mout_pll_spare", mout_pll_spare_p,
964 PLL_CON0_PLL_SPARE, 4, 1),
965 MUX(CLK_MOUT_CMU_BO_BUS, "mout_cmu_bo_bus", mout_cmu_bo_bus_p,
966 CLK_CON_MUX_MUX_CLKCMU_BO_BUS, 0, 3),
967 MUX(CLK_MOUT_CMU_BUS0_BUS, "mout_cmu_bus0_bus", mout_cmu_bus0_bus_p,
968 CLK_CON_MUX_MUX_CLKCMU_BUS0_BUS, 0, 3),
969 MUX(CLK_MOUT_CMU_BUS1_BUS, "mout_cmu_bus1_bus", mout_cmu_bus1_bus_p,
970 CLK_CON_MUX_MUX_CLKCMU_BUS1_BUS, 0, 3),
971 MUX(CLK_MOUT_CMU_BUS2_BUS, "mout_cmu_bus2_bus", mout_cmu_bus2_bus_p,
972 CLK_CON_MUX_MUX_CLKCMU_BUS2_BUS, 0, 3),
973 MUX(CLK_MOUT_CMU_CIS_CLK0, "mout_cmu_cis_clk0", mout_cmu_cis_clk0_7_p,
974 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK0, 0, 3),
975 MUX(CLK_MOUT_CMU_CIS_CLK1, "mout_cmu_cis_clk1", mout_cmu_cis_clk0_7_p,
976 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK1, 0, 3),
977 MUX(CLK_MOUT_CMU_CIS_CLK2, "mout_cmu_cis_clk2", mout_cmu_cis_clk0_7_p,
978 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK2, 0, 3),
979 MUX(CLK_MOUT_CMU_CIS_CLK3, "mout_cmu_cis_clk3", mout_cmu_cis_clk0_7_p,
980 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK3, 0, 3),
981 MUX(CLK_MOUT_CMU_CIS_CLK4, "mout_cmu_cis_clk4", mout_cmu_cis_clk0_7_p,
982 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK4, 0, 3),
983 MUX(CLK_MOUT_CMU_CIS_CLK5, "mout_cmu_cis_clk5", mout_cmu_cis_clk0_7_p,
984 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK5, 0, 3),
985 MUX(CLK_MOUT_CMU_CIS_CLK6, "mout_cmu_cis_clk6", mout_cmu_cis_clk0_7_p,
986 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK6, 0, 3),
987 MUX(CLK_MOUT_CMU_CIS_CLK7, "mout_cmu_cis_clk7", mout_cmu_cis_clk0_7_p,
988 CLK_CON_MUX_MUX_CLKCMU_CIS_CLK7, 0, 3),
989 MUX(CLK_MOUT_CMU_CMU_BOOST, "mout_cmu_cmu_boost", mout_cmu_cmu_boost_p,
990 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST, 0, 2),
991 MUX(CLK_MOUT_CMU_BOOST_OPTION1, "mout_cmu_boost_option1",
992 mout_cmu_cmu_boost_option1_p,
993 CLK_CON_MUX_MUX_CLKCMU_CMU_BOOST_OPTION1, 0, 1),
994 MUX(CLK_MOUT_CMU_CORE_BUS, "mout_cmu_core_bus", mout_cmu_core_bus_p,
995 CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 3),
996 MUX(CLK_MOUT_CMU_CPUCL0_DBG, "mout_cmu_cpucl0_dbg",
997 mout_cmu_cpucl0_dbg_p, CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 3),
998 MUX(CLK_MOUT_CMU_CPUCL0_SWITCH, "mout_cmu_cpucl0_switch",
999 mout_cmu_cpucl0_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL0_SWITCH,
1000 0, 3),
1001 MUX(CLK_MOUT_CMU_CPUCL1_SWITCH, "mout_cmu_cpucl1_switch",
1002 mout_cmu_cpucl1_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL1_SWITCH,
1003 0, 3),
1004 MUX(CLK_MOUT_CMU_CPUCL2_SWITCH, "mout_cmu_cpucl2_switch",
1005 mout_cmu_cpucl2_switch_p, CLK_CON_MUX_MUX_CLKCMU_CPUCL2_SWITCH,
1006 0, 3),
1007 MUX(CLK_MOUT_CMU_CSIS_BUS, "mout_cmu_csis_bus", mout_cmu_csis_bus_p,
1008 CLK_CON_MUX_MUX_CLKCMU_CSIS_BUS, 0, 3),
1009 MUX(CLK_MOUT_CMU_DISP_BUS, "mout_cmu_disp_bus", mout_cmu_disp_bus_p,
1010 CLK_CON_MUX_MUX_CLKCMU_DISP_BUS, 0, 3),
1011 MUX(CLK_MOUT_CMU_DNS_BUS, "mout_cmu_dns_bus", mout_cmu_dns_bus_p,
1012 CLK_CON_MUX_MUX_CLKCMU_DNS_BUS, 0, 3),
1013 MUX(CLK_MOUT_CMU_DPU_BUS, "mout_cmu_dpu_bus", mout_cmu_dpu_p,
1014 CLK_CON_MUX_MUX_CLKCMU_DPU_BUS, 0, 3),
1015 MUX(CLK_MOUT_CMU_EH_BUS, "mout_cmu_eh_bus", mout_cmu_eh_bus_p,
1016 CLK_CON_MUX_MUX_CLKCMU_EH_BUS, 0, 3),
1017 MUX(CLK_MOUT_CMU_G2D_G2D, "mout_cmu_g2d_g2d", mout_cmu_g2d_g2d_p,
1018 CLK_CON_MUX_MUX_CLKCMU_G2D_G2D, 0, 3),
1019 MUX(CLK_MOUT_CMU_G2D_MSCL, "mout_cmu_g2d_mscl", mout_cmu_g2d_mscl_p,
1020 CLK_CON_MUX_MUX_CLKCMU_G2D_MSCL, 0, 3),
1021 MUX(CLK_MOUT_CMU_G3AA_G3AA, "mout_cmu_g3aa_g3aa", mout_cmu_g3aa_g3aa_p,
1022 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 0, 3),
1023 MUX(CLK_MOUT_CMU_G3D_BUSD, "mout_cmu_g3d_busd", mout_cmu_g3d_busd_p,
1024 CLK_CON_MUX_MUX_CLKCMU_G3D_BUSD, 0, 3),
1025 MUX(CLK_MOUT_CMU_G3D_GLB, "mout_cmu_g3d_glb", mout_cmu_g3d_glb_p,
1026 CLK_CON_MUX_MUX_CLKCMU_G3D_GLB, 0, 3),
1027 MUX(CLK_MOUT_CMU_G3D_SWITCH, "mout_cmu_g3d_switch",
1028 mout_cmu_g3d_switch_p, CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 3),
1029 MUX(CLK_MOUT_CMU_GDC_GDC0, "mout_cmu_gdc_gdc0", mout_cmu_gdc_gdc0_p,
1030 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC0, 0, 3),
1031 MUX(CLK_MOUT_CMU_GDC_GDC1, "mout_cmu_gdc_gdc1", mout_cmu_gdc_gdc1_p,
1032 CLK_CON_MUX_MUX_CLKCMU_GDC_GDC1, 0, 3),
1033 MUX(CLK_MOUT_CMU_GDC_SCSC, "mout_cmu_gdc_scsc", mout_cmu_gdc_scsc_p,
1034 CLK_CON_MUX_MUX_CLKCMU_GDC_SCSC, 0, 3),
1035 MUX(CLK_MOUT_CMU_HPM, "mout_cmu_hpm", mout_cmu_hpm_p,
1036 CLK_CON_MUX_MUX_CLKCMU_HPM, 0, 2),
1037 MUX(CLK_MOUT_CMU_HSI0_BUS, "mout_cmu_hsi0_bus", mout_cmu_hsi0_bus_p,
1038 CLK_CON_MUX_MUX_CLKCMU_HSI0_BUS, 0, 3),
1039 MUX(CLK_MOUT_CMU_HSI0_DPGTC, "mout_cmu_hsi0_dpgtc",
1040 mout_cmu_hsi0_dpgtc_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_DPGTC, 0, 2),
1041 MUX(CLK_MOUT_CMU_HSI0_USB31DRD, "mout_cmu_hsi0_usb31drd",
1042 mout_cmu_hsi0_usb31drd_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USB31DRD,
1043 0, 1),
1044 MUX(CLK_MOUT_CMU_HSI0_USBDPDBG, "mout_cmu_hsi0_usbdpdbg",
1045 mout_cmu_hsi0_usbdpdbg_p, CLK_CON_MUX_MUX_CLKCMU_HSI0_USBDPDBG,
1046 0, 1),
1047 MUX(CLK_MOUT_CMU_HSI1_BUS, "mout_cmu_hsi1_bus", mout_cmu_hsi1_bus_p,
1048 CLK_CON_MUX_MUX_CLKCMU_HSI1_BUS, 0, 3),
1049 MUX(CLK_MOUT_CMU_HSI1_PCIE, "mout_cmu_hsi1_pcie", mout_cmu_hsi1_pcie_p,
1050 CLK_CON_MUX_MUX_CLKCMU_HSI1_PCIE, 0, 1),
1051 MUX(CLK_MOUT_CMU_HSI2_BUS, "mout_cmu_hsi2_bus", mout_cmu_hsi2_bus_p,
1052 CLK_CON_MUX_MUX_CLKCMU_HSI2_BUS, 0, 3),
1053 MUX(CLK_MOUT_CMU_HSI2_MMC_CARD, "mout_cmu_hsi2_mmc_card",
1054 mout_cmu_hsi2_mmc_card_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_MMC_CARD,
1055 0, 2),
1056 MUX(CLK_MOUT_CMU_HSI2_PCIE, "mout_cmu_hsi2_pcie", mout_cmu_hsi2_pcie0_p,
1057 CLK_CON_MUX_MUX_CLKCMU_HSI2_PCIE, 0, 1),
1058 MUX(CLK_MOUT_CMU_HSI2_UFS_EMBD, "mout_cmu_hsi2_ufs_embd",
1059 mout_cmu_hsi2_ufs_embd_p, CLK_CON_MUX_MUX_CLKCMU_HSI2_UFS_EMBD,
1060 0, 2),
1061 MUX(CLK_MOUT_CMU_IPP_BUS, "mout_cmu_ipp_bus", mout_cmu_ipp_bus_p,
1062 CLK_CON_MUX_MUX_CLKCMU_IPP_BUS, 0, 3),
1063 MUX(CLK_MOUT_CMU_ITP_BUS, "mout_cmu_itp_bus", mout_cmu_itp_bus_p,
1064 CLK_CON_MUX_MUX_CLKCMU_ITP_BUS, 0, 3),
1065 MUX(CLK_MOUT_CMU_MCSC_ITSC, "mout_cmu_mcsc_itsc", mout_cmu_mcsc_itsc_p,
1066 CLK_CON_MUX_MUX_CLKCMU_MCSC_ITSC, 0, 3),
1067 MUX(CLK_MOUT_CMU_MCSC_MCSC, "mout_cmu_mcsc_mcsc", mout_cmu_mcsc_mcsc_p,
1068 CLK_CON_MUX_MUX_CLKCMU_MCSC_MCSC, 0, 3),
1069 MUX(CLK_MOUT_CMU_MFC_MFC, "mout_cmu_mfc_mfc", mout_cmu_mfc_mfc_p,
1070 CLK_CON_MUX_MUX_CLKCMU_MFC_MFC, 0, 3),
1071 MUX(CLK_MOUT_CMU_MIF_BUSP, "mout_cmu_mif_busp", mout_cmu_mif_busp_p,
1072 CLK_CON_MUX_MUX_CLKCMU_MIF_BUSP, 0, 2),
1073 MUX(CLK_MOUT_CMU_MIF_SWITCH, "mout_cmu_mif_switch",
1074 mout_cmu_mif_switch_p, CLK_CON_MUX_MUX_CLKCMU_MIF_SWITCH, 0, 3),
1075 MUX(CLK_MOUT_CMU_MISC_BUS, "mout_cmu_misc_bus", mout_cmu_misc_bus_p,
1076 CLK_CON_MUX_MUX_CLKCMU_MISC_BUS, 0, 2),
1077 MUX(CLK_MOUT_CMU_MISC_SSS, "mout_cmu_misc_sss", mout_cmu_misc_sss_p,
1078 CLK_CON_MUX_MUX_CLKCMU_MISC_SSS, 0, 2),
1079 MUX(CLK_MOUT_CMU_PDP_BUS, "mout_cmu_pdp_bus", mout_cmu_pdp_bus_p,
1080 CLK_CON_MUX_MUX_CLKCMU_PDP_BUS, 0, 3),
1081 MUX(CLK_MOUT_CMU_PDP_VRA, "mout_cmu_pdp_vra", mout_cmu_pdp_vra_p,
1082 CLK_CON_MUX_MUX_CLKCMU_PDP_VRA, 0, 3),
1083 MUX(CLK_MOUT_CMU_PERIC0_BUS, "mout_cmu_peric0_bus",
1084 mout_cmu_peric0_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC0_BUS, 0, 2),
1085 MUX(CLK_MOUT_CMU_PERIC0_IP, "mout_cmu_peric0_ip", mout_cmu_peric0_ip_p,
1086 CLK_CON_MUX_MUX_CLKCMU_PERIC0_IP, 0, 2),
1087 MUX(CLK_MOUT_CMU_PERIC1_BUS, "mout_cmu_peric1_bus",
1088 mout_cmu_peric1_bus_p, CLK_CON_MUX_MUX_CLKCMU_PERIC1_BUS, 0, 2),
1089 MUX(CLK_MOUT_CMU_PERIC1_IP, "mout_cmu_peric1_ip", mout_cmu_peric1_ip_p,
1090 CLK_CON_MUX_MUX_CLKCMU_PERIC1_IP, 0, 2),
1091 MUX(CLK_MOUT_CMU_TNR_BUS, "mout_cmu_tnr_bus", mout_cmu_tnr_bus_p,
1092 CLK_CON_MUX_MUX_CLKCMU_TNR_BUS, 0, 3),
1093 MUX(CLK_MOUT_CMU_TOP_BOOST_OPTION1, "mout_cmu_top_boost_option1",
1094 mout_cmu_top_boost_option1_p,
1095 CLK_CON_MUX_MUX_CLKCMU_TOP_BOOST_OPTION1, 0, 1),
1096 MUX(CLK_MOUT_CMU_TOP_CMUREF, "mout_cmu_top_cmuref",
1097 mout_cmu_top_cmuref_p, CLK_CON_MUX_MUX_CLKCMU_TOP_CMUREF, 0, 2),
1098 MUX(CLK_MOUT_CMU_TPU_BUS, "mout_cmu_tpu_bus", mout_cmu_tpu_bus_p,
1099 CLK_CON_MUX_MUX_CLKCMU_TPU_BUS, 0, 3),
1100 MUX(CLK_MOUT_CMU_TPU_TPU, "mout_cmu_tpu_tpu", mout_cmu_tpu_tpu_p,
1101 CLK_CON_MUX_MUX_CLKCMU_TPU_TPU, 0, 3),
1102 MUX(CLK_MOUT_CMU_TPU_TPUCTL, "mout_cmu_tpu_tpuctl",
1103 mout_cmu_tpu_tpuctl_p, CLK_CON_MUX_MUX_CLKCMU_TPU_TPUCTL, 0, 3),
1104 MUX(CLK_MOUT_CMU_TPU_UART, "mout_cmu_tpu_uart", mout_cmu_tpu_uart_p,
1105 CLK_CON_MUX_MUX_CLKCMU_TPU_UART, 0, 2),
1106 MUX(CLK_MOUT_CMU_CMUREF, "mout_cmu_cmuref", mout_cmu_cmuref_p,
1107 CLK_CON_MUX_MUX_CMU_CMUREF, 0, 1),
1108 };
1109
1110 static const struct samsung_div_clock top_div_clks[] __initconst = {
1111 DIV(CLK_DOUT_CMU_BO_BUS, "dout_cmu_bo_bus", "gout_cmu_bo_bus",
1112 CLK_CON_DIV_CLKCMU_BO_BUS, 0, 4),
1113 DIV(CLK_DOUT_CMU_BUS0_BUS, "dout_cmu_bus0_bus", "gout_cmu_bus0_bus",
1114 CLK_CON_DIV_CLKCMU_BUS0_BUS, 0, 4),
1115 DIV(CLK_DOUT_CMU_BUS1_BUS, "dout_cmu_bus1_bus", "gout_cmu_bus1_bus",
1116 CLK_CON_DIV_CLKCMU_BUS1_BUS, 0, 4),
1117 DIV(CLK_DOUT_CMU_BUS2_BUS, "dout_cmu_bus2_bus", "gout_cmu_bus2_bus",
1118 CLK_CON_DIV_CLKCMU_BUS2_BUS, 0, 4),
1119 DIV(CLK_DOUT_CMU_CIS_CLK0, "dout_cmu_cis_clk0", "gout_cmu_cis_clk0",
1120 CLK_CON_DIV_CLKCMU_CIS_CLK0, 0, 5),
1121 DIV(CLK_DOUT_CMU_CIS_CLK1, "dout_cmu_cis_clk1", "gout_cmu_cis_clk1",
1122 CLK_CON_DIV_CLKCMU_CIS_CLK1, 0, 5),
1123 DIV(CLK_DOUT_CMU_CIS_CLK2, "dout_cmu_cis_clk2", "gout_cmu_cis_clk2",
1124 CLK_CON_DIV_CLKCMU_CIS_CLK2, 0, 5),
1125 DIV(CLK_DOUT_CMU_CIS_CLK3, "dout_cmu_cis_clk3", "gout_cmu_cis_clk3",
1126 CLK_CON_DIV_CLKCMU_CIS_CLK3, 0, 5),
1127 DIV(CLK_DOUT_CMU_CIS_CLK4, "dout_cmu_cis_clk4", "gout_cmu_cis_clk4",
1128 CLK_CON_DIV_CLKCMU_CIS_CLK4, 0, 5),
1129 DIV(CLK_DOUT_CMU_CIS_CLK5, "dout_cmu_cis_clk5", "gout_cmu_cis_clk5",
1130 CLK_CON_DIV_CLKCMU_CIS_CLK5, 0, 5),
1131 DIV(CLK_DOUT_CMU_CIS_CLK6, "dout_cmu_cis_clk6", "gout_cmu_cis_clk6",
1132 CLK_CON_DIV_CLKCMU_CIS_CLK6, 0, 5),
1133 DIV(CLK_DOUT_CMU_CIS_CLK7, "dout_cmu_cis_clk7", "gout_cmu_cis_clk7",
1134 CLK_CON_DIV_CLKCMU_CIS_CLK7, 0, 5),
1135 DIV(CLK_DOUT_CMU_CORE_BUS, "dout_cmu_core_bus", "gout_cmu_core_bus",
1136 CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
1137 DIV(CLK_DOUT_CMU_CPUCL0_DBG, "dout_cmu_cpucl0_dbg",
1138 "gout_cmu_cpucl0_dbg", CLK_CON_DIV_CLKCMU_CPUCL0_DBG, 0, 4),
1139 DIV(CLK_DOUT_CMU_CPUCL0_SWITCH, "dout_cmu_cpucl0_switch",
1140 "gout_cmu_cpucl0_switch", CLK_CON_DIV_CLKCMU_CPUCL0_SWITCH, 0, 3),
1141 DIV(CLK_DOUT_CMU_CPUCL1_SWITCH, "dout_cmu_cpucl1_switch",
1142 "gout_cmu_cpucl1_switch", CLK_CON_DIV_CLKCMU_CPUCL1_SWITCH, 0, 3),
1143 DIV(CLK_DOUT_CMU_CPUCL2_SWITCH, "dout_cmu_cpucl2_switch",
1144 "gout_cmu_cpucl2_switch", CLK_CON_DIV_CLKCMU_CPUCL2_SWITCH, 0, 3),
1145 DIV(CLK_DOUT_CMU_CSIS_BUS, "dout_cmu_csis_bus", "gout_cmu_csis_bus",
1146 CLK_CON_DIV_CLKCMU_CSIS_BUS, 0, 4),
1147 DIV(CLK_DOUT_CMU_DISP_BUS, "dout_cmu_disp_bus", "gout_cmu_disp_bus",
1148 CLK_CON_DIV_CLKCMU_DISP_BUS, 0, 4),
1149 DIV(CLK_DOUT_CMU_DNS_BUS, "dout_cmu_dns_bus", "gout_cmu_dns_bus",
1150 CLK_CON_DIV_CLKCMU_DNS_BUS, 0, 4),
1151 DIV(CLK_DOUT_CMU_DPU_BUS, "dout_cmu_dpu_bus", "gout_cmu_dpu_bus",
1152 CLK_CON_DIV_CLKCMU_DPU_BUS, 0, 4),
1153 DIV(CLK_DOUT_CMU_EH_BUS, "dout_cmu_eh_bus", "gout_cmu_eh_bus",
1154 CLK_CON_DIV_CLKCMU_EH_BUS, 0, 4),
1155 DIV(CLK_DOUT_CMU_G2D_G2D, "dout_cmu_g2d_g2d", "gout_cmu_g2d_g2d",
1156 CLK_CON_DIV_CLKCMU_G2D_G2D, 0, 4),
1157 DIV(CLK_DOUT_CMU_G2D_MSCL, "dout_cmu_g2d_mscl", "gout_cmu_g2d_mscl",
1158 CLK_CON_DIV_CLKCMU_G2D_MSCL, 0, 4),
1159 DIV(CLK_DOUT_CMU_G3AA_G3AA, "dout_cmu_g3aa_g3aa", "gout_cmu_g3aa_g3aa",
1160 CLK_CON_DIV_CLKCMU_G3AA_G3AA, 0, 4),
1161 DIV(CLK_DOUT_CMU_G3D_BUSD, "dout_cmu_g3d_busd", "gout_cmu_g3d_busd",
1162 CLK_CON_DIV_CLKCMU_G3D_BUSD, 0, 4),
1163 DIV(CLK_DOUT_CMU_G3D_GLB, "dout_cmu_g3d_glb", "gout_cmu_g3d_glb",
1164 CLK_CON_DIV_CLKCMU_G3D_GLB, 0, 4),
1165 DIV(CLK_DOUT_CMU_G3D_SWITCH, "dout_cmu_g3d_switch",
1166 "gout_cmu_g3d_switch", CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3),
1167 DIV(CLK_DOUT_CMU_GDC_GDC0, "dout_cmu_gdc_gdc0", "gout_cmu_gdc_gdc0",
1168 CLK_CON_DIV_CLKCMU_GDC_GDC0, 0, 4),
1169 DIV(CLK_DOUT_CMU_GDC_GDC1, "dout_cmu_gdc_gdc1", "gout_cmu_gdc_gdc1",
1170 CLK_CON_DIV_CLKCMU_GDC_GDC1, 0, 4),
1171 DIV(CLK_DOUT_CMU_GDC_SCSC, "dout_cmu_gdc_scsc", "gout_cmu_gdc_scsc",
1172 CLK_CON_DIV_CLKCMU_GDC_SCSC, 0, 4),
1173 DIV(CLK_DOUT_CMU_CMU_HPM, "dout_cmu_hpm", "gout_cmu_hpm",
1174 CLK_CON_DIV_CLKCMU_HPM, 0, 2),
1175 DIV(CLK_DOUT_CMU_HSI0_BUS, "dout_cmu_hsi0_bus", "gout_cmu_hsi0_bus",
1176 CLK_CON_DIV_CLKCMU_HSI0_BUS, 0, 4),
1177 DIV(CLK_DOUT_CMU_HSI0_DPGTC, "dout_cmu_hsi0_dpgtc",
1178 "gout_cmu_hsi0_dpgtc", CLK_CON_DIV_CLKCMU_HSI0_DPGTC, 0, 4),
1179 DIV(CLK_DOUT_CMU_HSI0_USB31DRD, "dout_cmu_hsi0_usb31drd",
1180 "gout_cmu_hsi0_usb31drd", CLK_CON_DIV_CLKCMU_HSI0_USB31DRD, 0, 5),
1181 DIV(CLK_DOUT_CMU_HSI1_BUS, "dout_cmu_hsi1_bus", "gout_cmu_hsi1_bus",
1182 CLK_CON_DIV_CLKCMU_HSI1_BUS, 0, 4),
1183 DIV(CLK_DOUT_CMU_HSI1_PCIE, "dout_cmu_hsi1_pcie", "gout_cmu_hsi1_pcie",
1184 CLK_CON_DIV_CLKCMU_HSI1_PCIE, 0, 3),
1185 DIV(CLK_DOUT_CMU_HSI2_BUS, "dout_cmu_hsi2_bus", "gout_cmu_hsi2_bus",
1186 CLK_CON_DIV_CLKCMU_HSI2_BUS, 0, 4),
1187 DIV(CLK_DOUT_CMU_HSI2_MMC_CARD, "dout_cmu_hsi2_mmc_card",
1188 "gout_cmu_hsi2_mmc_card", CLK_CON_DIV_CLKCMU_HSI2_MMC_CARD, 0, 9),
1189 DIV(CLK_DOUT_CMU_HSI2_PCIE, "dout_cmu_hsi2_pcie", "gout_cmu_hsi2_pcie",
1190 CLK_CON_DIV_CLKCMU_HSI2_PCIE, 0, 3),
1191 DIV(CLK_DOUT_CMU_HSI2_UFS_EMBD, "dout_cmu_hsi2_ufs_embd",
1192 "gout_cmu_hsi2_ufs_embd", CLK_CON_DIV_CLKCMU_HSI2_UFS_EMBD, 0, 4),
1193 DIV(CLK_DOUT_CMU_IPP_BUS, "dout_cmu_ipp_bus", "gout_cmu_ipp_bus",
1194 CLK_CON_DIV_CLKCMU_IPP_BUS, 0, 4),
1195 DIV(CLK_DOUT_CMU_ITP_BUS, "dout_cmu_itp_bus", "gout_cmu_itp_bus",
1196 CLK_CON_DIV_CLKCMU_ITP_BUS, 0, 4),
1197 DIV(CLK_DOUT_CMU_MCSC_ITSC, "dout_cmu_mcsc_itsc", "gout_cmu_mcsc_itsc",
1198 CLK_CON_DIV_CLKCMU_MCSC_ITSC, 0, 4),
1199 DIV(CLK_DOUT_CMU_MCSC_MCSC, "dout_cmu_mcsc_mcsc", "gout_cmu_mcsc_mcsc",
1200 CLK_CON_DIV_CLKCMU_MCSC_MCSC, 0, 4),
1201 DIV(CLK_DOUT_CMU_MFC_MFC, "dout_cmu_mfc_mfc", "gout_cmu_mfc_mfc",
1202 CLK_CON_DIV_CLKCMU_MFC_MFC, 0, 4),
1203 DIV(CLK_DOUT_CMU_MIF_BUSP, "dout_cmu_mif_busp", "gout_cmu_mif_busp",
1204 CLK_CON_DIV_CLKCMU_MIF_BUSP, 0, 4),
1205 DIV(CLK_DOUT_CMU_MISC_BUS, "dout_cmu_misc_bus", "gout_cmu_misc_bus",
1206 CLK_CON_DIV_CLKCMU_MISC_BUS, 0, 4),
1207 DIV(CLK_DOUT_CMU_MISC_SSS, "dout_cmu_misc_sss", "gout_cmu_misc_sss",
1208 CLK_CON_DIV_CLKCMU_MISC_SSS, 0, 4),
1209 DIV(CLK_DOUT_CMU_PDP_BUS, "dout_cmu_pdp_bus", "gout_cmu_pdp_bus",
1210 CLK_CON_DIV_CLKCMU_PDP_BUS, 0, 4),
1211 DIV(CLK_DOUT_CMU_PDP_VRA, "dout_cmu_pdp_vra", "gout_cmu_pdp_vra",
1212 CLK_CON_DIV_CLKCMU_PDP_VRA, 0, 4),
1213 DIV(CLK_DOUT_CMU_PERIC0_BUS, "dout_cmu_peric0_bus",
1214 "gout_cmu_peric0_bus", CLK_CON_DIV_CLKCMU_PERIC0_BUS, 0, 4),
1215 DIV(CLK_DOUT_CMU_PERIC0_IP, "dout_cmu_peric0_ip", "gout_cmu_peric0_ip",
1216 CLK_CON_DIV_CLKCMU_PERIC0_IP, 0, 4),
1217 DIV(CLK_DOUT_CMU_PERIC1_BUS, "dout_cmu_peric1_bus",
1218 "gout_cmu_peric1_bus", CLK_CON_DIV_CLKCMU_PERIC1_BUS, 0, 4),
1219 DIV(CLK_DOUT_CMU_PERIC1_IP, "dout_cmu_peric1_ip", "gout_cmu_peric1_ip",
1220 CLK_CON_DIV_CLKCMU_PERIC1_IP, 0, 4),
1221 DIV(CLK_DOUT_CMU_TNR_BUS, "dout_cmu_tnr_bus", "gout_cmu_tnr_bus",
1222 CLK_CON_DIV_CLKCMU_TNR_BUS, 0, 4),
1223 DIV(CLK_DOUT_CMU_TPU_BUS, "dout_cmu_tpu_bus", "gout_cmu_tpu_bus",
1224 CLK_CON_DIV_CLKCMU_TPU_BUS, 0, 4),
1225 DIV(CLK_DOUT_CMU_TPU_TPU, "dout_cmu_tpu_tpu", "gout_cmu_tpu_tpu",
1226 CLK_CON_DIV_CLKCMU_TPU_TPU, 0, 4),
1227 DIV(CLK_DOUT_CMU_TPU_TPUCTL, "dout_cmu_tpu_tpuctl",
1228 "gout_cmu_tpu_tpuctl", CLK_CON_DIV_CLKCMU_TPU_TPUCTL, 0, 4),
1229 DIV(CLK_DOUT_CMU_TPU_UART, "dout_cmu_tpu_uart", "gout_cmu_tpu_uart",
1230 CLK_CON_DIV_CLKCMU_TPU_UART, 0, 4),
1231 DIV(CLK_DOUT_CMU_CMU_BOOST, "dout_cmu_cmu_boost", "gout_cmu_cmu_boost",
1232 CLK_CON_DIV_DIV_CLKCMU_CMU_BOOST, 0, 2),
1233 DIV(CLK_DOUT_CMU_CMU_CMUREF, "dout_cmu_cmuref", "gout_cmu_cmuref",
1234 CLK_CON_DIV_DIV_CLK_CMU_CMUREF, 0, 2),
1235 DIV(CLK_DOUT_CMU_SHARED0_DIV2, "dout_cmu_shared0_div2",
1236 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
1237 DIV(CLK_DOUT_CMU_SHARED0_DIV3, "dout_cmu_shared0_div3",
1238 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
1239 DIV(CLK_DOUT_CMU_SHARED0_DIV4, "dout_cmu_shared0_div4",
1240 "dout_cmu_shared0_div2", CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
1241 DIV(CLK_DOUT_CMU_SHARED0_DIV5, "dout_cmu_shared0_div5",
1242 "mout_pll_shared0", CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
1243 DIV(CLK_DOUT_CMU_SHARED1_DIV2, "dout_cmu_shared1_div2",
1244 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
1245 DIV(CLK_DOUT_CMU_SHARED1_DIV3, "dout_cmu_shared1_div3",
1246 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
1247 DIV(CLK_DOUT_CMU_SHARED1_DIV4, "dout_cmu_shared1_div4",
1248 "mout_pll_shared1", CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
1249 DIV(CLK_DOUT_CMU_SHARED2_DIV2, "dout_cmu_shared2_div2",
1250 "mout_pll_shared2", CLK_CON_DIV_PLL_SHARED2_DIV2, 0, 1),
1251 DIV(CLK_DOUT_CMU_SHARED3_DIV2, "dout_cmu_shared3_div2",
1252 "mout_pll_shared3", CLK_CON_DIV_PLL_SHARED3_DIV2, 0, 1),
1253 };
1254
1255 static const struct samsung_fixed_factor_clock top_ffactor_clks[] __initconst = {
1256 FFACTOR(CLK_DOUT_CMU_HSI0_USBDPDBG, "dout_cmu_hsi0_usbdpdbg",
1257 "gout_cmu_hsi0_usbdpdbg", 1, 4, 0),
1258 FFACTOR(CLK_DOUT_CMU_OTP, "dout_cmu_otp", "oscclk", 1, 8, 0),
1259 };
1260
1261 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
1262 GATE(CLK_GOUT_CMU_BUS0_BOOST, "gout_cmu_bus0_boost",
1263 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS0_BOOST, 21, 0, 0),
1264 GATE(CLK_GOUT_CMU_BUS1_BOOST, "gout_cmu_bus1_boost",
1265 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS1_BOOST, 21, 0, 0),
1266 GATE(CLK_GOUT_CMU_BUS2_BOOST, "gout_cmu_bus2_boost",
1267 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_BUS2_BOOST, 21, 0, 0),
1268 GATE(CLK_GOUT_CMU_CORE_BOOST, "gout_cmu_core_boost",
1269 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CORE_BOOST, 21, 0, 0),
1270 GATE(CLK_GOUT_CMU_CPUCL0_BOOST, "gout_cmu_cpucl0_boost",
1271 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL0_BOOST,
1272 21, 0, 0),
1273 GATE(CLK_GOUT_CMU_CPUCL1_BOOST, "gout_cmu_cpucl1_boost",
1274 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL1_BOOST,
1275 21, 0, 0),
1276 GATE(CLK_GOUT_CMU_CPUCL2_BOOST, "gout_cmu_cpucl2_boost",
1277 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_CPUCL2_BOOST,
1278 21, 0, 0),
1279 GATE(CLK_GOUT_CMU_MIF_BOOST, "gout_cmu_mif_boost",
1280 "mout_cmu_boost_option1", CLK_CON_GAT_CLKCMU_MIF_BOOST,
1281 21, 0, 0),
1282 GATE(CLK_GOUT_CMU_MIF_SWITCH, "gout_cmu_mif_switch",
1283 "mout_cmu_mif_switch", CLK_CON_GAT_CLKCMU_MIF_SWITCH, 21, 0, 0),
1284 GATE(CLK_GOUT_CMU_BO_BUS, "gout_cmu_bo_bus", "mout_cmu_bo_bus",
1285 CLK_CON_GAT_GATE_CLKCMU_BO_BUS, 21, 0, 0),
1286 GATE(CLK_GOUT_CMU_BUS0_BUS, "gout_cmu_bus0_bus", "mout_cmu_bus0_bus",
1287 CLK_CON_GAT_GATE_CLKCMU_BUS0_BUS, 21, 0, 0),
1288 GATE(CLK_GOUT_CMU_BUS1_BUS, "gout_cmu_bus1_bus", "mout_cmu_bus1_bus",
1289 CLK_CON_GAT_GATE_CLKCMU_BUS1_BUS, 21, 0, 0),
1290 GATE(CLK_GOUT_CMU_BUS2_BUS, "gout_cmu_bus2_bus", "mout_cmu_bus2_bus",
1291 CLK_CON_GAT_GATE_CLKCMU_BUS2_BUS, 21, 0, 0),
1292 GATE(CLK_GOUT_CMU_CIS_CLK0, "gout_cmu_cis_clk0", "mout_cmu_cis_clk0",
1293 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK0, 21, 0, 0),
1294 GATE(CLK_GOUT_CMU_CIS_CLK1, "gout_cmu_cis_clk1", "mout_cmu_cis_clk1",
1295 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK1, 21, 0, 0),
1296 GATE(CLK_GOUT_CMU_CIS_CLK2, "gout_cmu_cis_clk2", "mout_cmu_cis_clk2",
1297 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK2, 21, 0, 0),
1298 GATE(CLK_GOUT_CMU_CIS_CLK3, "gout_cmu_cis_clk3", "mout_cmu_cis_clk3",
1299 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK3, 21, 0, 0),
1300 GATE(CLK_GOUT_CMU_CIS_CLK4, "gout_cmu_cis_clk4", "mout_cmu_cis_clk4",
1301 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK4, 21, 0, 0),
1302 GATE(CLK_GOUT_CMU_CIS_CLK5, "gout_cmu_cis_clk5", "mout_cmu_cis_clk5",
1303 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK5, 21, 0, 0),
1304 GATE(CLK_GOUT_CMU_CIS_CLK6, "gout_cmu_cis_clk6", "mout_cmu_cis_clk6",
1305 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK6, 21, 0, 0),
1306 GATE(CLK_GOUT_CMU_CIS_CLK7, "gout_cmu_cis_clk7", "mout_cmu_cis_clk7",
1307 CLK_CON_GAT_GATE_CLKCMU_CIS_CLK7, 21, 0, 0),
1308 GATE(CLK_GOUT_CMU_CMU_BOOST, "gout_cmu_cmu_boost", "mout_cmu_cmu_boost",
1309 CLK_CON_GAT_GATE_CLKCMU_CMU_BOOST, 21, 0, 0),
1310 GATE(CLK_GOUT_CMU_CORE_BUS, "gout_cmu_core_bus", "mout_cmu_core_bus",
1311 CLK_CON_GAT_GATE_CLKCMU_CORE_BUS, 21, 0, 0),
1312 GATE(CLK_GOUT_CMU_CPUCL0_DBG, "gout_cmu_cpucl0_dbg",
1313 "mout_cmu_cpucl0_dbg", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_DBG_BUS,
1314 21, 0, 0),
1315 GATE(CLK_GOUT_CMU_CPUCL0_SWITCH, "gout_cmu_cpucl0_switch",
1316 "mout_cmu_cpucl0_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL0_SWITCH,
1317 21, 0, 0),
1318 GATE(CLK_GOUT_CMU_CPUCL1_SWITCH, "gout_cmu_cpucl1_switch",
1319 "mout_cmu_cpucl1_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL1_SWITCH,
1320 21, 0, 0),
1321 GATE(CLK_GOUT_CMU_CPUCL2_SWITCH, "gout_cmu_cpucl2_switch",
1322 "mout_cmu_cpucl2_switch", CLK_CON_GAT_GATE_CLKCMU_CPUCL2_SWITCH,
1323 21, 0, 0),
1324 GATE(CLK_GOUT_CMU_CSIS_BUS, "gout_cmu_csis_bus", "mout_cmu_csis_bus",
1325 CLK_CON_GAT_GATE_CLKCMU_CSIS_BUS, 21, 0, 0),
1326 GATE(CLK_GOUT_CMU_DISP_BUS, "gout_cmu_disp_bus", "mout_cmu_disp_bus",
1327 CLK_CON_GAT_GATE_CLKCMU_DISP_BUS, 21, 0, 0),
1328 GATE(CLK_GOUT_CMU_DNS_BUS, "gout_cmu_dns_bus", "mout_cmu_dns_bus",
1329 CLK_CON_GAT_GATE_CLKCMU_DNS_BUS, 21, 0, 0),
1330 GATE(CLK_GOUT_CMU_DPU_BUS, "gout_cmu_dpu_bus", "mout_cmu_dpu_bus",
1331 CLK_CON_GAT_GATE_CLKCMU_DPU_BUS, 21, 0, 0),
1332 GATE(CLK_GOUT_CMU_EH_BUS, "gout_cmu_eh_bus", "mout_cmu_eh_bus",
1333 CLK_CON_GAT_GATE_CLKCMU_EH_BUS, 21, 0, 0),
1334 GATE(CLK_GOUT_CMU_G2D_G2D, "gout_cmu_g2d_g2d", "mout_cmu_g2d_g2d",
1335 CLK_CON_GAT_GATE_CLKCMU_G2D_G2D, 21, 0, 0),
1336 GATE(CLK_GOUT_CMU_G2D_MSCL, "gout_cmu_g2d_mscl", "mout_cmu_g2d_mscl",
1337 CLK_CON_GAT_GATE_CLKCMU_G2D_MSCL, 21, 0, 0),
1338 GATE(CLK_GOUT_CMU_G3AA_G3AA, "gout_cmu_g3aa_g3aa", "mout_cmu_g3aa_g3aa",
1339 CLK_CON_MUX_MUX_CLKCMU_G3AA_G3AA, 21, 0, 0),
1340 GATE(CLK_GOUT_CMU_G3D_BUSD, "gout_cmu_g3d_busd", "mout_cmu_g3d_busd",
1341 CLK_CON_GAT_GATE_CLKCMU_G3D_BUSD, 21, 0, 0),
1342 GATE(CLK_GOUT_CMU_G3D_GLB, "gout_cmu_g3d_glb", "mout_cmu_g3d_glb",
1343 CLK_CON_GAT_GATE_CLKCMU_G3D_GLB, 21, 0, 0),
1344 GATE(CLK_GOUT_CMU_G3D_SWITCH, "gout_cmu_g3d_switch",
1345 "mout_cmu_g3d_switch", CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH,
1346 21, 0, 0),
1347 GATE(CLK_GOUT_CMU_GDC_GDC0, "gout_cmu_gdc_gdc0", "mout_cmu_gdc_gdc0",
1348 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC0, 21, 0, 0),
1349 GATE(CLK_GOUT_CMU_GDC_GDC1, "gout_cmu_gdc_gdc1", "mout_cmu_gdc_gdc1",
1350 CLK_CON_GAT_GATE_CLKCMU_GDC_GDC1, 21, 0, 0),
1351 GATE(CLK_GOUT_CMU_GDC_SCSC, "gout_cmu_gdc_scsc", "mout_cmu_gdc_scsc",
1352 CLK_CON_GAT_GATE_CLKCMU_GDC_SCSC, 21, 0, 0),
1353 GATE(CLK_GOUT_CMU_HPM, "gout_cmu_hpm", "mout_cmu_hpm",
1354 CLK_CON_GAT_GATE_CLKCMU_HPM, 21, 0, 0),
1355 GATE(CLK_GOUT_CMU_HSI0_BUS, "gout_cmu_hsi0_bus", "mout_cmu_hsi0_bus",
1356 CLK_CON_GAT_GATE_CLKCMU_HSI0_BUS, 21, 0, 0),
1357 GATE(CLK_GOUT_CMU_HSI0_DPGTC, "gout_cmu_hsi0_dpgtc",
1358 "mout_cmu_hsi0_dpgtc", CLK_CON_GAT_GATE_CLKCMU_HSI0_DPGTC,
1359 21, 0, 0),
1360 GATE(CLK_GOUT_CMU_HSI0_USB31DRD, "gout_cmu_hsi0_usb31drd",
1361 "mout_cmu_hsi0_usb31drd", CLK_CON_GAT_GATE_CLKCMU_HSI0_USB31DRD,
1362 21, 0, 0),
1363 GATE(CLK_GOUT_CMU_HSI0_USBDPDBG, "gout_cmu_hsi0_usbdpdbg",
1364 "mout_cmu_hsi0_usbdpdbg", CLK_CON_GAT_GATE_CLKCMU_HSI0_USBDPDBG,
1365 21, 0, 0),
1366 GATE(CLK_GOUT_CMU_HSI1_BUS, "gout_cmu_hsi1_bus", "mout_cmu_hsi1_bus",
1367 CLK_CON_GAT_GATE_CLKCMU_HSI1_BUS, 21, 0, 0),
1368 GATE(CLK_GOUT_CMU_HSI1_PCIE, "gout_cmu_hsi1_pcie", "mout_cmu_hsi1_pcie",
1369 CLK_CON_GAT_GATE_CLKCMU_HSI1_PCIE, 21, 0, 0),
1370 GATE(CLK_GOUT_CMU_HSI2_BUS, "gout_cmu_hsi2_bus", "mout_cmu_hsi2_bus",
1371 CLK_CON_GAT_GATE_CLKCMU_HSI2_BUS, 21, 0, 0),
1372 GATE(CLK_GOUT_CMU_HSI2_MMC_CARD, "gout_cmu_hsi2_mmc_card",
1373 "mout_cmu_hsi2_mmc_card", CLK_CON_GAT_GATE_CLKCMU_HSI2_MMCCARD,
1374 21, 0, 0),
1375 GATE(CLK_GOUT_CMU_HSI2_PCIE, "gout_cmu_hsi2_pcie", "mout_cmu_hsi2_pcie",
1376 CLK_CON_GAT_GATE_CLKCMU_HSI2_PCIE, 21, 0, 0),
1377 GATE(CLK_GOUT_CMU_HSI2_UFS_EMBD, "gout_cmu_hsi2_ufs_embd",
1378 "mout_cmu_hsi2_ufs_embd", CLK_CON_GAT_GATE_CLKCMU_HSI2_UFS_EMBD,
1379 21, 0, 0),
1380 GATE(CLK_GOUT_CMU_IPP_BUS, "gout_cmu_ipp_bus", "mout_cmu_ipp_bus",
1381 CLK_CON_GAT_GATE_CLKCMU_IPP_BUS, 21, 0, 0),
1382 GATE(CLK_GOUT_CMU_ITP_BUS, "gout_cmu_itp_bus", "mout_cmu_itp_bus",
1383 CLK_CON_GAT_GATE_CLKCMU_ITP_BUS, 21, 0, 0),
1384 GATE(CLK_GOUT_CMU_MCSC_ITSC, "gout_cmu_mcsc_itsc", "mout_cmu_mcsc_itsc",
1385 CLK_CON_GAT_GATE_CLKCMU_MCSC_ITSC, 21, 0, 0),
1386 GATE(CLK_GOUT_CMU_MCSC_MCSC, "gout_cmu_mcsc_mcsc", "mout_cmu_mcsc_mcsc",
1387 CLK_CON_GAT_GATE_CLKCMU_MCSC_MCSC, 21, 0, 0),
1388 GATE(CLK_GOUT_CMU_MFC_MFC, "gout_cmu_mfc_mfc", "mout_cmu_mfc_mfc",
1389 CLK_CON_GAT_GATE_CLKCMU_MFC_MFC, 21, 0, 0),
1390 GATE(CLK_GOUT_CMU_MIF_BUSP, "gout_cmu_mif_busp", "mout_cmu_mif_busp",
1391 CLK_CON_GAT_GATE_CLKCMU_MIF_BUSP, 21, 0, 0),
1392 GATE(CLK_GOUT_CMU_MISC_BUS, "gout_cmu_misc_bus", "mout_cmu_misc_bus",
1393 CLK_CON_GAT_GATE_CLKCMU_MISC_BUS, 21, 0, 0),
1394 GATE(CLK_GOUT_CMU_MISC_SSS, "gout_cmu_misc_sss", "mout_cmu_misc_sss",
1395 CLK_CON_GAT_GATE_CLKCMU_MISC_SSS, 21, 0, 0),
1396 GATE(CLK_GOUT_CMU_PDP_BUS, "gout_cmu_pdp_bus", "mout_cmu_pdp_bus",
1397 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1398 GATE(CLK_GOUT_CMU_PDP_VRA, "gout_cmu_pdp_vra", "mout_cmu_pdp_vra",
1399 CLK_CON_GAT_GATE_CLKCMU_PDP_BUS, 21, 0, 0),
1400 GATE(CLK_GOUT_CMU_PERIC0_BUS, "gout_cmu_peric0_bus",
1401 "mout_cmu_peric0_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC0_BUS,
1402 21, 0, 0),
1403 GATE(CLK_GOUT_CMU_PERIC0_IP, "gout_cmu_peric0_ip", "mout_cmu_peric0_ip",
1404 CLK_CON_GAT_GATE_CLKCMU_PERIC0_IP, 21, 0, 0),
1405 GATE(CLK_GOUT_CMU_PERIC1_BUS, "gout_cmu_peric1_bus",
1406 "mout_cmu_peric1_bus", CLK_CON_GAT_GATE_CLKCMU_PERIC1_BUS,
1407 21, 0, 0),
1408 GATE(CLK_GOUT_CMU_PERIC1_IP, "gout_cmu_peric1_ip", "mout_cmu_peric1_ip",
1409 CLK_CON_GAT_GATE_CLKCMU_PERIC1_IP, 21, 0, 0),
1410 GATE(CLK_GOUT_CMU_TNR_BUS, "gout_cmu_tnr_bus", "mout_cmu_tnr_bus",
1411 CLK_CON_GAT_GATE_CLKCMU_TNR_BUS, 21, 0, 0),
1412 GATE(CLK_GOUT_CMU_TOP_CMUREF, "gout_cmu_top_cmuref",
1413 "mout_cmu_top_cmuref", CLK_CON_GAT_GATE_CLKCMU_TOP_CMUREF,
1414 21, 0, 0),
1415 GATE(CLK_GOUT_CMU_TPU_BUS, "gout_cmu_tpu_bus", "mout_cmu_tpu_bus",
1416 CLK_CON_GAT_GATE_CLKCMU_TPU_BUS, 21, 0, 0),
1417 GATE(CLK_GOUT_CMU_TPU_TPU, "gout_cmu_tpu_tpu", "mout_cmu_tpu_tpu",
1418 CLK_CON_GAT_GATE_CLKCMU_TPU_TPU, 21, 0, 0),
1419 GATE(CLK_GOUT_CMU_TPU_TPUCTL, "gout_cmu_tpu_tpuctl",
1420 "mout_cmu_tpu_tpuctl", CLK_CON_GAT_GATE_CLKCMU_TPU_TPUCTL,
1421 21, 0, 0),
1422 GATE(CLK_GOUT_CMU_TPU_UART, "gout_cmu_tpu_uart", "mout_cmu_tpu_uart",
1423 CLK_CON_GAT_GATE_CLKCMU_TPU_UART, 21, 0, 0),
1424 };
1425
1426 static const struct samsung_cmu_info top_cmu_info __initconst = {
1427 .pll_clks = top_pll_clks,
1428 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
1429 .mux_clks = top_mux_clks,
1430 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
1431 .div_clks = top_div_clks,
1432 .nr_div_clks = ARRAY_SIZE(top_div_clks),
1433 .fixed_factor_clks = top_ffactor_clks,
1434 .nr_fixed_factor_clks = ARRAY_SIZE(top_ffactor_clks),
1435 .gate_clks = top_gate_clks,
1436 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
1437 .nr_clk_ids = CLKS_NR_TOP,
1438 .clk_regs = top_clk_regs,
1439 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
1440 .auto_clock_gate = true,
1441 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
1442 .option_offset = CMU_CMU_TOP_CONTROLLER_OPTION,
1443 };
1444
gs101_cmu_top_init(struct device_node * np)1445 static void __init gs101_cmu_top_init(struct device_node *np)
1446 {
1447 exynos_arm64_register_cmu(NULL, np, &top_cmu_info);
1448 }
1449
1450 /* Register CMU_TOP early, as it's a dependency for other early domains */
1451 CLK_OF_DECLARE(gs101_cmu_top, "google,gs101-cmu-top",
1452 gs101_cmu_top_init);
1453
1454 /* ---- CMU_APM ------------------------------------------------------------- */
1455
1456 /* Register Offset definitions for CMU_APM (0x17400000) */
1457 #define APM_CMU_APM_CONTROLLER_OPTION 0x0800
1458 #define CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0 0x0810
1459 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNC 0x1000
1460 #define CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC 0x1004
1461 #define CLK_CON_DIV_DIV_CLK_APM_BOOST 0x1800
1462 #define CLK_CON_DIV_DIV_CLK_APM_USI0_UART 0x1804
1463 #define CLK_CON_DIV_DIV_CLK_APM_USI0_USI 0x1808
1464 #define CLK_CON_DIV_DIV_CLK_APM_USI1_UART 0x180c
1465 #define CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK 0x2000
1466 #define CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1 0x2004
1467 #define CLK_CON_GAT_CLK_CMU_BOOST_OPTION1 0x2008
1468 #define CLK_CON_GAT_CLK_CORE_BOOST_OPTION1 0x200c
1469 #define CLK_CON_GAT_GATE_CLKCMU_APM_FUNC 0x2010
1470 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK 0x2014
1471 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK 0x2018
1472 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK 0x201c
1473 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK 0x2020
1474 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK 0x2024
1475 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK 0x2028
1476 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK 0x202c
1477 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK 0x2030
1478 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK 0x2034
1479 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK 0x2038
1480 #define CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK 0x203c
1481 #define CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK 0x2040
1482 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK 0x2044
1483 #define CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK 0x2048
1484 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK 0x204c
1485 #define CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK 0x2050
1486 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK 0x2054
1487 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK 0x2058
1488 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK 0x205c
1489 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK 0x2060
1490 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK 0x2064
1491 #define CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK 0x2068
1492 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK 0x206c
1493 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK 0x2070
1494 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK 0x2074
1495 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK 0x207c
1496 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK 0x2080
1497 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK 0x2084
1498 #define CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK 0x2088
1499 #define CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK 0x208c
1500 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK 0x2090
1501 #define CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK 0x2094
1502 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK 0x2098
1503 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK 0x209c
1504 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK 0x20a0
1505 #define CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK 0x20a4
1506 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK 0x20a8
1507 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK 0x20ac
1508 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK 0x20b0
1509 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK 0x20b4
1510 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK 0x20b8
1511 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK 0x20bc
1512 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK 0x20c0
1513 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2 0x20c4
1514 #define CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK 0x20cc
1515 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK 0x20d0
1516 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK 0x20d4
1517 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK 0x20d8
1518 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK 0x20dc
1519 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK 0x20e0
1520 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK 0x20e4
1521 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK 0x20e8
1522 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK 0x20ec
1523 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK 0x20f0
1524 #define CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK 0x20f4
1525 #define CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK 0x20f8
1526 #define CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK 0x20fc
1527 #define PCH_CON_LHM_AXI_G_SWD_PCH 0x3000
1528 #define PCH_CON_LHM_AXI_P_AOCAPM_PCH 0x3004
1529 #define PCH_CON_LHM_AXI_P_APM_PCH 0x3008
1530 #define PCH_CON_LHS_AXI_D_APM_PCH 0x300c
1531 #define PCH_CON_LHS_AXI_G_DBGCORE_PCH 0x3010
1532 #define PCH_CON_LHS_AXI_G_SCAN2DRAM_PCH 0x3014
1533 #define QCH_CON_APBIF_GPIO_ALIVE_QCH 0x3018
1534 #define QCH_CON_APBIF_GPIO_FAR_ALIVE_QCH 0x301c
1535 #define QCH_CON_APBIF_PMU_ALIVE_QCH 0x3020
1536 #define QCH_CON_APBIF_RTC_QCH 0x3024
1537 #define QCH_CON_APBIF_TRTC_QCH 0x3028
1538 #define QCH_CON_APM_CMU_APM_QCH 0x302c
1539 #define QCH_CON_APM_USI0_UART_QCH 0x3030
1540 #define QCH_CON_APM_USI0_USI_QCH 0x3034
1541 #define QCH_CON_APM_USI1_UART_QCH 0x3038
1542 #define QCH_CON_D_TZPC_APM_QCH 0x303c
1543 #define QCH_CON_GPC_APM_QCH 0x3040
1544 #define QCH_CON_GREBEINTEGRATION_QCH_DBG 0x3044
1545 #define QCH_CON_GREBEINTEGRATION_QCH_GREBE 0x3048
1546 #define QCH_CON_INTMEM_QCH 0x304c
1547 #define QCH_CON_LHM_AXI_G_SWD_QCH 0x3050
1548 #define QCH_CON_LHM_AXI_P_AOCAPM_QCH 0x3054
1549 #define QCH_CON_LHM_AXI_P_APM_QCH 0x3058
1550 #define QCH_CON_LHS_AXI_D_APM_QCH 0x305c
1551 #define QCH_CON_LHS_AXI_G_DBGCORE_QCH 0x3060
1552 #define QCH_CON_LHS_AXI_G_SCAN2DRAM_QCH 0x3064
1553 #define QCH_CON_MAILBOX_APM_AOC_QCH 0x3068
1554 #define QCH_CON_MAILBOX_APM_AP_QCH 0x306c
1555 #define QCH_CON_MAILBOX_APM_GSA_QCH 0x3070
1556 #define QCH_CON_MAILBOX_APM_SWD_QCH 0x3078
1557 #define QCH_CON_MAILBOX_APM_TPU_QCH 0x307c
1558 #define QCH_CON_MAILBOX_AP_AOC_QCH 0x3080
1559 #define QCH_CON_MAILBOX_AP_DBGCORE_QCH 0x3084
1560 #define QCH_CON_PMU_INTR_GEN_QCH 0x3088
1561 #define QCH_CON_ROM_CRC32_HOST_QCH 0x308c
1562 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE 0x3090
1563 #define QCH_CON_RSTNSYNC_CLK_APM_BUS_QCH_GREBE_DBG 0x3094
1564 #define QCH_CON_SPEEDY_APM_QCH 0x3098
1565 #define QCH_CON_SPEEDY_SUB_APM_QCH 0x309c
1566 #define QCH_CON_SSMT_D_APM_QCH 0x30a0
1567 #define QCH_CON_SSMT_G_DBGCORE_QCH 0x30a4
1568 #define QCH_CON_SS_DBGCORE_QCH_DBG 0x30a8
1569 #define QCH_CON_SS_DBGCORE_QCH_GREBE 0x30ac
1570 #define QCH_CON_SYSMMU_D_APM_QCH 0x30b0
1571 #define QCH_CON_SYSREG_APM_QCH 0x30b8
1572 #define QCH_CON_UASC_APM_QCH 0x30bc
1573 #define QCH_CON_UASC_DBGCORE_QCH 0x30c0
1574 #define QCH_CON_UASC_G_SWD_QCH 0x30c4
1575 #define QCH_CON_UASC_P_AOCAPM_QCH 0x30c8
1576 #define QCH_CON_UASC_P_APM_QCH 0x30cc
1577 #define QCH_CON_WDT_APM_QCH 0x30d0
1578 #define QUEUE_CTRL_REG_BLK_APM_CMU_APM 0x3c00
1579
1580 static const unsigned long apm_clk_regs[] __initconst = {
1581 APM_CMU_APM_CONTROLLER_OPTION,
1582 CLKOUT_CON_BLK_APM_CMU_APM_CLKOUT0,
1583 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC,
1584 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC,
1585 CLK_CON_DIV_DIV_CLK_APM_BOOST,
1586 CLK_CON_DIV_DIV_CLK_APM_USI0_UART,
1587 CLK_CON_DIV_DIV_CLK_APM_USI0_USI,
1588 CLK_CON_DIV_DIV_CLK_APM_USI1_UART,
1589 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK,
1590 CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1,
1591 CLK_CON_GAT_CLK_CMU_BOOST_OPTION1,
1592 CLK_CON_GAT_CLK_CORE_BOOST_OPTION1,
1593 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC,
1594 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
1595 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
1596 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
1597 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK,
1598 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK,
1599 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
1600 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
1601 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
1602 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
1603 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
1604 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
1605 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK,
1606 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK,
1607 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
1608 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK,
1609 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK,
1610 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
1611 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
1612 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_APM_IPCLKPORT_I_CLK,
1613 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1614 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
1615 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
1616 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
1617 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
1618 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
1619 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
1620 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
1621 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
1622 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
1623 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
1624 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
1625 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
1626 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
1627 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1628 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_USI_IPCLKPORT_CLK,
1629 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
1630 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK,
1631 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
1632 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK,
1633 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK,
1634 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
1635 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
1636 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
1637 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
1638 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK,
1639 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK,
1640 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK,
1641 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
1642 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
1643 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK,
1644 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK,
1645 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
1646 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_PCLK,
1647 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK,
1648 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK,
1649 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK,
1650 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK,
1651 };
1652
1653 PNAME(mout_apm_func_p) = { "oscclk", "mout_apm_funcsrc",
1654 "pad_clk_apm", "oscclk" };
1655 PNAME(mout_apm_funcsrc_p) = { "pll_alv_div2_apm", "pll_alv_div4_apm",
1656 "pll_alv_div16_apm" };
1657
1658 static const struct samsung_fixed_rate_clock apm_fixed_clks[] __initconst = {
1659 FRATE(CLK_APM_PLL_DIV2_APM, "pll_alv_div2_apm", NULL, 0, 393216000),
1660 FRATE(CLK_APM_PLL_DIV4_APM, "pll_alv_div4_apm", NULL, 0, 196608000),
1661 FRATE(CLK_APM_PLL_DIV16_APM, "pll_alv_div16_apm", NULL, 0, 49152000),
1662 };
1663
1664 static const struct samsung_mux_clock apm_mux_clks[] __initconst = {
1665 MUX(CLK_MOUT_APM_FUNC, "mout_apm_func", mout_apm_func_p,
1666 CLK_CON_MUX_MUX_CLKCMU_APM_FUNC, 4, 1),
1667 MUX(CLK_MOUT_APM_FUNCSRC, "mout_apm_funcsrc", mout_apm_funcsrc_p,
1668 CLK_CON_MUX_MUX_CLKCMU_APM_FUNCSRC, 3, 1),
1669 };
1670
1671 static const struct samsung_div_clock apm_div_clks[] __initconst = {
1672 DIV(CLK_DOUT_APM_BOOST, "dout_apm_boost", "gout_apm_func",
1673 CLK_CON_DIV_DIV_CLK_APM_BOOST, 0, 1),
1674 DIV(CLK_DOUT_APM_USI0_UART, "dout_apm_usi0_uart", "gout_apm_func",
1675 CLK_CON_DIV_DIV_CLK_APM_USI0_UART, 0, 7),
1676 DIV(CLK_DOUT_APM_USI0_USI, "dout_apm_usi0_usi", "gout_apm_func",
1677 CLK_CON_DIV_DIV_CLK_APM_USI0_USI, 0, 7),
1678 DIV(CLK_DOUT_APM_USI1_UART, "dout_apm_usi1_uart", "gout_apm_func",
1679 CLK_CON_DIV_DIV_CLK_APM_USI1_UART, 0, 7),
1680 };
1681
1682 static const struct samsung_gate_clock apm_gate_clks[] __initconst = {
1683 GATE(CLK_GOUT_APM_APM_CMU_APM_PCLK,
1684 "gout_apm_apm_cmu_apm_pclk", "mout_apm_func",
1685 CLK_CON_GAT_CLK_BLK_APM_UID_APM_CMU_APM_IPCLKPORT_PCLK, 21, 0, 0),
1686 GATE(CLK_GOUT_BUS0_BOOST_OPTION1, "gout_bus0_boost_option1",
1687 "dout_apm_boost", CLK_CON_GAT_CLK_BUS0_BOOST_OPTION1, 21, 0, 0),
1688 GATE(CLK_GOUT_CMU_BOOST_OPTION1, "gout_cmu_boost_option1",
1689 "dout_apm_boost", CLK_CON_GAT_CLK_CMU_BOOST_OPTION1, 21, 0, 0),
1690 GATE(CLK_GOUT_CORE_BOOST_OPTION1, "gout_core_boost_option1",
1691 "dout_apm_boost", CLK_CON_GAT_CLK_CORE_BOOST_OPTION1, 21, 0, 0),
1692 GATE(CLK_GOUT_APM_FUNC, "gout_apm_func", "mout_apm_func",
1693 CLK_CON_GAT_GATE_CLKCMU_APM_FUNC, 21, 0, 0),
1694 GATE(CLK_GOUT_APM_APBIF_GPIO_ALIVE_PCLK,
1695 "gout_apm_apbif_gpio_alive_pclk", "gout_apm_func",
1696 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_ALIVE_IPCLKPORT_PCLK,
1697 21, 0, 0),
1698 GATE(CLK_GOUT_APM_APBIF_GPIO_FAR_ALIVE_PCLK,
1699 "gout_apm_apbif_gpio_far_alive_pclk", "gout_apm_func",
1700 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_GPIO_FAR_ALIVE_IPCLKPORT_PCLK,
1701 21, 0, 0),
1702 GATE(CLK_GOUT_APM_APBIF_PMU_ALIVE_PCLK,
1703 "gout_apm_apbif_pmu_alive_pclk", "gout_apm_func",
1704 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_PMU_ALIVE_IPCLKPORT_PCLK,
1705 21, 0, 0),
1706 GATE(CLK_GOUT_APM_APBIF_RTC_PCLK,
1707 "gout_apm_apbif_rtc_pclk", "gout_apm_func",
1708 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_RTC_IPCLKPORT_PCLK, 21, 0, 0),
1709 GATE(CLK_GOUT_APM_APBIF_TRTC_PCLK,
1710 "gout_apm_apbif_trtc_pclk", "gout_apm_func",
1711 CLK_CON_GAT_GOUT_BLK_APM_UID_APBIF_TRTC_IPCLKPORT_PCLK, 21, 0, 0),
1712 GATE(CLK_GOUT_APM_APM_USI0_UART_IPCLK,
1713 "gout_apm_apm_usi0_uart_ipclk", "dout_apm_usi0_uart",
1714 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_IPCLK,
1715 21, 0, 0),
1716 GATE(CLK_GOUT_APM_APM_USI0_UART_PCLK,
1717 "gout_apm_apm_usi0_uart_pclk", "gout_apm_func",
1718 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_UART_IPCLKPORT_PCLK,
1719 21, 0, 0),
1720 GATE(CLK_GOUT_APM_APM_USI0_USI_IPCLK,
1721 "gout_apm_apm_usi0_usi_ipclk", "dout_apm_usi0_usi",
1722 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_IPCLK,
1723 21, 0, 0),
1724 GATE(CLK_GOUT_APM_APM_USI0_USI_PCLK,
1725 "gout_apm_apm_usi0_usi_pclk", "gout_apm_func",
1726 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI0_USI_IPCLKPORT_PCLK,
1727 21, 0, 0),
1728 GATE(CLK_GOUT_APM_APM_USI1_UART_IPCLK,
1729 "gout_apm_apm_usi1_uart_ipclk", "dout_apm_usi1_uart",
1730 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_IPCLK,
1731 21, 0, 0),
1732 GATE(CLK_GOUT_APM_APM_USI1_UART_PCLK,
1733 "gout_apm_apm_usi1_uart_pclk", "gout_apm_func",
1734 CLK_CON_GAT_GOUT_BLK_APM_UID_APM_USI1_UART_IPCLKPORT_PCLK,
1735 21, 0, 0),
1736 GATE(CLK_GOUT_APM_D_TZPC_APM_PCLK,
1737 "gout_apm_d_tzpc_apm_pclk", "gout_apm_func",
1738 CLK_CON_GAT_GOUT_BLK_APM_UID_D_TZPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1739 GATE(CLK_GOUT_APM_GPC_APM_PCLK,
1740 "gout_apm_gpc_apm_pclk", "gout_apm_func",
1741 CLK_CON_GAT_GOUT_BLK_APM_UID_GPC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1742 GATE(CLK_GOUT_APM_GREBEINTEGRATION_HCLK,
1743 "gout_apm_grebeintegration_hclk", "gout_apm_func",
1744 CLK_CON_GAT_GOUT_BLK_APM_UID_GREBEINTEGRATION_IPCLKPORT_HCLK,
1745 21, 0, 0),
1746 GATE(CLK_GOUT_APM_INTMEM_ACLK,
1747 "gout_apm_intmem_aclk", "gout_apm_func",
1748 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_ACLK, 21, 0, 0),
1749 GATE(CLK_GOUT_APM_INTMEM_PCLK,
1750 "gout_apm_intmem_pclk", "gout_apm_func",
1751 CLK_CON_GAT_GOUT_BLK_APM_UID_INTMEM_IPCLKPORT_PCLK, 21, 0, 0),
1752 GATE(CLK_GOUT_APM_LHM_AXI_G_SWD_I_CLK,
1753 "gout_apm_lhm_axi_g_swd_i_clk", "gout_apm_func",
1754 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_G_SWD_IPCLKPORT_I_CLK,
1755 21, 0, 0),
1756 GATE(CLK_GOUT_APM_LHM_AXI_P_AOCAPM_I_CLK,
1757 "gout_apm_lhm_axi_p_aocapm_i_clk", "gout_apm_func",
1758 CLK_CON_GAT_GOUT_BLK_APM_UID_LHM_AXI_P_AOCAPM_IPCLKPORT_I_CLK,
1759 21, 0, 0),
1760 GATE(CLK_GOUT_APM_LHM_AXI_P_APM_I_CLK,
1761 "gout_apm_lhm_axi_p_apm_i_clk", "gout_apm_func",
1762 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1763 21, 0, 0),
1764 GATE(CLK_GOUT_APM_LHS_AXI_D_APM_I_CLK,
1765 "gout_apm_lhs_axi_d_apm_i_clk", "gout_apm_func",
1766 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_D_APM_IPCLKPORT_I_CLK,
1767 21, 0, 0),
1768 GATE(CLK_GOUT_APM_LHS_AXI_G_DBGCORE_I_CLK,
1769 "gout_apm_lhs_axi_g_dbgcore_i_clk", "gout_apm_func",
1770 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_DBGCORE_IPCLKPORT_I_CLK,
1771 21, 0, 0),
1772 GATE(CLK_GOUT_APM_LHS_AXI_G_SCAN2DRAM_I_CLK,
1773 "gout_apm_lhs_axi_g_scan2dram_i_clk",
1774 "gout_apm_func",
1775 CLK_CON_GAT_GOUT_BLK_APM_UID_LHS_AXI_G_SCAN2DRAM_IPCLKPORT_I_CLK,
1776 21, 0, 0),
1777 GATE(CLK_GOUT_APM_MAILBOX_APM_AOC_PCLK,
1778 "gout_apm_mailbox_apm_aoc_pclk", "gout_apm_func",
1779 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AOC_IPCLKPORT_PCLK,
1780 21, 0, 0),
1781 GATE(CLK_GOUT_APM_MAILBOX_APM_AP_PCLK,
1782 "gout_apm_mailbox_apm_ap_pclk", "gout_apm_func",
1783 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_AP_IPCLKPORT_PCLK,
1784 21, 0, 0),
1785 GATE(CLK_GOUT_APM_MAILBOX_APM_GSA_PCLK,
1786 "gout_apm_mailbox_apm_gsa_pclk", "gout_apm_func",
1787 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_GSA_IPCLKPORT_PCLK,
1788 21, 0, 0),
1789 GATE(CLK_GOUT_APM_MAILBOX_APM_SWD_PCLK,
1790 "gout_apm_mailbox_apm_swd_pclk", "gout_apm_func",
1791 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_SWD_IPCLKPORT_PCLK,
1792 21, 0, 0),
1793 GATE(CLK_GOUT_APM_MAILBOX_APM_TPU_PCLK,
1794 "gout_apm_mailbox_apm_tpu_pclk", "gout_apm_func",
1795 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_APM_TPU_IPCLKPORT_PCLK,
1796 21, 0, 0),
1797 GATE(CLK_GOUT_APM_MAILBOX_AP_AOC_PCLK,
1798 "gout_apm_mailbox_ap_aoc_pclk", "gout_apm_func",
1799 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_AOC_IPCLKPORT_PCLK,
1800 21, 0, 0),
1801 GATE(CLK_GOUT_APM_MAILBOX_AP_DBGCORE_PCLK,
1802 "gout_apm_mailbox_ap_dbgcore_pclk", "gout_apm_func",
1803 CLK_CON_GAT_GOUT_BLK_APM_UID_MAILBOX_AP_DBGCORE_IPCLKPORT_PCLK,
1804 21, 0, 0),
1805 GATE(CLK_GOUT_APM_PMU_INTR_GEN_PCLK,
1806 "gout_apm_pmu_intr_gen_pclk", "gout_apm_func",
1807 CLK_CON_GAT_GOUT_BLK_APM_UID_PMU_INTR_GEN_IPCLKPORT_PCLK,
1808 21, 0, 0),
1809 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_ACLK,
1810 "gout_apm_rom_crc32_host_aclk", "gout_apm_func",
1811 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_ACLK,
1812 21, 0, 0),
1813 GATE(CLK_GOUT_APM_ROM_CRC32_HOST_PCLK,
1814 "gout_apm_rom_crc32_host_pclk", "gout_apm_func",
1815 CLK_CON_GAT_GOUT_BLK_APM_UID_ROM_CRC32_HOST_IPCLKPORT_PCLK,
1816 21, 0, 0),
1817 GATE(CLK_GOUT_APM_CLK_APM_BUS_CLK,
1818 "gout_apm_clk_apm_bus_clk", "gout_apm_func",
1819 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_BUS_IPCLKPORT_CLK,
1820 21, 0, 0),
1821 GATE(CLK_GOUT_APM_CLK_APM_USI0_UART_CLK,
1822 "gout_apm_clk_apm_usi0_uart_clk",
1823 "dout_apm_usi0_uart",
1824 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1825 21, 0, 0),
1826 GATE(CLK_GOUT_APM_CLK_APM_USI0_USI_CLK,
1827 "gout_apm_clk_apm_usi0_usi_clk",
1828 "dout_apm_usi0_usi",
1829 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI0_UART_IPCLKPORT_CLK,
1830 21, 0, 0),
1831 GATE(CLK_GOUT_APM_CLK_APM_USI1_UART_CLK,
1832 "gout_apm_clk_apm_usi1_uart_clk",
1833 "dout_apm_usi1_uart",
1834 CLK_CON_GAT_GOUT_BLK_APM_UID_RSTNSYNC_CLK_APM_USI1_UART_IPCLKPORT_CLK,
1835 21, 0, 0),
1836 GATE(CLK_GOUT_APM_SPEEDY_APM_PCLK,
1837 "gout_apm_speedy_apm_pclk", "gout_apm_func",
1838 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_APM_IPCLKPORT_PCLK, 21, 0, 0),
1839 GATE(CLK_GOUT_APM_SPEEDY_SUB_APM_PCLK,
1840 "gout_apm_speedy_sub_apm_pclk", "gout_apm_func",
1841 CLK_CON_GAT_GOUT_BLK_APM_UID_SPEEDY_SUB_APM_IPCLKPORT_PCLK,
1842 21, 0, 0),
1843 GATE(CLK_GOUT_APM_SSMT_D_APM_ACLK,
1844 "gout_apm_ssmt_d_apm_aclk", "gout_apm_func",
1845 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_ACLK, 21, 0, 0),
1846 GATE(CLK_GOUT_APM_SSMT_D_APM_PCLK,
1847 "gout_apm_ssmt_d_apm_pclk", "gout_apm_func",
1848 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_D_APM_IPCLKPORT_PCLK, 21, 0, 0),
1849 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_ACLK,
1850 "gout_apm_ssmt_g_dbgcore_aclk", "gout_apm_func",
1851 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_ACLK,
1852 21, 0, 0),
1853 GATE(CLK_GOUT_APM_SSMT_G_DBGCORE_PCLK,
1854 "gout_apm_ssmt_g_dbgcore_pclk", "gout_apm_func",
1855 CLK_CON_GAT_GOUT_BLK_APM_UID_SSMT_G_DBGCORE_IPCLKPORT_PCLK,
1856 21, 0, 0),
1857 GATE(CLK_GOUT_APM_SS_DBGCORE_SS_DBGCORE_HCLK,
1858 "gout_apm_ss_dbgcore_ss_dbgcore_hclk",
1859 "gout_apm_func",
1860 CLK_CON_GAT_GOUT_BLK_APM_UID_SS_DBGCORE_IPCLKPORT_SS_DBGCORE_IPCLKPORT_HCLK,
1861 21, 0, 0),
1862 GATE(CLK_GOUT_APM_SYSMMU_D_APM_CLK_S2,
1863 "gout_apm_sysmmu_d_dpm_clk_s2", "gout_apm_func",
1864 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSMMU_D_APM_IPCLKPORT_CLK_S2,
1865 21, 0, 0),
1866 GATE(CLK_GOUT_APM_SYSREG_APM_PCLK,
1867 "gout_apm_sysreg_apm_pclk", "gout_apm_func",
1868 CLK_CON_GAT_GOUT_BLK_APM_UID_SYSREG_APM_IPCLKPORT_PCLK, 21, 0, 0),
1869 GATE(CLK_GOUT_APM_UASC_APM_ACLK,
1870 "gout_apm_uasc_apm_aclk", "gout_apm_func",
1871 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_ACLK, 21, 0, 0),
1872 GATE(CLK_GOUT_APM_UASC_APM_PCLK,
1873 "gout_apm_uasc_apm_pclk", "gout_apm_func",
1874 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_APM_IPCLKPORT_PCLK, 21, 0, 0),
1875 GATE(CLK_GOUT_APM_UASC_DBGCORE_ACLK,
1876 "gout_apm_uasc_dbgcore_aclk", "gout_apm_func",
1877 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_ACLK,
1878 21, 0, 0),
1879 GATE(CLK_GOUT_APM_UASC_DBGCORE_PCLK,
1880 "gout_apm_uasc_dbgcore_pclk", "gout_apm_func",
1881 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_DBGCORE_IPCLKPORT_PCLK,
1882 21, 0, 0),
1883 GATE(CLK_GOUT_APM_UASC_G_SWD_ACLK,
1884 "gout_apm_uasc_g_swd_aclk", "gout_apm_func",
1885 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_ACLK, 21, 0, 0),
1886 GATE(CLK_GOUT_APM_UASC_G_SWD_PCLK,
1887 "gout_apm_uasc_g_swd_pclk", "gout_apm_func",
1888 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1889 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_ACLK,
1890 "gout_apm_uasc_p_aocapm_aclk", "gout_apm_func",
1891 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_AOCAPM_IPCLKPORT_ACLK,
1892 21, 0, 0),
1893 GATE(CLK_GOUT_APM_UASC_P_AOCAPM_PCLK,
1894 "gout_apm_uasc_p_aocapm_pclk", "gout_apm_func",
1895 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_G_SWD_IPCLKPORT_PCLK, 21, 0, 0),
1896 GATE(CLK_GOUT_APM_UASC_P_APM_ACLK,
1897 "gout_apm_uasc_p_apm_aclk", "gout_apm_func",
1898 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1899 GATE(CLK_GOUT_APM_UASC_P_APM_PCLK,
1900 "gout_apm_uasc_p_apm_pclk", "gout_apm_func",
1901 CLK_CON_GAT_GOUT_BLK_APM_UID_UASC_P_APM_IPCLKPORT_PCLK, 21, CLK_IS_CRITICAL, 0),
1902 GATE(CLK_GOUT_APM_WDT_APM_PCLK,
1903 "gout_apm_wdt_apm_pclk", "gout_apm_func",
1904 CLK_CON_GAT_GOUT_BLK_APM_UID_WDT_APM_IPCLKPORT_PCLK, 21, 0, 0),
1905 GATE(CLK_GOUT_APM_XIU_DP_APM_ACLK,
1906 "gout_apm_xiu_dp_apm_aclk", "gout_apm_func",
1907 CLK_CON_GAT_GOUT_BLK_APM_UID_XIU_DP_APM_IPCLKPORT_ACLK, 21, CLK_IS_CRITICAL, 0),
1908 };
1909
1910 static const unsigned long dcrg_memclk_sysreg[] __initconst = {
1911 GS101_DRCG_EN_OFFSET,
1912 GS101_MEMCLK_OFFSET,
1913 };
1914
1915 static const struct samsung_cmu_info apm_cmu_info __initconst = {
1916 .mux_clks = apm_mux_clks,
1917 .nr_mux_clks = ARRAY_SIZE(apm_mux_clks),
1918 .div_clks = apm_div_clks,
1919 .nr_div_clks = ARRAY_SIZE(apm_div_clks),
1920 .gate_clks = apm_gate_clks,
1921 .nr_gate_clks = ARRAY_SIZE(apm_gate_clks),
1922 .fixed_clks = apm_fixed_clks,
1923 .nr_fixed_clks = ARRAY_SIZE(apm_fixed_clks),
1924 .nr_clk_ids = CLKS_NR_APM,
1925 .clk_regs = apm_clk_regs,
1926 .nr_clk_regs = ARRAY_SIZE(apm_clk_regs),
1927 .sysreg_clk_regs = dcrg_memclk_sysreg,
1928 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
1929 .auto_clock_gate = true,
1930 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
1931 .drcg_offset = GS101_DRCG_EN_OFFSET,
1932 .memclk_offset = GS101_MEMCLK_OFFSET,
1933 };
1934
1935 /* ---- CMU_DPU ------------------------------------------------------------- */
1936
1937 /* Register Offset definitions for CMU_DPU (0x1c000000) */
1938 #define PLL_CON0_MUX_CLKCMU_DPU_BUS_USER 0x0600
1939 #define PLL_CON1_MUX_CLKCMU_DPU_BUS_USER 0x0604
1940 #define DPU_CMU_DPU_CONTROLLER_OPTION 0x0800
1941 #define CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0 0x0810
1942 #define CLK_CON_DIV_DIV_CLK_DPU_BUSP 0x1800
1943 #define CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK 0x2000
1944 #define CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK 0x2004
1945 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM 0x2008
1946 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA 0x200c
1947 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP 0x2010
1948 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK 0x2014
1949 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK 0x2018
1950 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK 0x201c
1951 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK 0x2020
1952 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK 0x2024
1953 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK 0x2028
1954 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK 0x202c
1955 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK 0x2030
1956 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK 0x2034
1957 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK 0x2038
1958 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK 0x203c
1959 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK 0x2040
1960 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK 0x2044
1961 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK 0x2048
1962 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK 0x204c
1963 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK 0x2050
1964 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK 0x2054
1965 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK 0x2058
1966 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK 0x205c
1967 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK 0x2060
1968 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1 0x2064
1969 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2 0x2068
1970 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1 0x206c
1971 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2 0x2070
1972 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1 0x2074
1973 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2 0x2078
1974 #define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK 0x207c
1975 #define PCH_CON_LHM_AXI_P_DPU_PCH 0x3000
1976 #define PCH_CON_LHS_AXI_D0_DPU_PCH 0x3004
1977 #define PCH_CON_LHS_AXI_D1_DPU_PCH 0x3008
1978 #define PCH_CON_LHS_AXI_D2_DPU_PCH 0x300c
1979 #define QCH_CON_DPUF_QCH_DPU_DMA 0x3010
1980 #define QCH_CON_DPUF_QCH_DPU_DPP 0x3014
1981 #define QCH_CON_DPU_CMU_DPU_QCH 0x301c
1982 #define QCH_CON_D_TZPC_DPU_QCH 0x3020
1983 #define QCH_CON_GPC_DPU_QCH 0x3024
1984 #define QCH_CON_LHM_AXI_P_DPU_QCH 0x3028
1985 #define QCH_CON_LHS_AXI_D0_DPU_QCH 0x302c
1986 #define QCH_CON_LHS_AXI_D1_DPU_QCH 0x3030
1987 #define QCH_CON_LHS_AXI_D2_DPU_QCH 0x3034
1988 #define QCH_CON_PPMU_DPUD0_QCH 0x3038
1989 #define QCH_CON_PPMU_DPUD1_QCH 0x303c
1990 #define QCH_CON_PPMU_DPUD2_QCH 0x3040
1991 #define QCH_CON_SSMT_DPU0_QCH 0x3044
1992 #define QCH_CON_SSMT_DPU1_QCH 0x3048
1993 #define QCH_CON_SSMT_DPU2_QCH 0x304c
1994 #define QCH_CON_SYSMMU_DPUD0_QCH_S1 0x3050
1995 #define QCH_CON_SYSMMU_DPUD0_QCH_S2 0x3054
1996 #define QCH_CON_SYSMMU_DPUD1_QCH_S1 0x3058
1997 #define QCH_CON_SYSMMU_DPUD1_QCH_S2 0x305c
1998 #define QCH_CON_SYSMMU_DPUD2_QCH_S1 0x3060
1999 #define QCH_CON_SYSMMU_DPUD2_QCH_S2 0x3064
2000 #define QCH_CON_SYSREG_DPU_QCH 0x3068
2001 #define QUEUE_CTRL_REG_BLK_DPU_CMU_DPU 0x3c00
2002
2003 static const unsigned long dpu_clk_regs[] __initconst = {
2004 PLL_CON0_MUX_CLKCMU_DPU_BUS_USER,
2005 PLL_CON1_MUX_CLKCMU_DPU_BUS_USER,
2006 DPU_CMU_DPU_CONTROLLER_OPTION,
2007 CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0,
2008 CLK_CON_DIV_DIV_CLK_DPU_BUSP,
2009 CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK,
2010 CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,
2011 CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,
2012 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA,
2013 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP,
2014 CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK,
2015 CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK,
2016 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,
2017 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,
2018 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,
2019 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,
2020 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK,
2021 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK,
2022 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK,
2023 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK,
2024 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK,
2025 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK,
2026 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,
2027 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
2028 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK,
2029 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK,
2030 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK,
2031 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK,
2032 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK,
2033 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK,
2034 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1,
2035 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2,
2036 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1,
2037 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2,
2038 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1,
2039 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2,
2040 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK,
2041 PCH_CON_LHM_AXI_P_DPU_PCH,
2042 PCH_CON_LHS_AXI_D0_DPU_PCH,
2043 PCH_CON_LHS_AXI_D1_DPU_PCH,
2044 PCH_CON_LHS_AXI_D2_DPU_PCH,
2045 QCH_CON_DPUF_QCH_DPU_DMA,
2046 QCH_CON_DPUF_QCH_DPU_DPP,
2047 QCH_CON_DPU_CMU_DPU_QCH,
2048 QCH_CON_D_TZPC_DPU_QCH,
2049 QCH_CON_GPC_DPU_QCH,
2050 QCH_CON_LHM_AXI_P_DPU_QCH,
2051 QCH_CON_LHS_AXI_D0_DPU_QCH,
2052 QCH_CON_LHS_AXI_D1_DPU_QCH,
2053 QCH_CON_LHS_AXI_D2_DPU_QCH,
2054 QCH_CON_PPMU_DPUD0_QCH,
2055 QCH_CON_PPMU_DPUD1_QCH,
2056 QCH_CON_PPMU_DPUD2_QCH,
2057 QCH_CON_SSMT_DPU0_QCH,
2058 QCH_CON_SSMT_DPU1_QCH,
2059 QCH_CON_SSMT_DPU2_QCH,
2060 QCH_CON_SYSMMU_DPUD0_QCH_S1,
2061 QCH_CON_SYSMMU_DPUD0_QCH_S2,
2062 QCH_CON_SYSMMU_DPUD1_QCH_S1,
2063 QCH_CON_SYSMMU_DPUD1_QCH_S2,
2064 QCH_CON_SYSMMU_DPUD2_QCH_S1,
2065 QCH_CON_SYSMMU_DPUD2_QCH_S2,
2066 QCH_CON_SYSREG_DPU_QCH,
2067 QUEUE_CTRL_REG_BLK_DPU_CMU_DPU,
2068 };
2069
2070 /* List of parent clocks for Muxes in CMU_DPU */
2071 PNAME(mout_dpu_bus_user_p) = { "oscclk", "dout_cmu_dpu_bus" };
2072
2073 static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
2074 MUX(CLK_MOUT_DPU_BUS_USER, "mout_dpu_bus_user",
2075 mout_dpu_bus_user_p, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 4, 1),
2076 };
2077
2078 static const struct samsung_div_clock dpu_div_clks[] __initconst = {
2079 DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_bus_user",
2080 CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),
2081 };
2082
2083 static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {
2084 GATE(CLK_GOUT_DPU_PCLK, "gout_dpu_dpu_pclk",
2085 "dout_dpu_busp",
2086 CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2087 GATE(CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK, "gout_dpu_clk_dpu_oscclk_clk",
2088 "oscclk",
2089 CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,
2090 21, 0, 0),
2091 GATE(CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM, "gout_dpu_ad_apb_dpu_dma_pclkm",
2092 "mout_dpu_bus_user",
2093 CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,
2094 21, 0, 0),
2095 GATE(CLK_GOUT_DPU_DPUF_ACLK_DMA, "gout_dpu_dpuf_aclk_dma",
2096 "mout_dpu_bus_user",
2097 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, 21, 0, 0),
2098 GATE(CLK_GOUT_DPU_DPUF_ACLK_DPP, "gout_dpu_dpuf_aclk_dpp",
2099 "mout_dpu_bus_user",
2100 CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, 21, 0, 0),
2101 GATE(CLK_GOUT_DPU_D_TZPC_DPU_PCLK, "gout_dpu_d_tzpc_dpu_pclk",
2102 "dout_dpu_busp",
2103 CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2104 GATE(CLK_GOUT_DPU_GPC_DPU_PCLK, "gout_dpu_gpc_dpu_pclk",
2105 "dout_dpu_busp",
2106 CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2107 GATE(CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK, "gout_dpu_lhm_axi_p_dpu_i_clk",
2108 "dout_dpu_busp",
2109 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,
2110 21, 0, 0),
2111 GATE(CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK, "gout_dpu_lhs_axi_d0_dpu_i_clk",
2112 "mout_dpu_bus_user",
2113 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,
2114 21, 0, 0),
2115 GATE(CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK, "gout_dpu_lhs_axi_d1_dpu_i_clk",
2116 "mout_dpu_bus_user",
2117 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,
2118 21, 0, 0),
2119 GATE(CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK, "gout_dpu_lhs_axi_d2_dpu_i_clk",
2120 "mout_dpu_bus_user",
2121 CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,
2122 21, 0, 0),
2123 GATE(CLK_GOUT_DPU_PPMU_DPUD0_ACLK, "gout_dpu_ppmu_dpud0_aclk",
2124 "mout_dpu_bus_user",
2125 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, 21, 0, 0),
2126 GATE(CLK_GOUT_DPU_PPMU_DPUD0_PCLK, "gout_dpu_ppmu_dpud0_pclk",
2127 "dout_dpu_busp",
2128 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 21, 0, 0),
2129 GATE(CLK_GOUT_DPU_PPMU_DPUD1_ACLK, "gout_dpu_ppmu_dpud1_aclk",
2130 "mout_dpu_bus_user",
2131 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, 21, 0, 0),
2132 GATE(CLK_GOUT_DPU_PPMU_DPUD1_PCLK, "gout_dpu_ppmu_dpud1_pclk",
2133 "dout_dpu_busp",
2134 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 21, 0, 0),
2135 GATE(CLK_GOUT_DPU_PPMU_DPUD2_ACLK, "gout_dpu_ppmu_dpud2_aclk",
2136 "mout_dpu_bus_user",
2137 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, 21, 0, 0),
2138 GATE(CLK_GOUT_DPU_PPMU_DPUD2_PCLK, "gout_dpu_ppmu_dpud2_pclk",
2139 "dout_dpu_busp",
2140 CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 21, 0, 0),
2141 GATE(CLK_GOUT_DPU_CLK_DPU_BUSD_CLK, "gout_dpu_clk_dpu_busd_clk",
2142 "mout_dpu_bus_user",
2143 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,
2144 21, 0, 0),
2145 GATE(CLK_GOUT_DPU_CLK_DPU_BUSP_CLK, "gout_dpu_clk_dpu_busp_clk",
2146 "dout_dpu_busp",
2147 CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,
2148 21, 0, 0),
2149 GATE(CLK_GOUT_DPU_SSMT_DPU0_ACLK, "gout_dpu_ssmt_dpu0_aclk",
2150 "mout_dpu_bus_user",
2151 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, 21, 0, 0),
2152 GATE(CLK_GOUT_DPU_SSMT_DPU0_PCLK, "gout_dpu_ssmt_dpu0_pclk",
2153 "dout_dpu_busp",
2154 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, 21, 0, 0),
2155 GATE(CLK_GOUT_DPU_SSMT_DPU1_ACLK, "gout_dpu_ssmt_dpu1_aclk",
2156 "mout_dpu_bus_user",
2157 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, 21, 0, 0),
2158 GATE(CLK_GOUT_DPU_SSMT_DPU1_PCLK, "gout_dpu_ssmt_dpu1_pclk",
2159 "dout_dpu_busp",
2160 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, 21, 0, 0),
2161 GATE(CLK_GOUT_DPU_SSMT_DPU2_ACLK, "gout_dpu_ssmt_dpu2_aclk",
2162 "mout_dpu_bus_user",
2163 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, 21, 0, 0),
2164 GATE(CLK_GOUT_DPU_SSMT_DPU2_PCLK, "gout_dpu_ssmt_dpu2_pclk",
2165 "dout_dpu_busp",
2166 CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, 21, 0, 0),
2167 GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1, "gout_dpu_sysmmu_dpud0_clk_s1",
2168 "mout_dpu_bus_user",
2169 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1,
2170 21, 0, 0),
2171 GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2, "gout_dpu_sysmmu_dpud0_clk_s2",
2172 "mout_dpu_bus_user",
2173 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2,
2174 21, 0, 0),
2175 GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1, "gout_dpu_sysmmu_dpud1_clk_s1",
2176 "mout_dpu_bus_user",
2177 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1,
2178 21, 0, 0),
2179 GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2, "gout_dpu_sysmmu_dpud1_clk_s2",
2180 "mout_dpu_bus_user",
2181 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2,
2182 21, 0, 0),
2183 GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1, "gout_dpu_sysmmu_dpud2_clk_s1",
2184 "mout_dpu_bus_user",
2185 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1,
2186 21, 0, 0),
2187 GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2, "gout_dpu_sysmmu_dpud2_clk_s2",
2188 "mout_dpu_bus_user",
2189 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, 21, 0, 0),
2190 GATE(CLK_GOUT_DPU_SYSREG_DPU_PCLK, "gout_dpu_sysreg_dpu_pclk",
2191 "dout_dpu_busp",
2192 CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 21, 0, 0),
2193 };
2194
2195 static const struct samsung_cmu_info dpu_cmu_info __initconst = {
2196 .mux_clks = dpu_mux_clks,
2197 .nr_mux_clks = ARRAY_SIZE(dpu_mux_clks),
2198 .div_clks = dpu_div_clks,
2199 .nr_div_clks = ARRAY_SIZE(dpu_div_clks),
2200 .gate_clks = dpu_gate_clks,
2201 .nr_gate_clks = ARRAY_SIZE(dpu_gate_clks),
2202 .nr_clk_ids = CLKS_NR_DPU,
2203 .clk_regs = dpu_clk_regs,
2204 .nr_clk_regs = ARRAY_SIZE(dpu_clk_regs),
2205 .sysreg_clk_regs = dcrg_memclk_sysreg,
2206 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
2207 .clk_name = "bus",
2208 .auto_clock_gate = true,
2209 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
2210 .option_offset = DPU_CMU_DPU_CONTROLLER_OPTION,
2211 .drcg_offset = GS101_DRCG_EN_OFFSET,
2212 };
2213
2214 /* ---- CMU_HSI0 ------------------------------------------------------------ */
2215
2216 /* Register Offset definitions for CMU_HSI0 (0x11000000) */
2217 #define PLL_LOCKTIME_PLL_USB 0x0004
2218 #define PLL_CON0_PLL_USB 0x0140
2219 #define PLL_CON1_PLL_USB 0x0144
2220 #define PLL_CON2_PLL_USB 0x0148
2221 #define PLL_CON3_PLL_USB 0x014c
2222 #define PLL_CON4_PLL_USB 0x0150
2223 #define PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER 0x0600
2224 #define PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER 0x0604
2225 #define PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER 0x0610
2226 #define PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER 0x0614
2227 #define PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER 0x0620
2228 #define PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER 0x0624
2229 #define PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER 0x0630
2230 #define PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER 0x0634
2231 #define PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER 0x0640
2232 #define PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER 0x0644
2233 #define PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0650
2234 #define PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER 0x0654
2235 #define PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0660
2236 #define PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER 0x0664
2237 #define HSI0_CMU_HSI0_CONTROLLER_OPTION 0x0800
2238 #define CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0 0x0810
2239 #define CLK_CON_MUX_MUX_CLK_HSI0_BUS 0x1000
2240 #define CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF 0x1004
2241 #define CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD 0x1008
2242 #define CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD 0x1800
2243 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK 0x2000
2244 #define CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26 0x2004
2245 #define CLK_CON_GAT_CLK_HSI0_ALT 0x2008
2246 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK 0x200c
2247 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK 0x2010
2248 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK 0x2014
2249 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK 0x2018
2250 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK 0x201c
2251 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK 0x2020
2252 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK 0x2024
2253 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK 0x2028
2254 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK 0x202c
2255 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK 0x2030
2256 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK 0x2034
2257 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK 0x2038
2258 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK 0x203c
2259 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK 0x2040
2260 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK 0x2044
2261 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK 0x2048
2262 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK 0x204c
2263 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK 0x2050
2264 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2 0x2054
2265 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK 0x2058
2266 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK 0x205c
2267 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK 0x2060
2268 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK 0x2064
2269 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK 0x2068
2270 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL 0x206c
2271 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY 0x2070
2272 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26 0x2074
2273 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40 0x2078
2274 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL 0x207c
2275 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK 0x2080
2276 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK 0x2084
2277 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK 0x2088
2278 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK 0x208c
2279 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK 0x2090
2280 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK 0x2094
2281 #define CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK 0x2098
2282 #define DMYQCH_CON_USB31DRD_QCH 0x3000
2283 #define DMYQCH_CON_USB31DRD_QCH_REF 0x3004
2284 #define PCH_CON_LHM_AXI_G_ETR_HSI0_PCH 0x3008
2285 #define PCH_CON_LHM_AXI_P_AOCHSI0_PCH 0x300c
2286 #define PCH_CON_LHM_AXI_P_HSI0_PCH 0x3010
2287 #define PCH_CON_LHS_ACEL_D_HSI0_PCH 0x3014
2288 #define PCH_CON_LHS_AXI_D_HSI0AOC_PCH 0x3018
2289 #define QCH_CON_DP_LINK_QCH_GTC_CLK 0x301c
2290 #define QCH_CON_DP_LINK_QCH_PCLK 0x3020
2291 #define QCH_CON_D_TZPC_HSI0_QCH 0x3024
2292 #define QCH_CON_ETR_MIU_QCH_ACLK 0x3028
2293 #define QCH_CON_ETR_MIU_QCH_PCLK 0x302c
2294 #define QCH_CON_GPC_HSI0_QCH 0x3030
2295 #define QCH_CON_HSI0_CMU_HSI0_QCH 0x3034
2296 #define QCH_CON_LHM_AXI_G_ETR_HSI0_QCH 0x3038
2297 #define QCH_CON_LHM_AXI_P_AOCHSI0_QCH 0x303c
2298 #define QCH_CON_LHM_AXI_P_HSI0_QCH 0x3040
2299 #define QCH_CON_LHS_ACEL_D_HSI0_QCH 0x3044
2300 #define QCH_CON_LHS_AXI_D_HSI0AOC_QCH 0x3048
2301 #define QCH_CON_PPMU_HSI0_AOC_QCH 0x304c
2302 #define QCH_CON_PPMU_HSI0_BUS0_QCH 0x3050
2303 #define QCH_CON_SSMT_USB_QCH 0x3054
2304 #define QCH_CON_SYSMMU_USB_QCH 0x3058
2305 #define QCH_CON_SYSREG_HSI0_QCH 0x305c
2306 #define QCH_CON_UASC_HSI0_CTRL_QCH 0x3060
2307 #define QCH_CON_UASC_HSI0_LINK_QCH 0x3064
2308 #define QCH_CON_USB31DRD_QCH_APB 0x3068
2309 #define QCH_CON_USB31DRD_QCH_DBG 0x306c
2310 #define QCH_CON_USB31DRD_QCH_PCS 0x3070
2311 #define QCH_CON_USB31DRD_QCH_SLV_CTRL 0x3074
2312 #define QCH_CON_USB31DRD_QCH_SLV_LINK 0x3078
2313 #define QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0 0x3c00
2314
2315 static const unsigned long hsi0_clk_regs[] __initconst = {
2316 PLL_LOCKTIME_PLL_USB,
2317 PLL_CON0_PLL_USB,
2318 PLL_CON1_PLL_USB,
2319 PLL_CON2_PLL_USB,
2320 PLL_CON3_PLL_USB,
2321 PLL_CON4_PLL_USB,
2322 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER,
2323 PLL_CON1_MUX_CLKCMU_HSI0_ALT_USER,
2324 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER,
2325 PLL_CON1_MUX_CLKCMU_HSI0_BUS_USER,
2326 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER,
2327 PLL_CON1_MUX_CLKCMU_HSI0_DPGTC_USER,
2328 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER,
2329 PLL_CON1_MUX_CLKCMU_HSI0_TCXO_USER,
2330 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER,
2331 PLL_CON1_MUX_CLKCMU_HSI0_USB20_USER,
2332 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER,
2333 PLL_CON1_MUX_CLKCMU_HSI0_USB31DRD_USER,
2334 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER,
2335 PLL_CON1_MUX_CLKCMU_HSI0_USPDPDBG_USER,
2336 HSI0_CMU_HSI0_CONTROLLER_OPTION,
2337 CLKOUT_CON_BLK_HSI0_CMU_HSI0_CLKOUT0,
2338 CLK_CON_MUX_MUX_CLK_HSI0_BUS,
2339 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF,
2340 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD,
2341 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD,
2342 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
2343 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
2344 CLK_CON_GAT_CLK_HSI0_ALT,
2345 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
2346 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK,
2347 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
2348 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK,
2349 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK,
2350 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK,
2351 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
2352 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
2353 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
2354 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
2355 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
2356 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
2357 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
2358 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
2359 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
2360 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
2361 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
2362 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
2363 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
2364 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
2365 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
2366 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
2367 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
2368 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
2369 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
2370 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
2371 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
2372 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
2373 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
2374 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
2375 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
2376 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
2377 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
2378 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
2379 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
2380 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
2381 DMYQCH_CON_USB31DRD_QCH,
2382 DMYQCH_CON_USB31DRD_QCH_REF,
2383 PCH_CON_LHM_AXI_G_ETR_HSI0_PCH,
2384 PCH_CON_LHM_AXI_P_AOCHSI0_PCH,
2385 PCH_CON_LHM_AXI_P_HSI0_PCH,
2386 PCH_CON_LHS_ACEL_D_HSI0_PCH,
2387 PCH_CON_LHS_AXI_D_HSI0AOC_PCH,
2388 QCH_CON_DP_LINK_QCH_GTC_CLK,
2389 QCH_CON_DP_LINK_QCH_PCLK,
2390 QCH_CON_D_TZPC_HSI0_QCH,
2391 QCH_CON_ETR_MIU_QCH_ACLK,
2392 QCH_CON_ETR_MIU_QCH_PCLK,
2393 QCH_CON_GPC_HSI0_QCH,
2394 QCH_CON_HSI0_CMU_HSI0_QCH,
2395 QCH_CON_LHM_AXI_G_ETR_HSI0_QCH,
2396 QCH_CON_LHM_AXI_P_AOCHSI0_QCH,
2397 QCH_CON_LHM_AXI_P_HSI0_QCH,
2398 QCH_CON_LHS_ACEL_D_HSI0_QCH,
2399 QCH_CON_LHS_AXI_D_HSI0AOC_QCH,
2400 QCH_CON_PPMU_HSI0_AOC_QCH,
2401 QCH_CON_PPMU_HSI0_BUS0_QCH,
2402 QCH_CON_SSMT_USB_QCH,
2403 QCH_CON_SYSMMU_USB_QCH,
2404 QCH_CON_SYSREG_HSI0_QCH,
2405 QCH_CON_UASC_HSI0_CTRL_QCH,
2406 QCH_CON_UASC_HSI0_LINK_QCH,
2407 QCH_CON_USB31DRD_QCH_APB,
2408 QCH_CON_USB31DRD_QCH_DBG,
2409 QCH_CON_USB31DRD_QCH_PCS,
2410 QCH_CON_USB31DRD_QCH_SLV_CTRL,
2411 QCH_CON_USB31DRD_QCH_SLV_LINK,
2412 QUEUE_CTRL_REG_BLK_HSI0_CMU_HSI0,
2413 };
2414
2415 /* List of parent clocks for Muxes in CMU_HSI0 */
2416 PNAME(mout_pll_usb_p) = { "oscclk", "fout_usb_pll" };
2417 PNAME(mout_hsi0_alt_user_p) = { "oscclk",
2418 "gout_hsi0_clk_hsi0_alt" };
2419 PNAME(mout_hsi0_bus_user_p) = { "oscclk", "dout_cmu_hsi0_bus" };
2420 PNAME(mout_hsi0_dpgtc_user_p) = { "oscclk", "dout_cmu_hsi0_dpgtc" };
2421 PNAME(mout_hsi0_tcxo_user_p) = { "oscclk", "tcxo_hsi1_hsi0" };
2422 PNAME(mout_hsi0_usb20_user_p) = { "oscclk", "usb20phy_phy_clock" };
2423 PNAME(mout_hsi0_usb31drd_user_p) = { "oscclk",
2424 "dout_cmu_hsi0_usb31drd" };
2425 PNAME(mout_hsi0_usbdpdbg_user_p) = { "oscclk",
2426 "dout_cmu_hsi0_usbdpdbg" };
2427 PNAME(mout_hsi0_bus_p) = { "mout_hsi0_bus_user",
2428 "mout_hsi0_alt_user" };
2429 PNAME(mout_hsi0_usb20_ref_p) = { "mout_pll_usb",
2430 "mout_hsi0_tcxo_user" };
2431 PNAME(mout_hsi0_usb31drd_p) = { "fout_usb_pll",
2432 "mout_hsi0_usb31drd_user",
2433 "dout_hsi0_usb31drd",
2434 "fout_usb_pll" };
2435
2436 static const struct samsung_pll_rate_table hsi0_usb_pll_rates[] __initconst = {
2437 PLL_35XX_RATE(24576000, 19200000, 150, 6, 5),
2438 { /* sentinel */ }
2439 };
2440
2441 static const struct samsung_pll_clock hsi0_pll_clks[] __initconst = {
2442 PLL(pll_0518x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
2443 PLL_LOCKTIME_PLL_USB, PLL_CON3_PLL_USB,
2444 hsi0_usb_pll_rates),
2445 };
2446
2447 static const struct samsung_mux_clock hsi0_mux_clks[] __initconst = {
2448 MUX(CLK_MOUT_PLL_USB,
2449 "mout_pll_usb", mout_pll_usb_p,
2450 PLL_CON0_PLL_USB, 4, 1),
2451 MUX(CLK_MOUT_HSI0_ALT_USER,
2452 "mout_hsi0_alt_user", mout_hsi0_alt_user_p,
2453 PLL_CON0_MUX_CLKCMU_HSI0_ALT_USER, 4, 1),
2454 MUX(CLK_MOUT_HSI0_BUS_USER,
2455 "mout_hsi0_bus_user", mout_hsi0_bus_user_p,
2456 PLL_CON0_MUX_CLKCMU_HSI0_BUS_USER, 4, 1),
2457 MUX(CLK_MOUT_HSI0_DPGTC_USER,
2458 "mout_hsi0_dpgtc_user", mout_hsi0_dpgtc_user_p,
2459 PLL_CON0_MUX_CLKCMU_HSI0_DPGTC_USER, 4, 1),
2460 MUX(CLK_MOUT_HSI0_TCXO_USER,
2461 "mout_hsi0_tcxo_user", mout_hsi0_tcxo_user_p,
2462 PLL_CON0_MUX_CLKCMU_HSI0_TCXO_USER, 4, 1),
2463 MUX(CLK_MOUT_HSI0_USB20_USER,
2464 "mout_hsi0_usb20_user", mout_hsi0_usb20_user_p,
2465 PLL_CON0_MUX_CLKCMU_HSI0_USB20_USER, 4, 1),
2466 MUX(CLK_MOUT_HSI0_USB31DRD_USER,
2467 "mout_hsi0_usb31drd_user", mout_hsi0_usb31drd_user_p,
2468 PLL_CON0_MUX_CLKCMU_HSI0_USB31DRD_USER, 4, 1),
2469 MUX(CLK_MOUT_HSI0_USBDPDBG_USER,
2470 "mout_hsi0_usbdpdbg_user", mout_hsi0_usbdpdbg_user_p,
2471 PLL_CON0_MUX_CLKCMU_HSI0_USPDPDBG_USER, 4, 1),
2472 MUX(CLK_MOUT_HSI0_BUS,
2473 "mout_hsi0_bus", mout_hsi0_bus_p,
2474 CLK_CON_MUX_MUX_CLK_HSI0_BUS, 0, 1),
2475 MUX(CLK_MOUT_HSI0_USB20_REF,
2476 "mout_hsi0_usb20_ref", mout_hsi0_usb20_ref_p,
2477 CLK_CON_MUX_MUX_CLK_HSI0_USB20_REF, 0, 1),
2478 MUX(CLK_MOUT_HSI0_USB31DRD,
2479 "mout_hsi0_usb31drd", mout_hsi0_usb31drd_p,
2480 CLK_CON_MUX_MUX_CLK_HSI0_USB31DRD, 0, 2),
2481 };
2482
2483 static const struct samsung_div_clock hsi0_div_clks[] __initconst = {
2484 DIV(CLK_DOUT_HSI0_USB31DRD,
2485 "dout_hsi0_usb31drd", "mout_hsi0_usb20_user",
2486 CLK_CON_DIV_DIV_CLK_HSI0_USB31DRD, 0, 3),
2487 };
2488
2489 static const struct samsung_gate_clock hsi0_gate_clks[] __initconst = {
2490 /* TODO: should have a driver for this */
2491 GATE(CLK_GOUT_HSI0_PCLK,
2492 "gout_hsi0_hsi0_pclk", "mout_hsi0_bus",
2493 CLK_CON_GAT_CLK_BLK_HSI0_UID_HSI0_CMU_HSI0_IPCLKPORT_PCLK,
2494 21, CLK_IGNORE_UNUSED, 0),
2495 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_SUSPEND_CLK_26,
2496 "gout_hsi0_usb31drd_i_usb31drd_suspend_clk_26",
2497 "mout_hsi0_usb20_ref",
2498 CLK_CON_GAT_CLK_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_SUSPEND_CLK_26,
2499 21, 0, 0),
2500 GATE(CLK_GOUT_HSI0_CLK_HSI0_ALT,
2501 "gout_hsi0_clk_hsi0_alt", "ioclk_clk_hsi0_alt",
2502 CLK_CON_GAT_CLK_HSI0_ALT, 21, 0, 0),
2503 GATE(CLK_GOUT_HSI0_DP_LINK_I_DP_GTC_CLK,
2504 "gout_hsi0_dp_link_i_dp_gtc_clk", "mout_hsi0_dpgtc_user",
2505 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_DP_GTC_CLK,
2506 21, 0, 0),
2507 GATE(CLK_GOUT_HSI0_DP_LINK_I_PCLK,
2508 "gout_hsi0_dp_link_i_pclk", "mout_hsi0_bus",
2509 CLK_CON_GAT_GOUT_BLK_HSI0_UID_DP_LINK_IPCLKPORT_I_PCLK, 21, 0, 0),
2510 GATE(CLK_GOUT_HSI0_D_TZPC_HSI0_PCLK,
2511 "gout_hsi0_d_tzpc_hsi0_pclk", "mout_hsi0_bus",
2512 CLK_CON_GAT_GOUT_BLK_HSI0_UID_D_TZPC_HSI0_IPCLKPORT_PCLK,
2513 21, 0, 0),
2514 GATE(CLK_GOUT_HSI0_ETR_MIU_I_ACLK,
2515 "gout_hsi0_etr_miu_i_aclk", "mout_hsi0_bus",
2516 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_ACLK, 21, 0, 0),
2517 GATE(CLK_GOUT_HSI0_ETR_MIU_I_PCLK,
2518 "gout_hsi0_etr_miu_i_pclk", "mout_hsi0_bus",
2519 CLK_CON_GAT_GOUT_BLK_HSI0_UID_ETR_MIU_IPCLKPORT_I_PCLK, 21, 0, 0),
2520 GATE(CLK_GOUT_HSI0_GPC_HSI0_PCLK,
2521 "gout_hsi0_gpc_hsi0_pclk", "mout_hsi0_bus",
2522 CLK_CON_GAT_GOUT_BLK_HSI0_UID_GPC_HSI0_IPCLKPORT_PCLK, 21, 0, 0),
2523 GATE(CLK_GOUT_HSI0_LHM_AXI_G_ETR_HSI0_I_CLK,
2524 "gout_hsi0_lhm_axi_g_etr_hsi0_i_clk", "mout_hsi0_bus",
2525 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_G_ETR_HSI0_IPCLKPORT_I_CLK,
2526 21, 0, 0),
2527 GATE(CLK_GOUT_HSI0_LHM_AXI_P_AOCHSI0_I_CLK,
2528 "gout_hsi0_lhm_axi_p_aochsi0_i_clk", "mout_hsi0_bus",
2529 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_AOCHSI0_IPCLKPORT_I_CLK,
2530 21, 0, 0),
2531 /* TODO: should have a driver for this */
2532 GATE(CLK_GOUT_HSI0_LHM_AXI_P_HSI0_I_CLK,
2533 "gout_hsi0_lhm_axi_p_hsi0_i_clk", "mout_hsi0_bus",
2534 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHM_AXI_P_HSI0_IPCLKPORT_I_CLK,
2535 21, CLK_IGNORE_UNUSED, 0),
2536 /* TODO: should have a driver for this */
2537 GATE(CLK_GOUT_HSI0_LHS_ACEL_D_HSI0_I_CLK,
2538 "gout_hsi0_lhs_acel_d_hsi0_i_clk", "mout_hsi0_bus",
2539 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_ACEL_D_HSI0_IPCLKPORT_I_CLK,
2540 21, CLK_IGNORE_UNUSED, 0),
2541 GATE(CLK_GOUT_HSI0_LHS_AXI_D_HSI0AOC_I_CLK,
2542 "gout_hsi0_lhs_axi_d_hsi0aoc_i_clk", "mout_hsi0_bus",
2543 CLK_CON_GAT_GOUT_BLK_HSI0_UID_LHS_AXI_D_HSI0AOC_IPCLKPORT_I_CLK,
2544 21, 0, 0),
2545 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_ACLK,
2546 "gout_hsi0_ppmu_hsi0_aoc_aclk", "mout_hsi0_bus",
2547 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_ACLK,
2548 21, 0, 0),
2549 GATE(CLK_GOUT_HSI0_PPMU_HSI0_AOC_PCLK,
2550 "gout_hsi0_ppmu_hsi0_aoc_pclk", "mout_hsi0_bus",
2551 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_AOC_IPCLKPORT_PCLK,
2552 21, 0, 0),
2553 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_ACLK,
2554 "gout_hsi0_ppmu_hsi0_bus0_aclk", "mout_hsi0_bus",
2555 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_ACLK,
2556 21, 0, 0),
2557 GATE(CLK_GOUT_HSI0_PPMU_HSI0_BUS0_PCLK,
2558 "gout_hsi0_ppmu_hsi0_bus0_pclk", "mout_hsi0_bus",
2559 CLK_CON_GAT_GOUT_BLK_HSI0_UID_PPMU_HSI0_BUS0_IPCLKPORT_PCLK,
2560 21, 0, 0),
2561 GATE(CLK_GOUT_HSI0_CLK_HSI0_BUS_CLK,
2562 "gout_hsi0_clk_hsi0_bus_clk", "mout_hsi0_bus",
2563 CLK_CON_GAT_GOUT_BLK_HSI0_UID_RSTNSYNC_CLK_HSI0_BUS_IPCLKPORT_CLK,
2564 21, 0, 0),
2565 /* TODO: should have a driver for this */
2566 GATE(CLK_GOUT_HSI0_SSMT_USB_ACLK,
2567 "gout_hsi0_ssmt_usb_aclk", "mout_hsi0_bus",
2568 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_ACLK,
2569 21, CLK_IGNORE_UNUSED, 0),
2570 /* TODO: should have a driver for this */
2571 GATE(CLK_GOUT_HSI0_SSMT_USB_PCLK,
2572 "gout_hsi0_ssmt_usb_pclk", "mout_hsi0_bus",
2573 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SSMT_USB_IPCLKPORT_PCLK,
2574 21, CLK_IGNORE_UNUSED, 0),
2575 /* TODO: should have a driver for this */
2576 GATE(CLK_GOUT_HSI0_SYSMMU_USB_CLK_S2,
2577 "gout_hsi0_sysmmu_usb_clk_s2", "mout_hsi0_bus",
2578 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSMMU_USB_IPCLKPORT_CLK_S2,
2579 21, CLK_IGNORE_UNUSED, 0),
2580 GATE(CLK_GOUT_HSI0_SYSREG_HSI0_PCLK,
2581 "gout_hsi0_sysreg_hsi0_pclk", "mout_hsi0_bus",
2582 CLK_CON_GAT_GOUT_BLK_HSI0_UID_SYSREG_HSI0_IPCLKPORT_PCLK,
2583 21, 0, 0),
2584 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_ACLK,
2585 "gout_hsi0_uasc_hsi0_ctrl_aclk", "mout_hsi0_bus",
2586 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_ACLK,
2587 21, 0, 0),
2588 GATE(CLK_GOUT_HSI0_UASC_HSI0_CTRL_PCLK,
2589 "gout_hsi0_uasc_hsi0_ctrl_pclk", "mout_hsi0_bus",
2590 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_CTRL_IPCLKPORT_PCLK,
2591 21, 0, 0),
2592 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_ACLK,
2593 "gout_hsi0_uasc_hsi0_link_aclk", "mout_hsi0_bus",
2594 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_ACLK,
2595 21, 0, 0),
2596 GATE(CLK_GOUT_HSI0_UASC_HSI0_LINK_PCLK,
2597 "gout_hsi0_uasc_hsi0_link_pclk", "mout_hsi0_bus",
2598 CLK_CON_GAT_GOUT_BLK_HSI0_UID_UASC_HSI0_LINK_IPCLKPORT_PCLK,
2599 21, 0, 0),
2600 GATE(CLK_GOUT_HSI0_USB31DRD_ACLK_PHYCTRL,
2601 "gout_hsi0_usb31drd_aclk_phyctrl", "mout_hsi0_bus",
2602 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_ACLK_PHYCTRL,
2603 21, 0, 0),
2604 GATE(CLK_GOUT_HSI0_USB31DRD_BUS_CLK_EARLY,
2605 "gout_hsi0_usb31drd_bus_clk_early", "mout_hsi0_bus",
2606 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_BUS_CLK_EARLY,
2607 21, 0, 0),
2608 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB20_PHY_REFCLK_26,
2609 "gout_hsi0_usb31drd_i_usb20_phy_refclk_26", "mout_hsi0_usb20_ref",
2610 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB20_PHY_REFCLK_26,
2611 21, 0, 0),
2612 GATE(CLK_GOUT_HSI0_USB31DRD_I_USB31DRD_REF_CLK_40,
2613 "gout_hsi0_usb31drd_i_usb31drd_ref_clk_40", "mout_hsi0_usb31drd",
2614 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USB31DRD_REF_CLK_40,
2615 21, 0, 0),
2616 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_REF_SOC_PLL,
2617 "gout_hsi0_usb31drd_i_usbdpphy_ref_soc_pll",
2618 "mout_hsi0_usbdpdbg_user",
2619 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_REF_SOC_PLL,
2620 21, 0, 0),
2621 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBDPPHY_SCL_APB_PCLK,
2622 "gout_hsi0_usb31drd_i_usbdpphy_scl_apb_pclk", "mout_hsi0_bus",
2623 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBDPPHY_SCL_APB_PCLK,
2624 21, 0, 0),
2625 GATE(CLK_GOUT_HSI0_USB31DRD_I_USBPCS_APB_CLK,
2626 "gout_hsi0_usb31drd_i_usbpcs_apb_clk", "mout_hsi0_bus",
2627 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_I_USBPCS_APB_CLK,
2628 21, 0, 0),
2629 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_I_ACLK,
2630 "gout_hsi0_usb31drd_usbdpphy_i_aclk", "mout_hsi0_bus",
2631 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_I_ACLK,
2632 21, 0, 0),
2633 GATE(CLK_GOUT_HSI0_USB31DRD_USBDPPHY_UDBG_I_APB_PCLK,
2634 "gout_hsi0_usb31drd_usbdpphy_udbg_i_apb_pclk", "mout_hsi0_bus",
2635 CLK_CON_GAT_GOUT_BLK_HSI0_UID_USB31DRD_IPCLKPORT_USBDPPHY_UDBG_I_APB_PCLK,
2636 21, 0, 0),
2637 /* TODO: should have a driver for this */
2638 GATE(CLK_GOUT_HSI0_XIU_D0_HSI0_ACLK,
2639 "gout_hsi0_xiu_d0_hsi0_aclk", "mout_hsi0_bus",
2640 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D0_HSI0_IPCLKPORT_ACLK,
2641 21, CLK_IGNORE_UNUSED, 0),
2642 /* TODO: should have a driver for this */
2643 GATE(CLK_GOUT_HSI0_XIU_D1_HSI0_ACLK,
2644 "gout_hsi0_xiu_d1_hsi0_aclk", "mout_hsi0_bus",
2645 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_D1_HSI0_IPCLKPORT_ACLK,
2646 21, CLK_IGNORE_UNUSED, 0),
2647 /* TODO: should have a driver for this */
2648 GATE(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK,
2649 "gout_hsi0_xiu_p_hsi0_aclk", "mout_hsi0_bus",
2650 CLK_CON_GAT_GOUT_BLK_HSI0_UID_XIU_P_HSI0_IPCLKPORT_ACLK,
2651 21, CLK_IGNORE_UNUSED, 0),
2652 };
2653
2654 static const struct samsung_fixed_rate_clock hsi0_fixed_clks[] __initconst = {
2655 FRATE(0, "tcxo_hsi1_hsi0", NULL, 0, 26000000),
2656 FRATE(0, "usb20phy_phy_clock", NULL, 0, 120000000),
2657 /* until we implement APMGSA */
2658 FRATE(0, "ioclk_clk_hsi0_alt", NULL, 0, 213000000),
2659 };
2660
2661 static const struct samsung_cmu_info hsi0_cmu_info __initconst = {
2662 .pll_clks = hsi0_pll_clks,
2663 .nr_pll_clks = ARRAY_SIZE(hsi0_pll_clks),
2664 .mux_clks = hsi0_mux_clks,
2665 .nr_mux_clks = ARRAY_SIZE(hsi0_mux_clks),
2666 .div_clks = hsi0_div_clks,
2667 .nr_div_clks = ARRAY_SIZE(hsi0_div_clks),
2668 .gate_clks = hsi0_gate_clks,
2669 .nr_gate_clks = ARRAY_SIZE(hsi0_gate_clks),
2670 .fixed_clks = hsi0_fixed_clks,
2671 .nr_fixed_clks = ARRAY_SIZE(hsi0_fixed_clks),
2672 .nr_clk_ids = CLKS_NR_HSI0,
2673 .clk_regs = hsi0_clk_regs,
2674 .nr_clk_regs = ARRAY_SIZE(hsi0_clk_regs),
2675 .sysreg_clk_regs = dcrg_memclk_sysreg,
2676 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
2677 .clk_name = "bus",
2678 .auto_clock_gate = true,
2679 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
2680 .option_offset = HSI0_CMU_HSI0_CONTROLLER_OPTION,
2681 .drcg_offset = GS101_DRCG_EN_OFFSET,
2682 .memclk_offset = GS101_MEMCLK_OFFSET,
2683 };
2684
2685 /* ---- CMU_HSI2 ------------------------------------------------------------ */
2686
2687 /* Register Offset definitions for CMU_HSI2 (0x14400000) */
2688 #define PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER 0x0600
2689 #define PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER 0x0604
2690 #define PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0610
2691 #define PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER 0x0614
2692 #define PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER 0x0620
2693 #define PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER 0x0624
2694 #define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0630
2695 #define PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x0634
2696 #define HSI2_CMU_HSI2_CONTROLLER_OPTION 0x0800
2697 #define CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0 0x0810
2698 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2000
2699 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN 0x2004
2700 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK 0x2008
2701 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK 0x200c
2702 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK 0x2010
2703 #define CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK 0x2014
2704 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK 0x201c
2705 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK 0x2020
2706 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK 0x2024
2707 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK 0x2028
2708 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK 0x202c
2709 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK 0x2030
2710 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK 0x2034
2711 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN 0x2038
2712 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x203c
2713 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2040
2714 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2044
2715 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2048
2716 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG 0x204c
2717 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG 0x2050
2718 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG 0x2054
2719 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK 0x2058
2720 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK 0x205c
2721 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK 0x2060
2722 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK 0x2064
2723 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK 0x2068
2724 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK 0x206c
2725 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK 0x2070
2726 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK 0x2074
2727 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK 0x2078
2728 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK 0x207c
2729 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK 0x2080
2730 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK 0x2084
2731 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK 0x2088
2732 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK 0x208c
2733 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK 0x2090
2734 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK 0x2094
2735 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK 0x2098
2736 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK 0x209c
2737 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK 0x20a0
2738 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK 0x20a4
2739 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2 0x20a8
2740 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK 0x20ac
2741 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK 0x20b0
2742 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK 0x20b4
2743 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK 0x20b8
2744 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK 0x20bc
2745 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK 0x20c0
2746 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK 0x20c4
2747 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK 0x20c8
2748 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK 0x20cc
2749 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK 0x20d0
2750 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO 0x20d4
2751 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK 0x20d8
2752 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK 0x20dc
2753 #define CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK 0x20e0
2754 #define DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1 0x3000
2755 #define PCH_CON_LHM_AXI_P_HSI2_PCH 0x3008
2756 #define PCH_CON_LHS_ACEL_D_HSI2_PCH 0x300c
2757 #define QCH_CON_D_TZPC_HSI2_QCH 0x3010
2758 #define QCH_CON_GPC_HSI2_QCH 0x3014
2759 #define QCH_CON_GPIO_HSI2_QCH 0x3018
2760 #define QCH_CON_HSI2_CMU_HSI2_QCH 0x301c
2761 #define QCH_CON_LHM_AXI_P_HSI2_QCH 0x3020
2762 #define QCH_CON_LHS_ACEL_D_HSI2_QCH 0x3024
2763 #define QCH_CON_MMC_CARD_QCH 0x3028
2764 #define QCH_CON_PCIE_GEN4_1_QCH_APB_1 0x302c
2765 #define QCH_CON_PCIE_GEN4_1_QCH_APB_2 0x3030
2766 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_1 0x3034
2767 #define QCH_CON_PCIE_GEN4_1_QCH_AXI_2 0x3038
2768 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_1 0x303c
2769 #define QCH_CON_PCIE_GEN4_1_QCH_DBG_2 0x3040
2770 #define QCH_CON_PCIE_GEN4_1_QCH_PCS_APB 0x3044
2771 #define QCH_CON_PCIE_GEN4_1_QCH_PMA_APB 0x3048
2772 #define QCH_CON_PCIE_GEN4_1_QCH_UDBG 0x304c
2773 #define QCH_CON_PCIE_IA_GEN4A_1_QCH 0x3050
2774 #define QCH_CON_PCIE_IA_GEN4B_1_QCH 0x3054
2775 #define QCH_CON_PPMU_HSI2_QCH 0x3058
2776 #define QCH_CON_QE_MMC_CARD_HSI2_QCH 0x305c
2777 #define QCH_CON_QE_PCIE_GEN4A_HSI2_QCH 0x3060
2778 #define QCH_CON_QE_PCIE_GEN4B_HSI2_QCH 0x3064
2779 #define QCH_CON_QE_UFS_EMBD_HSI2_QCH 0x3068
2780 #define QCH_CON_SSMT_HSI2_QCH 0x306c
2781 #define QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH 0x3070
2782 #define QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH 0x3074
2783 #define QCH_CON_SYSMMU_HSI2_QCH 0x3078
2784 #define QCH_CON_SYSREG_HSI2_QCH 0x307c
2785 #define QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH 0x3080
2786 #define QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH 0x3084
2787 #define QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH 0x3088
2788 #define QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH 0x308c
2789 #define QCH_CON_UFS_EMBD_QCH 0x3090
2790 #define QCH_CON_UFS_EMBD_QCH_FMP 0x3094
2791 #define QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2 0x3c00
2792
2793 static const unsigned long hsi2_clk_regs[] __initconst = {
2794 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER,
2795 PLL_CON1_MUX_CLKCMU_HSI2_BUS_USER,
2796 PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2797 PLL_CON1_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2798 PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
2799 PLL_CON1_MUX_CLKCMU_HSI2_PCIE_USER,
2800 PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2801 PLL_CON1_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2802 HSI2_CMU_HSI2_CONTROLLER_OPTION,
2803 CLKOUT_CON_BLK_HSI2_CMU_HSI2_CLKOUT0,
2804 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2805 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2806 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
2807 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
2808 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
2809 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
2810 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
2811 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK,
2812 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK,
2813 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
2814 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
2815 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
2816 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
2817 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
2818 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2819 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2820 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2821 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2822 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2823 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2824 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2825 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2826 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
2827 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
2828 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
2829 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
2830 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
2831 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
2832 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
2833 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
2834 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
2835 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
2836 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
2837 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
2838 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
2839 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
2840 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
2841 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
2842 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
2843 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
2844 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
2845 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
2846 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
2847 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
2848 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
2849 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
2850 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
2851 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
2852 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
2853 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
2854 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
2855 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
2856 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
2857 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
2858 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
2859 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
2860 DMYQCH_CON_PCIE_GEN4_1_QCH_SCLK_1,
2861 PCH_CON_LHM_AXI_P_HSI2_PCH,
2862 PCH_CON_LHS_ACEL_D_HSI2_PCH,
2863 QCH_CON_D_TZPC_HSI2_QCH,
2864 QCH_CON_GPC_HSI2_QCH,
2865 QCH_CON_GPIO_HSI2_QCH,
2866 QCH_CON_HSI2_CMU_HSI2_QCH,
2867 QCH_CON_LHM_AXI_P_HSI2_QCH,
2868 QCH_CON_LHS_ACEL_D_HSI2_QCH,
2869 QCH_CON_MMC_CARD_QCH,
2870 QCH_CON_PCIE_GEN4_1_QCH_APB_1,
2871 QCH_CON_PCIE_GEN4_1_QCH_APB_2,
2872 QCH_CON_PCIE_GEN4_1_QCH_AXI_1,
2873 QCH_CON_PCIE_GEN4_1_QCH_AXI_2,
2874 QCH_CON_PCIE_GEN4_1_QCH_DBG_1,
2875 QCH_CON_PCIE_GEN4_1_QCH_DBG_2,
2876 QCH_CON_PCIE_GEN4_1_QCH_PCS_APB,
2877 QCH_CON_PCIE_GEN4_1_QCH_PMA_APB,
2878 QCH_CON_PCIE_GEN4_1_QCH_UDBG,
2879 QCH_CON_PCIE_IA_GEN4A_1_QCH,
2880 QCH_CON_PCIE_IA_GEN4B_1_QCH,
2881 QCH_CON_PPMU_HSI2_QCH,
2882 QCH_CON_QE_MMC_CARD_HSI2_QCH,
2883 QCH_CON_QE_PCIE_GEN4A_HSI2_QCH,
2884 QCH_CON_QE_PCIE_GEN4B_HSI2_QCH,
2885 QCH_CON_QE_UFS_EMBD_HSI2_QCH,
2886 QCH_CON_SSMT_HSI2_QCH,
2887 QCH_CON_SSMT_PCIE_IA_GEN4A_1_QCH,
2888 QCH_CON_SSMT_PCIE_IA_GEN4B_1_QCH,
2889 QCH_CON_SYSMMU_HSI2_QCH,
2890 QCH_CON_SYSREG_HSI2_QCH,
2891 QCH_CON_UASC_PCIE_GEN4A_DBI_1_QCH,
2892 QCH_CON_UASC_PCIE_GEN4A_SLV_1_QCH,
2893 QCH_CON_UASC_PCIE_GEN4B_DBI_1_QCH,
2894 QCH_CON_UASC_PCIE_GEN4B_SLV_1_QCH,
2895 QCH_CON_UFS_EMBD_QCH,
2896 QCH_CON_UFS_EMBD_QCH_FMP,
2897 QUEUE_CTRL_REG_BLK_HSI2_CMU_HSI2,
2898 };
2899
2900 PNAME(mout_hsi2_bus_user_p) = { "oscclk", "dout_cmu_hsi2_bus" };
2901 PNAME(mout_hsi2_mmc_card_user_p) = { "oscclk", "dout_cmu_hsi2_mmc_card" };
2902 PNAME(mout_hsi2_pcie_user_p) = { "oscclk", "dout_cmu_hsi2_pcie" };
2903 PNAME(mout_hsi2_ufs_embd_user_p) = { "oscclk", "dout_cmu_hsi2_ufs_embd" };
2904
2905 static const struct samsung_mux_clock hsi2_mux_clks[] __initconst = {
2906 MUX(CLK_MOUT_HSI2_BUS_USER, "mout_hsi2_bus_user", mout_hsi2_bus_user_p,
2907 PLL_CON0_MUX_CLKCMU_HSI2_BUS_USER, 4, 1),
2908 MUX(CLK_MOUT_HSI2_MMC_CARD_USER, "mout_hsi2_mmc_card_user",
2909 mout_hsi2_mmc_card_user_p, PLL_CON0_MUX_CLKCMU_HSI2_MMC_CARD_USER,
2910 4, 1),
2911 MUX(CLK_MOUT_HSI2_PCIE_USER, "mout_hsi2_pcie_user",
2912 mout_hsi2_pcie_user_p, PLL_CON0_MUX_CLKCMU_HSI2_PCIE_USER,
2913 4, 1),
2914 MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_hsi2_ufs_embd_user",
2915 mout_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER,
2916 4, 1),
2917 };
2918
2919 static const struct samsung_gate_clock hsi2_gate_clks[] __initconst = {
2920 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_PHY_REFCLK_IN,
2921 "gout_hsi2_pcie_gen4_1_pcie_003_phy_refclk_in",
2922 "mout_hsi2_pcie_user",
2923 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2924 21, 0, 0),
2925 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_PHY_REFCLK_IN,
2926 "gout_hsi2_pcie_gen4_1_pcie_004_phy_refclk_in",
2927 "mout_hsi2_pcie_user",
2928 CLK_CON_GAT_CLK_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_PHY_REFCLK_IN,
2929 21, 0, 0),
2930 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_ACLK,
2931 "gout_hsi2_ssmt_pcie_ia_gen4a_1_aclk", "mout_hsi2_bus_user",
2932 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_ACLK,
2933 21, 0, 0),
2934 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4A_1_PCLK,
2935 "gout_hsi2_ssmt_pcie_ia_gen4a_1_pclk", "mout_hsi2_bus_user",
2936 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4A_1_IPCLKPORT_PCLK,
2937 21, 0, 0),
2938 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_ACLK,
2939 "gout_hsi2_ssmt_pcie_ia_gen4b_1_aclk", "mout_hsi2_bus_user",
2940 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_ACLK,
2941 21, 0, 0),
2942 GATE(CLK_GOUT_HSI2_SSMT_PCIE_IA_GEN4B_1_PCLK,
2943 "gout_hsi2_ssmt_pcie_ia_gen4b_1_pclk", "mout_hsi2_bus_user",
2944 CLK_CON_GAT_CLK_BLK_HSI2_UID_SSMT_PCIE_IA_GEN4B_1_IPCLKPORT_PCLK,
2945 21, 0, 0),
2946 GATE(CLK_GOUT_HSI2_D_TZPC_HSI2_PCLK,
2947 "gout_hsi2_d_tzpc_hsi2_pclk", "mout_hsi2_bus_user",
2948 CLK_CON_GAT_GOUT_BLK_HSI2_UID_D_TZPC_HSI2_IPCLKPORT_PCLK,
2949 21, 0, 0),
2950 GATE(CLK_GOUT_HSI2_GPC_HSI2_PCLK,
2951 "gout_hsi2_gpc_hsi2_pclk", "mout_hsi2_bus_user",
2952 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPC_HSI2_IPCLKPORT_PCLK, 21, 0, 0),
2953 GATE(CLK_GOUT_HSI2_GPIO_HSI2_PCLK,
2954 "gout_hsi2_gpio_hsi2_pclk", "mout_hsi2_bus_user",
2955 CLK_CON_GAT_GOUT_BLK_HSI2_UID_GPIO_HSI2_IPCLKPORT_PCLK, 21,
2956 CLK_IGNORE_UNUSED, 0),
2957 /* Disabling this clock makes the system hang. Mark the clock as critical. */
2958 GATE(CLK_GOUT_HSI2_HSI2_CMU_HSI2_PCLK,
2959 "gout_hsi2_hsi2_cmu_hsi2_pclk", "mout_hsi2_bus_user",
2960 CLK_CON_GAT_GOUT_BLK_HSI2_UID_HSI2_CMU_HSI2_IPCLKPORT_PCLK,
2961 21, CLK_IS_CRITICAL, 0),
2962 /* Disabling this clock makes the system hang. Mark the clock as critical. */
2963 GATE(CLK_GOUT_HSI2_LHM_AXI_P_HSI2_I_CLK,
2964 "gout_hsi2_lhm_axi_p_hsi2_i_clk", "mout_hsi2_bus_user",
2965 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHM_AXI_P_HSI2_IPCLKPORT_I_CLK,
2966 21, CLK_IS_CRITICAL, 0),
2967 /* TODO: should have a driver for this */
2968 GATE(CLK_GOUT_HSI2_LHS_ACEL_D_HSI2_I_CLK,
2969 "gout_hsi2_lhs_acel_d_hsi2_i_clk", "mout_hsi2_bus_user",
2970 CLK_CON_GAT_GOUT_BLK_HSI2_UID_LHS_ACEL_D_HSI2_IPCLKPORT_I_CLK,
2971 21, CLK_IGNORE_UNUSED, 0),
2972 GATE(CLK_GOUT_HSI2_MMC_CARD_I_ACLK,
2973 "gout_hsi2_mmc_card_i_aclk", "mout_hsi2_bus_user",
2974 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_I_ACLK,
2975 21, 0, 0),
2976 GATE(CLK_GOUT_HSI2_MMC_CARD_SDCLKIN,
2977 "gout_hsi2_mmc_card_sdclkin", "mout_hsi2_mmc_card_user",
2978 CLK_CON_GAT_GOUT_BLK_HSI2_UID_MMC_CARD_IPCLKPORT_SDCLKIN,
2979 21, 0, 0),
2980 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_DBI_ACLK_UG,
2981 "gout_hsi2_pcie_gen4_1_pcie_003_dbi_aclk_ug", "mout_hsi2_bus_user",
2982 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
2983 21, 0, 0),
2984 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_MSTR_ACLK_UG,
2985 "gout_hsi2_pcie_gen4_1_pcie_003_mstr_aclk_ug",
2986 "mout_hsi2_bus_user",
2987 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
2988 21, 0, 0),
2989 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_SLV_ACLK_UG,
2990 "gout_hsi2_pcie_gen4_1_pcie_003_slv_aclk_ug", "mout_hsi2_bus_user",
2991 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_G4X2_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
2992 21, 0, 0),
2993 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_003_I_DRIVER_APB_CLK,
2994 "gout_hsi2_pcie_gen4_1_pcie_003_i_driver_apb_clk",
2995 "mout_hsi2_bus_user",
2996 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_003_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
2997 21, 0, 0),
2998 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_DBI_ACLK_UG,
2999 "gout_hsi2_pcie_gen4_1_pcie_004_dbi_aclk_ug", "mout_hsi2_bus_user",
3000 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_DBI_ACLK_UG,
3001 21, 0, 0),
3002 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_MSTR_ACLK_UG,
3003 "gout_hsi2_pcie_gen4_1_pcie_004_mstr_aclk_ug",
3004 "mout_hsi2_bus_user",
3005 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_MSTR_ACLK_UG,
3006 21, 0, 0),
3007 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_SLV_ACLK_UG,
3008 "gout_hsi2_pcie_gen4_1_pcie_004_slv_aclk_ug", "mout_hsi2_bus_user",
3009 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_G4X1_DWC_PCIE_CTL_INST_0_SLV_ACLK_UG,
3010 21, 0, 0),
3011 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCIE_004_I_DRIVER_APB_CLK,
3012 "gout_hsi2_pcie_gen4_1_pcie_004_i_driver_apb_clk",
3013 "mout_hsi2_bus_user",
3014 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCIE_004_PCIE_SUB_CTRL_INST_0_I_DRIVER_APB_CLK,
3015 21, 0, 0),
3016 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PHY_UDBG_I_APB_PCLK,
3017 "gout_hsi2_pcie_gen4_1_pcs_pma_phy_udbg_i_apb_pclk",
3018 "mout_hsi2_bus_user",
3019 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PHY_UDBG_I_APB_PCLK,
3020 21, 0, 0),
3021 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PIPE_PAL_PCIE_I_APB_PCLK,
3022 "gout_hsi2_pcie_gen4_1_pcs_pma_pipe_pal_pcie_i_apb_pclk",
3023 "mout_hsi2_bus_user",
3024 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_PIPE_PAL_PCIE_INST_0_I_APB_PCLK,
3025 21, 0, 0),
3026 GATE(CLK_GOUT_HSI2_PCIE_GEN4_1_PCS_PMA_PCIEPHY210X2_QCH_I_APB_PCLK,
3027 "gout_hsi2_pcie_gen4_1_pcs_pma_pciephy210x2_qch_i_apb_pclk",
3028 "mout_hsi2_bus_user",
3029 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_GEN4_1_IPCLKPORT_PCS_PMA_INST_0_SF_PCIEPHY210X2_LN05LPE_QCH_TM_WRAPPER_INST_0_I_APB_PCLK,
3030 21, 0, 0),
3031 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4A_1_I_CLK,
3032 "gout_hsi2_pcie_ia_gen4a_1_i_clk", "mout_hsi2_bus_user",
3033 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4A_1_IPCLKPORT_I_CLK,
3034 21, 0, 0),
3035 GATE(CLK_GOUT_HSI2_PCIE_IA_GEN4B_1_I_CLK,
3036 "gout_hsi2_pcie_ia_gen4b_1_i_clk", "mout_hsi2_bus_user",
3037 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PCIE_IA_GEN4B_1_IPCLKPORT_I_CLK,
3038 21, 0, 0),
3039 GATE(CLK_GOUT_HSI2_PPMU_HSI2_ACLK,
3040 "gout_hsi2_ppmu_hsi2_aclk", "mout_hsi2_bus_user",
3041 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_ACLK,
3042 21, 0, 0),
3043 GATE(CLK_GOUT_HSI2_PPMU_HSI2_PCLK,
3044 "gout_hsi2_ppmu_hsi2_pclk", "mout_hsi2_bus_user",
3045 CLK_CON_GAT_GOUT_BLK_HSI2_UID_PPMU_HSI2_IPCLKPORT_PCLK,
3046 21, 0, 0),
3047 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_ACLK,
3048 "gout_hsi2_qe_mmc_card_hsi2_aclk", "mout_hsi2_bus_user",
3049 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_ACLK,
3050 21, 0, 0),
3051 GATE(CLK_GOUT_HSI2_QE_MMC_CARD_HSI2_PCLK,
3052 "gout_hsi2_qe_mmc_card_hsi2_pclk", "mout_hsi2_bus_user",
3053 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_MMC_CARD_HSI2_IPCLKPORT_PCLK,
3054 21, 0, 0),
3055 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_ACLK,
3056 "gout_hsi2_qe_pcie_gen4a_hsi2_aclk", "mout_hsi2_bus_user",
3057 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_ACLK,
3058 21, 0, 0),
3059 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4A_HSI2_PCLK,
3060 "gout_hsi2_qe_pcie_gen4a_hsi2_pclk", "mout_hsi2_bus_user",
3061 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4A_HSI2_IPCLKPORT_PCLK,
3062 21, 0, 0),
3063 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_ACLK,
3064 "gout_hsi2_qe_pcie_gen4b_hsi2_aclk", "mout_hsi2_bus_user",
3065 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_ACLK,
3066 21, 0, 0),
3067 GATE(CLK_GOUT_HSI2_QE_PCIE_GEN4B_HSI2_PCLK,
3068 "gout_hsi2_qe_pcie_gen4b_hsi2_pclk", "mout_hsi2_bus_user",
3069 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_PCIE_GEN4B_HSI2_IPCLKPORT_PCLK,
3070 21, 0, 0),
3071 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_ACLK,
3072 "gout_hsi2_qe_ufs_embd_hsi2_aclk", "mout_hsi2_bus_user",
3073 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_ACLK,
3074 21, CLK_IS_CRITICAL, 0),
3075 GATE(CLK_GOUT_HSI2_QE_UFS_EMBD_HSI2_PCLK,
3076 "gout_hsi2_qe_ufs_embd_hsi2_pclk", "mout_hsi2_bus_user",
3077 CLK_CON_GAT_GOUT_BLK_HSI2_UID_QE_UFS_EMBD_HSI2_IPCLKPORT_PCLK,
3078 21, CLK_IS_CRITICAL, 0),
3079 GATE(CLK_GOUT_HSI2_CLK_HSI2_BUS_CLK,
3080 "gout_hsi2_clk_hsi2_bus_clk", "mout_hsi2_bus_user",
3081 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_BUS_IPCLKPORT_CLK,
3082 21, CLK_IS_CRITICAL, 0),
3083 GATE(CLK_GOUT_HSI2_CLK_HSI2_OSCCLK_CLK,
3084 "gout_hsi2_clk_hsi2_oscclk_clk", "oscclk",
3085 CLK_CON_GAT_GOUT_BLK_HSI2_UID_RSTNSYNC_CLK_HSI2_OSCCLK_IPCLKPORT_CLK,
3086 21, 0, 0),
3087 /* TODO: should have a driver for this */
3088 GATE(CLK_GOUT_HSI2_SSMT_HSI2_ACLK,
3089 "gout_hsi2_ssmt_hsi2_aclk", "mout_hsi2_bus_user",
3090 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_ACLK,
3091 21, CLK_IGNORE_UNUSED, 0),
3092 /* TODO: should have a driver for this */
3093 GATE(CLK_GOUT_HSI2_SSMT_HSI2_PCLK,
3094 "gout_hsi2_ssmt_hsi2_pclk", "mout_hsi2_bus_user",
3095 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SSMT_HSI2_IPCLKPORT_PCLK,
3096 21, CLK_IGNORE_UNUSED, 0),
3097 /* TODO: should have a driver for this */
3098 GATE(CLK_GOUT_HSI2_SYSMMU_HSI2_CLK_S2,
3099 "gout_hsi2_sysmmu_hsi2_clk_s2", "mout_hsi2_bus_user",
3100 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSMMU_HSI2_IPCLKPORT_CLK_S2,
3101 21, CLK_IGNORE_UNUSED, 0),
3102 GATE(CLK_GOUT_HSI2_SYSREG_HSI2_PCLK,
3103 "gout_hsi2_sysreg_hsi2_pclk", "mout_hsi2_bus_user",
3104 CLK_CON_GAT_GOUT_BLK_HSI2_UID_SYSREG_HSI2_IPCLKPORT_PCLK,
3105 21, CLK_IS_CRITICAL, 0),
3106 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_ACLK,
3107 "gout_hsi2_uasc_pcie_gen4a_dbi_1_aclk", "mout_hsi2_bus_user",
3108 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_ACLK,
3109 21, 0, 0),
3110 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_DBI_1_PCLK,
3111 "gout_hsi2_uasc_pcie_gen4a_dbi_1_pclk", "mout_hsi2_bus_user",
3112 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_DBI_1_IPCLKPORT_PCLK,
3113 21, 0, 0),
3114 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_ACLK,
3115 "gout_hsi2_uasc_pcie_gen4a_slv_1_aclk", "mout_hsi2_bus_user",
3116 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_ACLK,
3117 21, 0, 0),
3118 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4A_SLV_1_PCLK,
3119 "gout_hsi2_uasc_pcie_gen4a_slv_1_pclk", "mout_hsi2_bus_user",
3120 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4A_SLV_1_IPCLKPORT_PCLK,
3121 21, 0, 0),
3122 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_ACLK,
3123 "gout_hsi2_uasc_pcie_gen4b_dbi_1_aclk", "mout_hsi2_bus_user",
3124 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_ACLK,
3125 21, 0, 0),
3126 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_DBI_1_PCLK,
3127 "gout_hsi2_uasc_pcie_gen4b_dbi_1_pclk", "mout_hsi2_bus_user",
3128 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_DBI_1_IPCLKPORT_PCLK,
3129 21, 0, 0),
3130 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_ACLK,
3131 "gout_hsi2_uasc_pcie_gen4b_slv_1_aclk", "mout_hsi2_bus_user",
3132 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_ACLK,
3133 21, 0, 0),
3134 GATE(CLK_GOUT_HSI2_UASC_PCIE_GEN4B_SLV_1_PCLK,
3135 "gout_hsi2_uasc_pcie_gen4b_slv_1_pclk", "mout_hsi2_bus_user",
3136 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UASC_PCIE_GEN4B_SLV_1_IPCLKPORT_PCLK,
3137 21, 0, 0),
3138 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_ACLK,
3139 "gout_hsi2_ufs_embd_i_aclk", "mout_hsi2_bus_user",
3140 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_ACLK,
3141 21, CLK_IS_CRITICAL, 0),
3142 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_CLK_UNIPRO,
3143 "gout_hsi2_ufs_embd_i_clk_unipro", "mout_hsi2_ufs_embd_user",
3144 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_CLK_UNIPRO,
3145 21, CLK_IS_CRITICAL, 0),
3146 GATE(CLK_GOUT_HSI2_UFS_EMBD_I_FMP_CLK,
3147 "gout_hsi2_ufs_embd_i_fmp_clk", "mout_hsi2_bus_user",
3148 CLK_CON_GAT_GOUT_BLK_HSI2_UID_UFS_EMBD_IPCLKPORT_I_FMP_CLK,
3149 21, CLK_IS_CRITICAL, 0),
3150 /* TODO: should have a driver for this */
3151 GATE(CLK_GOUT_HSI2_XIU_D_HSI2_ACLK,
3152 "gout_hsi2_xiu_d_hsi2_aclk", "mout_hsi2_bus_user",
3153 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_D_HSI2_IPCLKPORT_ACLK,
3154 21, CLK_IGNORE_UNUSED, 0),
3155 /* TODO: should have a driver for this */
3156 GATE(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK,
3157 "gout_hsi2_xiu_p_hsi2_aclk", "mout_hsi2_bus_user",
3158 CLK_CON_GAT_GOUT_BLK_HSI2_UID_XIU_P_HSI2_IPCLKPORT_ACLK,
3159 21, CLK_IGNORE_UNUSED, 0),
3160 };
3161
3162 static const struct samsung_cmu_info hsi2_cmu_info __initconst = {
3163 .mux_clks = hsi2_mux_clks,
3164 .nr_mux_clks = ARRAY_SIZE(hsi2_mux_clks),
3165 .gate_clks = hsi2_gate_clks,
3166 .nr_gate_clks = ARRAY_SIZE(hsi2_gate_clks),
3167 .nr_clk_ids = CLKS_NR_HSI2,
3168 .clk_regs = hsi2_clk_regs,
3169 .nr_clk_regs = ARRAY_SIZE(hsi2_clk_regs),
3170 .sysreg_clk_regs = dcrg_memclk_sysreg,
3171 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
3172 .clk_name = "bus",
3173 .auto_clock_gate = true,
3174 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
3175 .option_offset = HSI2_CMU_HSI2_CONTROLLER_OPTION,
3176 .drcg_offset = GS101_DRCG_EN_OFFSET,
3177 .memclk_offset = GS101_MEMCLK_OFFSET,
3178 };
3179
3180 /* ---- CMU_MISC ------------------------------------------------------------ */
3181
3182 /* Register Offset definitions for CMU_MISC (0x10010000) */
3183 #define PLL_CON0_MUX_CLKCMU_MISC_BUS_USER 0x0600
3184 #define PLL_CON1_MUX_CLKCMU_MISC_BUS_USER 0x0604
3185 #define PLL_CON0_MUX_CLKCMU_MISC_SSS_USER 0x0610
3186 #define PLL_CON1_MUX_CLKCMU_MISC_SSS_USER 0x0614
3187 #define MISC_CMU_MISC_CONTROLLER_OPTION 0x0800
3188 #define CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0 0x0810
3189 #define CLK_CON_MUX_MUX_CLK_MISC_GIC 0x1000
3190 #define CLK_CON_DIV_DIV_CLK_MISC_BUSP 0x1800
3191 #define CLK_CON_DIV_DIV_CLK_MISC_GIC 0x1804
3192 #define CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK 0x2000
3193 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK 0x2004
3194 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK 0x2008
3195 #define CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK 0x200c
3196 #define CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK 0x2010
3197 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM 0x2014
3198 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM 0x2018
3199 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM 0x201c
3200 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A 0x2020
3201 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK 0x2024
3202 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK 0x2028
3203 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK 0x202c
3204 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK 0x2030
3205 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK 0x2034
3206 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK 0x2038
3207 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK 0x203c
3208 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK 0x2040
3209 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK 0x2044
3210 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK 0x2048
3211 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK 0x204c
3212 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK 0x2050
3213 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK 0x2054
3214 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK 0x2058
3215 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK 0x205c
3216 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK 0x2060
3217 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK 0x2064
3218 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK 0x2068
3219 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK 0x206c
3220 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK 0x2070
3221 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK 0x2074
3222 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK 0x2078
3223 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK 0x207c
3224 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK 0x2080
3225 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK 0x2084
3226 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK 0x2088
3227 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK 0x208c
3228 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK 0x2090
3229 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK 0x2094
3230 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK 0x2098
3231 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK 0x209c
3232 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK 0x20a0
3233 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK 0x20a4
3234 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK 0x20a8
3235 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK 0x20ac
3236 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK 0x20b0
3237 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK 0x20b4
3238 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK 0x20b8
3239 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK 0x20bc
3240 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK 0x20c0
3241 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK 0x20c4
3242 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK 0x20c8
3243 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK 0x20cc
3244 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK 0x20d0
3245 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK 0x20d4
3246 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK 0x20d8
3247 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK 0x20dc
3248 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK 0x20e0
3249 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK 0x20e4
3250 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK 0x20e8
3251 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK 0x20ec
3252 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK 0x20f0
3253 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2 0x20f4
3254 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1 0x20f8
3255 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK 0x20fc
3256 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK 0x2100
3257 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK 0x2104
3258 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK 0x2108
3259 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK 0x210c
3260 #define CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK 0x2110
3261 #define DMYQCH_CON_PPMU_DMA_QCH 0x3000
3262 #define DMYQCH_CON_PUF_QCH 0x3004
3263 #define PCH_CON_LHM_AXI_D_SSS_PCH 0x300c
3264 #define PCH_CON_LHM_AXI_P_GIC_PCH 0x3010
3265 #define PCH_CON_LHM_AXI_P_MISC_PCH 0x3014
3266 #define PCH_CON_LHS_ACEL_D_MISC_PCH 0x3018
3267 #define PCH_CON_LHS_AST_IRI_GICCPU_PCH 0x301c
3268 #define PCH_CON_LHS_AXI_D_SSS_PCH 0x3020
3269 #define QCH_CON_ADM_AHB_SSS_QCH 0x3024
3270 #define QCH_CON_DIT_QCH 0x3028
3271 #define QCH_CON_GIC_QCH 0x3030
3272 #define QCH_CON_LHM_AST_ICC_CPUGIC_QCH 0x3038
3273 #define QCH_CON_LHM_AXI_D_SSS_QCH 0x303c
3274 #define QCH_CON_LHM_AXI_P_GIC_QCH 0x3040
3275 #define QCH_CON_LHM_AXI_P_MISC_QCH 0x3044
3276 #define QCH_CON_LHS_ACEL_D_MISC_QCH 0x3048
3277 #define QCH_CON_LHS_AST_IRI_GICCPU_QCH 0x304c
3278 #define QCH_CON_LHS_AXI_D_SSS_QCH 0x3050
3279 #define QCH_CON_MCT_QCH 0x3054
3280 #define QCH_CON_MISC_CMU_MISC_QCH 0x3058
3281 #define QCH_CON_OTP_CON_BIRA_QCH 0x305c
3282 #define QCH_CON_OTP_CON_BISR_QCH 0x3060
3283 #define QCH_CON_OTP_CON_TOP_QCH 0x3064
3284 #define QCH_CON_PDMA_QCH 0x3068
3285 #define QCH_CON_PPMU_MISC_QCH 0x306c
3286 #define QCH_CON_QE_DIT_QCH 0x3070
3287 #define QCH_CON_QE_PDMA_QCH 0x3074
3288 #define QCH_CON_QE_PPMU_DMA_QCH 0x3078
3289 #define QCH_CON_QE_RTIC_QCH 0x307c
3290 #define QCH_CON_QE_SPDMA_QCH 0x3080
3291 #define QCH_CON_QE_SSS_QCH 0x3084
3292 #define QCH_CON_RTIC_QCH 0x3088
3293 #define QCH_CON_SPDMA_QCH 0x308c
3294 #define QCH_CON_SSMT_DIT_QCH 0x3090
3295 #define QCH_CON_SSMT_PDMA_QCH 0x3094
3296 #define QCH_CON_SSMT_PPMU_DMA_QCH 0x3098
3297 #define QCH_CON_SSMT_RTIC_QCH 0x309c
3298 #define QCH_CON_SSMT_SPDMA_QCH 0x30a0
3299 #define QCH_CON_SSMT_SSS_QCH 0x30a4
3300 #define QCH_CON_SSS_QCH 0x30a8
3301 #define QCH_CON_SYSMMU_MISC_QCH 0x30ac
3302 #define QCH_CON_SYSMMU_SSS_QCH 0x30b0
3303 #define QCH_CON_SYSREG_MISC_QCH 0x30b4
3304 #define QCH_CON_TMU_SUB_QCH 0x30b8
3305 #define QCH_CON_TMU_TOP_QCH 0x30bc
3306 #define QCH_CON_WDT_CLUSTER0_QCH 0x30c0
3307 #define QCH_CON_WDT_CLUSTER1_QCH 0x30c4
3308 #define QUEUE_CTRL_REG_BLK_MISC_CMU_MISC 0x3c00
3309
3310 static const unsigned long misc_clk_regs[] __initconst = {
3311 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER,
3312 PLL_CON1_MUX_CLKCMU_MISC_BUS_USER,
3313 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER,
3314 PLL_CON1_MUX_CLKCMU_MISC_SSS_USER,
3315 MISC_CMU_MISC_CONTROLLER_OPTION,
3316 CLKOUT_CON_BLK_MISC_CMU_MISC_CLKOUT0,
3317 CLK_CON_MUX_MUX_CLK_MISC_GIC,
3318 CLK_CON_DIV_DIV_CLK_MISC_BUSP,
3319 CLK_CON_DIV_DIV_CLK_MISC_GIC,
3320 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
3321 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
3322 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
3323 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
3324 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
3325 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
3326 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
3327 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_PUF_IPCLKPORT_PCLKM,
3328 CLK_CON_GAT_GOUT_BLK_MISC_UID_DIT_IPCLKPORT_ICLKL2A,
3329 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
3330 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
3331 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
3332 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
3333 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
3334 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
3335 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
3336 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
3337 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
3338 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
3339 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
3340 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
3341 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
3342 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
3343 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
3344 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_DMA_IPCLKPORT_ACLK,
3345 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
3346 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
3347 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
3348 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
3349 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
3350 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
3351 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
3352 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
3353 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
3354 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
3355 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
3356 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
3357 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
3358 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
3359 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
3360 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
3361 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
3362 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
3363 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
3364 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
3365 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
3366 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
3367 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
3368 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
3369 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
3370 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
3371 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
3372 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
3373 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
3374 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
3375 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
3376 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
3377 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
3378 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
3379 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
3380 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
3381 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
3382 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
3383 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
3384 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
3385 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
3386 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
3387 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
3388 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
3389 DMYQCH_CON_PPMU_DMA_QCH,
3390 DMYQCH_CON_PUF_QCH,
3391 PCH_CON_LHM_AXI_D_SSS_PCH,
3392 PCH_CON_LHM_AXI_P_GIC_PCH,
3393 PCH_CON_LHM_AXI_P_MISC_PCH,
3394 PCH_CON_LHS_ACEL_D_MISC_PCH,
3395 PCH_CON_LHS_AST_IRI_GICCPU_PCH,
3396 PCH_CON_LHS_AXI_D_SSS_PCH,
3397 QCH_CON_ADM_AHB_SSS_QCH,
3398 QCH_CON_DIT_QCH,
3399 QCH_CON_GIC_QCH,
3400 QCH_CON_LHM_AST_ICC_CPUGIC_QCH,
3401 QCH_CON_LHM_AXI_D_SSS_QCH,
3402 QCH_CON_LHM_AXI_P_GIC_QCH,
3403 QCH_CON_LHM_AXI_P_MISC_QCH,
3404 QCH_CON_LHS_ACEL_D_MISC_QCH,
3405 QCH_CON_LHS_AST_IRI_GICCPU_QCH,
3406 QCH_CON_LHS_AXI_D_SSS_QCH,
3407 QCH_CON_MCT_QCH,
3408 QCH_CON_MISC_CMU_MISC_QCH,
3409 QCH_CON_OTP_CON_BIRA_QCH,
3410 QCH_CON_OTP_CON_BISR_QCH,
3411 QCH_CON_OTP_CON_TOP_QCH,
3412 QCH_CON_PDMA_QCH,
3413 QCH_CON_PPMU_MISC_QCH,
3414 QCH_CON_QE_DIT_QCH,
3415 QCH_CON_QE_PDMA_QCH,
3416 QCH_CON_QE_PPMU_DMA_QCH,
3417 QCH_CON_QE_RTIC_QCH,
3418 QCH_CON_QE_SPDMA_QCH,
3419 QCH_CON_QE_SSS_QCH,
3420 QCH_CON_RTIC_QCH,
3421 QCH_CON_SPDMA_QCH,
3422 QCH_CON_SSMT_DIT_QCH,
3423 QCH_CON_SSMT_PDMA_QCH,
3424 QCH_CON_SSMT_PPMU_DMA_QCH,
3425 QCH_CON_SSMT_RTIC_QCH,
3426 QCH_CON_SSMT_SPDMA_QCH,
3427 QCH_CON_SSMT_SSS_QCH,
3428 QCH_CON_SSS_QCH,
3429 QCH_CON_SYSMMU_MISC_QCH,
3430 QCH_CON_SYSMMU_SSS_QCH,
3431 QCH_CON_SYSREG_MISC_QCH,
3432 QCH_CON_TMU_SUB_QCH,
3433 QCH_CON_TMU_TOP_QCH,
3434 QCH_CON_WDT_CLUSTER0_QCH,
3435 QCH_CON_WDT_CLUSTER1_QCH,
3436 QUEUE_CTRL_REG_BLK_MISC_CMU_MISC,
3437 };
3438
3439 /* List of parent clocks for Muxes in CMU_MISC */
3440 PNAME(mout_misc_bus_user_p) = { "oscclk", "dout_cmu_misc_bus" };
3441 PNAME(mout_misc_sss_user_p) = { "oscclk", "dout_cmu_misc_sss" };
3442 PNAME(mout_misc_gic_p) = { "dout_misc_gic", "oscclk" };
3443
3444 static const struct samsung_mux_clock misc_mux_clks[] __initconst = {
3445 MUX(CLK_MOUT_MISC_BUS_USER, "mout_misc_bus_user", mout_misc_bus_user_p,
3446 PLL_CON0_MUX_CLKCMU_MISC_BUS_USER, 4, 1),
3447 MUX(CLK_MOUT_MISC_SSS_USER, "mout_misc_sss_user", mout_misc_sss_user_p,
3448 PLL_CON0_MUX_CLKCMU_MISC_SSS_USER, 4, 1),
3449 MUX(CLK_MOUT_MISC_GIC, "mout_misc_gic", mout_misc_gic_p,
3450 CLK_CON_MUX_MUX_CLK_MISC_GIC, 0, 0),
3451 };
3452
3453 static const struct samsung_div_clock misc_div_clks[] __initconst = {
3454 DIV(CLK_DOUT_MISC_BUSP, "dout_misc_busp", "mout_misc_bus_user",
3455 CLK_CON_DIV_DIV_CLK_MISC_BUSP, 0, 3),
3456 DIV(CLK_DOUT_MISC_GIC, "dout_misc_gic", "mout_misc_bus_user",
3457 CLK_CON_DIV_DIV_CLK_MISC_GIC, 0, 3),
3458 };
3459
3460 static const struct samsung_gate_clock misc_gate_clks[] __initconst = {
3461 GATE(CLK_GOUT_MISC_MISC_CMU_MISC_PCLK,
3462 "gout_misc_misc_cmu_misc_pclk", "dout_misc_busp",
3463 CLK_CON_GAT_CLK_BLK_MISC_UID_MISC_CMU_MISC_IPCLKPORT_PCLK,
3464 21, 0, 0),
3465 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_I_OSCCLK,
3466 "gout_misc_otp_con_bira_i_oscclk", "oscclk",
3467 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_I_OSCCLK,
3468 21, 0, 0),
3469 GATE(CLK_GOUT_MISC_OTP_CON_BISR_I_OSCCLK,
3470 "gout_misc_otp_con_bisr_i_oscclk", "oscclk",
3471 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_I_OSCCLK,
3472 21, 0, 0),
3473 GATE(CLK_GOUT_MISC_OTP_CON_TOP_I_OSCCLK,
3474 "gout_misc_otp_con_top_i_oscclk", "oscclk",
3475 CLK_CON_GAT_CLK_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_I_OSCCLK,
3476 21, 0, 0),
3477 GATE(CLK_GOUT_MISC_CLK_MISC_OSCCLK_CLK,
3478 "gout_misc_clk_misc_oscclk_clk", "oscclk",
3479 CLK_CON_GAT_CLK_BLK_MISC_UID_RSTNSYNC_CLK_MISC_OSCCLK_IPCLKPORT_CLK,
3480 21, 0, 0),
3481 GATE(CLK_GOUT_MISC_ADM_AHB_SSS_HCLKM,
3482 "gout_misc_adm_ahb_sss_hclkm", "mout_misc_sss_user",
3483 CLK_CON_GAT_GOUT_BLK_MISC_UID_ADM_AHB_SSS_IPCLKPORT_HCLKM,
3484 21, 0, 0),
3485 GATE(CLK_GOUT_MISC_AD_APB_DIT_PCLKM,
3486 "gout_misc_ad_apb_dit_pclkm", "mout_misc_bus_user",
3487 CLK_CON_GAT_GOUT_BLK_MISC_UID_AD_APB_DIT_IPCLKPORT_PCLKM,
3488 21, 0, 0),
3489 GATE(CLK_GOUT_MISC_D_TZPC_MISC_PCLK,
3490 "gout_misc_d_tzpc_misc_pclk", "dout_misc_busp",
3491 CLK_CON_GAT_GOUT_BLK_MISC_UID_D_TZPC_MISC_IPCLKPORT_PCLK,
3492 21, 0, 0),
3493 GATE(CLK_GOUT_MISC_GIC_GICCLK,
3494 "gout_misc_gic_gicclk", "mout_misc_gic",
3495 CLK_CON_GAT_GOUT_BLK_MISC_UID_GIC_IPCLKPORT_GICCLK,
3496 21, 0, 0),
3497 GATE(CLK_GOUT_MISC_GPC_MISC_PCLK,
3498 "gout_misc_gpc_misc_pclk", "dout_misc_busp",
3499 CLK_CON_GAT_GOUT_BLK_MISC_UID_GPC_MISC_IPCLKPORT_PCLK,
3500 21, 0, 0),
3501 GATE(CLK_GOUT_MISC_LHM_AST_ICC_CPUGIC_I_CLK,
3502 "gout_misc_lhm_ast_icc_gpugic_i_clk", "mout_misc_gic",
3503 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AST_ICC_CPUGIC_IPCLKPORT_I_CLK,
3504 21, 0, 0),
3505 GATE(CLK_GOUT_MISC_LHM_AXI_D_SSS_I_CLK,
3506 "gout_misc_lhm_axi_d_sss_i_clk", "mout_misc_bus_user",
3507 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_D_SSS_IPCLKPORT_I_CLK,
3508 21, 0, 0),
3509 GATE(CLK_GOUT_MISC_LHM_AXI_P_GIC_I_CLK,
3510 "gout_misc_lhm_axi_p_gic_i_clk", "mout_misc_gic",
3511 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_GIC_IPCLKPORT_I_CLK,
3512 21, 0, 0),
3513 GATE(CLK_GOUT_MISC_LHM_AXI_P_MISC_I_CLK,
3514 "gout_misc_lhm_axi_p_misc_i_clk", "dout_misc_busp",
3515 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHM_AXI_P_MISC_IPCLKPORT_I_CLK,
3516 21, 0, 0),
3517 GATE(CLK_GOUT_MISC_LHS_ACEL_D_MISC_I_CLK,
3518 "gout_misc_lhs_acel_d_misc_i_clk", "mout_misc_bus_user",
3519 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_ACEL_D_MISC_IPCLKPORT_I_CLK,
3520 21, 0, 0),
3521 GATE(CLK_GOUT_MISC_LHS_AST_IRI_GICCPU_I_CLK,
3522 "gout_misc_lhs_ast_iri_giccpu_i_clk", "mout_misc_gic",
3523 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AST_IRI_GICCPU_IPCLKPORT_I_CLK,
3524 21, 0, 0),
3525 GATE(CLK_GOUT_MISC_LHS_AXI_D_SSS_I_CLK,
3526 "gout_misc_lhs_axi_d_sss_i_clk", "mout_misc_sss_user",
3527 CLK_CON_GAT_GOUT_BLK_MISC_UID_LHS_AXI_D_SSS_IPCLKPORT_I_CLK,
3528 21, 0, 0),
3529 GATE(CLK_GOUT_MISC_MCT_PCLK, "gout_misc_mct_pclk",
3530 "dout_misc_busp",
3531 CLK_CON_GAT_GOUT_BLK_MISC_UID_MCT_IPCLKPORT_PCLK,
3532 21, 0, 0),
3533 GATE(CLK_GOUT_MISC_OTP_CON_BIRA_PCLK,
3534 "gout_misc_otp_con_bira_pclk", "dout_misc_busp",
3535 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BIRA_IPCLKPORT_PCLK,
3536 21, 0, 0),
3537 GATE(CLK_GOUT_MISC_OTP_CON_BISR_PCLK,
3538 "gout_misc_otp_con_bisr_pclk", "dout_misc_busp",
3539 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_BISR_IPCLKPORT_PCLK,
3540 21, 0, 0),
3541 GATE(CLK_GOUT_MISC_OTP_CON_TOP_PCLK,
3542 "gout_misc_otp_con_top_pclk", "dout_misc_busp",
3543 CLK_CON_GAT_GOUT_BLK_MISC_UID_OTP_CON_TOP_IPCLKPORT_PCLK,
3544 21, 0, 0),
3545 GATE(CLK_GOUT_MISC_PDMA_ACLK, "gout_misc_pdma_aclk",
3546 "mout_misc_bus_user",
3547 CLK_CON_GAT_GOUT_BLK_MISC_UID_PDMA_IPCLKPORT_ACLK,
3548 21, 0, 0),
3549 GATE(CLK_GOUT_MISC_PPMU_MISC_ACLK,
3550 "gout_misc_ppmu_misc_aclk", "mout_misc_bus_user",
3551 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_ACLK,
3552 21, 0, 0),
3553 GATE(CLK_GOUT_MISC_PPMU_MISC_PCLK,
3554 "gout_misc_ppmu_misc_pclk", "dout_misc_busp",
3555 CLK_CON_GAT_GOUT_BLK_MISC_UID_PPMU_MISC_IPCLKPORT_PCLK,
3556 21, 0, 0),
3557 GATE(CLK_GOUT_MISC_PUF_I_CLK,
3558 "gout_misc_puf_i_clk", "mout_misc_sss_user",
3559 CLK_CON_GAT_GOUT_BLK_MISC_UID_PUF_IPCLKPORT_I_CLK,
3560 21, 0, 0),
3561 GATE(CLK_GOUT_MISC_QE_DIT_ACLK,
3562 "gout_misc_qe_dit_aclk", "mout_misc_bus_user",
3563 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_ACLK,
3564 21, 0, 0),
3565 GATE(CLK_GOUT_MISC_QE_DIT_PCLK,
3566 "gout_misc_qe_dit_pclk", "dout_misc_busp",
3567 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_DIT_IPCLKPORT_PCLK,
3568 21, 0, 0),
3569 GATE(CLK_GOUT_MISC_QE_PDMA_ACLK,
3570 "gout_misc_qe_pdma_aclk", "mout_misc_bus_user",
3571 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_ACLK,
3572 21, 0, 0),
3573 GATE(CLK_GOUT_MISC_QE_PDMA_PCLK,
3574 "gout_misc_qe_pdma_pclk", "dout_misc_busp",
3575 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PDMA_IPCLKPORT_PCLK,
3576 21, 0, 0),
3577 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_ACLK,
3578 "gout_misc_qe_ppmu_dma_aclk", "mout_misc_bus_user",
3579 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_ACLK,
3580 21, 0, 0),
3581 GATE(CLK_GOUT_MISC_QE_PPMU_DMA_PCLK,
3582 "gout_misc_qe_ppmu_dma_pclk", "dout_misc_busp",
3583 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_PPMU_DMA_IPCLKPORT_PCLK,
3584 21, 0, 0),
3585 GATE(CLK_GOUT_MISC_QE_RTIC_ACLK,
3586 "gout_misc_qe_rtic_aclk", "mout_misc_bus_user",
3587 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_ACLK,
3588 21, 0, 0),
3589 GATE(CLK_GOUT_MISC_QE_RTIC_PCLK,
3590 "gout_misc_qe_rtic_pclk", "dout_misc_busp",
3591 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_RTIC_IPCLKPORT_PCLK,
3592 21, 0, 0),
3593 GATE(CLK_GOUT_MISC_QE_SPDMA_ACLK,
3594 "gout_misc_qe_spdma_aclk", "mout_misc_bus_user",
3595 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_ACLK,
3596 21, 0, 0),
3597 GATE(CLK_GOUT_MISC_QE_SPDMA_PCLK,
3598 "gout_misc_qe_spdma_pclk", "dout_misc_busp",
3599 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SPDMA_IPCLKPORT_PCLK,
3600 21, 0, 0),
3601 GATE(CLK_GOUT_MISC_QE_SSS_ACLK,
3602 "gout_misc_qe_sss_aclk", "mout_misc_sss_user",
3603 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_ACLK,
3604 21, 0, 0),
3605 GATE(CLK_GOUT_MISC_QE_SSS_PCLK,
3606 "gout_misc_qe_sss_pclk", "dout_misc_busp",
3607 CLK_CON_GAT_GOUT_BLK_MISC_UID_QE_SSS_IPCLKPORT_PCLK,
3608 21, 0, 0),
3609 GATE(CLK_GOUT_MISC_CLK_MISC_BUSD_CLK,
3610 "gout_misc_clk_misc_busd_clk", "mout_misc_bus_user",
3611 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSD_IPCLKPORT_CLK,
3612 21, 0, 0),
3613 GATE(CLK_GOUT_MISC_CLK_MISC_BUSP_CLK,
3614 "gout_misc_clk_misc_busp_clk", "dout_misc_busp",
3615 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_BUSP_IPCLKPORT_CLK,
3616 21, 0, 0),
3617 GATE(CLK_GOUT_MISC_CLK_MISC_GIC_CLK,
3618 "gout_misc_clk_misc_gic_clk", "mout_misc_gic",
3619 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_GIC_IPCLKPORT_CLK,
3620 21, 0, 0),
3621 GATE(CLK_GOUT_MISC_CLK_MISC_SSS_CLK,
3622 "gout_misc_clk_misc_sss_clk", "mout_misc_sss_user",
3623 CLK_CON_GAT_GOUT_BLK_MISC_UID_RSTNSYNC_CLK_MISC_SSS_IPCLKPORT_CLK,
3624 21, 0, 0),
3625 GATE(CLK_GOUT_MISC_RTIC_I_ACLK,
3626 "gout_misc_rtic_i_aclk", "mout_misc_bus_user",
3627 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_ACLK,
3628 21, 0, 0),
3629 GATE(CLK_GOUT_MISC_RTIC_I_PCLK, "gout_misc_rtic_i_pclk",
3630 "dout_misc_busp",
3631 CLK_CON_GAT_GOUT_BLK_MISC_UID_RTIC_IPCLKPORT_I_PCLK,
3632 21, 0, 0),
3633 GATE(CLK_GOUT_MISC_SPDMA_ACLK,
3634 "gout_misc_spdma_ipclockport_aclk", "mout_misc_bus_user",
3635 CLK_CON_GAT_GOUT_BLK_MISC_UID_SPDMA_IPCLKPORT_ACLK,
3636 21, 0, 0),
3637 GATE(CLK_GOUT_MISC_SSMT_DIT_ACLK,
3638 "gout_misc_ssmt_dit_aclk", "mout_misc_bus_user",
3639 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_ACLK,
3640 21, 0, 0),
3641 GATE(CLK_GOUT_MISC_SSMT_DIT_PCLK,
3642 "gout_misc_ssmt_dit_pclk", "dout_misc_busp",
3643 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_DIT_IPCLKPORT_PCLK,
3644 21, 0, 0),
3645 GATE(CLK_GOUT_MISC_SSMT_PDMA_ACLK,
3646 "gout_misc_ssmt_pdma_aclk", "mout_misc_bus_user",
3647 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_ACLK,
3648 21, 0, 0),
3649 GATE(CLK_GOUT_MISC_SSMT_PDMA_PCLK,
3650 "gout_misc_ssmt_pdma_pclk", "dout_misc_busp",
3651 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PDMA_IPCLKPORT_PCLK,
3652 21, 0, 0),
3653 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_ACLK,
3654 "gout_misc_ssmt_ppmu_dma_aclk", "mout_misc_bus_user",
3655 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_ACLK,
3656 21, 0, 0),
3657 GATE(CLK_GOUT_MISC_SSMT_PPMU_DMA_PCLK,
3658 "gout_misc_ssmt_ppmu_dma_pclk", "dout_misc_busp",
3659 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_PPMU_DMA_IPCLKPORT_PCLK,
3660 21, 0, 0),
3661 GATE(CLK_GOUT_MISC_SSMT_RTIC_ACLK,
3662 "gout_misc_ssmt_rtic_aclk", "mout_misc_bus_user",
3663 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_ACLK,
3664 21, 0, 0),
3665 GATE(CLK_GOUT_MISC_SSMT_RTIC_PCLK,
3666 "gout_misc_ssmt_rtic_pclk", "dout_misc_busp",
3667 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_RTIC_IPCLKPORT_PCLK,
3668 21, 0, 0),
3669 GATE(CLK_GOUT_MISC_SSMT_SPDMA_ACLK,
3670 "gout_misc_ssmt_spdma_aclk", "mout_misc_bus_user",
3671 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_ACLK,
3672 21, 0, 0),
3673 GATE(CLK_GOUT_MISC_SSMT_SPDMA_PCLK,
3674 "gout_misc_ssmt_spdma_pclk", "dout_misc_busp",
3675 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SPDMA_IPCLKPORT_PCLK,
3676 21, 0, 0),
3677 GATE(CLK_GOUT_MISC_SSMT_SSS_ACLK,
3678 "gout_misc_ssmt_sss_aclk", "mout_misc_bus_user",
3679 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_ACLK,
3680 21, 0, 0),
3681 GATE(CLK_GOUT_MISC_SSMT_SSS_PCLK,
3682 "gout_misc_ssmt_sss_pclk", "dout_misc_busp",
3683 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSMT_SSS_IPCLKPORT_PCLK,
3684 21, 0, 0),
3685 GATE(CLK_GOUT_MISC_SSS_I_ACLK,
3686 "gout_misc_sss_i_aclk", "mout_misc_bus_user",
3687 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_ACLK,
3688 21, 0, 0),
3689 GATE(CLK_GOUT_MISC_SSS_I_PCLK,
3690 "gout_misc_sss_i_pclk", "dout_misc_busp",
3691 CLK_CON_GAT_GOUT_BLK_MISC_UID_SSS_IPCLKPORT_I_PCLK,
3692 21, 0, 0),
3693 GATE(CLK_GOUT_MISC_SYSMMU_MISC_CLK_S2,
3694 "gout_misc_sysmmu_misc_clk_s2", "mout_misc_bus_user",
3695 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_MISC_IPCLKPORT_CLK_S2,
3696 21, 0, 0),
3697 GATE(CLK_GOUT_MISC_SYSMMU_SSS_CLK_S1,
3698 "gout_misc_sysmmu_sss_clk_s1", "mout_misc_sss_user",
3699 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSMMU_SSS_IPCLKPORT_CLK_S1,
3700 21, 0, 0),
3701 GATE(CLK_GOUT_MISC_SYSREG_MISC_PCLK,
3702 "gout_misc_sysreg_misc_pclk", "dout_misc_busp",
3703 CLK_CON_GAT_GOUT_BLK_MISC_UID_SYSREG_MISC_IPCLKPORT_PCLK,
3704 21, 0, 0),
3705 GATE(CLK_GOUT_MISC_TMU_SUB_PCLK,
3706 "gout_misc_tmu_sub_pclk", "dout_misc_busp",
3707 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_SUB_IPCLKPORT_PCLK,
3708 21, 0, 0),
3709 GATE(CLK_GOUT_MISC_TMU_TOP_PCLK,
3710 "gout_misc_tmu_top_pclk", "dout_misc_busp",
3711 CLK_CON_GAT_GOUT_BLK_MISC_UID_TMU_TOP_IPCLKPORT_PCLK,
3712 21, 0, 0),
3713 GATE(CLK_GOUT_MISC_WDT_CLUSTER0_PCLK,
3714 "gout_misc_wdt_cluster0_pclk", "dout_misc_busp",
3715 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER0_IPCLKPORT_PCLK,
3716 21, 0, 0),
3717 GATE(CLK_GOUT_MISC_WDT_CLUSTER1_PCLK,
3718 "gout_misc_wdt_cluster1_pclk", "dout_misc_busp",
3719 CLK_CON_GAT_GOUT_BLK_MISC_UID_WDT_CLUSTER1_IPCLKPORT_PCLK,
3720 21, 0, 0),
3721 GATE(CLK_GOUT_MISC_XIU_D_MISC_ACLK,
3722 "gout_misc_xiu_d_misc_aclk", "mout_misc_bus_user",
3723 CLK_CON_GAT_GOUT_BLK_MISC_UID_XIU_D_MISC_IPCLKPORT_ACLK,
3724 21, 0, 0),
3725 };
3726
3727 static const struct samsung_cmu_info misc_cmu_info __initconst = {
3728 .mux_clks = misc_mux_clks,
3729 .nr_mux_clks = ARRAY_SIZE(misc_mux_clks),
3730 .div_clks = misc_div_clks,
3731 .nr_div_clks = ARRAY_SIZE(misc_div_clks),
3732 .gate_clks = misc_gate_clks,
3733 .nr_gate_clks = ARRAY_SIZE(misc_gate_clks),
3734 .nr_clk_ids = CLKS_NR_MISC,
3735 .clk_regs = misc_clk_regs,
3736 .nr_clk_regs = ARRAY_SIZE(misc_clk_regs),
3737 .sysreg_clk_regs = dcrg_memclk_sysreg,
3738 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_memclk_sysreg),
3739 .clk_name = "bus",
3740 .auto_clock_gate = true,
3741 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
3742 .option_offset = MISC_CMU_MISC_CONTROLLER_OPTION,
3743 .drcg_offset = GS101_DRCG_EN_OFFSET,
3744 .memclk_offset = GS101_MEMCLK_OFFSET,
3745 };
3746
gs101_cmu_misc_init(struct device_node * np)3747 static void __init gs101_cmu_misc_init(struct device_node *np)
3748 {
3749 exynos_arm64_register_cmu(NULL, np, &misc_cmu_info);
3750 }
3751
3752 /* Register CMU_MISC early, as it's needed for MCT timer */
3753 CLK_OF_DECLARE(gs101_cmu_misc, "google,gs101-cmu-misc",
3754 gs101_cmu_misc_init);
3755
3756 /* ---- CMU_PERIC0 ---------------------------------------------------------- */
3757
3758 /* Register Offset definitions for CMU_PERIC0 (0x10800000) */
3759 #define PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER 0x0600
3760 #define PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER 0x0604
3761 #define PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER 0x0610
3762 #define PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER 0x0614
3763 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0620
3764 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER 0x0624
3765 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0640
3766 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER 0x0644
3767 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0650
3768 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER 0x0654
3769 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0660
3770 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER 0x0664
3771 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0670
3772 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER 0x0674
3773 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0680
3774 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER 0x0684
3775 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0690
3776 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER 0x0694
3777 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a0
3778 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER 0x06a4
3779 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b0
3780 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER 0x06b4
3781 #define PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c0
3782 #define PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER 0x06c4
3783 #define PERIC0_CMU_PERIC0_CONTROLLER_OPTION 0x0800
3784 #define CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0 0x0810
3785 #define CLK_CON_DIV_DIV_CLK_PERIC0_I3C 0x1800
3786 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART 0x1804
3787 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI 0x180c
3788 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI 0x1810
3789 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI 0x1814
3790 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI 0x1820
3791 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI 0x1824
3792 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI 0x1828
3793 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI 0x182c
3794 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI 0x1830
3795 #define CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI 0x1834
3796 #define CLK_CON_BUF_CLKBUF_PERIC0_IP 0x2000
3797 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK 0x2004
3798 #define CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK 0x2008
3799 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK 0x200c
3800 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK 0x2010
3801 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK 0x2014
3802 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK 0x2018
3803 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0 0x201c
3804 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1 0x2020
3805 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10 0x2024
3806 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11 0x2028
3807 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12 0x202c
3808 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13 0x2030
3809 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14 0x2034
3810 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15 0x2038
3811 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2 0x203c
3812 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3 0x2040
3813 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4 0x2044
3814 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5 0x2048
3815 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6 0x204c
3816 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7 0x2050
3817 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8 0x2054
3818 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9 0x2058
3819 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0 0x205c
3820 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1 0x2060
3821 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10 0x2064
3822 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11 0x2068
3823 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12 0x206c
3824 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13 0x2070
3825 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14 0x2074
3826 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15 0x2078
3827 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2 0x207c
3828 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3 0x2080
3829 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4 0x2084
3830 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5 0x2088
3831 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6 0x208c
3832 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7 0x2090
3833 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8 0x2094
3834 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9 0x2098
3835 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0 0x209c
3836 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2 0x20a4
3837 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0 0x20a8
3838 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2 0x20b0
3839 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK 0x20b4
3840 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK 0x20b8
3841 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK 0x20bc
3842 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK 0x20c4
3843 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK 0x20c8
3844 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK 0x20cc
3845 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK 0x20d0
3846 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK 0x20d4
3847 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK 0x20d8
3848 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK 0x20dc
3849 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK 0x20e0
3850 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK 0x20e4
3851 #define CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK 0x20e8
3852 #define DMYQCH_CON_PERIC0_TOP0_QCH_S1 0x3000
3853 #define DMYQCH_CON_PERIC0_TOP0_QCH_S2 0x3004
3854 #define DMYQCH_CON_PERIC0_TOP0_QCH_S3 0x3008
3855 #define DMYQCH_CON_PERIC0_TOP0_QCH_S4 0x300c
3856 #define DMYQCH_CON_PERIC0_TOP0_QCH_S5 0x3010
3857 #define DMYQCH_CON_PERIC0_TOP0_QCH_S6 0x3014
3858 #define DMYQCH_CON_PERIC0_TOP0_QCH_S7 0x3018
3859 #define DMYQCH_CON_PERIC0_TOP0_QCH_S8 0x301c
3860 #define PCH_CON_LHM_AXI_P_PERIC0_PCH 0x3020
3861 #define QCH_CON_D_TZPC_PERIC0_QCH 0x3024
3862 #define QCH_CON_GPC_PERIC0_QCH 0x3028
3863 #define QCH_CON_GPIO_PERIC0_QCH 0x302c
3864 #define QCH_CON_LHM_AXI_P_PERIC0_QCH 0x3030
3865 #define QCH_CON_PERIC0_CMU_PERIC0_QCH 0x3034
3866 #define QCH_CON_PERIC0_TOP0_QCH_I3C1 0x3038
3867 #define QCH_CON_PERIC0_TOP0_QCH_I3C2 0x303c
3868 #define QCH_CON_PERIC0_TOP0_QCH_I3C3 0x3040
3869 #define QCH_CON_PERIC0_TOP0_QCH_I3C4 0x3044
3870 #define QCH_CON_PERIC0_TOP0_QCH_I3C5 0x3048
3871 #define QCH_CON_PERIC0_TOP0_QCH_I3C6 0x304c
3872 #define QCH_CON_PERIC0_TOP0_QCH_I3C7 0x3050
3873 #define QCH_CON_PERIC0_TOP0_QCH_I3C8 0x3054
3874 #define QCH_CON_PERIC0_TOP0_QCH_USI1_USI 0x3058
3875 #define QCH_CON_PERIC0_TOP0_QCH_USI2_USI 0x305c
3876 #define QCH_CON_PERIC0_TOP0_QCH_USI3_USI 0x3060
3877 #define QCH_CON_PERIC0_TOP0_QCH_USI4_USI 0x3064
3878 #define QCH_CON_PERIC0_TOP0_QCH_USI5_USI 0x3068
3879 #define QCH_CON_PERIC0_TOP0_QCH_USI6_USI 0x306c
3880 #define QCH_CON_PERIC0_TOP0_QCH_USI7_USI 0x3070
3881 #define QCH_CON_PERIC0_TOP0_QCH_USI8_USI 0x3074
3882 #define QCH_CON_PERIC0_TOP1_QCH_USI0_UART 0x3078
3883 #define QCH_CON_PERIC0_TOP1_QCH_USI14_UART 0x307c
3884 #define QCH_CON_SYSREG_PERIC0_QCH 0x3080
3885 #define QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0 0x3c00
3886
3887 static const unsigned long peric0_clk_regs[] __initconst = {
3888 PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER,
3889 PLL_CON1_MUX_CLKCMU_PERIC0_BUS_USER,
3890 PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER,
3891 PLL_CON1_MUX_CLKCMU_PERIC0_I3C_USER,
3892 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER,
3893 PLL_CON1_MUX_CLKCMU_PERIC0_USI0_UART_USER,
3894 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER,
3895 PLL_CON1_MUX_CLKCMU_PERIC0_USI14_USI_USER,
3896 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER,
3897 PLL_CON1_MUX_CLKCMU_PERIC0_USI1_USI_USER,
3898 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER,
3899 PLL_CON1_MUX_CLKCMU_PERIC0_USI2_USI_USER,
3900 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER,
3901 PLL_CON1_MUX_CLKCMU_PERIC0_USI3_USI_USER,
3902 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER,
3903 PLL_CON1_MUX_CLKCMU_PERIC0_USI4_USI_USER,
3904 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER,
3905 PLL_CON1_MUX_CLKCMU_PERIC0_USI5_USI_USER,
3906 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER,
3907 PLL_CON1_MUX_CLKCMU_PERIC0_USI6_USI_USER,
3908 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER,
3909 PLL_CON1_MUX_CLKCMU_PERIC0_USI7_USI_USER,
3910 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER,
3911 PLL_CON1_MUX_CLKCMU_PERIC0_USI8_USI_USER,
3912 PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
3913 CLKOUT_CON_BLK_PERIC0_CMU_PERIC0_CLKOUT0,
3914 CLK_CON_DIV_DIV_CLK_PERIC0_I3C,
3915 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART,
3916 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI,
3917 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI,
3918 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI,
3919 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI,
3920 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI,
3921 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI,
3922 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI,
3923 CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI,
3924 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI,
3925 CLK_CON_BUF_CLKBUF_PERIC0_IP,
3926 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
3927 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
3928 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
3929 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
3930 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
3931 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
3932 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
3933 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
3934 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
3935 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
3936 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
3937 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
3938 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
3939 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
3940 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
3941 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
3942 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
3943 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
3944 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
3945 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
3946 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
3947 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
3948 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
3949 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
3950 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
3951 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
3952 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
3953 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
3954 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
3955 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
3956 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
3957 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
3958 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
3959 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
3960 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
3961 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
3962 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
3963 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
3964 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
3965 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
3966 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
3967 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
3968 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
3969 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
3970 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
3971 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
3972 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
3973 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
3974 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
3975 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
3976 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
3977 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
3978 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
3979 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
3980 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
3981 DMYQCH_CON_PERIC0_TOP0_QCH_S1,
3982 DMYQCH_CON_PERIC0_TOP0_QCH_S2,
3983 DMYQCH_CON_PERIC0_TOP0_QCH_S3,
3984 DMYQCH_CON_PERIC0_TOP0_QCH_S4,
3985 DMYQCH_CON_PERIC0_TOP0_QCH_S5,
3986 DMYQCH_CON_PERIC0_TOP0_QCH_S6,
3987 DMYQCH_CON_PERIC0_TOP0_QCH_S7,
3988 DMYQCH_CON_PERIC0_TOP0_QCH_S8,
3989 PCH_CON_LHM_AXI_P_PERIC0_PCH,
3990 QCH_CON_D_TZPC_PERIC0_QCH,
3991 QCH_CON_GPC_PERIC0_QCH,
3992 QCH_CON_GPIO_PERIC0_QCH,
3993 QCH_CON_LHM_AXI_P_PERIC0_QCH,
3994 QCH_CON_PERIC0_CMU_PERIC0_QCH,
3995 QCH_CON_PERIC0_TOP0_QCH_I3C1,
3996 QCH_CON_PERIC0_TOP0_QCH_I3C2,
3997 QCH_CON_PERIC0_TOP0_QCH_I3C3,
3998 QCH_CON_PERIC0_TOP0_QCH_I3C4,
3999 QCH_CON_PERIC0_TOP0_QCH_I3C5,
4000 QCH_CON_PERIC0_TOP0_QCH_I3C6,
4001 QCH_CON_PERIC0_TOP0_QCH_I3C7,
4002 QCH_CON_PERIC0_TOP0_QCH_I3C8,
4003 QCH_CON_PERIC0_TOP0_QCH_USI1_USI,
4004 QCH_CON_PERIC0_TOP0_QCH_USI2_USI,
4005 QCH_CON_PERIC0_TOP0_QCH_USI3_USI,
4006 QCH_CON_PERIC0_TOP0_QCH_USI4_USI,
4007 QCH_CON_PERIC0_TOP0_QCH_USI5_USI,
4008 QCH_CON_PERIC0_TOP0_QCH_USI6_USI,
4009 QCH_CON_PERIC0_TOP0_QCH_USI7_USI,
4010 QCH_CON_PERIC0_TOP0_QCH_USI8_USI,
4011 QCH_CON_PERIC0_TOP1_QCH_USI0_UART,
4012 QCH_CON_PERIC0_TOP1_QCH_USI14_UART,
4013 QCH_CON_SYSREG_PERIC0_QCH,
4014 QUEUE_CTRL_REG_BLK_PERIC0_CMU_PERIC0,
4015 };
4016
4017 /* List of parent clocks for Muxes in CMU_PERIC0 */
4018 PNAME(mout_peric0_bus_user_p) = { "oscclk", "dout_cmu_peric0_bus" };
4019 PNAME(mout_peric0_i3c_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
4020 PNAME(mout_peric0_usi0_uart_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
4021 PNAME(mout_peric0_usi_usi_user_p) = { "oscclk", "dout_cmu_peric0_ip" };
4022
4023 static const struct samsung_mux_clock peric0_mux_clks[] __initconst = {
4024 MUX(CLK_MOUT_PERIC0_BUS_USER, "mout_peric0_bus_user",
4025 mout_peric0_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_BUS_USER, 4, 1),
4026 MUX(CLK_MOUT_PERIC0_I3C_USER, "mout_peric0_i3c_user",
4027 mout_peric0_i3c_user_p, PLL_CON0_MUX_CLKCMU_PERIC0_I3C_USER, 4, 1),
4028 MUX(CLK_MOUT_PERIC0_USI0_UART_USER,
4029 "mout_peric0_usi0_uart_user", mout_peric0_usi0_uart_user_p,
4030 PLL_CON0_MUX_CLKCMU_PERIC0_USI0_UART_USER, 4, 1),
4031 nMUX(CLK_MOUT_PERIC0_USI14_USI_USER,
4032 "mout_peric0_usi14_usi_user", mout_peric0_usi_usi_user_p,
4033 PLL_CON0_MUX_CLKCMU_PERIC0_USI14_USI_USER, 4, 1),
4034 nMUX(CLK_MOUT_PERIC0_USI1_USI_USER,
4035 "mout_peric0_usi1_usi_user", mout_peric0_usi_usi_user_p,
4036 PLL_CON0_MUX_CLKCMU_PERIC0_USI1_USI_USER, 4, 1),
4037 nMUX(CLK_MOUT_PERIC0_USI2_USI_USER,
4038 "mout_peric0_usi2_usi_user", mout_peric0_usi_usi_user_p,
4039 PLL_CON0_MUX_CLKCMU_PERIC0_USI2_USI_USER, 4, 1),
4040 nMUX(CLK_MOUT_PERIC0_USI3_USI_USER,
4041 "mout_peric0_usi3_usi_user", mout_peric0_usi_usi_user_p,
4042 PLL_CON0_MUX_CLKCMU_PERIC0_USI3_USI_USER, 4, 1),
4043 nMUX(CLK_MOUT_PERIC0_USI4_USI_USER,
4044 "mout_peric0_usi4_usi_user", mout_peric0_usi_usi_user_p,
4045 PLL_CON0_MUX_CLKCMU_PERIC0_USI4_USI_USER, 4, 1),
4046 nMUX(CLK_MOUT_PERIC0_USI5_USI_USER,
4047 "mout_peric0_usi5_usi_user", mout_peric0_usi_usi_user_p,
4048 PLL_CON0_MUX_CLKCMU_PERIC0_USI5_USI_USER, 4, 1),
4049 nMUX(CLK_MOUT_PERIC0_USI6_USI_USER,
4050 "mout_peric0_usi6_usi_user", mout_peric0_usi_usi_user_p,
4051 PLL_CON0_MUX_CLKCMU_PERIC0_USI6_USI_USER, 4, 1),
4052 nMUX(CLK_MOUT_PERIC0_USI7_USI_USER,
4053 "mout_peric0_usi7_usi_user", mout_peric0_usi_usi_user_p,
4054 PLL_CON0_MUX_CLKCMU_PERIC0_USI7_USI_USER, 4, 1),
4055 nMUX(CLK_MOUT_PERIC0_USI8_USI_USER,
4056 "mout_peric0_usi8_usi_user", mout_peric0_usi_usi_user_p,
4057 PLL_CON0_MUX_CLKCMU_PERIC0_USI8_USI_USER, 4, 1),
4058 };
4059
4060 static const struct samsung_div_clock peric0_div_clks[] __initconst = {
4061 DIV(CLK_DOUT_PERIC0_I3C, "dout_peric0_i3c", "mout_peric0_i3c_user",
4062 CLK_CON_DIV_DIV_CLK_PERIC0_I3C, 0, 4),
4063 DIV(CLK_DOUT_PERIC0_USI0_UART,
4064 "dout_peric0_usi0_uart", "mout_peric0_usi0_uart_user",
4065 CLK_CON_DIV_DIV_CLK_PERIC0_USI0_UART, 0, 4),
4066 DIV_F(CLK_DOUT_PERIC0_USI14_USI,
4067 "dout_peric0_usi14_usi", "mout_peric0_usi14_usi_user",
4068 CLK_CON_DIV_DIV_CLK_PERIC0_USI14_USI, 0, 4,
4069 CLK_SET_RATE_PARENT, 0),
4070 DIV_F(CLK_DOUT_PERIC0_USI1_USI,
4071 "dout_peric0_usi1_usi", "mout_peric0_usi1_usi_user",
4072 CLK_CON_DIV_DIV_CLK_PERIC0_USI1_USI, 0, 4,
4073 CLK_SET_RATE_PARENT, 0),
4074 DIV_F(CLK_DOUT_PERIC0_USI2_USI,
4075 "dout_peric0_usi2_usi", "mout_peric0_usi2_usi_user",
4076 CLK_CON_DIV_DIV_CLK_PERIC0_USI2_USI, 0, 4,
4077 CLK_SET_RATE_PARENT, 0),
4078 DIV_F(CLK_DOUT_PERIC0_USI3_USI,
4079 "dout_peric0_usi3_usi", "mout_peric0_usi3_usi_user",
4080 CLK_CON_DIV_DIV_CLK_PERIC0_USI3_USI, 0, 4,
4081 CLK_SET_RATE_PARENT, 0),
4082 DIV_F(CLK_DOUT_PERIC0_USI4_USI,
4083 "dout_peric0_usi4_usi", "mout_peric0_usi4_usi_user",
4084 CLK_CON_DIV_DIV_CLK_PERIC0_USI4_USI, 0, 4,
4085 CLK_SET_RATE_PARENT, 0),
4086 DIV_F(CLK_DOUT_PERIC0_USI5_USI,
4087 "dout_peric0_usi5_usi", "mout_peric0_usi5_usi_user",
4088 CLK_CON_DIV_DIV_CLK_PERIC0_USI5_USI, 0, 4,
4089 CLK_SET_RATE_PARENT, 0),
4090 DIV_F(CLK_DOUT_PERIC0_USI6_USI,
4091 "dout_peric0_usi6_usi", "mout_peric0_usi6_usi_user",
4092 CLK_CON_DIV_DIV_CLK_PERIC0_USI6_USI, 0, 4,
4093 CLK_SET_RATE_PARENT, 0),
4094 DIV_F(CLK_DOUT_PERIC0_USI7_USI,
4095 "dout_peric0_usi7_usi", "mout_peric0_usi7_usi_user",
4096 CLK_CON_DIV_DIV_CLK_PERIC0_USI7_USI, 0, 4,
4097 CLK_SET_RATE_PARENT, 0),
4098 DIV_F(CLK_DOUT_PERIC0_USI8_USI,
4099 "dout_peric0_usi8_usi", "mout_peric0_usi8_usi_user",
4100 CLK_CON_DIV_DIV_CLK_PERIC0_USI8_USI, 0, 4,
4101 CLK_SET_RATE_PARENT, 0),
4102 };
4103
4104 static const struct samsung_gate_clock peric0_gate_clks[] __initconst = {
4105 /* Disabling this clock makes the system hang. Mark the clock as critical. */
4106 GATE(CLK_GOUT_PERIC0_PERIC0_CMU_PERIC0_PCLK,
4107 "gout_peric0_peric0_cmu_peric0_pclk", "mout_peric0_bus_user",
4108 CLK_CON_GAT_CLK_BLK_PERIC0_UID_PERIC0_CMU_PERIC0_IPCLKPORT_PCLK,
4109 21, CLK_IS_CRITICAL, 0),
4110 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_OSCCLK_CLK,
4111 "gout_peric0_clk_peric0_oscclk_clk", "oscclk",
4112 CLK_CON_GAT_CLK_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_OSCCLK_IPCLKPORT_CLK,
4113 21, 0, 0),
4114 GATE(CLK_GOUT_PERIC0_D_TZPC_PERIC0_PCLK,
4115 "gout_peric0_d_tzpc_peric0_pclk", "mout_peric0_bus_user",
4116 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_D_TZPC_PERIC0_IPCLKPORT_PCLK,
4117 21, 0, 0),
4118 GATE(CLK_GOUT_PERIC0_GPC_PERIC0_PCLK,
4119 "gout_peric0_gpc_peric0_pclk", "mout_peric0_bus_user",
4120 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPC_PERIC0_IPCLKPORT_PCLK,
4121 21, 0, 0),
4122 GATE(CLK_GOUT_PERIC0_GPIO_PERIC0_PCLK,
4123 "gout_peric0_gpio_peric0_pclk", "mout_peric0_bus_user",
4124 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_GPIO_PERIC0_IPCLKPORT_PCLK,
4125 21, CLK_IGNORE_UNUSED, 0),
4126 /* Disabling this clock makes the system hang. Mark the clock as critical. */
4127 GATE(CLK_GOUT_PERIC0_LHM_AXI_P_PERIC0_I_CLK,
4128 "gout_peric0_lhm_axi_p_peric0_i_clk", "mout_peric0_bus_user",
4129 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_LHM_AXI_P_PERIC0_IPCLKPORT_I_CLK,
4130 21, CLK_IS_CRITICAL, 0),
4131 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_0,
4132 "gout_peric0_peric0_top0_ipclk_0", "dout_peric0_usi1_usi",
4133 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_0,
4134 21, CLK_SET_RATE_PARENT, 0),
4135 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_1,
4136 "gout_peric0_peric0_top0_ipclk_1", "dout_peric0_usi2_usi",
4137 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_1,
4138 21, CLK_SET_RATE_PARENT, 0),
4139 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_10,
4140 "gout_peric0_peric0_top0_ipclk_10", "dout_peric0_i3c",
4141 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_10,
4142 21, 0, 0),
4143 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_11,
4144 "gout_peric0_peric0_top0_ipclk_11", "dout_peric0_i3c",
4145 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_11,
4146 21, 0, 0),
4147 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_12,
4148 "gout_peric0_peric0_top0_ipclk_12", "dout_peric0_i3c",
4149 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_12,
4150 21, 0, 0),
4151 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_13,
4152 "gout_peric0_peric0_top0_ipclk_13", "dout_peric0_i3c",
4153 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_13,
4154 21, 0, 0),
4155 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_14,
4156 "gout_peric0_peric0_top0_ipclk_14", "dout_peric0_i3c",
4157 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_14,
4158 21, 0, 0),
4159 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_15,
4160 "gout_peric0_peric0_top0_ipclk_15", "dout_peric0_i3c",
4161 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_15,
4162 21, 0, 0),
4163 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_2,
4164 "gout_peric0_peric0_top0_ipclk_2", "dout_peric0_usi3_usi",
4165 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_2,
4166 21, CLK_SET_RATE_PARENT, 0),
4167 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_3,
4168 "gout_peric0_peric0_top0_ipclk_3", "dout_peric0_usi4_usi",
4169 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_3,
4170 21, CLK_SET_RATE_PARENT, 0),
4171 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_4,
4172 "gout_peric0_peric0_top0_ipclk_4", "dout_peric0_usi5_usi",
4173 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_4,
4174 21, CLK_SET_RATE_PARENT, 0),
4175 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_5,
4176 "gout_peric0_peric0_top0_ipclk_5", "dout_peric0_usi6_usi",
4177 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_5,
4178 21, CLK_SET_RATE_PARENT, 0),
4179 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_6,
4180 "gout_peric0_peric0_top0_ipclk_6", "dout_peric0_usi7_usi",
4181 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_6,
4182 21, CLK_SET_RATE_PARENT, 0),
4183 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_7,
4184 "gout_peric0_peric0_top0_ipclk_7", "dout_peric0_usi8_usi",
4185 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_7,
4186 21, CLK_SET_RATE_PARENT, 0),
4187 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_8,
4188 "gout_peric0_peric0_top0_ipclk_8", "dout_peric0_i3c",
4189 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_8,
4190 21, 0, 0),
4191 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_IPCLK_9,
4192 "gout_peric0_peric0_top0_ipclk_9", "dout_peric0_i3c",
4193 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_IPCLK_9,
4194 21, 0, 0),
4195 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_0,
4196 "gout_peric0_peric0_top0_pclk_0", "mout_peric0_bus_user",
4197 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_0,
4198 21, 0, 0),
4199 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_1,
4200 "gout_peric0_peric0_top0_pclk_1", "mout_peric0_bus_user",
4201 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_1,
4202 21, 0, 0),
4203 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_10,
4204 "gout_peric0_peric0_top0_pclk_10", "mout_peric0_bus_user",
4205 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_10,
4206 21, 0, 0),
4207 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_11,
4208 "gout_peric0_peric0_top0_pclk_11", "mout_peric0_bus_user",
4209 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_11,
4210 21, 0, 0),
4211 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_12,
4212 "gout_peric0_peric0_top0_pclk_12", "mout_peric0_bus_user",
4213 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_12,
4214 21, 0, 0),
4215 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_13,
4216 "gout_peric0_peric0_top0_pclk_13", "mout_peric0_bus_user",
4217 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_13,
4218 21, 0, 0),
4219 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_14,
4220 "gout_peric0_peric0_top0_pclk_14", "mout_peric0_bus_user",
4221 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_14,
4222 21, 0, 0),
4223 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_15,
4224 "gout_peric0_peric0_top0_pclk_15", "mout_peric0_bus_user",
4225 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_15,
4226 21, 0, 0),
4227 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_2,
4228 "gout_peric0_peric0_top0_pclk_2", "mout_peric0_bus_user",
4229 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_2,
4230 21, 0, 0),
4231 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_3,
4232 "gout_peric0_peric0_top0_pclk_3", "mout_peric0_bus_user",
4233 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_3,
4234 21, 0, 0),
4235 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_4,
4236 "gout_peric0_peric0_top0_pclk_4", "mout_peric0_bus_user",
4237 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_4,
4238 21, 0, 0),
4239 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_5,
4240 "gout_peric0_peric0_top0_pclk_5", "mout_peric0_bus_user",
4241 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_5,
4242 21, 0, 0),
4243 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_6,
4244 "gout_peric0_peric0_top0_pclk_6", "mout_peric0_bus_user",
4245 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_6,
4246 21, 0, 0),
4247 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_7,
4248 "gout_peric0_peric0_top0_pclk_7", "mout_peric0_bus_user",
4249 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_7,
4250 21, 0, 0),
4251 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_8,
4252 "gout_peric0_peric0_top0_pclk_8", "mout_peric0_bus_user",
4253 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_8,
4254 21, 0, 0),
4255 GATE(CLK_GOUT_PERIC0_PERIC0_TOP0_PCLK_9,
4256 "gout_peric0_peric0_top0_pclk_9", "mout_peric0_bus_user",
4257 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP0_IPCLKPORT_PCLK_9,
4258 21, 0, 0),
4259 /* Disabling this clock makes the system hang. Mark the clock as critical. */
4260 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_0,
4261 "gout_peric0_peric0_top1_ipclk_0", "dout_peric0_usi0_uart",
4262 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_0,
4263 21, CLK_IS_CRITICAL, 0),
4264 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_IPCLK_2,
4265 "gout_peric0_peric0_top1_ipclk_2", "dout_peric0_usi14_usi",
4266 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_IPCLK_2,
4267 21, CLK_SET_RATE_PARENT, 0),
4268 /* Disabling this clock makes the system hang. Mark the clock as critical. */
4269 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_0,
4270 "gout_peric0_peric0_top1_pclk_0", "mout_peric0_bus_user",
4271 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_0,
4272 21, CLK_IS_CRITICAL, 0),
4273 GATE(CLK_GOUT_PERIC0_PERIC0_TOP1_PCLK_2,
4274 "gout_peric0_peric0_top1_pclk_2", "mout_peric0_bus_user",
4275 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_PERIC0_TOP1_IPCLKPORT_PCLK_2,
4276 21, 0, 0),
4277 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_BUSP_CLK,
4278 "gout_peric0_clk_peric0_busp_clk", "mout_peric0_bus_user",
4279 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_BUSP_IPCLKPORT_CLK,
4280 21, 0, 0),
4281 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_I3C_CLK,
4282 "gout_peric0_clk_peric0_i3c_clk", "dout_peric0_i3c",
4283 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_I3C_IPCLKPORT_CLK,
4284 21, 0, 0),
4285 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI0_UART_CLK,
4286 "gout_peric0_clk_peric0_usi0_uart_clk", "dout_peric0_usi0_uart",
4287 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI0_UART_IPCLKPORT_CLK,
4288 21, 0, 0),
4289 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI14_USI_CLK,
4290 "gout_peric0_clk_peric0_usi14_usi_clk", "dout_peric0_usi14_usi",
4291 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI14_USI_IPCLKPORT_CLK,
4292 21, 0, 0),
4293 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI1_USI_CLK,
4294 "gout_peric0_clk_peric0_usi1_usi_clk", "dout_peric0_usi1_usi",
4295 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI1_USI_IPCLKPORT_CLK,
4296 21, 0, 0),
4297 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI2_USI_CLK,
4298 "gout_peric0_clk_peric0_usi2_usi_clk", "dout_peric0_usi2_usi",
4299 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI2_USI_IPCLKPORT_CLK,
4300 21, 0, 0),
4301 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI3_USI_CLK,
4302 "gout_peric0_clk_peric0_usi3_usi_clk", "dout_peric0_usi3_usi",
4303 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI3_USI_IPCLKPORT_CLK,
4304 21, 0, 0),
4305 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI4_USI_CLK,
4306 "gout_peric0_clk_peric0_usi4_usi_clk", "dout_peric0_usi4_usi",
4307 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI4_USI_IPCLKPORT_CLK,
4308 21, 0, 0),
4309 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI5_USI_CLK,
4310 "gout_peric0_clk_peric0_usi5_usi_clk", "dout_peric0_usi5_usi",
4311 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI5_USI_IPCLKPORT_CLK,
4312 21, 0, 0),
4313 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI6_USI_CLK,
4314 "gout_peric0_clk_peric0_usi6_usi_clk", "dout_peric0_usi6_usi",
4315 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI6_USI_IPCLKPORT_CLK,
4316 21, 0, 0),
4317 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI7_USI_CLK,
4318 "gout_peric0_clk_peric0_usi7_usi_clk", "dout_peric0_usi7_usi",
4319 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI7_USI_IPCLKPORT_CLK,
4320 21, 0, 0),
4321 GATE(CLK_GOUT_PERIC0_CLK_PERIC0_USI8_USI_CLK,
4322 "gout_peric0_clk_peric0_usi8_usi_clk", "dout_peric0_usi8_usi",
4323 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_RSTNSYNC_CLK_PERIC0_USI8_USI_IPCLKPORT_CLK,
4324 21, 0, 0),
4325 GATE(CLK_GOUT_PERIC0_SYSREG_PERIC0_PCLK,
4326 "gout_peric0_sysreg_peric0_pclk", "mout_peric0_bus_user",
4327 CLK_CON_GAT_GOUT_BLK_PERIC0_UID_SYSREG_PERIC0_IPCLKPORT_PCLK,
4328 21, 0, 0),
4329 };
4330
4331 static const unsigned long dcrg_sysreg[] __initconst = {
4332 GS101_DRCG_EN_OFFSET,
4333 };
4334
4335 static const struct samsung_cmu_info peric0_cmu_info __initconst = {
4336 .mux_clks = peric0_mux_clks,
4337 .nr_mux_clks = ARRAY_SIZE(peric0_mux_clks),
4338 .div_clks = peric0_div_clks,
4339 .nr_div_clks = ARRAY_SIZE(peric0_div_clks),
4340 .gate_clks = peric0_gate_clks,
4341 .nr_gate_clks = ARRAY_SIZE(peric0_gate_clks),
4342 .nr_clk_ids = CLKS_NR_PERIC0,
4343 .clk_regs = peric0_clk_regs,
4344 .nr_clk_regs = ARRAY_SIZE(peric0_clk_regs),
4345 .sysreg_clk_regs = dcrg_sysreg,
4346 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg),
4347 .clk_name = "bus",
4348 .auto_clock_gate = true,
4349 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
4350 .option_offset = PERIC0_CMU_PERIC0_CONTROLLER_OPTION,
4351 .drcg_offset = GS101_DRCG_EN_OFFSET,
4352 };
4353
4354 /* ---- CMU_PERIC1 ---------------------------------------------------------- */
4355
4356 /* Register Offset definitions for CMU_PERIC1 (0x10c00000) */
4357 #define PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER 0x0600
4358 #define PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER 0x0604
4359 #define PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER 0x0610
4360 #define PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER 0x0614
4361 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0620
4362 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER 0x0624
4363 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0630
4364 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER 0x0634
4365 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0640
4366 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER 0x0644
4367 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0650
4368 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER 0x0654
4369 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0660
4370 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER 0x0664
4371 #define PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0670
4372 #define PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER 0x0674
4373 #define PERIC1_CMU_PERIC1_CONTROLLER_OPTION 0x0800
4374 #define CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0 0x0810
4375 #define CLK_CON_DIV_DIV_CLK_PERIC1_I3C 0x1800
4376 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI 0x1804
4377 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI 0x1808
4378 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI 0x180c
4379 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI 0x1810
4380 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI 0x1814
4381 #define CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI 0x1818
4382 #define CLK_CON_BUF_CLKBUF_PERIC1_IP 0x2000
4383 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK 0x2004
4384 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK 0x2008
4385 #define CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK 0x200c
4386 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK 0x2010
4387 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK 0x2014
4388 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK 0x2018
4389 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK 0x201c
4390 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1 0x2020
4391 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2 0x2024
4392 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3 0x2028
4393 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4 0x202c
4394 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5 0x2030
4395 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6 0x2034
4396 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8 0x2038
4397 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1 0x203c
4398 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15 0x2040
4399 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2 0x2044
4400 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3 0x2048
4401 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4 0x204c
4402 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5 0x2050
4403 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6 0x2054
4404 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8 0x2058
4405 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK 0x205c
4406 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK 0x2060
4407 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK 0x2064
4408 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK 0x2068
4409 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK 0x206c
4410 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK 0x2070
4411 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK 0x2074
4412 #define CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK 0x2078
4413 #define DMYQCH_CON_PERIC1_TOP0_QCH_S 0x3000
4414 #define PCH_CON_LHM_AXI_P_PERIC1_PCH 0x3004
4415 #define QCH_CON_D_TZPC_PERIC1_QCH 0x3008
4416 #define QCH_CON_GPC_PERIC1_QCH 0x300c
4417 #define QCH_CON_GPIO_PERIC1_QCH 0x3010
4418 #define QCH_CON_LHM_AXI_P_PERIC1_QCH 0x3014
4419 #define QCH_CON_PERIC1_CMU_PERIC1_QCH 0x3018
4420 #define QCH_CON_PERIC1_TOP0_QCH_I3C0 0x301c
4421 #define QCH_CON_PERIC1_TOP0_QCH_PWM 0x3020
4422 #define QCH_CON_PERIC1_TOP0_QCH_USI0_USI 0x3024
4423 #define QCH_CON_PERIC1_TOP0_QCH_USI10_USI 0x3028
4424 #define QCH_CON_PERIC1_TOP0_QCH_USI11_USI 0x302c
4425 #define QCH_CON_PERIC1_TOP0_QCH_USI12_USI 0x3030
4426 #define QCH_CON_PERIC1_TOP0_QCH_USI13_USI 0x3034
4427 #define QCH_CON_PERIC1_TOP0_QCH_USI9_USI 0x3038
4428 #define QCH_CON_SYSREG_PERIC1_QCH 0x303c
4429 #define QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1 0x3c00
4430
4431 static const unsigned long peric1_clk_regs[] __initconst = {
4432 PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER,
4433 PLL_CON1_MUX_CLKCMU_PERIC1_BUS_USER,
4434 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER,
4435 PLL_CON1_MUX_CLKCMU_PERIC1_I3C_USER,
4436 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER,
4437 PLL_CON1_MUX_CLKCMU_PERIC1_USI0_USI_USER,
4438 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4439 PLL_CON1_MUX_CLKCMU_PERIC1_USI10_USI_USER,
4440 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4441 PLL_CON1_MUX_CLKCMU_PERIC1_USI11_USI_USER,
4442 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4443 PLL_CON1_MUX_CLKCMU_PERIC1_USI12_USI_USER,
4444 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER,
4445 PLL_CON1_MUX_CLKCMU_PERIC1_USI13_USI_USER,
4446 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER,
4447 PLL_CON1_MUX_CLKCMU_PERIC1_USI9_USI_USER,
4448 PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
4449 CLKOUT_CON_BLK_PERIC1_CMU_PERIC1_CLKOUT0,
4450 CLK_CON_DIV_DIV_CLK_PERIC1_I3C,
4451 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI,
4452 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI,
4453 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI,
4454 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI,
4455 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI,
4456 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI,
4457 CLK_CON_BUF_CLKBUF_PERIC1_IP,
4458 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
4459 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
4460 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
4461 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
4462 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
4463 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
4464 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
4465 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
4466 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
4467 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
4468 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
4469 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
4470 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
4471 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
4472 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
4473 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
4474 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
4475 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
4476 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
4477 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
4478 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
4479 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
4480 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
4481 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
4482 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
4483 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
4484 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
4485 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
4486 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
4487 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
4488 DMYQCH_CON_PERIC1_TOP0_QCH_S,
4489 PCH_CON_LHM_AXI_P_PERIC1_PCH,
4490 QCH_CON_D_TZPC_PERIC1_QCH,
4491 QCH_CON_GPC_PERIC1_QCH,
4492 QCH_CON_GPIO_PERIC1_QCH,
4493 QCH_CON_LHM_AXI_P_PERIC1_QCH,
4494 QCH_CON_PERIC1_CMU_PERIC1_QCH,
4495 QCH_CON_PERIC1_TOP0_QCH_I3C0,
4496 QCH_CON_PERIC1_TOP0_QCH_PWM,
4497 QCH_CON_PERIC1_TOP0_QCH_USI0_USI,
4498 QCH_CON_PERIC1_TOP0_QCH_USI10_USI,
4499 QCH_CON_PERIC1_TOP0_QCH_USI11_USI,
4500 QCH_CON_PERIC1_TOP0_QCH_USI12_USI,
4501 QCH_CON_PERIC1_TOP0_QCH_USI13_USI,
4502 QCH_CON_PERIC1_TOP0_QCH_USI9_USI,
4503 QCH_CON_SYSREG_PERIC1_QCH,
4504 QUEUE_CTRL_REG_BLK_PERIC1_CMU_PERIC1,
4505 };
4506
4507 /* List of parent clocks for Muxes in CMU_PERIC1 */
4508 PNAME(mout_peric1_bus_user_p) = { "oscclk", "dout_cmu_peric1_bus" };
4509 PNAME(mout_peric1_nonbususer_p) = { "oscclk", "dout_cmu_peric1_ip" };
4510
4511 static const struct samsung_mux_clock peric1_mux_clks[] __initconst = {
4512 MUX(CLK_MOUT_PERIC1_BUS_USER, "mout_peric1_bus_user",
4513 mout_peric1_bus_user_p, PLL_CON0_MUX_CLKCMU_PERIC1_BUS_USER, 4, 1),
4514 MUX(CLK_MOUT_PERIC1_I3C_USER,
4515 "mout_peric1_i3c_user", mout_peric1_nonbususer_p,
4516 PLL_CON0_MUX_CLKCMU_PERIC1_I3C_USER, 4, 1),
4517 nMUX(CLK_MOUT_PERIC1_USI0_USI_USER,
4518 "mout_peric1_usi0_usi_user", mout_peric1_nonbususer_p,
4519 PLL_CON0_MUX_CLKCMU_PERIC1_USI0_USI_USER, 4, 1),
4520 nMUX(CLK_MOUT_PERIC1_USI10_USI_USER,
4521 "mout_peric1_usi10_usi_user", mout_peric1_nonbususer_p,
4522 PLL_CON0_MUX_CLKCMU_PERIC1_USI10_USI_USER, 4, 1),
4523 nMUX(CLK_MOUT_PERIC1_USI11_USI_USER,
4524 "mout_peric1_usi11_usi_user", mout_peric1_nonbususer_p,
4525 PLL_CON0_MUX_CLKCMU_PERIC1_USI11_USI_USER, 4, 1),
4526 nMUX(CLK_MOUT_PERIC1_USI12_USI_USER,
4527 "mout_peric1_usi12_usi_user", mout_peric1_nonbususer_p,
4528 PLL_CON0_MUX_CLKCMU_PERIC1_USI12_USI_USER, 4, 1),
4529 nMUX(CLK_MOUT_PERIC1_USI13_USI_USER,
4530 "mout_peric1_usi13_usi_user", mout_peric1_nonbususer_p,
4531 PLL_CON0_MUX_CLKCMU_PERIC1_USI13_USI_USER, 4, 1),
4532 nMUX(CLK_MOUT_PERIC1_USI9_USI_USER,
4533 "mout_peric1_usi9_usi_user", mout_peric1_nonbususer_p,
4534 PLL_CON0_MUX_CLKCMU_PERIC1_USI9_USI_USER, 4, 1),
4535 };
4536
4537 static const struct samsung_div_clock peric1_div_clks[] __initconst = {
4538 DIV(CLK_DOUT_PERIC1_I3C, "dout_peric1_i3c", "mout_peric1_i3c_user",
4539 CLK_CON_DIV_DIV_CLK_PERIC1_I3C, 0, 4),
4540 DIV_F(CLK_DOUT_PERIC1_USI0_USI,
4541 "dout_peric1_usi0_usi", "mout_peric1_usi0_usi_user",
4542 CLK_CON_DIV_DIV_CLK_PERIC1_USI0_USI, 0, 4,
4543 CLK_SET_RATE_PARENT, 0),
4544 DIV_F(CLK_DOUT_PERIC1_USI10_USI,
4545 "dout_peric1_usi10_usi", "mout_peric1_usi10_usi_user",
4546 CLK_CON_DIV_DIV_CLK_PERIC1_USI10_USI, 0, 4,
4547 CLK_SET_RATE_PARENT, 0),
4548 DIV_F(CLK_DOUT_PERIC1_USI11_USI,
4549 "dout_peric1_usi11_usi", "mout_peric1_usi11_usi_user",
4550 CLK_CON_DIV_DIV_CLK_PERIC1_USI11_USI, 0, 4,
4551 CLK_SET_RATE_PARENT, 0),
4552 DIV_F(CLK_DOUT_PERIC1_USI12_USI,
4553 "dout_peric1_usi12_usi", "mout_peric1_usi12_usi_user",
4554 CLK_CON_DIV_DIV_CLK_PERIC1_USI12_USI, 0, 4,
4555 CLK_SET_RATE_PARENT, 0),
4556 DIV_F(CLK_DOUT_PERIC1_USI13_USI,
4557 "dout_peric1_usi13_usi", "mout_peric1_usi13_usi_user",
4558 CLK_CON_DIV_DIV_CLK_PERIC1_USI13_USI, 0, 4,
4559 CLK_SET_RATE_PARENT, 0),
4560 DIV_F(CLK_DOUT_PERIC1_USI9_USI,
4561 "dout_peric1_usi9_usi", "mout_peric1_usi9_usi_user",
4562 CLK_CON_DIV_DIV_CLK_PERIC1_USI9_USI, 0, 4,
4563 CLK_SET_RATE_PARENT, 0),
4564 };
4565
4566 static const struct samsung_gate_clock peric1_gate_clks[] __initconst = {
4567 GATE(CLK_GOUT_PERIC1_PCLK,
4568 "gout_peric1_peric1_pclk", "mout_peric1_bus_user",
4569 CLK_CON_GAT_CLK_BLK_PERIC1_UID_PERIC1_CMU_PERIC1_IPCLKPORT_PCLK,
4570 21, CLK_IS_CRITICAL, 0),
4571 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_I3C_CLK,
4572 "gout_peric1_clk_peric1_i3c_clk", "dout_peric1_i3c",
4573 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_I3C_IPCLKPORT_CLK,
4574 21, 0, 0),
4575 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_OSCCLK_CLK,
4576 "gout_peric1_clk_peric1_oscclk_clk", "oscclk",
4577 CLK_CON_GAT_CLK_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_OSCCLK_IPCLKPORT_CLK,
4578 21, 0, 0),
4579 GATE(CLK_GOUT_PERIC1_D_TZPC_PERIC1_PCLK,
4580 "gout_peric1_d_tzpc_peric1_pclk", "mout_peric1_bus_user",
4581 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_D_TZPC_PERIC1_IPCLKPORT_PCLK,
4582 21, 0, 0),
4583 GATE(CLK_GOUT_PERIC1_GPC_PERIC1_PCLK,
4584 "gout_peric1_gpc_peric1_pclk", "mout_peric1_bus_user",
4585 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPC_PERIC1_IPCLKPORT_PCLK,
4586 21, 0, 0),
4587 GATE(CLK_GOUT_PERIC1_GPIO_PERIC1_PCLK,
4588 "gout_peric1_gpio_peric1_pclk", "mout_peric1_bus_user",
4589 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_GPIO_PERIC1_IPCLKPORT_PCLK,
4590 21, CLK_IGNORE_UNUSED, 0),
4591 GATE(CLK_GOUT_PERIC1_LHM_AXI_P_PERIC1_I_CLK,
4592 "gout_peric1_lhm_axi_p_peric1_i_clk", "mout_peric1_bus_user",
4593 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_LHM_AXI_P_PERIC1_IPCLKPORT_I_CLK,
4594 21, CLK_IS_CRITICAL, 0),
4595 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_1,
4596 "gout_peric1_peric1_top0_ipclk_1", "dout_peric1_usi0_usi",
4597 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_1,
4598 21, CLK_SET_RATE_PARENT, 0),
4599 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_2,
4600 "gout_peric1_peric1_top0_ipclk_2", "dout_peric1_usi9_usi",
4601 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_2,
4602 21, CLK_SET_RATE_PARENT, 0),
4603 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_3,
4604 "gout_peric1_peric1_top0_ipclk_3", "dout_peric1_usi10_usi",
4605 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_3,
4606 21, CLK_SET_RATE_PARENT, 0),
4607 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_4,
4608 "gout_peric1_peric1_top0_ipclk_4", "dout_peric1_usi11_usi",
4609 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_4,
4610 21, CLK_SET_RATE_PARENT, 0),
4611 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_5,
4612 "gout_peric1_peric1_top0_ipclk_5", "dout_peric1_usi12_usi",
4613 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_5,
4614 21, CLK_SET_RATE_PARENT, 0),
4615 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_6,
4616 "gout_peric1_peric1_top0_ipclk_6", "dout_peric1_usi13_usi",
4617 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_6,
4618 21, CLK_SET_RATE_PARENT, 0),
4619 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_IPCLK_8,
4620 "gout_peric1_peric1_top0_ipclk_8", "dout_peric1_i3c",
4621 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_IPCLK_8,
4622 21, 0, 0),
4623 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_1,
4624 "gout_peric1_peric1_top0_pclk_1", "mout_peric1_bus_user",
4625 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_1,
4626 21, 0, 0),
4627 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_15,
4628 "gout_peric1_peric1_top0_pclk_15", "mout_peric1_bus_user",
4629 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_15,
4630 21, 0, 0),
4631 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_2,
4632 "gout_peric1_peric1_top0_pclk_2", "mout_peric1_bus_user",
4633 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_2,
4634 21, 0, 0),
4635 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_3,
4636 "gout_peric1_peric1_top0_pclk_3", "mout_peric1_bus_user",
4637 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_3,
4638 21, 0, 0),
4639 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_4,
4640 "gout_peric1_peric1_top0_pclk_4", "mout_peric1_bus_user",
4641 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_4,
4642 21, 0, 0),
4643 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_5,
4644 "gout_peric1_peric1_top0_pclk_5", "mout_peric1_bus_user",
4645 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_5,
4646 21, 0, 0),
4647 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_6,
4648 "gout_peric1_peric1_top0_pclk_6", "mout_peric1_bus_user",
4649 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_6,
4650 21, 0, 0),
4651 GATE(CLK_GOUT_PERIC1_PERIC1_TOP0_PCLK_8,
4652 "gout_peric1_peric1_top0_pclk_8", "mout_peric1_bus_user",
4653 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_PERIC1_TOP0_IPCLKPORT_PCLK_8,
4654 21, 0, 0),
4655 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_BUSP_CLK,
4656 "gout_peric1_clk_peric1_busp_clk", "mout_peric1_bus_user",
4657 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_BUSP_IPCLKPORT_CLK,
4658 21, 0, 0),
4659 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI0_USI_CLK,
4660 "gout_peric1_clk_peric1_usi0_usi_clk", "dout_peric1_usi0_usi",
4661 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI0_USI_IPCLKPORT_CLK,
4662 21, 0, 0),
4663 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI10_USI_CLK,
4664 "gout_peric1_clk_peric1_usi10_usi_clk", "dout_peric1_usi10_usi",
4665 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI10_USI_IPCLKPORT_CLK,
4666 21, 0, 0),
4667 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI11_USI_CLK,
4668 "gout_peric1_clk_peric1_usi11_usi_clk", "dout_peric1_usi11_usi",
4669 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI11_USI_IPCLKPORT_CLK,
4670 21, 0, 0),
4671 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI12_USI_CLK,
4672 "gout_peric1_clk_peric1_usi12_usi_clk", "dout_peric1_usi12_usi",
4673 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI12_USI_IPCLKPORT_CLK,
4674 21, 0, 0),
4675 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI13_USI_CLK,
4676 "gout_peric1_clk_peric1_usi13_usi_clk", "dout_peric1_usi13_usi",
4677 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI13_USI_IPCLKPORT_CLK,
4678 21, 0, 0),
4679 GATE(CLK_GOUT_PERIC1_CLK_PERIC1_USI9_USI_CLK,
4680 "gout_peric1_clk_peric1_usi9_usi_clk", "dout_peric1_usi9_usi",
4681 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_RSTNSYNC_CLK_PERIC1_USI9_USI_IPCLKPORT_CLK,
4682 21, 0, 0),
4683 GATE(CLK_GOUT_PERIC1_SYSREG_PERIC1_PCLK,
4684 "gout_peric1_sysreg_peric1_pclk", "mout_peric1_bus_user",
4685 CLK_CON_GAT_GOUT_BLK_PERIC1_UID_SYSREG_PERIC1_IPCLKPORT_PCLK,
4686 21, 0, 0),
4687 };
4688
4689 static const struct samsung_cmu_info peric1_cmu_info __initconst = {
4690 .mux_clks = peric1_mux_clks,
4691 .nr_mux_clks = ARRAY_SIZE(peric1_mux_clks),
4692 .div_clks = peric1_div_clks,
4693 .nr_div_clks = ARRAY_SIZE(peric1_div_clks),
4694 .gate_clks = peric1_gate_clks,
4695 .nr_gate_clks = ARRAY_SIZE(peric1_gate_clks),
4696 .nr_clk_ids = CLKS_NR_PERIC1,
4697 .clk_regs = peric1_clk_regs,
4698 .nr_clk_regs = ARRAY_SIZE(peric1_clk_regs),
4699 .sysreg_clk_regs = dcrg_sysreg,
4700 .nr_sysreg_clk_regs = ARRAY_SIZE(dcrg_sysreg),
4701 .clk_name = "bus",
4702 .auto_clock_gate = true,
4703 .gate_dbg_offset = GS101_GATE_DBG_OFFSET,
4704 .option_offset = PERIC1_CMU_PERIC1_CONTROLLER_OPTION,
4705 .drcg_offset = GS101_DRCG_EN_OFFSET,
4706 };
4707
4708 /* ---- platform_driver ----------------------------------------------------- */
4709
gs101_cmu_probe(struct platform_device * pdev)4710 static int __init gs101_cmu_probe(struct platform_device *pdev)
4711 {
4712 const struct samsung_cmu_info *info;
4713 struct device *dev = &pdev->dev;
4714
4715 info = of_device_get_match_data(dev);
4716 exynos_arm64_register_cmu(dev, dev->of_node, info);
4717
4718 return 0;
4719 }
4720
4721 static const struct of_device_id gs101_cmu_of_match[] = {
4722 {
4723 .compatible = "google,gs101-cmu-apm",
4724 .data = &apm_cmu_info,
4725 }, {
4726 .compatible = "google,gs101-cmu-dpu",
4727 .data = &dpu_cmu_info,
4728 }, {
4729 .compatible = "google,gs101-cmu-hsi0",
4730 .data = &hsi0_cmu_info,
4731 }, {
4732 .compatible = "google,gs101-cmu-hsi2",
4733 .data = &hsi2_cmu_info,
4734 }, {
4735 .compatible = "google,gs101-cmu-peric0",
4736 .data = &peric0_cmu_info,
4737 }, {
4738 .compatible = "google,gs101-cmu-peric1",
4739 .data = &peric1_cmu_info,
4740 }, {
4741 },
4742 };
4743
4744 static struct platform_driver gs101_cmu_driver __refdata = {
4745 .driver = {
4746 .name = "gs101-cmu",
4747 .of_match_table = gs101_cmu_of_match,
4748 .suppress_bind_attrs = true,
4749 },
4750 .probe = gs101_cmu_probe,
4751 };
4752
gs101_cmu_init(void)4753 static int __init gs101_cmu_init(void)
4754 {
4755 return platform_driver_register(&gs101_cmu_driver);
4756 }
4757 core_initcall(gs101_cmu_init);
4758