| /linux/arch/arm/kernel/ |
| H A D | fiqasm.S | 26 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
39 mov r2, #PSR_I_BIT | PSR_F_BIT | FIQ_MODE
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| H A D | entry-armv.S | 323 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
324 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
328 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
329 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
337 ARM( msr cpsr_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
338 THUMB( mov r0, #ABT_MODE | PSR_I_BIT | PSR_F_BIT )
342 ARM( msr cpsr_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
343 THUMB( mov r0, #SVC_MODE | PSR_I_BIT | PSR_F_BIT )
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| H A D | iwmmxt.S | 192 orr r2, ip, #PSR_I_BIT @ disable interrupts
239 orr r2, ip, #PSR_I_BIT @ disable interrupts
277 orr r2, ip, #PSR_I_BIT @ disable interrupts
340 orr ip, r2, #PSR_I_BIT @ disable interrupts
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| H A D | setup.c | 581 PLC_r (PSR_F_BIT | PSR_I_BIT | IRQ_MODE), in cpu_init()
583 PLC_r (PSR_F_BIT | PSR_I_BIT | ABT_MODE), in cpu_init()
585 PLC_r (PSR_F_BIT | PSR_I_BIT | UND_MODE), in cpu_init()
587 PLC_r (PSR_F_BIT | PSR_I_BIT | FIQ_MODE), in cpu_init()
589 PLC_l (PSR_F_BIT | PSR_I_BIT | SVC_MODE) in cpu_init()
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| H A D | entry-header.S | 346 tst r1, #PSR_I_BIT | 0x0f
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| /linux/arch/arm/include/asm/ |
| H A D | ptrace.h | 50 (!((regs)->ARM_cpsr & PSR_I_BIT))
68 if ((regs->ARM_cpsr & PSR_I_BIT) == 0) { in valid_user_regs()
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| H A D | irqflags.h | 19 #define IRQMASK_I_BIT PSR_I_BIT
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| H A D | assembler.h | 107 msr cpsr_c, #PSR_I_BIT | SVC_MODE
197 tst \oldcpsr, #PSR_I_BIT
446 orr \reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
461 setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
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| /linux/arch/arm/mach-s3c/ |
| H A D | sleep-s3c64xx.S | 40 msr cpsr_c, #PSR_I_BIT | PSR_F_BIT | SVC_MODE
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| /linux/tools/testing/selftests/arm64/signal/testcases/ |
| H A D | mangle_pstate_invalid_daif_bits.c | 23 uc->uc_mcontext.pstate |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT; in mangle_invalid_pstate_run()
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| /linux/arch/arm64/include/asm/ |
| H A D | ptrace.h | 20 (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
238 return (regs->pstate & PSR_I_BIT) || !irqs_priority_unmasked(regs); in regs_get_register()
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| H A D | cpuidle.h | 20 write_sysreg(c->daif_bits | PSR_I_BIT | PSR_F_BIT, \
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| H A D | efi.h | 51 #define ARCH_EFI_IRQ_FLAGS_MASK (PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
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| H A D | irqflags.h | 104 return flags & PSR_I_BIT; in __daif_irqs_disabled_flags()
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| /linux/arch/arm/mach-rockchip/ |
| H A D | sleep.S | 20 setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off
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| /linux/arch/arm/mm/ |
| H A D | proc-feroceon.S | 264 orr r3, r2, #PSR_I_BIT
311 orr r3, r2, #PSR_I_BIT
343 orr r3, r2, #PSR_I_BIT
375 orr r3, r2, #PSR_I_BIT
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| H A D | proc-xsc3.S | 110 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
457 mov r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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| H A D | proc-xscale.S | 148 mov r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
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| /linux/arch/arm64/include/uapi/asm/ |
| H A D | ptrace.h | 46 #define PSR_I_BIT 0x00000080 macro
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| /linux/tools/testing/selftests/kvm/arm64/ |
| H A D | mmio_sign_ext.c | 20 #define SPSR_EL0 (PSR_MODE_EL0t | PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT)
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| /linux/arch/arm64/kvm/hyp/nvhe/ |
| H A D | host.S | 114 mov lr, #(PSR_F_BIT | PSR_I_BIT | PSR_A_BIT | PSR_D_BIT |\
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| H A D | hyp-main.c | 1703 spsr_el2 |= PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT |
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| /linux/arch/arm/probes/kprobes/ |
| H A D | test-core.c | 1146 regs->ARM_cpsr |= PSR_I_BIT; in setup_test_context()
1234 regs->ARM_cpsr &= ~PSR_I_BIT; in test_after_pre_handler()
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| /linux/arch/arm64/kernel/ |
| H A D | process.c | 193 pstate & PSR_I_BIT ? 'I' : 'i', in print_pstate()
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| H A D | smp.c | 187 WARN_ON(!(cpuflags & PSR_I_BIT)); in init_gic_priority_masking()
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