xref: /linux/drivers/accel/habanalabs/include/gaudi2/asic_reg/psoc_reset_conf_masks.h (revision 9a87ffc99ec8eb8d35eed7c4f816d75f5cc9662e)
1 /* SPDX-License-Identifier: GPL-2.0
2  *
3  * Copyright 2016-2020 HabanaLabs, Ltd.
4  * All Rights Reserved.
5  *
6  */
7 
8 /************************************
9  ** This is an auto-generated file **
10  **       DO NOT EDIT BELOW        **
11  ************************************/
12 
13 #ifndef ASIC_REG_PSOC_RESET_CONF_MASKS_H_
14 #define ASIC_REG_PSOC_RESET_CONF_MASKS_H_
15 
16 /*
17  *****************************************
18  *   PSOC_RESET_CONF
19  *   (Prototype: PSOC_RESET_CONF)
20  *****************************************
21  */
22 
23 /* PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG */
24 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_SHIFT 0
25 #define PSOC_RESET_CONF_PSOC_PRSTN_RST_CFG_EN_MASK 0x1
26 
27 /* PSOC_RESET_CONF_PSOC_SOFT_RST_CFG */
28 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_SHIFT 0
29 #define PSOC_RESET_CONF_PSOC_SOFT_RST_CFG_EN_MASK 0x1
30 
31 /* PSOC_RESET_CONF_PSOC_FW_RST_CFG */
32 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_SHIFT 0
33 #define PSOC_RESET_CONF_PSOC_FW_RST_CFG_EN_MASK 0x1
34 
35 /* PSOC_RESET_CONF_PSOC_WD_RST_CFG */
36 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_SHIFT 0
37 #define PSOC_RESET_CONF_PSOC_WD_RST_CFG_EN_MASK 0x1
38 
39 /* PSOC_RESET_CONF_PSOC_MNL_RST_CFG */
40 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_SHIFT 0
41 #define PSOC_RESET_CONF_PSOC_MNL_RST_CFG_EN_MASK 0x1
42 
43 /* PSOC_RESET_CONF_PSOC_FLR_RST_CFG */
44 #define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_SHIFT 0
45 #define PSOC_RESET_CONF_PSOC_FLR_RST_CFG_EN_MASK 0x1
46 
47 /* PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG */
48 #define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_SHIFT 0
49 #define PSOC_RESET_CONF_PSOC_ECC_DERR_RST_CFG_EN_MASK 0x1
50 
51 /* PSOC_RESET_CONF_PSOC_SW_RST_CFG */
52 #define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_SHIFT 0
53 #define PSOC_RESET_CONF_PSOC_SW_RST_CFG_EN_MASK 0x1
54 
55 /* PSOC_RESET_CONF_CPU_PRSTN_RST_CFG */
56 #define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_SHIFT 0
57 #define PSOC_RESET_CONF_CPU_PRSTN_RST_CFG_EN_MASK 0x1
58 
59 /* PSOC_RESET_CONF_CPU_SOFT_RST_CFG */
60 #define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_SHIFT 0
61 #define PSOC_RESET_CONF_CPU_SOFT_RST_CFG_EN_MASK 0x1
62 
63 /* PSOC_RESET_CONF_CPU_FW_RST_CFG */
64 #define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_SHIFT 0
65 #define PSOC_RESET_CONF_CPU_FW_RST_CFG_EN_MASK 0x1
66 
67 /* PSOC_RESET_CONF_CPU_WD_RST_CFG */
68 #define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_SHIFT 0
69 #define PSOC_RESET_CONF_CPU_WD_RST_CFG_EN_MASK 0x1
70 
71 /* PSOC_RESET_CONF_CPU_MNL_RST_CFG */
72 #define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_SHIFT 0
73 #define PSOC_RESET_CONF_CPU_MNL_RST_CFG_EN_MASK 0x1
74 
75 /* PSOC_RESET_CONF_CPU_FLR_RST_CFG */
76 #define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_SHIFT 0
77 #define PSOC_RESET_CONF_CPU_FLR_RST_CFG_EN_MASK 0x1
78 
79 /* PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG */
80 #define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_SHIFT 0
81 #define PSOC_RESET_CONF_CPU_ECC_DERR_RST_CFG_EN_MASK 0x1
82 
83 /* PSOC_RESET_CONF_CPU_SW_RST_CFG */
84 #define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_SHIFT 0
85 #define PSOC_RESET_CONF_CPU_SW_RST_CFG_EN_MASK 0x1
86 
87 /* PSOC_RESET_CONF_ARC_PRSTN_RST_CFG */
88 #define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_SHIFT 0
89 #define PSOC_RESET_CONF_ARC_PRSTN_RST_CFG_EN_MASK 0x3
90 
91 /* PSOC_RESET_CONF_ARC_SOFT_RST_CFG */
92 #define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_SHIFT 0
93 #define PSOC_RESET_CONF_ARC_SOFT_RST_CFG_EN_MASK 0x3
94 
95 /* PSOC_RESET_CONF_ARC_FW_RST_CFG */
96 #define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_SHIFT 0
97 #define PSOC_RESET_CONF_ARC_FW_RST_CFG_EN_MASK 0x3
98 
99 /* PSOC_RESET_CONF_ARC_WD_RST_CFG */
100 #define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_SHIFT 0
101 #define PSOC_RESET_CONF_ARC_WD_RST_CFG_EN_MASK 0x3
102 
103 /* PSOC_RESET_CONF_ARC_MNL_RST_CFG */
104 #define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_SHIFT 0
105 #define PSOC_RESET_CONF_ARC_MNL_RST_CFG_EN_MASK 0x3
106 
107 /* PSOC_RESET_CONF_ARC_FLR_RST_CFG */
108 #define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_SHIFT 0
109 #define PSOC_RESET_CONF_ARC_FLR_RST_CFG_EN_MASK 0x3
110 
111 /* PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG */
112 #define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_SHIFT 0
113 #define PSOC_RESET_CONF_ARC_ECC_DERR_RST_CFG_EN_MASK 0x3
114 
115 /* PSOC_RESET_CONF_ARC_SW_RST_CFG */
116 #define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_SHIFT 0
117 #define PSOC_RESET_CONF_ARC_SW_RST_CFG_EN_MASK 0x3
118 
119 /* PSOC_RESET_CONF_SIF_PRSTN_RST_CFG */
120 #define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_SHIFT 0
121 #define PSOC_RESET_CONF_SIF_PRSTN_RST_CFG_EN_MASK 0xF
122 
123 /* PSOC_RESET_CONF_SIF_SOFT_RST_CFG */
124 #define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_SHIFT 0
125 #define PSOC_RESET_CONF_SIF_SOFT_RST_CFG_EN_MASK 0xF
126 
127 /* PSOC_RESET_CONF_SIF_FW_RST_CFG */
128 #define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_SHIFT 0
129 #define PSOC_RESET_CONF_SIF_FW_RST_CFG_EN_MASK 0xF
130 
131 /* PSOC_RESET_CONF_SIF_WD_RST_CFG */
132 #define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_SHIFT 0
133 #define PSOC_RESET_CONF_SIF_WD_RST_CFG_EN_MASK 0xF
134 
135 /* PSOC_RESET_CONF_SIF_MNL_RST_CFG */
136 #define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_SHIFT 0
137 #define PSOC_RESET_CONF_SIF_MNL_RST_CFG_EN_MASK 0xF
138 
139 /* PSOC_RESET_CONF_SIF_FLR_RST_CFG */
140 #define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_SHIFT 0
141 #define PSOC_RESET_CONF_SIF_FLR_RST_CFG_EN_MASK 0xF
142 
143 /* PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG */
144 #define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_SHIFT 0
145 #define PSOC_RESET_CONF_SIF_ECC_DERR_RST_CFG_EN_MASK 0xF
146 
147 /* PSOC_RESET_CONF_SIF_SW_RST_CFG */
148 #define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_SHIFT 0
149 #define PSOC_RESET_CONF_SIF_SW_RST_CFG_EN_MASK 0xF
150 
151 /* PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG */
152 #define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_SHIFT 0
153 #define PSOC_RESET_CONF_SRAM_PRSTN_RST_CFG_EN_MASK 0xF
154 
155 /* PSOC_RESET_CONF_SRAM_SOFT_RST_CFG */
156 #define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_SHIFT 0
157 #define PSOC_RESET_CONF_SRAM_SOFT_RST_CFG_EN_MASK 0xF
158 
159 /* PSOC_RESET_CONF_SRAM_FW_RST_CFG */
160 #define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_SHIFT 0
161 #define PSOC_RESET_CONF_SRAM_FW_RST_CFG_EN_MASK 0xF
162 
163 /* PSOC_RESET_CONF_SRAM_WD_RST_CFG */
164 #define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_SHIFT 0
165 #define PSOC_RESET_CONF_SRAM_WD_RST_CFG_EN_MASK 0xF
166 
167 /* PSOC_RESET_CONF_SRAM_MNL_RST_CFG */
168 #define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_SHIFT 0
169 #define PSOC_RESET_CONF_SRAM_MNL_RST_CFG_EN_MASK 0xF
170 
171 /* PSOC_RESET_CONF_SRAM_FLR_RST_CFG */
172 #define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_SHIFT 0
173 #define PSOC_RESET_CONF_SRAM_FLR_RST_CFG_EN_MASK 0xF
174 
175 /* PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG */
176 #define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_SHIFT 0
177 #define PSOC_RESET_CONF_SRAM_ECC_DERR_RST_CFG_EN_MASK 0xF
178 
179 /* PSOC_RESET_CONF_SRAM_SW_RST_CFG */
180 #define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_SHIFT 0
181 #define PSOC_RESET_CONF_SRAM_SW_RST_CFG_EN_MASK 0xF
182 
183 /* PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG */
184 #define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_SHIFT 0
185 #define PSOC_RESET_CONF_PCIE_CTRL_PRSTN_RST_CFG_EN_MASK 0x1
186 
187 /* PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG */
188 #define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_SHIFT 0
189 #define PSOC_RESET_CONF_PCIE_CTRL_SOFT_RST_CFG_EN_MASK 0x1
190 
191 /* PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG */
192 #define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_SHIFT 0
193 #define PSOC_RESET_CONF_PCIE_CTRL_FW_RST_CFG_EN_MASK 0x1
194 
195 /* PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG */
196 #define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_SHIFT 0
197 #define PSOC_RESET_CONF_PCIE_CTRL_WD_RST_CFG_EN_MASK 0x1
198 
199 /* PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG */
200 #define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_SHIFT 0
201 #define PSOC_RESET_CONF_PCIE_CTRL_MNL_RST_CFG_EN_MASK 0x1
202 
203 /* PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG */
204 #define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_SHIFT 0
205 #define PSOC_RESET_CONF_PCIE_CTRL_FLR_RST_CFG_EN_MASK 0x1
206 
207 /* PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG */
208 #define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_SHIFT 0
209 #define PSOC_RESET_CONF_PCIE_CTRL_ECC_DERR_RST_CFG_EN_MASK 0x1
210 
211 /* PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG */
212 #define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_SHIFT 0
213 #define PSOC_RESET_CONF_PCIE_CTRL_SW_RST_CFG_EN_MASK 0x1
214 
215 /* PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG */
216 #define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_SHIFT 0
217 #define PSOC_RESET_CONF_PCIE_PHY_CFG_PRSTN_RST_CFG_EN_MASK 0x1
218 
219 /* PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG */
220 #define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_SHIFT 0
221 #define PSOC_RESET_CONF_PCIE_PHY_CFG_SOFT_RST_CFG_EN_MASK 0x1
222 
223 /* PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG */
224 #define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_SHIFT 0
225 #define PSOC_RESET_CONF_PCIE_PHY_CFG_FW_RST_CFG_EN_MASK 0x1
226 
227 /* PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG */
228 #define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_SHIFT 0
229 #define PSOC_RESET_CONF_PCIE_PHY_CFG_WD_RST_CFG_EN_MASK 0x1
230 
231 /* PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG */
232 #define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_SHIFT 0
233 #define PSOC_RESET_CONF_PCIE_PHY_CFG_MNL_RST_CFG_EN_MASK 0x1
234 
235 /* PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG */
236 #define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_SHIFT 0
237 #define PSOC_RESET_CONF_PCIE_PHY_CFG_FLR_RST_CFG_EN_MASK 0x1
238 
239 /* PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG */
240 #define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_SHIFT 0
241 #define PSOC_RESET_CONF_PCIE_PHY_CFG_ECC_DERR_RST_CFG_EN_MASK 0x1
242 
243 /* PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG */
244 #define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_SHIFT 0
245 #define PSOC_RESET_CONF_PCIE_PHY_CFG_SW_RST_CFG_EN_MASK 0x1
246 
247 /* PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG */
248 #define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_SHIFT 0
249 #define PSOC_RESET_CONF_PCIE_IF_PRSTN_RST_CFG_EN_MASK 0x1
250 
251 /* PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG */
252 #define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_SHIFT 0
253 #define PSOC_RESET_CONF_PCIE_IF_SOFT_RST_CFG_EN_MASK 0x1
254 
255 /* PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG */
256 #define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_SHIFT 0
257 #define PSOC_RESET_CONF_PCIE_IF_FW_RST_CFG_EN_MASK 0x1
258 
259 /* PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG */
260 #define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_SHIFT 0
261 #define PSOC_RESET_CONF_PCIE_IF_WD_RST_CFG_EN_MASK 0x1
262 
263 /* PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG */
264 #define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_SHIFT 0
265 #define PSOC_RESET_CONF_PCIE_IF_MNL_RST_CFG_EN_MASK 0x1
266 
267 /* PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG */
268 #define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_SHIFT 0
269 #define PSOC_RESET_CONF_PCIE_IF_FLR_RST_CFG_EN_MASK 0x1
270 
271 /* PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG */
272 #define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_SHIFT 0
273 #define PSOC_RESET_CONF_PCIE_IF_ECC_DERR_RST_CFG_EN_MASK 0x1
274 
275 /* PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG */
276 #define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_SHIFT 0
277 #define PSOC_RESET_CONF_PCIE_IF_SW_RST_CFG_EN_MASK 0x1
278 
279 /* PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG */
280 #define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_SHIFT 0
281 #define PSOC_RESET_CONF_TPC_DIV_PRSTN_RST_CFG_EN_MASK 0x1F
282 
283 /* PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG */
284 #define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_SHIFT 0
285 #define PSOC_RESET_CONF_TPC_DIV_SOFT_RST_CFG_EN_MASK 0x1F
286 
287 /* PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG */
288 #define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_SHIFT 0
289 #define PSOC_RESET_CONF_TPC_DIV_FW_RST_CFG_EN_MASK 0x1F
290 
291 /* PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG */
292 #define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_SHIFT 0
293 #define PSOC_RESET_CONF_TPC_DIV_WD_RST_CFG_EN_MASK 0x1F
294 
295 /* PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG */
296 #define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_SHIFT 0
297 #define PSOC_RESET_CONF_TPC_DIV_MNL_RST_CFG_EN_MASK 0x1F
298 
299 /* PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG */
300 #define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_SHIFT 0
301 #define PSOC_RESET_CONF_TPC_DIV_FLR_RST_CFG_EN_MASK 0x1F
302 
303 /* PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG */
304 #define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0
305 #define PSOC_RESET_CONF_TPC_DIV_ECC_DERR_RST_CFG_EN_MASK 0x1F
306 
307 /* PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG */
308 #define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_SHIFT 0
309 #define PSOC_RESET_CONF_TPC_DIV_SW_RST_CFG_EN_MASK 0x1F
310 
311 /* PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG */
312 #define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_SHIFT 0
313 #define PSOC_RESET_CONF_HBM_DIV_PRSTN_RST_CFG_EN_MASK 0x3F
314 
315 /* PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG */
316 #define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_SHIFT 0
317 #define PSOC_RESET_CONF_HBM_DIV_SOFT_RST_CFG_EN_MASK 0x3F
318 
319 /* PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG */
320 #define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_SHIFT 0
321 #define PSOC_RESET_CONF_HBM_DIV_FW_RST_CFG_EN_MASK 0x3F
322 
323 /* PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG */
324 #define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_SHIFT 0
325 #define PSOC_RESET_CONF_HBM_DIV_WD_RST_CFG_EN_MASK 0x3F
326 
327 /* PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG */
328 #define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_SHIFT 0
329 #define PSOC_RESET_CONF_HBM_DIV_MNL_RST_CFG_EN_MASK 0x3F
330 
331 /* PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG */
332 #define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_SHIFT 0
333 #define PSOC_RESET_CONF_HBM_DIV_FLR_RST_CFG_EN_MASK 0x3F
334 
335 /* PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG */
336 #define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_SHIFT 0
337 #define PSOC_RESET_CONF_HBM_DIV_ECC_DERR_RST_CFG_EN_MASK 0x3F
338 
339 /* PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG */
340 #define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_SHIFT 0
341 #define PSOC_RESET_CONF_HBM_DIV_SW_RST_CFG_EN_MASK 0x3F
342 
343 /* PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG */
344 #define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_SHIFT 0
345 #define PSOC_RESET_CONF_PMMU_PRSTN_RST_CFG_EN_MASK 0x1
346 
347 /* PSOC_RESET_CONF_PMMU_SOFT_RST_CFG */
348 #define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_SHIFT 0
349 #define PSOC_RESET_CONF_PMMU_SOFT_RST_CFG_EN_MASK 0x1
350 
351 /* PSOC_RESET_CONF_PMMU_FW_RST_CFG */
352 #define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_SHIFT 0
353 #define PSOC_RESET_CONF_PMMU_FW_RST_CFG_EN_MASK 0x1
354 
355 /* PSOC_RESET_CONF_PMMU_WD_RST_CFG */
356 #define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_SHIFT 0
357 #define PSOC_RESET_CONF_PMMU_WD_RST_CFG_EN_MASK 0x1
358 
359 /* PSOC_RESET_CONF_PMMU_MNL_RST_CFG */
360 #define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_SHIFT 0
361 #define PSOC_RESET_CONF_PMMU_MNL_RST_CFG_EN_MASK 0x1
362 
363 /* PSOC_RESET_CONF_PMMU_FLR_RST_CFG */
364 #define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_SHIFT 0
365 #define PSOC_RESET_CONF_PMMU_FLR_RST_CFG_EN_MASK 0x1
366 
367 /* PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG */
368 #define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_SHIFT 0
369 #define PSOC_RESET_CONF_PMMU_ECC_DERR_RST_CFG_EN_MASK 0x1
370 
371 /* PSOC_RESET_CONF_PMMU_SW_RST_CFG */
372 #define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_SHIFT 0
373 #define PSOC_RESET_CONF_PMMU_SW_RST_CFG_EN_MASK 0x1
374 
375 /* PSOC_RESET_CONF_PM_PRSTN_RST_CFG */
376 #define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_SHIFT 0
377 #define PSOC_RESET_CONF_PM_PRSTN_RST_CFG_EN_MASK 0xF
378 
379 /* PSOC_RESET_CONF_PM_SOFT_RST_CFG */
380 #define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_SHIFT 0
381 #define PSOC_RESET_CONF_PM_SOFT_RST_CFG_EN_MASK 0xF
382 
383 /* PSOC_RESET_CONF_PM_FW_RST_CFG */
384 #define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_SHIFT 0
385 #define PSOC_RESET_CONF_PM_FW_RST_CFG_EN_MASK 0xF
386 
387 /* PSOC_RESET_CONF_PM_WD_RST_CFG */
388 #define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_SHIFT 0
389 #define PSOC_RESET_CONF_PM_WD_RST_CFG_EN_MASK 0xF
390 
391 /* PSOC_RESET_CONF_PM_MNL_RST_CFG */
392 #define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_SHIFT 0
393 #define PSOC_RESET_CONF_PM_MNL_RST_CFG_EN_MASK 0xF
394 
395 /* PSOC_RESET_CONF_PM_FLR_RST_CFG */
396 #define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_SHIFT 0
397 #define PSOC_RESET_CONF_PM_FLR_RST_CFG_EN_MASK 0xF
398 
399 /* PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG */
400 #define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_SHIFT 0
401 #define PSOC_RESET_CONF_PM_ECC_DERR_RST_CFG_EN_MASK 0xF
402 
403 /* PSOC_RESET_CONF_PM_SW_RST_CFG */
404 #define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_SHIFT 0
405 #define PSOC_RESET_CONF_PM_SW_RST_CFG_EN_MASK 0xF
406 
407 /* PSOC_RESET_CONF_TS_PRSTN_RST_CFG */
408 #define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_SHIFT 0
409 #define PSOC_RESET_CONF_TS_PRSTN_RST_CFG_EN_MASK 0xF
410 
411 /* PSOC_RESET_CONF_TS_SOFT_RST_CFG */
412 #define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_SHIFT 0
413 #define PSOC_RESET_CONF_TS_SOFT_RST_CFG_EN_MASK 0xF
414 
415 /* PSOC_RESET_CONF_TS_FW_RST_CFG */
416 #define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_SHIFT 0
417 #define PSOC_RESET_CONF_TS_FW_RST_CFG_EN_MASK 0xF
418 
419 /* PSOC_RESET_CONF_TS_WD_RST_CFG */
420 #define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_SHIFT 0
421 #define PSOC_RESET_CONF_TS_WD_RST_CFG_EN_MASK 0xF
422 
423 /* PSOC_RESET_CONF_TS_MNL_RST_CFG */
424 #define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_SHIFT 0
425 #define PSOC_RESET_CONF_TS_MNL_RST_CFG_EN_MASK 0xF
426 
427 /* PSOC_RESET_CONF_TS_FLR_RST_CFG */
428 #define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_SHIFT 0
429 #define PSOC_RESET_CONF_TS_FLR_RST_CFG_EN_MASK 0xF
430 
431 /* PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG */
432 #define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_SHIFT 0
433 #define PSOC_RESET_CONF_TS_ECC_DERR_RST_CFG_EN_MASK 0xF
434 
435 /* PSOC_RESET_CONF_TS_SW_RST_CFG */
436 #define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_SHIFT 0
437 #define PSOC_RESET_CONF_TS_SW_RST_CFG_EN_MASK 0xF
438 
439 /* PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG */
440 #define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_SHIFT 0
441 #define PSOC_RESET_CONF_TS_IF_PRSTN_RST_CFG_EN_MASK 0xF
442 
443 /* PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG */
444 #define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_SHIFT 0
445 #define PSOC_RESET_CONF_TS_IF_SOFT_RST_CFG_EN_MASK 0xF
446 
447 /* PSOC_RESET_CONF_TS_IF_FW_RST_CFG */
448 #define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_SHIFT 0
449 #define PSOC_RESET_CONF_TS_IF_FW_RST_CFG_EN_MASK 0xF
450 
451 /* PSOC_RESET_CONF_TS_IF_WD_RST_CFG */
452 #define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_SHIFT 0
453 #define PSOC_RESET_CONF_TS_IF_WD_RST_CFG_EN_MASK 0xF
454 
455 /* PSOC_RESET_CONF_TS_IF_MNL_RST_CFG */
456 #define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_SHIFT 0
457 #define PSOC_RESET_CONF_TS_IF_MNL_RST_CFG_EN_MASK 0xF
458 
459 /* PSOC_RESET_CONF_TS_IF_FLR_RST_CFG */
460 #define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_SHIFT 0
461 #define PSOC_RESET_CONF_TS_IF_FLR_RST_CFG_EN_MASK 0xF
462 
463 /* PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG */
464 #define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_SHIFT 0
465 #define PSOC_RESET_CONF_TS_IF_ECC_DERR_RST_CFG_EN_MASK 0xF
466 
467 /* PSOC_RESET_CONF_TS_IF_SW_RST_CFG */
468 #define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_SHIFT 0
469 #define PSOC_RESET_CONF_TS_IF_SW_RST_CFG_EN_MASK 0xF
470 
471 /* PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG */
472 #define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_SHIFT 0
473 #define PSOC_RESET_CONF_PLL_L_PRSTN_RST_CFG_EN_MASK 0xFFFFFFFF
474 
475 /* PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG */
476 #define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_SHIFT 0
477 #define PSOC_RESET_CONF_PLL_L_SOFT_RST_CFG_EN_MASK 0xFFFFFFFF
478 
479 /* PSOC_RESET_CONF_PLL_L_FW_RST_CFG */
480 #define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_SHIFT 0
481 #define PSOC_RESET_CONF_PLL_L_FW_RST_CFG_EN_MASK 0xFFFFFFFF
482 
483 /* PSOC_RESET_CONF_PLL_L_WD_RST_CFG */
484 #define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_SHIFT 0
485 #define PSOC_RESET_CONF_PLL_L_WD_RST_CFG_EN_MASK 0xFFFFFFFF
486 
487 /* PSOC_RESET_CONF_PLL_L_MNL_RST_CFG */
488 #define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_SHIFT 0
489 #define PSOC_RESET_CONF_PLL_L_MNL_RST_CFG_EN_MASK 0xFFFFFFFF
490 
491 /* PSOC_RESET_CONF_PLL_L_FLR_RST_CFG */
492 #define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_SHIFT 0
493 #define PSOC_RESET_CONF_PLL_L_FLR_RST_CFG_EN_MASK 0xFFFFFFFF
494 
495 /* PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG */
496 #define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_SHIFT 0
497 #define PSOC_RESET_CONF_PLL_L_ECC_DERR_RST_CFG_EN_MASK 0xFFFFFFFF
498 
499 /* PSOC_RESET_CONF_PLL_L_SW_RST_CFG */
500 #define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_SHIFT 0
501 #define PSOC_RESET_CONF_PLL_L_SW_RST_CFG_EN_MASK 0xFFFFFFFF
502 
503 /* PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG */
504 #define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_SHIFT 0
505 #define PSOC_RESET_CONF_PLL_H_PRSTN_RST_CFG_EN_MASK 0x3
506 
507 /* PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG */
508 #define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_SHIFT 0
509 #define PSOC_RESET_CONF_PLL_H_SOFT_RST_CFG_EN_MASK 0x3
510 
511 /* PSOC_RESET_CONF_PLL_H_FW_RST_CFG */
512 #define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_SHIFT 0
513 #define PSOC_RESET_CONF_PLL_H_FW_RST_CFG_EN_MASK 0x3
514 
515 /* PSOC_RESET_CONF_PLL_H_WD_RST_CFG */
516 #define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_SHIFT 0
517 #define PSOC_RESET_CONF_PLL_H_WD_RST_CFG_EN_MASK 0x3
518 
519 /* PSOC_RESET_CONF_PLL_H_MNL_RST_CFG */
520 #define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_SHIFT 0
521 #define PSOC_RESET_CONF_PLL_H_MNL_RST_CFG_EN_MASK 0x3
522 
523 /* PSOC_RESET_CONF_PLL_H_FLR_RST_CFG */
524 #define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_SHIFT 0
525 #define PSOC_RESET_CONF_PLL_H_FLR_RST_CFG_EN_MASK 0x3
526 
527 /* PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG */
528 #define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_SHIFT 0
529 #define PSOC_RESET_CONF_PLL_H_ECC_DERR_RST_CFG_EN_MASK 0x3
530 
531 /* PSOC_RESET_CONF_PLL_H_SW_RST_CFG */
532 #define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_SHIFT 0
533 #define PSOC_RESET_CONF_PLL_H_SW_RST_CFG_EN_MASK 0x3
534 
535 /* PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG */
536 #define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_SHIFT 0
537 #define PSOC_RESET_CONF_MME_EUS_PRSTN_RST_CFG_EN_MASK 0xF
538 
539 /* PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG */
540 #define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_SHIFT 0
541 #define PSOC_RESET_CONF_MME_EUS_SOFT_RST_CFG_EN_MASK 0xF
542 
543 /* PSOC_RESET_CONF_MME_EUS_FW_RST_CFG */
544 #define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_SHIFT 0
545 #define PSOC_RESET_CONF_MME_EUS_FW_RST_CFG_EN_MASK 0xF
546 
547 /* PSOC_RESET_CONF_MME_EUS_WD_RST_CFG */
548 #define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_SHIFT 0
549 #define PSOC_RESET_CONF_MME_EUS_WD_RST_CFG_EN_MASK 0xF
550 
551 /* PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG */
552 #define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_SHIFT 0
553 #define PSOC_RESET_CONF_MME_EUS_MNL_RST_CFG_EN_MASK 0xF
554 
555 /* PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG */
556 #define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_SHIFT 0
557 #define PSOC_RESET_CONF_MME_EUS_FLR_RST_CFG_EN_MASK 0xF
558 
559 /* PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG */
560 #define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_SHIFT 0
561 #define PSOC_RESET_CONF_MME_EUS_ECC_DERR_RST_CFG_EN_MASK 0xF
562 
563 /* PSOC_RESET_CONF_MME_EUS_SW_RST_CFG */
564 #define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_SHIFT 0
565 #define PSOC_RESET_CONF_MME_EUS_SW_RST_CFG_EN_MASK 0xF
566 
567 /* PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG */
568 #define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_SHIFT 0
569 #define PSOC_RESET_CONF_MSS_CLS_PRSTN_RST_CFG_EN_MASK 0xF
570 
571 /* PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG */
572 #define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_SHIFT 0
573 #define PSOC_RESET_CONF_MSS_CLS_SOFT_RST_CFG_EN_MASK 0xF
574 
575 /* PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG */
576 #define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_SHIFT 0
577 #define PSOC_RESET_CONF_MSS_CLS_FW_RST_CFG_EN_MASK 0xF
578 
579 /* PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG */
580 #define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_SHIFT 0
581 #define PSOC_RESET_CONF_MSS_CLS_WD_RST_CFG_EN_MASK 0xF
582 
583 /* PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG */
584 #define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_SHIFT 0
585 #define PSOC_RESET_CONF_MSS_CLS_MNL_RST_CFG_EN_MASK 0xF
586 
587 /* PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG */
588 #define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_SHIFT 0
589 #define PSOC_RESET_CONF_MSS_CLS_FLR_RST_CFG_EN_MASK 0xF
590 
591 /* PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG */
592 #define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_SHIFT 0
593 #define PSOC_RESET_CONF_MSS_CLS_ECC_DERR_RST_CFG_EN_MASK 0xF
594 
595 /* PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG */
596 #define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_SHIFT 0
597 #define PSOC_RESET_CONF_MSS_CLS_SW_RST_CFG_EN_MASK 0xF
598 
599 /* PSOC_RESET_CONF_TPC_PRSTN_RST_CFG */
600 #define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_SHIFT 0
601 #define PSOC_RESET_CONF_TPC_PRSTN_RST_CFG_EN_MASK 0x1FFFFFF
602 
603 /* PSOC_RESET_CONF_TPC_SOFT_RST_CFG */
604 #define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_SHIFT 0
605 #define PSOC_RESET_CONF_TPC_SOFT_RST_CFG_EN_MASK 0x1FFFFFF
606 
607 /* PSOC_RESET_CONF_TPC_FW_RST_CFG */
608 #define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_SHIFT 0
609 #define PSOC_RESET_CONF_TPC_FW_RST_CFG_EN_MASK 0x1FFFFFF
610 
611 /* PSOC_RESET_CONF_TPC_WD_RST_CFG */
612 #define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_SHIFT 0
613 #define PSOC_RESET_CONF_TPC_WD_RST_CFG_EN_MASK 0x1FFFFFF
614 
615 /* PSOC_RESET_CONF_TPC_MNL_RST_CFG */
616 #define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_SHIFT 0
617 #define PSOC_RESET_CONF_TPC_MNL_RST_CFG_EN_MASK 0x1FFFFFF
618 
619 /* PSOC_RESET_CONF_TPC_FLR_RST_CFG */
620 #define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_SHIFT 0
621 #define PSOC_RESET_CONF_TPC_FLR_RST_CFG_EN_MASK 0x1FFFFFF
622 
623 /* PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG */
624 #define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_SHIFT 0
625 #define PSOC_RESET_CONF_TPC_ECC_DERR_RST_CFG_EN_MASK 0x1FFFFFF
626 
627 /* PSOC_RESET_CONF_TPC_SW_RST_CFG */
628 #define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_SHIFT 0
629 #define PSOC_RESET_CONF_TPC_SW_RST_CFG_EN_MASK 0x1FFFFFF
630 
631 /* PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG */
632 #define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_SHIFT 0
633 #define PSOC_RESET_CONF_HIF_HMMU_PRSTN_RST_CFG_EN_MASK 0xF
634 
635 /* PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG */
636 #define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_SHIFT 0
637 #define PSOC_RESET_CONF_HIF_HMMU_SOFT_RST_CFG_EN_MASK 0xF
638 
639 /* PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG */
640 #define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_SHIFT 0
641 #define PSOC_RESET_CONF_HIF_HMMU_FW_RST_CFG_EN_MASK 0xF
642 
643 /* PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG */
644 #define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_SHIFT 0
645 #define PSOC_RESET_CONF_HIF_HMMU_WD_RST_CFG_EN_MASK 0xF
646 
647 /* PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG */
648 #define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_SHIFT 0
649 #define PSOC_RESET_CONF_HIF_HMMU_MNL_RST_CFG_EN_MASK 0xF
650 
651 /* PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG */
652 #define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_SHIFT 0
653 #define PSOC_RESET_CONF_HIF_HMMU_FLR_RST_CFG_EN_MASK 0xF
654 
655 /* PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG */
656 #define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_SHIFT 0
657 #define PSOC_RESET_CONF_HIF_HMMU_ECC_DERR_RST_CFG_EN_MASK 0xF
658 
659 /* PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG */
660 #define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_SHIFT 0
661 #define PSOC_RESET_CONF_HIF_HMMU_SW_RST_CFG_EN_MASK 0xF
662 
663 /* PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG */
664 #define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_SHIFT 0
665 #define PSOC_RESET_CONF_XBAR_PRSTN_RST_CFG_EN_MASK 0xF
666 
667 /* PSOC_RESET_CONF_XBAR_SOFT_RST_CFG */
668 #define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_SHIFT 0
669 #define PSOC_RESET_CONF_XBAR_SOFT_RST_CFG_EN_MASK 0xF
670 
671 /* PSOC_RESET_CONF_XBAR_FW_RST_CFG */
672 #define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_SHIFT 0
673 #define PSOC_RESET_CONF_XBAR_FW_RST_CFG_EN_MASK 0xF
674 
675 /* PSOC_RESET_CONF_XBAR_WD_RST_CFG */
676 #define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_SHIFT 0
677 #define PSOC_RESET_CONF_XBAR_WD_RST_CFG_EN_MASK 0xF
678 
679 /* PSOC_RESET_CONF_XBAR_MNL_RST_CFG */
680 #define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_SHIFT 0
681 #define PSOC_RESET_CONF_XBAR_MNL_RST_CFG_EN_MASK 0xF
682 
683 /* PSOC_RESET_CONF_XBAR_FLR_RST_CFG */
684 #define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_SHIFT 0
685 #define PSOC_RESET_CONF_XBAR_FLR_RST_CFG_EN_MASK 0xF
686 
687 /* PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG */
688 #define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_SHIFT 0
689 #define PSOC_RESET_CONF_XBAR_ECC_DERR_RST_CFG_EN_MASK 0xF
690 
691 /* PSOC_RESET_CONF_XBAR_SW_RST_CFG */
692 #define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_SHIFT 0
693 #define PSOC_RESET_CONF_XBAR_SW_RST_CFG_EN_MASK 0xF
694 
695 /* PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG */
696 #define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_SHIFT 0
697 #define PSOC_RESET_CONF_SFT_XFT_TFT_PRSTN_RST_CFG_EN_MASK 0xF
698 
699 /* PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG */
700 #define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_SHIFT 0
701 #define PSOC_RESET_CONF_SFT_XFT_TFT_SOFT_RST_CFG_EN_MASK 0xF
702 
703 /* PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG */
704 #define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_SHIFT 0
705 #define PSOC_RESET_CONF_SFT_XFT_TFT_FW_RST_CFG_EN_MASK 0xF
706 
707 /* PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG */
708 #define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_SHIFT 0
709 #define PSOC_RESET_CONF_SFT_XFT_TFT_WD_RST_CFG_EN_MASK 0xF
710 
711 /* PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG */
712 #define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_SHIFT 0
713 #define PSOC_RESET_CONF_SFT_XFT_TFT_MNL_RST_CFG_EN_MASK 0xF
714 
715 /* PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG */
716 #define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_SHIFT 0
717 #define PSOC_RESET_CONF_SFT_XFT_TFT_FLR_RST_CFG_EN_MASK 0xF
718 
719 /* PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG */
720 #define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_SHIFT 0
721 #define PSOC_RESET_CONF_SFT_XFT_TFT_ECC_DERR_RST_CFG_EN_MASK 0xF
722 
723 /* PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG */
724 #define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_SHIFT 0
725 #define PSOC_RESET_CONF_SFT_XFT_TFT_SW_RST_CFG_EN_MASK 0xF
726 
727 /* PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG */
728 #define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_SHIFT 0
729 #define PSOC_RESET_CONF_DDMA_PRSTN_RST_CFG_EN_MASK 0xFF
730 
731 /* PSOC_RESET_CONF_DDMA_SOFT_RST_CFG */
732 #define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_SHIFT 0
733 #define PSOC_RESET_CONF_DDMA_SOFT_RST_CFG_EN_MASK 0xFF
734 
735 /* PSOC_RESET_CONF_DDMA_FW_RST_CFG */
736 #define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_SHIFT 0
737 #define PSOC_RESET_CONF_DDMA_FW_RST_CFG_EN_MASK 0xFF
738 
739 /* PSOC_RESET_CONF_DDMA_WD_RST_CFG */
740 #define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_SHIFT 0
741 #define PSOC_RESET_CONF_DDMA_WD_RST_CFG_EN_MASK 0xFF
742 
743 /* PSOC_RESET_CONF_DDMA_MNL_RST_CFG */
744 #define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_SHIFT 0
745 #define PSOC_RESET_CONF_DDMA_MNL_RST_CFG_EN_MASK 0xFF
746 
747 /* PSOC_RESET_CONF_DDMA_FLR_RST_CFG */
748 #define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_SHIFT 0
749 #define PSOC_RESET_CONF_DDMA_FLR_RST_CFG_EN_MASK 0xFF
750 
751 /* PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG */
752 #define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
753 #define PSOC_RESET_CONF_DDMA_ECC_DERR_RST_CFG_EN_MASK 0xFF
754 
755 /* PSOC_RESET_CONF_DDMA_SW_RST_CFG */
756 #define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_SHIFT 0
757 #define PSOC_RESET_CONF_DDMA_SW_RST_CFG_EN_MASK 0xFF
758 
759 /* PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG */
760 #define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_SHIFT 0
761 #define PSOC_RESET_CONF_KDMA_PRSTN_RST_CFG_EN_MASK 0x1
762 
763 /* PSOC_RESET_CONF_KDMA_SOFT_RST_CFG */
764 #define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_SHIFT 0
765 #define PSOC_RESET_CONF_KDMA_SOFT_RST_CFG_EN_MASK 0x1
766 
767 /* PSOC_RESET_CONF_KDMA_FW_RST_CFG */
768 #define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_SHIFT 0
769 #define PSOC_RESET_CONF_KDMA_FW_RST_CFG_EN_MASK 0x1
770 
771 /* PSOC_RESET_CONF_KDMA_WD_RST_CFG */
772 #define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_SHIFT 0
773 #define PSOC_RESET_CONF_KDMA_WD_RST_CFG_EN_MASK 0x1
774 
775 /* PSOC_RESET_CONF_KDMA_MNL_RST_CFG */
776 #define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_SHIFT 0
777 #define PSOC_RESET_CONF_KDMA_MNL_RST_CFG_EN_MASK 0x1
778 
779 /* PSOC_RESET_CONF_KDMA_FLR_RST_CFG */
780 #define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_SHIFT 0
781 #define PSOC_RESET_CONF_KDMA_FLR_RST_CFG_EN_MASK 0x1
782 
783 /* PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG */
784 #define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
785 #define PSOC_RESET_CONF_KDMA_ECC_DERR_RST_CFG_EN_MASK 0x1
786 
787 /* PSOC_RESET_CONF_KDMA_SW_RST_CFG */
788 #define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_SHIFT 0
789 #define PSOC_RESET_CONF_KDMA_SW_RST_CFG_EN_MASK 0x1
790 
791 /* PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG */
792 #define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_SHIFT 0
793 #define PSOC_RESET_CONF_PDMA_PRSTN_RST_CFG_EN_MASK 0x3
794 
795 /* PSOC_RESET_CONF_PDMA_SOFT_RST_CFG */
796 #define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_SHIFT 0
797 #define PSOC_RESET_CONF_PDMA_SOFT_RST_CFG_EN_MASK 0x3
798 
799 /* PSOC_RESET_CONF_PDMA_FW_RST_CFG */
800 #define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_SHIFT 0
801 #define PSOC_RESET_CONF_PDMA_FW_RST_CFG_EN_MASK 0x3
802 
803 /* PSOC_RESET_CONF_PDMA_WD_RST_CFG */
804 #define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_SHIFT 0
805 #define PSOC_RESET_CONF_PDMA_WD_RST_CFG_EN_MASK 0x3
806 
807 /* PSOC_RESET_CONF_PDMA_MNL_RST_CFG */
808 #define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_SHIFT 0
809 #define PSOC_RESET_CONF_PDMA_MNL_RST_CFG_EN_MASK 0x3
810 
811 /* PSOC_RESET_CONF_PDMA_FLR_RST_CFG */
812 #define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_SHIFT 0
813 #define PSOC_RESET_CONF_PDMA_FLR_RST_CFG_EN_MASK 0x3
814 
815 /* PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG */
816 #define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_SHIFT 0
817 #define PSOC_RESET_CONF_PDMA_ECC_DERR_RST_CFG_EN_MASK 0x3
818 
819 /* PSOC_RESET_CONF_PDMA_SW_RST_CFG */
820 #define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_SHIFT 0
821 #define PSOC_RESET_CONF_PDMA_SW_RST_CFG_EN_MASK 0x3
822 
823 /* PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG */
824 #define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_SHIFT 0
825 #define PSOC_RESET_CONF_ARC_SS_PRSTN_RST_CFG_EN_MASK 0x1F
826 
827 /* PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG */
828 #define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_SHIFT 0
829 #define PSOC_RESET_CONF_ARC_SS_SOFT_RST_CFG_EN_MASK 0x1F
830 
831 /* PSOC_RESET_CONF_ARC_SS_FW_RST_CFG */
832 #define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_SHIFT 0
833 #define PSOC_RESET_CONF_ARC_SS_FW_RST_CFG_EN_MASK 0x1F
834 
835 /* PSOC_RESET_CONF_ARC_SS_WD_RST_CFG */
836 #define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_SHIFT 0
837 #define PSOC_RESET_CONF_ARC_SS_WD_RST_CFG_EN_MASK 0x1F
838 
839 /* PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG */
840 #define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_SHIFT 0
841 #define PSOC_RESET_CONF_ARC_SS_MNL_RST_CFG_EN_MASK 0x1F
842 
843 /* PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG */
844 #define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_SHIFT 0
845 #define PSOC_RESET_CONF_ARC_SS_FLR_RST_CFG_EN_MASK 0x1F
846 
847 /* PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG */
848 #define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_SHIFT 0
849 #define PSOC_RESET_CONF_ARC_SS_ECC_DERR_RST_CFG_EN_MASK 0x1F
850 
851 /* PSOC_RESET_CONF_ARC_SS_SW_RST_CFG */
852 #define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_SHIFT 0
853 #define PSOC_RESET_CONF_ARC_SS_SW_RST_CFG_EN_MASK 0x1F
854 
855 /* PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG */
856 #define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_SHIFT 0
857 #define PSOC_RESET_CONF_ROTATOR_PRSTN_RST_CFG_EN_MASK 0x3
858 
859 /* PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG */
860 #define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_SHIFT 0
861 #define PSOC_RESET_CONF_ROTATOR_SOFT_RST_CFG_EN_MASK 0x3
862 
863 /* PSOC_RESET_CONF_ROTATOR_FW_RST_CFG */
864 #define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_SHIFT 0
865 #define PSOC_RESET_CONF_ROTATOR_FW_RST_CFG_EN_MASK 0x3
866 
867 /* PSOC_RESET_CONF_ROTATOR_WD_RST_CFG */
868 #define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_SHIFT 0
869 #define PSOC_RESET_CONF_ROTATOR_WD_RST_CFG_EN_MASK 0x3
870 
871 /* PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG */
872 #define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_SHIFT 0
873 #define PSOC_RESET_CONF_ROTATOR_MNL_RST_CFG_EN_MASK 0x3
874 
875 /* PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG */
876 #define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_SHIFT 0
877 #define PSOC_RESET_CONF_ROTATOR_FLR_RST_CFG_EN_MASK 0x3
878 
879 /* PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG */
880 #define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_SHIFT 0
881 #define PSOC_RESET_CONF_ROTATOR_ECC_DERR_RST_CFG_EN_MASK 0x3
882 
883 /* PSOC_RESET_CONF_ROTATOR_SW_RST_CFG */
884 #define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_SHIFT 0
885 #define PSOC_RESET_CONF_ROTATOR_SW_RST_CFG_EN_MASK 0x3
886 
887 /* PSOC_RESET_CONF_SM_PRSTN_RST_CFG */
888 #define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_SHIFT 0
889 #define PSOC_RESET_CONF_SM_PRSTN_RST_CFG_EN_MASK 0xF
890 
891 /* PSOC_RESET_CONF_SM_SOFT_RST_CFG */
892 #define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_SHIFT 0
893 #define PSOC_RESET_CONF_SM_SOFT_RST_CFG_EN_MASK 0xF
894 
895 /* PSOC_RESET_CONF_SM_FW_RST_CFG */
896 #define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_SHIFT 0
897 #define PSOC_RESET_CONF_SM_FW_RST_CFG_EN_MASK 0xF
898 
899 /* PSOC_RESET_CONF_SM_WD_RST_CFG */
900 #define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_SHIFT 0
901 #define PSOC_RESET_CONF_SM_WD_RST_CFG_EN_MASK 0xF
902 
903 /* PSOC_RESET_CONF_SM_MNL_RST_CFG */
904 #define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_SHIFT 0
905 #define PSOC_RESET_CONF_SM_MNL_RST_CFG_EN_MASK 0xF
906 
907 /* PSOC_RESET_CONF_SM_FLR_RST_CFG */
908 #define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_SHIFT 0
909 #define PSOC_RESET_CONF_SM_FLR_RST_CFG_EN_MASK 0xF
910 
911 /* PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG */
912 #define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_SHIFT 0
913 #define PSOC_RESET_CONF_SM_ECC_DERR_RST_CFG_EN_MASK 0xF
914 
915 /* PSOC_RESET_CONF_SM_SW_RST_CFG */
916 #define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_SHIFT 0
917 #define PSOC_RESET_CONF_SM_SW_RST_CFG_EN_MASK 0xF
918 
919 /* PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG */
920 #define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_SHIFT 0
921 #define PSOC_RESET_CONF_VIDEO_DEC_PRSTN_RST_CFG_EN_MASK 0x3FF
922 
923 /* PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG */
924 #define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_SHIFT 0
925 #define PSOC_RESET_CONF_VIDEO_DEC_SOFT_RST_CFG_EN_MASK 0x3FF
926 
927 /* PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG */
928 #define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_SHIFT 0
929 #define PSOC_RESET_CONF_VIDEO_DEC_FW_RST_CFG_EN_MASK 0x3FF
930 
931 /* PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG */
932 #define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_SHIFT 0
933 #define PSOC_RESET_CONF_VIDEO_DEC_WD_RST_CFG_EN_MASK 0x3FF
934 
935 /* PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG */
936 #define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_SHIFT 0
937 #define PSOC_RESET_CONF_VIDEO_DEC_MNL_RST_CFG_EN_MASK 0x3FF
938 
939 /* PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG */
940 #define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_SHIFT 0
941 #define PSOC_RESET_CONF_VIDEO_DEC_FLR_RST_CFG_EN_MASK 0x3FF
942 
943 /* PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG */
944 #define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_SHIFT 0
945 #define PSOC_RESET_CONF_VIDEO_DEC_ECC_DERR_RST_CFG_EN_MASK 0x3FF
946 
947 /* PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG */
948 #define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_SHIFT 0
949 #define PSOC_RESET_CONF_VIDEO_DEC_SW_RST_CFG_EN_MASK 0x3FF
950 
951 /* PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG */
952 #define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_SHIFT 0
953 #define PSOC_RESET_CONF_HBM_MC_PRSTN_RST_CFG_EN_MASK 0x3F
954 
955 /* PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG */
956 #define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_SHIFT 0
957 #define PSOC_RESET_CONF_HBM_MC_SOFT_RST_CFG_EN_MASK 0x3F
958 
959 /* PSOC_RESET_CONF_HBM_MC_FW_RST_CFG */
960 #define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_SHIFT 0
961 #define PSOC_RESET_CONF_HBM_MC_FW_RST_CFG_EN_MASK 0x3F
962 
963 /* PSOC_RESET_CONF_HBM_MC_WD_RST_CFG */
964 #define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_SHIFT 0
965 #define PSOC_RESET_CONF_HBM_MC_WD_RST_CFG_EN_MASK 0x3F
966 
967 /* PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG */
968 #define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_SHIFT 0
969 #define PSOC_RESET_CONF_HBM_MC_MNL_RST_CFG_EN_MASK 0x3F
970 
971 /* PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG */
972 #define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_SHIFT 0
973 #define PSOC_RESET_CONF_HBM_MC_FLR_RST_CFG_EN_MASK 0x3F
974 
975 /* PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG */
976 #define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_SHIFT 0
977 #define PSOC_RESET_CONF_HBM_MC_ECC_DERR_RST_CFG_EN_MASK 0x3F
978 
979 /* PSOC_RESET_CONF_HBM_MC_SW_RST_CFG */
980 #define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_SHIFT 0
981 #define PSOC_RESET_CONF_HBM_MC_SW_RST_CFG_EN_MASK 0x3F
982 
983 /* PSOC_RESET_CONF_NIC_PRSTN_RST_CFG */
984 #define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_SHIFT 0
985 #define PSOC_RESET_CONF_NIC_PRSTN_RST_CFG_EN_MASK 0xFFF
986 
987 /* PSOC_RESET_CONF_NIC_SOFT_RST_CFG */
988 #define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_SHIFT 0
989 #define PSOC_RESET_CONF_NIC_SOFT_RST_CFG_EN_MASK 0xFFF
990 
991 /* PSOC_RESET_CONF_NIC_FW_RST_CFG */
992 #define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_SHIFT 0
993 #define PSOC_RESET_CONF_NIC_FW_RST_CFG_EN_MASK 0xFFF
994 
995 /* PSOC_RESET_CONF_NIC_WD_RST_CFG */
996 #define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_SHIFT 0
997 #define PSOC_RESET_CONF_NIC_WD_RST_CFG_EN_MASK 0xFFF
998 
999 /* PSOC_RESET_CONF_NIC_MNL_RST_CFG */
1000 #define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_SHIFT 0
1001 #define PSOC_RESET_CONF_NIC_MNL_RST_CFG_EN_MASK 0xFFF
1002 
1003 /* PSOC_RESET_CONF_NIC_FLR_RST_CFG */
1004 #define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_SHIFT 0
1005 #define PSOC_RESET_CONF_NIC_FLR_RST_CFG_EN_MASK 0xFFF
1006 
1007 /* PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG */
1008 #define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_SHIFT 0
1009 #define PSOC_RESET_CONF_NIC_ECC_DERR_RST_CFG_EN_MASK 0xFFF
1010 
1011 /* PSOC_RESET_CONF_NIC_SW_RST_CFG */
1012 #define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_SHIFT 0
1013 #define PSOC_RESET_CONF_NIC_SW_RST_CFG_EN_MASK 0xFFF
1014 
1015 /* PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG */
1016 #define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_SHIFT 0
1017 #define PSOC_RESET_CONF_NIC_PRT_PRSTN_RST_CFG_EN_MASK 0xFFF
1018 
1019 /* PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG */
1020 #define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_SHIFT 0
1021 #define PSOC_RESET_CONF_NIC_PRT_SOFT_RST_CFG_EN_MASK 0xFFF
1022 
1023 /* PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG */
1024 #define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_SHIFT 0
1025 #define PSOC_RESET_CONF_NIC_PRT_FW_RST_CFG_EN_MASK 0xFFF
1026 
1027 /* PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG */
1028 #define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_SHIFT 0
1029 #define PSOC_RESET_CONF_NIC_PRT_WD_RST_CFG_EN_MASK 0xFFF
1030 
1031 /* PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG */
1032 #define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_SHIFT 0
1033 #define PSOC_RESET_CONF_NIC_PRT_MNL_RST_CFG_EN_MASK 0xFFF
1034 
1035 /* PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG */
1036 #define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_SHIFT 0
1037 #define PSOC_RESET_CONF_NIC_PRT_FLR_RST_CFG_EN_MASK 0xFFF
1038 
1039 /* PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG */
1040 #define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_SHIFT 0
1041 #define PSOC_RESET_CONF_NIC_PRT_ECC_DERR_RST_CFG_EN_MASK 0xFFF
1042 
1043 /* PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG */
1044 #define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_SHIFT 0
1045 #define PSOC_RESET_CONF_NIC_PRT_SW_RST_CFG_EN_MASK 0xFFF
1046 
1047 /* PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG */
1048 #define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_SHIFT 0
1049 #define PSOC_RESET_CONF_NIC_CH_PRSTN_RST_CFG_EN_MASK 0x7
1050 
1051 /* PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG */
1052 #define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_SHIFT 0
1053 #define PSOC_RESET_CONF_NIC_CH_SOFT_RST_CFG_EN_MASK 0x7
1054 
1055 /* PSOC_RESET_CONF_NIC_CH_FW_RST_CFG */
1056 #define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_SHIFT 0
1057 #define PSOC_RESET_CONF_NIC_CH_FW_RST_CFG_EN_MASK 0x7
1058 
1059 /* PSOC_RESET_CONF_NIC_CH_WD_RST_CFG */
1060 #define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_SHIFT 0
1061 #define PSOC_RESET_CONF_NIC_CH_WD_RST_CFG_EN_MASK 0x7
1062 
1063 /* PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG */
1064 #define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_SHIFT 0
1065 #define PSOC_RESET_CONF_NIC_CH_MNL_RST_CFG_EN_MASK 0x7
1066 
1067 /* PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG */
1068 #define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_SHIFT 0
1069 #define PSOC_RESET_CONF_NIC_CH_FLR_RST_CFG_EN_MASK 0x7
1070 
1071 /* PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG */
1072 #define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_SHIFT 0
1073 #define PSOC_RESET_CONF_NIC_CH_ECC_DERR_RST_CFG_EN_MASK 0x7
1074 
1075 /* PSOC_RESET_CONF_NIC_CH_SW_RST_CFG */
1076 #define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_SHIFT 0
1077 #define PSOC_RESET_CONF_NIC_CH_SW_RST_CFG_EN_MASK 0x7
1078 
1079 /* PSOC_RESET_CONF_SOFT_RST */
1080 #define PSOC_RESET_CONF_SOFT_RST_IND_SHIFT 0
1081 #define PSOC_RESET_CONF_SOFT_RST_IND_MASK 0x1
1082 
1083 /* PSOC_RESET_CONF_SW_ALL_RST */
1084 #define PSOC_RESET_CONF_SW_ALL_RST_IND_SHIFT 0
1085 #define PSOC_RESET_CONF_SW_ALL_RST_IND_MASK 0x1
1086 
1087 /* PSOC_RESET_CONF_UNIT_RST_N */
1088 #define PSOC_RESET_CONF_UNIT_RST_N_IND_SHIFT 0
1089 #define PSOC_RESET_CONF_UNIT_RST_N_IND_MASK 0x1
1090 
1091 /* PSOC_RESET_CONF_PSOC_UNIT_RST */
1092 #define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_SHIFT 0
1093 #define PSOC_RESET_CONF_PSOC_UNIT_RST_EN_MASK 0x1
1094 
1095 /* PSOC_RESET_CONF_CPU_UNIT_RST */
1096 #define PSOC_RESET_CONF_CPU_UNIT_RST_EN_SHIFT 0
1097 #define PSOC_RESET_CONF_CPU_UNIT_RST_EN_MASK 0x1
1098 
1099 /* PSOC_RESET_CONF_ARC_UNIT_RST */
1100 #define PSOC_RESET_CONF_ARC_UNIT_RST_EN_SHIFT 0
1101 #define PSOC_RESET_CONF_ARC_UNIT_RST_EN_MASK 0x3
1102 
1103 /* PSOC_RESET_CONF_SIF_UNIT_RST */
1104 #define PSOC_RESET_CONF_SIF_UNIT_RST_EN_SHIFT 0
1105 #define PSOC_RESET_CONF_SIF_UNIT_RST_EN_MASK 0xF
1106 
1107 /* PSOC_RESET_CONF_SRAM_UNIT_RST */
1108 #define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_SHIFT 0
1109 #define PSOC_RESET_CONF_SRAM_UNIT_RST_EN_MASK 0xF
1110 
1111 /* PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST */
1112 #define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_SHIFT 0
1113 #define PSOC_RESET_CONF_PCIE_CTRL_UNIT_RST_EN_MASK 0x1
1114 
1115 /* PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST */
1116 #define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_SHIFT 0
1117 #define PSOC_RESET_CONF_PCIE_PHY_CFG_UNIT_RST_EN_MASK 0x1
1118 
1119 /* PSOC_RESET_CONF_PCIE_IF_UNIT_RST */
1120 #define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_SHIFT 0
1121 #define PSOC_RESET_CONF_PCIE_IF_UNIT_RST_EN_MASK 0x1
1122 
1123 /* PSOC_RESET_CONF_TPC_DIV_UNIT_RST */
1124 #define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_SHIFT 0
1125 #define PSOC_RESET_CONF_TPC_DIV_UNIT_RST_EN_MASK 0x1F
1126 
1127 /* PSOC_RESET_CONF_HBM_DIV_UNIT_RST */
1128 #define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_SHIFT 0
1129 #define PSOC_RESET_CONF_HBM_DIV_UNIT_RST_EN_MASK 0x3F
1130 
1131 /* PSOC_RESET_CONF_PMMU_UNIT_RST */
1132 #define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_SHIFT 0
1133 #define PSOC_RESET_CONF_PMMU_UNIT_RST_EN_MASK 0x1
1134 
1135 /* PSOC_RESET_CONF_PM_UNIT_RST */
1136 #define PSOC_RESET_CONF_PM_UNIT_RST_EN_SHIFT 0
1137 #define PSOC_RESET_CONF_PM_UNIT_RST_EN_MASK 0xF
1138 
1139 /* PSOC_RESET_CONF_TS_UNIT_RST */
1140 #define PSOC_RESET_CONF_TS_UNIT_RST_EN_SHIFT 0
1141 #define PSOC_RESET_CONF_TS_UNIT_RST_EN_MASK 0xF
1142 
1143 /* PSOC_RESET_CONF_TS_IF_UNIT_RST */
1144 #define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_SHIFT 0
1145 #define PSOC_RESET_CONF_TS_IF_UNIT_RST_EN_MASK 0xF
1146 
1147 /* PSOC_RESET_CONF_PLL_L_UNIT_RST */
1148 #define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_SHIFT 0
1149 #define PSOC_RESET_CONF_PLL_L_UNIT_RST_EN_MASK 0xFFFFFFFF
1150 
1151 /* PSOC_RESET_CONF_PLL_H_UNIT_RST */
1152 #define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_SHIFT 0
1153 #define PSOC_RESET_CONF_PLL_H_UNIT_RST_EN_MASK 0x3
1154 
1155 /* PSOC_RESET_CONF_MME_EUS_UNIT_RST */
1156 #define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_SHIFT 0
1157 #define PSOC_RESET_CONF_MME_EUS_UNIT_RST_EN_MASK 0xF
1158 
1159 /* PSOC_RESET_CONF_MSS_CLS_UNIT_RST */
1160 #define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_SHIFT 0
1161 #define PSOC_RESET_CONF_MSS_CLS_UNIT_RST_EN_MASK 0xF
1162 
1163 /* PSOC_RESET_CONF_TPC_UNIT_RST */
1164 #define PSOC_RESET_CONF_TPC_UNIT_RST_EN_SHIFT 0
1165 #define PSOC_RESET_CONF_TPC_UNIT_RST_EN_MASK 0x1FFFFFF
1166 
1167 /* PSOC_RESET_CONF_HIF_HMMU_UNIT_RST */
1168 #define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_SHIFT 0
1169 #define PSOC_RESET_CONF_HIF_HMMU_UNIT_RST_EN_MASK 0xF
1170 
1171 /* PSOC_RESET_CONF_XBAR_UNIT_RST */
1172 #define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_SHIFT 0
1173 #define PSOC_RESET_CONF_XBAR_UNIT_RST_EN_MASK 0xF
1174 
1175 /* PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST */
1176 #define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_SHIFT 0
1177 #define PSOC_RESET_CONF_SFT_XFT_TFT_UNIT_RST_EN_MASK 0xF
1178 
1179 /* PSOC_RESET_CONF_DDMA_UNIT_RST */
1180 #define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_SHIFT 0
1181 #define PSOC_RESET_CONF_DDMA_UNIT_RST_EN_MASK 0xFF
1182 
1183 /* PSOC_RESET_CONF_KDMA_UNIT_RST */
1184 #define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_SHIFT 0
1185 #define PSOC_RESET_CONF_KDMA_UNIT_RST_EN_MASK 0x1
1186 
1187 /* PSOC_RESET_CONF_PDMA_UNIT_RST */
1188 #define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_SHIFT 0
1189 #define PSOC_RESET_CONF_PDMA_UNIT_RST_EN_MASK 0x3
1190 
1191 /* PSOC_RESET_CONF_ARC_SS_UNIT_RST */
1192 #define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_SHIFT 0
1193 #define PSOC_RESET_CONF_ARC_SS_UNIT_RST_EN_MASK 0x1F
1194 
1195 /* PSOC_RESET_CONF_ROTATOR_UNIT_RST */
1196 #define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_SHIFT 0
1197 #define PSOC_RESET_CONF_ROTATOR_UNIT_RST_EN_MASK 0x3
1198 
1199 /* PSOC_RESET_CONF_SM_UNIT_RST */
1200 #define PSOC_RESET_CONF_SM_UNIT_RST_EN_SHIFT 0
1201 #define PSOC_RESET_CONF_SM_UNIT_RST_EN_MASK 0xF
1202 
1203 /* PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST */
1204 #define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_SHIFT 0
1205 #define PSOC_RESET_CONF_VIDEO_DEC_UNIT_RST_EN_MASK 0x3FF
1206 
1207 /* PSOC_RESET_CONF_HBM_MC_UNIT_RST */
1208 #define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_SHIFT 0
1209 #define PSOC_RESET_CONF_HBM_MC_UNIT_RST_EN_MASK 0x3F
1210 
1211 /* PSOC_RESET_CONF_NIC_UNIT_RST */
1212 #define PSOC_RESET_CONF_NIC_UNIT_RST_EN_SHIFT 0
1213 #define PSOC_RESET_CONF_NIC_UNIT_RST_EN_MASK 0xFFF
1214 
1215 /* PSOC_RESET_CONF_NIC_PRT_UNIT_RST */
1216 #define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_SHIFT 0
1217 #define PSOC_RESET_CONF_NIC_PRT_UNIT_RST_EN_MASK 0xFFF
1218 
1219 /* PSOC_RESET_CONF_NIC_CH_UNIT_RST */
1220 #define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_SHIFT 0
1221 #define PSOC_RESET_CONF_NIC_CH_UNIT_RST_EN_MASK 0x7
1222 
1223 /* PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL */
1224 #define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1225 #define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1226 #define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1227 #define PSOC_RESET_CONF_PSOC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1228 
1229 /* PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL */
1230 #define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1231 #define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1232 #define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1233 #define PSOC_RESET_CONF_CPU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1234 
1235 /* PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL */
1236 #define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1237 #define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1238 #define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1239 #define PSOC_RESET_CONF_ARC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1240 
1241 /* PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL */
1242 #define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1243 #define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1244 #define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1245 #define PSOC_RESET_CONF_ARC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1246 
1247 /* PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL */
1248 #define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1249 #define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1250 #define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1251 #define PSOC_RESET_CONF_SIF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1252 
1253 /* PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL */
1254 #define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1255 #define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1256 #define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1257 #define PSOC_RESET_CONF_SIF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1258 
1259 /* PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL */
1260 #define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1261 #define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1262 #define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1263 #define PSOC_RESET_CONF_SIF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1264 
1265 /* PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL */
1266 #define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1267 #define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1268 #define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1269 #define PSOC_RESET_CONF_SIF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1270 
1271 /* PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL */
1272 #define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1273 #define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1274 #define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1275 #define PSOC_RESET_CONF_SRAM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1276 
1277 /* PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL */
1278 #define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1279 #define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1280 #define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1281 #define PSOC_RESET_CONF_SRAM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1282 
1283 /* PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL */
1284 #define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1285 #define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1286 #define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1287 #define PSOC_RESET_CONF_SRAM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1288 
1289 /* PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL */
1290 #define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1291 #define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1292 #define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1293 #define PSOC_RESET_CONF_SRAM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1294 
1295 /* PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL */
1296 #define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1297 #define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1298 #define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1299 #define PSOC_RESET_CONF_PCIE_CTRL_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1300 
1301 /* PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL */
1302 #define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1303 #define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1304 #define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1305 #define PSOC_RESET_CONF_PCIE_PHY_CFG_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1306 
1307 /* PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL */
1308 #define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1309 #define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1310 #define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1311 #define PSOC_RESET_CONF_PCIE_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1312 
1313 /* PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL */
1314 #define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1315 #define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1316 #define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1317 #define PSOC_RESET_CONF_TPC_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1318 
1319 /* PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL */
1320 #define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1321 #define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1322 #define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1323 #define PSOC_RESET_CONF_TPC_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1324 
1325 /* PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL */
1326 #define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1327 #define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1328 #define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1329 #define PSOC_RESET_CONF_TPC_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1330 
1331 /* PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL */
1332 #define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1333 #define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1334 #define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1335 #define PSOC_RESET_CONF_TPC_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1336 
1337 /* PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL */
1338 #define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
1339 #define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1340 #define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1341 #define PSOC_RESET_CONF_TPC_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1342 
1343 /* PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL */
1344 #define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1345 #define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1346 #define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1347 #define PSOC_RESET_CONF_HBM_DIV_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1348 
1349 /* PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL */
1350 #define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1351 #define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1352 #define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1353 #define PSOC_RESET_CONF_HBM_DIV_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1354 
1355 /* PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL */
1356 #define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1357 #define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1358 #define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1359 #define PSOC_RESET_CONF_HBM_DIV_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1360 
1361 /* PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL */
1362 #define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1363 #define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1364 #define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1365 #define PSOC_RESET_CONF_HBM_DIV_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1366 
1367 /* PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL */
1368 #define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
1369 #define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1370 #define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1371 #define PSOC_RESET_CONF_HBM_DIV_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1372 
1373 /* PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL */
1374 #define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
1375 #define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1376 #define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1377 #define PSOC_RESET_CONF_HBM_DIV_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1378 
1379 /* PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL */
1380 #define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1381 #define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1382 #define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1383 #define PSOC_RESET_CONF_PMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1384 
1385 /* PSOC_RESET_CONF_PM_0_CLK_RST_CTRL */
1386 #define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1387 #define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1388 #define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1389 #define PSOC_RESET_CONF_PM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1390 
1391 /* PSOC_RESET_CONF_PM_1_CLK_RST_CTRL */
1392 #define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1393 #define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1394 #define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1395 #define PSOC_RESET_CONF_PM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1396 
1397 /* PSOC_RESET_CONF_PM_2_CLK_RST_CTRL */
1398 #define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1399 #define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1400 #define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1401 #define PSOC_RESET_CONF_PM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1402 
1403 /* PSOC_RESET_CONF_PM_3_CLK_RST_CTRL */
1404 #define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1405 #define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1406 #define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1407 #define PSOC_RESET_CONF_PM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1408 
1409 /* PSOC_RESET_CONF_TS_0_CLK_RST_CTRL */
1410 #define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1411 #define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1412 #define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1413 #define PSOC_RESET_CONF_TS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1414 
1415 /* PSOC_RESET_CONF_TS_1_CLK_RST_CTRL */
1416 #define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1417 #define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1418 #define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1419 #define PSOC_RESET_CONF_TS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1420 
1421 /* PSOC_RESET_CONF_TS_2_CLK_RST_CTRL */
1422 #define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1423 #define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1424 #define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1425 #define PSOC_RESET_CONF_TS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1426 
1427 /* PSOC_RESET_CONF_TS_3_CLK_RST_CTRL */
1428 #define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1429 #define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1430 #define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1431 #define PSOC_RESET_CONF_TS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1432 
1433 /* PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL */
1434 #define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1435 #define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1436 #define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1437 #define PSOC_RESET_CONF_TS_IF_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1438 
1439 /* PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL */
1440 #define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1441 #define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1442 #define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1443 #define PSOC_RESET_CONF_TS_IF_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1444 
1445 /* PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL */
1446 #define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1447 #define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1448 #define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1449 #define PSOC_RESET_CONF_TS_IF_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1450 
1451 /* PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL */
1452 #define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1453 #define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1454 #define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1455 #define PSOC_RESET_CONF_TS_IF_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1456 
1457 /* PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL */
1458 #define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1459 #define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1460 #define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1461 #define PSOC_RESET_CONF_PLL_L_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1462 
1463 /* PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL */
1464 #define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1465 #define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1466 #define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1467 #define PSOC_RESET_CONF_PLL_L_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1468 
1469 /* PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL */
1470 #define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1471 #define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1472 #define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1473 #define PSOC_RESET_CONF_PLL_L_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1474 
1475 /* PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL */
1476 #define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1477 #define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1478 #define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1479 #define PSOC_RESET_CONF_PLL_L_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1480 
1481 /* PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL */
1482 #define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
1483 #define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1484 #define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1485 #define PSOC_RESET_CONF_PLL_L_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1486 
1487 /* PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL */
1488 #define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
1489 #define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1490 #define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1491 #define PSOC_RESET_CONF_PLL_L_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1492 
1493 /* PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL */
1494 #define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
1495 #define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1496 #define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1497 #define PSOC_RESET_CONF_PLL_L_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1498 
1499 /* PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL */
1500 #define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
1501 #define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1502 #define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1503 #define PSOC_RESET_CONF_PLL_L_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1504 
1505 /* PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL */
1506 #define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
1507 #define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1508 #define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1509 #define PSOC_RESET_CONF_PLL_L_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1510 
1511 /* PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL */
1512 #define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
1513 #define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1514 #define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1515 #define PSOC_RESET_CONF_PLL_L_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1516 
1517 /* PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL */
1518 #define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
1519 #define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1520 #define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1521 #define PSOC_RESET_CONF_PLL_L_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1522 
1523 /* PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL */
1524 #define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
1525 #define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1526 #define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1527 #define PSOC_RESET_CONF_PLL_L_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1528 
1529 /* PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL */
1530 #define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_SHIFT 0
1531 #define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1532 #define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1533 #define PSOC_RESET_CONF_PLL_L_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1534 
1535 /* PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL */
1536 #define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_SHIFT 0
1537 #define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1538 #define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1539 #define PSOC_RESET_CONF_PLL_L_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1540 
1541 /* PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL */
1542 #define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_SHIFT 0
1543 #define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1544 #define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1545 #define PSOC_RESET_CONF_PLL_L_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1546 
1547 /* PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL */
1548 #define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_SHIFT 0
1549 #define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1550 #define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1551 #define PSOC_RESET_CONF_PLL_L_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1552 
1553 /* PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL */
1554 #define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_SHIFT 0
1555 #define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1556 #define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1557 #define PSOC_RESET_CONF_PLL_L_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1558 
1559 /* PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL */
1560 #define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_SHIFT 0
1561 #define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1562 #define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1563 #define PSOC_RESET_CONF_PLL_L_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1564 
1565 /* PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL */
1566 #define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_SHIFT 0
1567 #define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1568 #define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1569 #define PSOC_RESET_CONF_PLL_L_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1570 
1571 /* PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL */
1572 #define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_SHIFT 0
1573 #define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1574 #define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1575 #define PSOC_RESET_CONF_PLL_L_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1576 
1577 /* PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL */
1578 #define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_SHIFT 0
1579 #define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1580 #define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1581 #define PSOC_RESET_CONF_PLL_L_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1582 
1583 /* PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL */
1584 #define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_SHIFT 0
1585 #define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1586 #define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1587 #define PSOC_RESET_CONF_PLL_L_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1588 
1589 /* PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL */
1590 #define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_SHIFT 0
1591 #define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1592 #define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1593 #define PSOC_RESET_CONF_PLL_L_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1594 
1595 /* PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL */
1596 #define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_SHIFT 0
1597 #define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1598 #define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1599 #define PSOC_RESET_CONF_PLL_L_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1600 
1601 /* PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL */
1602 #define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_SHIFT 0
1603 #define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1604 #define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1605 #define PSOC_RESET_CONF_PLL_L_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1606 
1607 /* PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL */
1608 #define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_SHIFT 0
1609 #define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1610 #define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1611 #define PSOC_RESET_CONF_PLL_L_25_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1612 
1613 /* PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL */
1614 #define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_SHIFT 0
1615 #define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1616 #define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1617 #define PSOC_RESET_CONF_PLL_L_26_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1618 
1619 /* PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL */
1620 #define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_SHIFT 0
1621 #define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1622 #define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1623 #define PSOC_RESET_CONF_PLL_L_27_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1624 
1625 /* PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL */
1626 #define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_SHIFT 0
1627 #define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1628 #define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1629 #define PSOC_RESET_CONF_PLL_L_28_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1630 
1631 /* PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL */
1632 #define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_SHIFT 0
1633 #define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1634 #define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1635 #define PSOC_RESET_CONF_PLL_L_29_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1636 
1637 /* PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL */
1638 #define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_SHIFT 0
1639 #define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1640 #define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1641 #define PSOC_RESET_CONF_PLL_L_30_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1642 
1643 /* PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL */
1644 #define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_SHIFT 0
1645 #define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1646 #define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1647 #define PSOC_RESET_CONF_PLL_L_31_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1648 
1649 /* PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL */
1650 #define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1651 #define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1652 #define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1653 #define PSOC_RESET_CONF_PLL_H_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1654 
1655 /* PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL */
1656 #define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1657 #define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1658 #define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1659 #define PSOC_RESET_CONF_PLL_H_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1660 
1661 /* PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL */
1662 #define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1663 #define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1664 #define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1665 #define PSOC_RESET_CONF_MME_EUS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1666 
1667 /* PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL */
1668 #define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1669 #define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1670 #define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1671 #define PSOC_RESET_CONF_MME_EUS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1672 
1673 /* PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL */
1674 #define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1675 #define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1676 #define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1677 #define PSOC_RESET_CONF_MME_EUS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1678 
1679 /* PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL */
1680 #define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1681 #define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1682 #define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1683 #define PSOC_RESET_CONF_MME_EUS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1684 
1685 /* PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL */
1686 #define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1687 #define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1688 #define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1689 #define PSOC_RESET_CONF_MSS_CLS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1690 
1691 /* PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL */
1692 #define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1693 #define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1694 #define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1695 #define PSOC_RESET_CONF_MSS_CLS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1696 
1697 /* PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL */
1698 #define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1699 #define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1700 #define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1701 #define PSOC_RESET_CONF_MSS_CLS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1702 
1703 /* PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL */
1704 #define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1705 #define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1706 #define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1707 #define PSOC_RESET_CONF_MSS_CLS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1708 
1709 /* PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL */
1710 #define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1711 #define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1712 #define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1713 #define PSOC_RESET_CONF_TPC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1714 
1715 /* PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL */
1716 #define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1717 #define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1718 #define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1719 #define PSOC_RESET_CONF_TPC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1720 
1721 /* PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL */
1722 #define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1723 #define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1724 #define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1725 #define PSOC_RESET_CONF_TPC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1726 
1727 /* PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL */
1728 #define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1729 #define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1730 #define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1731 #define PSOC_RESET_CONF_TPC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1732 
1733 /* PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL */
1734 #define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
1735 #define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1736 #define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1737 #define PSOC_RESET_CONF_TPC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1738 
1739 /* PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL */
1740 #define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
1741 #define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1742 #define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1743 #define PSOC_RESET_CONF_TPC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1744 
1745 /* PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL */
1746 #define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
1747 #define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1748 #define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1749 #define PSOC_RESET_CONF_TPC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1750 
1751 /* PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL */
1752 #define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
1753 #define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1754 #define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1755 #define PSOC_RESET_CONF_TPC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1756 
1757 /* PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL */
1758 #define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
1759 #define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1760 #define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1761 #define PSOC_RESET_CONF_TPC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1762 
1763 /* PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL */
1764 #define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
1765 #define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1766 #define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1767 #define PSOC_RESET_CONF_TPC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1768 
1769 /* PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL */
1770 #define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
1771 #define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1772 #define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1773 #define PSOC_RESET_CONF_TPC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1774 
1775 /* PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL */
1776 #define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
1777 #define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1778 #define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1779 #define PSOC_RESET_CONF_TPC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1780 
1781 /* PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL */
1782 #define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_SHIFT 0
1783 #define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1784 #define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1785 #define PSOC_RESET_CONF_TPC_12_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1786 
1787 /* PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL */
1788 #define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_SHIFT 0
1789 #define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1790 #define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1791 #define PSOC_RESET_CONF_TPC_13_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1792 
1793 /* PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL */
1794 #define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_SHIFT 0
1795 #define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1796 #define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1797 #define PSOC_RESET_CONF_TPC_14_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1798 
1799 /* PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL */
1800 #define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_SHIFT 0
1801 #define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1802 #define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1803 #define PSOC_RESET_CONF_TPC_15_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1804 
1805 /* PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL */
1806 #define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_SHIFT 0
1807 #define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1808 #define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1809 #define PSOC_RESET_CONF_TPC_16_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1810 
1811 /* PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL */
1812 #define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_SHIFT 0
1813 #define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1814 #define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1815 #define PSOC_RESET_CONF_TPC_17_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1816 
1817 /* PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL */
1818 #define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_SHIFT 0
1819 #define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1820 #define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1821 #define PSOC_RESET_CONF_TPC_18_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1822 
1823 /* PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL */
1824 #define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_SHIFT 0
1825 #define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1826 #define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1827 #define PSOC_RESET_CONF_TPC_19_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1828 
1829 /* PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL */
1830 #define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_SHIFT 0
1831 #define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1832 #define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1833 #define PSOC_RESET_CONF_TPC_20_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1834 
1835 /* PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL */
1836 #define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_SHIFT 0
1837 #define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1838 #define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1839 #define PSOC_RESET_CONF_TPC_21_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1840 
1841 /* PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL */
1842 #define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_SHIFT 0
1843 #define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1844 #define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1845 #define PSOC_RESET_CONF_TPC_22_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1846 
1847 /* PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL */
1848 #define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_SHIFT 0
1849 #define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1850 #define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1851 #define PSOC_RESET_CONF_TPC_23_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1852 
1853 /* PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL */
1854 #define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_SHIFT 0
1855 #define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1856 #define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1857 #define PSOC_RESET_CONF_TPC_24_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1858 
1859 /* PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL */
1860 #define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1861 #define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1862 #define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1863 #define PSOC_RESET_CONF_HIF_HMMU_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1864 
1865 /* PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL */
1866 #define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1867 #define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1868 #define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1869 #define PSOC_RESET_CONF_HIF_HMMU_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1870 
1871 /* PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL */
1872 #define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1873 #define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1874 #define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1875 #define PSOC_RESET_CONF_HIF_HMMU_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1876 
1877 /* PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL */
1878 #define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1879 #define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1880 #define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1881 #define PSOC_RESET_CONF_HIF_HMMU_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1882 
1883 /* PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL */
1884 #define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1885 #define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1886 #define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1887 #define PSOC_RESET_CONF_XBAR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1888 
1889 /* PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL */
1890 #define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1891 #define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1892 #define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1893 #define PSOC_RESET_CONF_XBAR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1894 
1895 /* PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL */
1896 #define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1897 #define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1898 #define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1899 #define PSOC_RESET_CONF_XBAR_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1900 
1901 /* PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL */
1902 #define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1903 #define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1904 #define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1905 #define PSOC_RESET_CONF_XBAR_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1906 
1907 /* PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL */
1908 #define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1909 #define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1910 #define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1911 #define PSOC_RESET_CONF_SFT_XFT_TFT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1912 
1913 /* PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL */
1914 #define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1915 #define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1916 #define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1917 #define PSOC_RESET_CONF_SFT_XFT_TFT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1918 
1919 /* PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL */
1920 #define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1921 #define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1922 #define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1923 #define PSOC_RESET_CONF_SFT_XFT_TFT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1924 
1925 /* PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL */
1926 #define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1927 #define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1928 #define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1929 #define PSOC_RESET_CONF_SFT_XFT_TFT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1930 
1931 /* PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL */
1932 #define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1933 #define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1934 #define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1935 #define PSOC_RESET_CONF_DDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1936 
1937 /* PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL */
1938 #define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1939 #define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1940 #define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1941 #define PSOC_RESET_CONF_DDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1942 
1943 /* PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL */
1944 #define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
1945 #define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1946 #define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1947 #define PSOC_RESET_CONF_DDMA_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1948 
1949 /* PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL */
1950 #define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
1951 #define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1952 #define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1953 #define PSOC_RESET_CONF_DDMA_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1954 
1955 /* PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL */
1956 #define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
1957 #define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1958 #define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1959 #define PSOC_RESET_CONF_DDMA_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1960 
1961 /* PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL */
1962 #define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
1963 #define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1964 #define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1965 #define PSOC_RESET_CONF_DDMA_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1966 
1967 /* PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL */
1968 #define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
1969 #define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1970 #define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1971 #define PSOC_RESET_CONF_DDMA_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1972 
1973 /* PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL */
1974 #define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
1975 #define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1976 #define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1977 #define PSOC_RESET_CONF_DDMA_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1978 
1979 /* PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL */
1980 #define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1981 #define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1982 #define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1983 #define PSOC_RESET_CONF_KDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1984 
1985 /* PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL */
1986 #define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1987 #define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1988 #define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1989 #define PSOC_RESET_CONF_PDMA_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1990 
1991 /* PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL */
1992 #define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
1993 #define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
1994 #define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
1995 #define PSOC_RESET_CONF_PDMA_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
1996 
1997 /* PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL */
1998 #define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
1999 #define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2000 #define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2001 #define PSOC_RESET_CONF_ARC_SS_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2002 
2003 /* PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL */
2004 #define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2005 #define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2006 #define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2007 #define PSOC_RESET_CONF_ARC_SS_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2008 
2009 /* PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL */
2010 #define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
2011 #define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2012 #define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2013 #define PSOC_RESET_CONF_ARC_SS_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2014 
2015 /* PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL */
2016 #define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
2017 #define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2018 #define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2019 #define PSOC_RESET_CONF_ARC_SS_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2020 
2021 /* PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL */
2022 #define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
2023 #define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2024 #define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2025 #define PSOC_RESET_CONF_ARC_SS_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2026 
2027 /* PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL */
2028 #define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
2029 #define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2030 #define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2031 #define PSOC_RESET_CONF_ROTATOR_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2032 
2033 /* PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL */
2034 #define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2035 #define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2036 #define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2037 #define PSOC_RESET_CONF_ROTATOR_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2038 
2039 /* PSOC_RESET_CONF_SM_0_CLK_RST_CTRL */
2040 #define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
2041 #define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2042 #define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2043 #define PSOC_RESET_CONF_SM_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2044 
2045 /* PSOC_RESET_CONF_SM_1_CLK_RST_CTRL */
2046 #define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2047 #define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2048 #define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2049 #define PSOC_RESET_CONF_SM_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2050 
2051 /* PSOC_RESET_CONF_SM_2_CLK_RST_CTRL */
2052 #define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
2053 #define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2054 #define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2055 #define PSOC_RESET_CONF_SM_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2056 
2057 /* PSOC_RESET_CONF_SM_3_CLK_RST_CTRL */
2058 #define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
2059 #define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2060 #define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2061 #define PSOC_RESET_CONF_SM_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2062 
2063 /* PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL */
2064 #define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
2065 #define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2066 #define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2067 #define PSOC_RESET_CONF_VIDEO_DEC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2068 
2069 /* PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL */
2070 #define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2071 #define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2072 #define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2073 #define PSOC_RESET_CONF_VIDEO_DEC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2074 
2075 /* PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL */
2076 #define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
2077 #define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2078 #define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2079 #define PSOC_RESET_CONF_VIDEO_DEC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2080 
2081 /* PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL */
2082 #define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
2083 #define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2084 #define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2085 #define PSOC_RESET_CONF_VIDEO_DEC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2086 
2087 /* PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL */
2088 #define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
2089 #define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2090 #define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2091 #define PSOC_RESET_CONF_VIDEO_DEC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2092 
2093 /* PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL */
2094 #define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
2095 #define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2096 #define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2097 #define PSOC_RESET_CONF_VIDEO_DEC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2098 
2099 /* PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL */
2100 #define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
2101 #define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2102 #define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2103 #define PSOC_RESET_CONF_VIDEO_DEC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2104 
2105 /* PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL */
2106 #define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
2107 #define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2108 #define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2109 #define PSOC_RESET_CONF_VIDEO_DEC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2110 
2111 /* PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL */
2112 #define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
2113 #define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2114 #define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2115 #define PSOC_RESET_CONF_VIDEO_DEC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2116 
2117 /* PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL */
2118 #define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
2119 #define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2120 #define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2121 #define PSOC_RESET_CONF_VIDEO_DEC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2122 
2123 /* PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL */
2124 #define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
2125 #define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2126 #define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2127 #define PSOC_RESET_CONF_HBM_MC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2128 
2129 /* PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL */
2130 #define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2131 #define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2132 #define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2133 #define PSOC_RESET_CONF_HBM_MC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2134 
2135 /* PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL */
2136 #define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
2137 #define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2138 #define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2139 #define PSOC_RESET_CONF_HBM_MC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2140 
2141 /* PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL */
2142 #define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
2143 #define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2144 #define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2145 #define PSOC_RESET_CONF_HBM_MC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2146 
2147 /* PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL */
2148 #define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
2149 #define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2150 #define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2151 #define PSOC_RESET_CONF_HBM_MC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2152 
2153 /* PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL */
2154 #define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
2155 #define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2156 #define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2157 #define PSOC_RESET_CONF_HBM_MC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2158 
2159 /* PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL */
2160 #define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
2161 #define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2162 #define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2163 #define PSOC_RESET_CONF_NIC_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2164 
2165 /* PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL */
2166 #define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2167 #define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2168 #define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2169 #define PSOC_RESET_CONF_NIC_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2170 
2171 /* PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL */
2172 #define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
2173 #define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2174 #define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2175 #define PSOC_RESET_CONF_NIC_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2176 
2177 /* PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL */
2178 #define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
2179 #define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2180 #define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2181 #define PSOC_RESET_CONF_NIC_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2182 
2183 /* PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL */
2184 #define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
2185 #define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2186 #define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2187 #define PSOC_RESET_CONF_NIC_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2188 
2189 /* PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL */
2190 #define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
2191 #define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2192 #define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2193 #define PSOC_RESET_CONF_NIC_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2194 
2195 /* PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL */
2196 #define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
2197 #define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2198 #define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2199 #define PSOC_RESET_CONF_NIC_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2200 
2201 /* PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL */
2202 #define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
2203 #define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2204 #define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2205 #define PSOC_RESET_CONF_NIC_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2206 
2207 /* PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL */
2208 #define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
2209 #define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2210 #define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2211 #define PSOC_RESET_CONF_NIC_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2212 
2213 /* PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL */
2214 #define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
2215 #define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2216 #define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2217 #define PSOC_RESET_CONF_NIC_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2218 
2219 /* PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL */
2220 #define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
2221 #define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2222 #define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2223 #define PSOC_RESET_CONF_NIC_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2224 
2225 /* PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL */
2226 #define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
2227 #define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2228 #define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2229 #define PSOC_RESET_CONF_NIC_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2230 
2231 /* PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL */
2232 #define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
2233 #define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2234 #define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2235 #define PSOC_RESET_CONF_NIC_PRT_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2236 
2237 /* PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL */
2238 #define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2239 #define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2240 #define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2241 #define PSOC_RESET_CONF_NIC_PRT_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2242 
2243 /* PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL */
2244 #define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
2245 #define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2246 #define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2247 #define PSOC_RESET_CONF_NIC_PRT_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2248 
2249 /* PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL */
2250 #define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_SHIFT 0
2251 #define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2252 #define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2253 #define PSOC_RESET_CONF_NIC_PRT_3_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2254 
2255 /* PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL */
2256 #define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_SHIFT 0
2257 #define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2258 #define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2259 #define PSOC_RESET_CONF_NIC_PRT_4_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2260 
2261 /* PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL */
2262 #define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_SHIFT 0
2263 #define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2264 #define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2265 #define PSOC_RESET_CONF_NIC_PRT_5_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2266 
2267 /* PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL */
2268 #define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_SHIFT 0
2269 #define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2270 #define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2271 #define PSOC_RESET_CONF_NIC_PRT_6_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2272 
2273 /* PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL */
2274 #define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_SHIFT 0
2275 #define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2276 #define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2277 #define PSOC_RESET_CONF_NIC_PRT_7_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2278 
2279 /* PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL */
2280 #define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_SHIFT 0
2281 #define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2282 #define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2283 #define PSOC_RESET_CONF_NIC_PRT_8_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2284 
2285 /* PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL */
2286 #define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_SHIFT 0
2287 #define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2288 #define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2289 #define PSOC_RESET_CONF_NIC_PRT_9_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2290 
2291 /* PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL */
2292 #define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_SHIFT 0
2293 #define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2294 #define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2295 #define PSOC_RESET_CONF_NIC_PRT_10_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2296 
2297 /* PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL */
2298 #define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_SHIFT 0
2299 #define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2300 #define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2301 #define PSOC_RESET_CONF_NIC_PRT_11_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2302 
2303 /* PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL */
2304 #define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_SHIFT 0
2305 #define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2306 #define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2307 #define PSOC_RESET_CONF_NIC_CH_0_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2308 
2309 /* PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL */
2310 #define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_SHIFT 0
2311 #define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2312 #define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2313 #define PSOC_RESET_CONF_NIC_CH_1_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2314 
2315 /* PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL */
2316 #define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_SHIFT 0
2317 #define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_RST_SEL_MASK 0xFF
2318 #define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_SHIFT 16
2319 #define PSOC_RESET_CONF_NIC_CH_2_CLK_RST_CTRL_CLK_DIS_MASK 0x10000
2320 
2321 #endif /* ASIC_REG_PSOC_RESET_CONF_MASKS_H_ */
2322