1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PSOC_ETR_MASKS_H_ 14 #define ASIC_REG_PSOC_ETR_MASKS_H_ 15 16 /* 17 ***************************************** 18 * PSOC_ETR 19 * (Prototype: ETR) 20 ***************************************** 21 */ 22 23 /* PSOC_ETR_RSZ */ 24 #define PSOC_ETR_RSZ_RSZ_ETR_SHIFT 0 25 #define PSOC_ETR_RSZ_RSZ_ETR_MASK 0x7FFFFFFF 26 27 /* PSOC_ETR_STS */ 28 #define PSOC_ETR_STS_FULL_SHIFT 0 29 #define PSOC_ETR_STS_FULL_MASK 0x1 30 #define PSOC_ETR_STS_TRIGGERED_SHIFT 1 31 #define PSOC_ETR_STS_TRIGGERED_MASK 0x2 32 #define PSOC_ETR_STS_TMCREADY_SHIFT 2 33 #define PSOC_ETR_STS_TMCREADY_MASK 0x4 34 #define PSOC_ETR_STS_FTEMPTY_SHIFT 3 35 #define PSOC_ETR_STS_FTEMPTY_MASK 0x8 36 #define PSOC_ETR_STS_EMPTY_SHIFT 4 37 #define PSOC_ETR_STS_EMPTY_MASK 0x10 38 #define PSOC_ETR_STS_MEMERR_SHIFT 5 39 #define PSOC_ETR_STS_MEMERR_MASK 0x20 40 41 /* PSOC_ETR_RRD */ 42 #define PSOC_ETR_RRD_RRD_SHIFT 0 43 #define PSOC_ETR_RRD_RRD_MASK 0xFFFFFFFF 44 45 /* PSOC_ETR_RRP */ 46 #define PSOC_ETR_RRP_RRP_SHIFT 0 47 #define PSOC_ETR_RRP_RRP_MASK 0xFFFFFFFF 48 49 /* PSOC_ETR_RWP */ 50 #define PSOC_ETR_RWP_RWP_SHIFT 0 51 #define PSOC_ETR_RWP_RWP_MASK 0xFFFFFFFF 52 53 /* PSOC_ETR_TRG */ 54 #define PSOC_ETR_TRG_TRG_SHIFT 0 55 #define PSOC_ETR_TRG_TRG_MASK 0xFFFFFFFF 56 57 /* PSOC_ETR_CTL */ 58 #define PSOC_ETR_CTL_TRACECAPTEN_SHIFT 0 59 #define PSOC_ETR_CTL_TRACECAPTEN_MASK 0x1 60 61 /* PSOC_ETR_RWD */ 62 #define PSOC_ETR_RWD_RWD_SHIFT 0 63 #define PSOC_ETR_RWD_RWD_MASK 0xFFFFFFFF 64 65 /* PSOC_ETR_MODE */ 66 #define PSOC_ETR_MODE_MODE_SHIFT 0 67 #define PSOC_ETR_MODE_MODE_MASK 0x3 68 69 /* PSOC_ETR_LBUFLEVEL */ 70 #define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_SHIFT 0 71 #define PSOC_ETR_LBUFLEVEL_LBUFLEVEL_MASK 0x7FFFFFFF 72 73 /* PSOC_ETR_CBUFLEVEL */ 74 #define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_SHIFT 0 75 #define PSOC_ETR_CBUFLEVEL_CBUFLEVEL_MASK 0x7FFFFFFF 76 77 /* PSOC_ETR_BUFWM */ 78 #define PSOC_ETR_BUFWM_BUFWM_SHIFT 0 79 #define PSOC_ETR_BUFWM_BUFWM_MASK 0x3FFFFFFF 80 81 /* PSOC_ETR_RRPHI */ 82 #define PSOC_ETR_RRPHI_RRPHI_SHIFT 0 83 #define PSOC_ETR_RRPHI_RRPHI_MASK 0xFF 84 85 /* PSOC_ETR_RWPHI */ 86 #define PSOC_ETR_RWPHI_RWPHI_SHIFT 0 87 #define PSOC_ETR_RWPHI_RWPHI_MASK 0xFF 88 89 /* PSOC_ETR_AXICTL */ 90 #define PSOC_ETR_AXICTL_PROTCTRLBIT0_SHIFT 0 91 #define PSOC_ETR_AXICTL_PROTCTRLBIT0_MASK 0x1 92 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_SHIFT 1 93 #define PSOC_ETR_AXICTL_PROTCTRLBIT1_MASK 0x2 94 #define PSOC_ETR_AXICTL_CACHECTRLBIT0_SHIFT 2 95 #define PSOC_ETR_AXICTL_CACHECTRLBIT0_MASK 0x4 96 #define PSOC_ETR_AXICTL_CACHECTRLBIT1_SHIFT 3 97 #define PSOC_ETR_AXICTL_CACHECTRLBIT1_MASK 0x8 98 #define PSOC_ETR_AXICTL_CACHECTRLBIT2_SHIFT 4 99 #define PSOC_ETR_AXICTL_CACHECTRLBIT2_MASK 0x10 100 #define PSOC_ETR_AXICTL_CACHECTRLBIT3_SHIFT 5 101 #define PSOC_ETR_AXICTL_CACHECTRLBIT3_MASK 0x20 102 #define PSOC_ETR_AXICTL_SCATTERGATHERMODE_SHIFT 7 103 #define PSOC_ETR_AXICTL_SCATTERGATHERMODE_MASK 0x80 104 #define PSOC_ETR_AXICTL_WRBURSTLEN_SHIFT 8 105 #define PSOC_ETR_AXICTL_WRBURSTLEN_MASK 0xF00 106 107 /* PSOC_ETR_DBALO */ 108 #define PSOC_ETR_DBALO_BUFADDRLO_SHIFT 0 109 #define PSOC_ETR_DBALO_BUFADDRLO_MASK 0xFFFFFFFF 110 111 /* PSOC_ETR_DBAHI */ 112 #define PSOC_ETR_DBAHI_BUFADDRHI_SHIFT 0 113 #define PSOC_ETR_DBAHI_BUFADDRHI_MASK 0xFF 114 115 /* PSOC_ETR_FFSR */ 116 #define PSOC_ETR_FFSR_FLINPROG_SHIFT 0 117 #define PSOC_ETR_FFSR_FLINPROG_MASK 0x1 118 #define PSOC_ETR_FFSR_FTSTOPPED_SHIFT 1 119 #define PSOC_ETR_FFSR_FTSTOPPED_MASK 0x2 120 121 /* PSOC_ETR_FFCR */ 122 #define PSOC_ETR_FFCR_ENFT_SHIFT 0 123 #define PSOC_ETR_FFCR_ENFT_MASK 0x1 124 #define PSOC_ETR_FFCR_ENTI_SHIFT 1 125 #define PSOC_ETR_FFCR_ENTI_MASK 0x2 126 #define PSOC_ETR_FFCR_FONFLIN_SHIFT 4 127 #define PSOC_ETR_FFCR_FONFLIN_MASK 0x10 128 #define PSOC_ETR_FFCR_FONTRIGEVT_SHIFT 5 129 #define PSOC_ETR_FFCR_FONTRIGEVT_MASK 0x20 130 #define PSOC_ETR_FFCR_FLUSHMAN_SHIFT 6 131 #define PSOC_ETR_FFCR_FLUSHMAN_MASK 0x40 132 #define PSOC_ETR_FFCR_TRIGONTRIGIN_SHIFT 8 133 #define PSOC_ETR_FFCR_TRIGONTRIGIN_MASK 0x100 134 #define PSOC_ETR_FFCR_TRIGONTRIGEVT_SHIFT 9 135 #define PSOC_ETR_FFCR_TRIGONTRIGEVT_MASK 0x200 136 #define PSOC_ETR_FFCR_TRIGONFL_SHIFT 10 137 #define PSOC_ETR_FFCR_TRIGONFL_MASK 0x400 138 #define PSOC_ETR_FFCR_STOPONFL_SHIFT 12 139 #define PSOC_ETR_FFCR_STOPONFL_MASK 0x1000 140 #define PSOC_ETR_FFCR_STOPONTRIGEVT_SHIFT 13 141 #define PSOC_ETR_FFCR_STOPONTRIGEVT_MASK 0x2000 142 143 /* PSOC_ETR_PSCR */ 144 #define PSOC_ETR_PSCR_PSCOUNT_SHIFT 0 145 #define PSOC_ETR_PSCR_PSCOUNT_MASK 0x1F 146 147 /* PSOC_ETR_ITMISCOP0 */ 148 #define PSOC_ETR_ITMISCOP0_ACQCOMP_SHIFT 0 149 #define PSOC_ETR_ITMISCOP0_ACQCOMP_MASK 0x1 150 #define PSOC_ETR_ITMISCOP0_FULL_SHIFT 1 151 #define PSOC_ETR_ITMISCOP0_FULL_MASK 0x2 152 153 /* PSOC_ETR_ITTRFLIN */ 154 #define PSOC_ETR_ITTRFLIN_TRIGIN_SHIFT 0 155 #define PSOC_ETR_ITTRFLIN_TRIGIN_MASK 0x1 156 #define PSOC_ETR_ITTRFLIN_FLUSHIN_SHIFT 1 157 #define PSOC_ETR_ITTRFLIN_FLUSHIN_MASK 0x2 158 159 /* PSOC_ETR_ITATBDATA0 */ 160 #define PSOC_ETR_ITATBDATA0_ATDATASBIT0_SHIFT 0 161 #define PSOC_ETR_ITATBDATA0_ATDATASBIT0_MASK 0x1 162 #define PSOC_ETR_ITATBDATA0_ATDATASBIT7_SHIFT 1 163 #define PSOC_ETR_ITATBDATA0_ATDATASBIT7_MASK 0x2 164 #define PSOC_ETR_ITATBDATA0_ATDATASBIT15_SHIFT 2 165 #define PSOC_ETR_ITATBDATA0_ATDATASBIT15_MASK 0x4 166 #define PSOC_ETR_ITATBDATA0_ATDATASBIT23_SHIFT 3 167 #define PSOC_ETR_ITATBDATA0_ATDATASBIT23_MASK 0x8 168 #define PSOC_ETR_ITATBDATA0_ATDATASBIT31_SHIFT 4 169 #define PSOC_ETR_ITATBDATA0_ATDATASBIT31_MASK 0x10 170 #define PSOC_ETR_ITATBDATA0_ATDATASBIT39_SHIFT 5 171 #define PSOC_ETR_ITATBDATA0_ATDATASBIT39_MASK 0x20 172 #define PSOC_ETR_ITATBDATA0_ATDATASBIT47_SHIFT 6 173 #define PSOC_ETR_ITATBDATA0_ATDATASBIT47_MASK 0x40 174 #define PSOC_ETR_ITATBDATA0_ATDATASBIT55_SHIFT 7 175 #define PSOC_ETR_ITATBDATA0_ATDATASBIT55_MASK 0x80 176 #define PSOC_ETR_ITATBDATA0_ATDATASBIT63_SHIFT 8 177 #define PSOC_ETR_ITATBDATA0_ATDATASBIT63_MASK 0x100 178 179 /* PSOC_ETR_ITATBCTR2 */ 180 #define PSOC_ETR_ITATBCTR2_ATREADYS_SHIFT 0 181 #define PSOC_ETR_ITATBCTR2_ATREADYS_MASK 0x1 182 #define PSOC_ETR_ITATBCTR2_AFVALIDS_SHIFT 1 183 #define PSOC_ETR_ITATBCTR2_AFVALIDS_MASK 0x2 184 #define PSOC_ETR_ITATBCTR2_SYNCREQS_SHIFT 2 185 #define PSOC_ETR_ITATBCTR2_SYNCREQS_MASK 0x4 186 187 /* PSOC_ETR_ITATBCTR1 */ 188 #define PSOC_ETR_ITATBCTR1_ATIDS_SHIFT 0 189 #define PSOC_ETR_ITATBCTR1_ATIDS_MASK 0x7F 190 191 /* PSOC_ETR_ITATBCTR0 */ 192 #define PSOC_ETR_ITATBCTR0_ATVALIDS_SHIFT 0 193 #define PSOC_ETR_ITATBCTR0_ATVALIDS_MASK 0x1 194 #define PSOC_ETR_ITATBCTR0_AFREADYS_SHIFT 1 195 #define PSOC_ETR_ITATBCTR0_AFREADYS_MASK 0x2 196 #define PSOC_ETR_ITATBCTR0_ATBYTESS_SHIFT 8 197 #define PSOC_ETR_ITATBCTR0_ATBYTESS_MASK 0x700 198 199 /* PSOC_ETR_ITCTRL */ 200 #define PSOC_ETR_ITCTRL_INTEGRATION_MODE_SHIFT 0 201 #define PSOC_ETR_ITCTRL_INTEGRATION_MODE_MASK 0x1 202 203 /* PSOC_ETR_CLAIMSET */ 204 #define PSOC_ETR_CLAIMSET_CLAIMSET_SHIFT 0 205 #define PSOC_ETR_CLAIMSET_CLAIMSET_MASK 0xF 206 207 /* PSOC_ETR_CLAIMCLR */ 208 #define PSOC_ETR_CLAIMCLR_CLAIMCLR_SHIFT 0 209 #define PSOC_ETR_CLAIMCLR_CLAIMCLR_MASK 0xF 210 211 /* PSOC_ETR_LAR */ 212 #define PSOC_ETR_LAR_ACCESS_W_SHIFT 0 213 #define PSOC_ETR_LAR_ACCESS_W_MASK 0xFFFFFFFF 214 215 /* PSOC_ETR_LSR */ 216 #define PSOC_ETR_LSR_LOCKEXIST_SHIFT 0 217 #define PSOC_ETR_LSR_LOCKEXIST_MASK 0x1 218 #define PSOC_ETR_LSR_LOCKGRANT_SHIFT 1 219 #define PSOC_ETR_LSR_LOCKGRANT_MASK 0x2 220 #define PSOC_ETR_LSR_LOCKTYPE_SHIFT 2 221 #define PSOC_ETR_LSR_LOCKTYPE_MASK 0x4 222 223 /* PSOC_ETR_AUTHSTATUS */ 224 #define PSOC_ETR_AUTHSTATUS_NSID_SHIFT 0 225 #define PSOC_ETR_AUTHSTATUS_NSID_MASK 0x3 226 #define PSOC_ETR_AUTHSTATUS_NSNID_SHIFT 2 227 #define PSOC_ETR_AUTHSTATUS_NSNID_MASK 0xC 228 #define PSOC_ETR_AUTHSTATUS_SID_SHIFT 4 229 #define PSOC_ETR_AUTHSTATUS_SID_MASK 0x30 230 #define PSOC_ETR_AUTHSTATUS_SNID_SHIFT 6 231 #define PSOC_ETR_AUTHSTATUS_SNID_MASK 0xC0 232 233 /* PSOC_ETR_DEVID */ 234 #define PSOC_ETR_DEVID_ATBINPORTCOUNT_SHIFT 0 235 #define PSOC_ETR_DEVID_ATBINPORTCOUNT_MASK 0x1F 236 #define PSOC_ETR_DEVID_CLKSCHEME_SHIFT 5 237 #define PSOC_ETR_DEVID_CLKSCHEME_MASK 0x20 238 #define PSOC_ETR_DEVID_CONFIGTYPE_SHIFT 6 239 #define PSOC_ETR_DEVID_CONFIGTYPE_MASK 0xC0 240 #define PSOC_ETR_DEVID_MEMWIDTH_SHIFT 8 241 #define PSOC_ETR_DEVID_MEMWIDTH_MASK 0x700 242 #define PSOC_ETR_DEVID_WBUF_DEPTH_SHIFT 11 243 #define PSOC_ETR_DEVID_WBUF_DEPTH_MASK 0x3800 244 245 /* PSOC_ETR_DEVTYPE */ 246 #define PSOC_ETR_DEVTYPE_MAJOR_TYPE_SHIFT 0 247 #define PSOC_ETR_DEVTYPE_MAJOR_TYPE_MASK 0xF 248 #define PSOC_ETR_DEVTYPE_SUB_TYPE_SHIFT 4 249 #define PSOC_ETR_DEVTYPE_SUB_TYPE_MASK 0xF0 250 251 /* PSOC_ETR_PERIPHID4 */ 252 #define PSOC_ETR_PERIPHID4_JEP106_CONT_SHIFT 0 253 #define PSOC_ETR_PERIPHID4_JEP106_CONT_MASK 0xF 254 #define PSOC_ETR_PERIPHID4_FOURKB_COUNT_SHIFT 4 255 #define PSOC_ETR_PERIPHID4_FOURKB_COUNT_MASK 0xF0 256 257 /* PSOC_ETR_PERIPHID5 */ 258 #define PSOC_ETR_PERIPHID5_PERIPHID5_SHIFT 0 259 #define PSOC_ETR_PERIPHID5_PERIPHID5_MASK 0xFFFFFFFF 260 261 /* PSOC_ETR_PERIPHID6 */ 262 #define PSOC_ETR_PERIPHID6_PERIPHID6_SHIFT 0 263 #define PSOC_ETR_PERIPHID6_PERIPHID6_MASK 0xFFFFFFFF 264 265 /* PSOC_ETR_PERIPHID7 */ 266 #define PSOC_ETR_PERIPHID7_PERIPHID7_SHIFT 0 267 #define PSOC_ETR_PERIPHID7_PERIPHID7_MASK 0xFFFFFFFF 268 269 /* PSOC_ETR_PERIPHID0 */ 270 #define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_SHIFT 0 271 #define PSOC_ETR_PERIPHID0_PART_NUMBER_BITS7TO0_MASK 0xFF 272 273 /* PSOC_ETR_PERIPHID1 */ 274 #define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_SHIFT 0 275 #define PSOC_ETR_PERIPHID1_PART_NUMBER_BITS11TO8_MASK 0xF 276 #define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_SHIFT 4 277 #define PSOC_ETR_PERIPHID1_JEP106_BITS3TO0_MASK 0xF0 278 279 /* PSOC_ETR_PERIPHID2 */ 280 #define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_SHIFT 0 281 #define PSOC_ETR_PERIPHID2_JEP106_BITS6TO4_MASK 0x7 282 #define PSOC_ETR_PERIPHID2_JEDEC_SHIFT 3 283 #define PSOC_ETR_PERIPHID2_JEDEC_MASK 0x8 284 #define PSOC_ETR_PERIPHID2_REVISION_SHIFT 4 285 #define PSOC_ETR_PERIPHID2_REVISION_MASK 0xF0 286 287 /* PSOC_ETR_PERIPHID3 */ 288 #define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_SHIFT 0 289 #define PSOC_ETR_PERIPHID3_CUSTOMER_MODIFIED_MASK 0xF 290 #define PSOC_ETR_PERIPHID3_REVAND_SHIFT 4 291 #define PSOC_ETR_PERIPHID3_REVAND_MASK 0xF0 292 293 /* PSOC_ETR_COMPID0 */ 294 #define PSOC_ETR_COMPID0_PREAMBLE_SHIFT 0 295 #define PSOC_ETR_COMPID0_PREAMBLE_MASK 0xFF 296 297 /* PSOC_ETR_COMPID1 */ 298 #define PSOC_ETR_COMPID1_PREAMBLE_SHIFT 0 299 #define PSOC_ETR_COMPID1_PREAMBLE_MASK 0xF 300 #define PSOC_ETR_COMPID1_F_CLASS_SHIFT 4 301 #define PSOC_ETR_COMPID1_F_CLASS_MASK 0xF0 302 303 /* PSOC_ETR_COMPID2 */ 304 #define PSOC_ETR_COMPID2_PREAMBLE_SHIFT 0 305 #define PSOC_ETR_COMPID2_PREAMBLE_MASK 0xFF 306 307 /* PSOC_ETR_COMPID3 */ 308 #define PSOC_ETR_COMPID3_PREAMBLE_SHIFT 0 309 #define PSOC_ETR_COMPID3_PREAMBLE_MASK 0xFF 310 311 #endif /* ASIC_REG_PSOC_ETR_MASKS_H_ */ 312