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Searched refs:PRIV_STATE (Results 1 – 12 of 12) sorted by relevance

/linux/drivers/gpu/drm/amd/amdkfd/
H A Dcik_regs.h64 #define PRIV_STATE (1 << 30) macro
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1528 #define PRIV_STATE (1 << 30) macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c1481 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v11_0_mqd_init()
H A Dmes_v12_1.c1326 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v12_1_mqd_init()
H A Dmes_v12_0.c1550 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in mes_v12_0_mqd_init()
H A Dgfx_v12_0.c3022 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); in gfx_v12_0_gfx_mqd_init()
3252 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v12_0_compute_mqd_init()
H A Dgfx_v11_0.c4182 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); in gfx_v11_0_gfx_mqd_init()
4412 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v11_0_compute_mqd_init()
H A Dgfx_v9_4_3.c1847 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_4_3_xcc_mqd_init()
H A Dgfx_v12_1.c2513 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v12_1_compute_mqd_init()
H A Dgfx_v10_0.c6792 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1); in gfx_v10_0_gfx_mqd_init()
6994 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v10_0_compute_mqd_init()
H A Dgfx_v8_0.c4474 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v8_0_mqd_init()
H A Dgfx_v9_0.c3638 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); in gfx_v9_0_mqd_init()