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Searched refs:PRIV_REG_INT_ENABLE (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1335 # define PRIV_REG_INT_ENABLE (1 << 23) macro
1368 # define PRIV_REG_INT_ENABLE (1 << 23) macro
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4_3.c3260 PRIV_REG_INT_ENABLE, in gfx_v9_4_3_set_priv_reg_fault_state()
3270 PRIV_REG_INT_ENABLE, in gfx_v9_4_3_set_priv_reg_fault_state()
H A Dgfx_v12_0.c4951 PRIV_REG_INT_ENABLE, in gfx_v12_0_set_priv_reg_fault_state()
4965 PRIV_REG_INT_ENABLE, in gfx_v12_0_set_priv_reg_fault_state()
H A Dgfx_v9_0.c6109 PRIV_REG_INT_ENABLE, in gfx_v9_0_set_priv_reg_fault_state()
6119 PRIV_REG_INT_ENABLE, in gfx_v9_0_set_priv_reg_fault_state()
H A Dgfx_v11_0.c6614 PRIV_REG_INT_ENABLE, in gfx_v11_0_set_priv_reg_fault_state()
6628 PRIV_REG_INT_ENABLE, in gfx_v11_0_set_priv_reg_fault_state()
H A Dgfx_v12_1.c4044 PRIV_REG_INT_ENABLE, in gfx_v12_1_set_priv_reg_fault_state()
H A Dgfx_v10_0.c9251 PRIV_REG_INT_ENABLE, in gfx_v10_0_set_priv_reg_fault_state()
9265 PRIV_REG_INT_ENABLE, in gfx_v10_0_set_priv_reg_fault_state()
H A Dgfx_v8_0.c6354 WREG32_FIELD(CP_INT_CNTL_RING0, PRIV_REG_INT_ENABLE, in gfx_v8_0_set_priv_reg_fault_state()