Searched refs:PP_SMU_RESULT_OK (Results 1 – 4 of 4) sorted by relevance
561 return PP_SMU_RESULT_OK; in pp_nv_set_wm_ranges()577 return PP_SMU_RESULT_OK; in pp_nv_set_display_count()594 return PP_SMU_RESULT_OK; in pp_nv_set_min_deep_sleep_dcfclk()617 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_dcefclk_by_freq()640 return PP_SMU_RESULT_OK; in pp_nv_set_hard_min_uclk_by_freq()653 return PP_SMU_RESULT_OK; in pp_nv_set_pstate_handshake_support()688 return PP_SMU_RESULT_OK; in pp_nv_set_voltage_by_freq()705 return PP_SMU_RESULT_OK; in pp_nv_get_maximum_sustainable_clocks()723 return PP_SMU_RESULT_OK; in pp_nv_get_uclk_dpm_states()739 return PP_SMU_RESULT_OK; in pp_rn_get_dpm_clock_table()[all …]
63 PP_SMU_RESULT_OK = 1, enumerator
774 if (status == PP_SMU_RESULT_OK && in rn_clk_mgr_construct()
2358 uclk_states_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()2368 clock_limits_available = (status == PP_SMU_RESULT_OK); in init_soc_bounding_box()