Searched refs:PPE (Results 1 – 5 of 5) sorted by relevance
43 PPE = (1 << 2), enumerator93 control |= PPE; /* Enable prefetch/posting for disk */ in mpiix_set_piomode()
34 PPE = 0x60, /* parallel poll enable (base) */ enumerator
20 The third region is the PPE register base and size.
129 reads from its PPE mailbox channel. When data has been read success-
22580 QUALCOMM PPE DRIVER