| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| H A D | dcn30_clk_mgr.c | 267 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn3_update_clocks()
270 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn3_update_clocks()
284 …dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz… in dcn3_update_clocks()
365 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn3_set_hard_min_memclk()
368 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn3_set_hard_min_memclk()
371 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn3_set_hard_min_memclk()
384 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, in dcn3_set_hard_max_memclk()
395 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn3_set_max_memclk()
403 dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz); in dcn3_set_min_memclk()
416 dcn3_init_single_clock(clk_mgr, PPCLK_UCLK, in dcn3_get_memclk_states_from_smu()
[all …]
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| H A D | dcn30_smu11_driver_if.h | 10 PPCLK_UCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 718 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); in dcn32_update_clocks()
719 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); in dcn32_update_clocks()
721 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn32_update_clocks()
724 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz); in dcn32_update_clocks()
757 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, in dcn32_update_clocks()
760 …dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz… in dcn32_update_clocks()
1003 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn32_set_hard_min_memclk()
1006 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn32_set_hard_min_memclk()
1009 dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, in dcn32_set_hard_min_memclk()
1022 dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz); in dcn32_set_hard_max_memclk()
[all …]
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| H A D | dcn32_smu13_driver_if.h | 10 PPCLK_UCLK, enumerator
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| /linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/ |
| H A D | dcn401_clk_mgr.c | 84 case PPCLK_UCLK: in dcn401_is_ppclk_dpm_enabled()
125 case PPCLK_UCLK: in dcn401_is_ppclk_idle_dpm_enabled()
781 bool is_idle_dpm_enabled = dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) && in dcn401_build_update_bandwidth_clocks_sequence()
783 dcn401_is_ppclk_idle_dpm_enabled(clk_mgr_internal, PPCLK_UCLK) && in dcn401_build_update_bandwidth_clocks_sequence()
892 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) { in dcn401_build_update_bandwidth_clocks_sequence()
908 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) { in dcn401_build_update_bandwidth_clocks_sequence()
916 …r_base->clks.p_state_change_support && dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) { in dcn401_build_update_bandwidth_clocks_sequence()
1009 block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK; in dcn401_build_update_bandwidth_clocks_sequence()
1019 dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) { in dcn401_build_update_bandwidth_clocks_sequence()
1067 if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_UCLK)) { in dcn401_build_update_bandwidth_clocks_sequence()
[all …]
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| H A D | dcn401_smu14_driver_if.h | 13 PPCLK_UCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/ |
| H A D | smu13_driver_if_v13_0_6.h | 179 PPCLK_UCLK, enumerator
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| H A D | smu13_driver_if_aldebaran.h | 247 PPCLK_UCLK, enumerator
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| H A D | smu11_driver_if_arcturus.h | 369 PPCLK_UCLK, enumerator
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| H A D | smu11_driver_if_navi10.h | 372 PPCLK_UCLK, enumerator
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| H A D | smu13_driver_if_v13_0_0.h | 442 PPCLK_UCLK, enumerator
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| H A D | smu13_driver_if_v13_0_7.h | 443 PPCLK_UCLK, enumerator
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| H A D | smu11_driver_if_sienna_cichlid.h | 476 PPCLK_UCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| H A D | navi10_ppt.c | 156 CLK_MAP(UCLK, PPCLK_UCLK),
157 CLK_MAP(MCLK, PPCLK_UCLK),
574 *value = metrics->CurrClock[PPCLK_UCLK]; in navi10_get_legacy_smu_metrics_data()
660 *value = metrics->CurrClock[PPCLK_UCLK]; in navi10_get_smu_metrics_data()
749 *value = metrics->CurrClock[PPCLK_UCLK]; in navi12_get_legacy_smu_metrics_data()
835 *value = metrics->CurrClock[PPCLK_UCLK]; in navi12_get_smu_metrics_data()
1011 if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete) in navi10_set_default_dpm_table()
1186 case PPCLK_UCLK: in navi10_get_current_clk_freq_by_table()
2061 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels; in navi10_get_uclk_dpm_states()
2745 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; in navi10_get_legacy_gpu_metrics()
[all …]
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| H A D | arcturus_ppt.c | 167 CLK_MAP(UCLK, PPCLK_UCLK),
168 CLK_MAP(MCLK, PPCLK_UCLK),
405 if (!driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete) in arcturus_set_default_dpm_table()
623 *value = metrics->CurrClock[PPCLK_UCLK]; in arcturus_get_smu_metrics_data()
728 case PPCLK_UCLK: in arcturus_get_current_clk_freq_by_table()
911 (PPCLK_UCLK << 16) | (freq & 0xffff), in arcturus_upload_dpm_level()
1849 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; in arcturus_get_gpu_metrics()
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| H A D | sienna_cichlid_ppt.c | 171 CLK_MAP(UCLK, PPCLK_UCLK),
172 CLK_MAP(MCLK, PPCLK_UCLK),
790 *value = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : in sienna_cichlid_get_smu_metrics_data()
791 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : in sienna_cichlid_get_smu_metrics_data()
792 metrics->CurrClock[PPCLK_UCLK]; in sienna_cichlid_get_smu_metrics_data()
1007 if (!table_member[PPCLK_UCLK].SnapToDiscrete) in sienna_cichlid_set_default_dpm_table()
1210 case PPCLK_UCLK: in sienna_cichlid_get_current_clk_freq_by_table()
2022 num_discrete_levels = table_member1[PPCLK_UCLK].NumDiscreteLevels; in sienna_cichlid_get_uclk_dpm_states()
2749 gpu_metrics->current_uclk = use_metrics_v3 ? metrics_v3->CurrClock[PPCLK_UCLK] : in sienna_cichlid_get_gpu_metrics()
2750 use_metrics_v2 ? metrics_v2->CurrClock[PPCLK_UCLK] : metrics->CurrClock[PPCLK_UCLK]; in sienna_cichlid_get_gpu_metrics()
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | aldebaran_ppt.c | 162 CLK_MAP(UCLK, PPCLK_UCLK),
163 CLK_MAP(MCLK, PPCLK_UCLK),
650 *value = metrics->CurrClock[PPCLK_UCLK]; in aldebaran_get_smu_metrics_data()
753 case PPCLK_UCLK: in aldebaran_get_current_clk_freq_by_table()
886 (PPCLK_UCLK << 16) | (freq & 0xffff), in aldebaran_upload_dpm_level()
1687 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; in aldebaran_get_gpu_metrics()
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| H A D | smu_v13_0_7_ppt.c | 170 CLK_MAP(UCLK, PPCLK_UCLK),
171 CLK_MAP(MCLK, PPCLK_UCLK),
762 *value = metrics->CurrClock[PPCLK_UCLK]; in smu_v13_0_7_get_smu_metrics_data()
1021 case PPCLK_UCLK: in smu_v13_0_7_get_current_clk_freq_by_table()
2119 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; in smu_v13_0_7_get_gpu_metrics()
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| H A D | smu_v13_0_0_ppt.c | 179 CLK_MAP(UCLK, PPCLK_UCLK),
180 CLK_MAP(MCLK, PPCLK_UCLK),
749 *value = metrics->CurrClock[PPCLK_UCLK]; in smu_v13_0_0_get_smu_metrics_data()
1011 case PPCLK_UCLK: in smu_v13_0_0_get_current_clk_freq_by_table()
2117 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; in smu_v13_0_0_get_gpu_metrics()
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| H A D | smu_v13_0_6_ppt.c | 188 CLK_MAP(UCLK, PPCLK_UCLK),
189 CLK_MAP(MCLK, PPCLK_UCLK),
1474 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL); in smu_v13_0_6_upload_dpm_level()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| H A D | vega12_hwmgr.c | 682 ret = vega12_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); in vega12_setup_default_dpm_tables()
1179 (PPCLK_UCLK << 16) | (min_freq & 0xffff), in vega12_upload_dpm_min_level()
1187 (PPCLK_UCLK << 16) | (min_freq & 0xffff), in vega12_upload_dpm_min_level()
1272 (PPCLK_UCLK << 16) | (max_freq & 0xffff), in vega12_upload_dpm_max_level()
1373 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false) == 0, in vega12_dpm_get_mclk()
1378 vega12_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true) == 0, in vega12_dpm_get_mclk()
1451 smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetDpmClockFreq, (PPCLK_UCLK << 16), in vega12_get_current_mclk_freq()
2553 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level, in vega12_set_uclk_to_highest_dpm_level()
2927 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK]; in vega12_get_gpu_metrics()
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| H A D | vega20_hwmgr.c | 623 ret = vega20_setup_single_dpm_table(hwmgr, dpm_table, PPCLK_UCLK); in vega20_setup_memclk_dpm_table()
1630 PPCLK_UCLK)) == 0, in vega20_init_max_sustainable_clocks()
1843 (PPCLK_UCLK << 16) | (min_freq & 0xffff), in vega20_upload_dpm_min_level()
1946 (PPCLK_UCLK << 16) | (max_freq & 0xffff), in vega20_upload_dpm_max_level()
2101 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, false); in vega20_dpm_get_mclk()
2106 ret = vega20_get_clock_ranges(hwmgr, &mem_clk, PPCLK_UCLK, true); in vega20_dpm_get_mclk()
2233 PPCLK_UCLK, in vega20_read_sensor()
2382 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level, in vega20_notify_smc_display_config_after_ps_adjustment()
3407 ret = vega20_get_current_clk_freq(hwmgr, PPCLK_UCLK, &now); in vega20_emit_clock_levels()
3654 (PPCLK_UCLK << 16) | dpm_table->dpm_state.hard_min_level, in vega20_set_uclk_to_highest_dpm_level()
[all …]
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_2_ppt.c | 150 CLK_MAP(UCLK, PPCLK_UCLK),
151 CLK_MAP(MCLK, PPCLK_UCLK),
641 *value = metrics->CurrClock[PPCLK_UCLK]; in smu_v14_0_2_get_smu_metrics_data()
896 case PPCLK_UCLK: in smu_v14_0_2_get_current_clk_freq_by_table()
2172 gpu_metrics->current_uclk = metrics->CurrClock[PPCLK_UCLK]; in smu_v14_0_2_get_gpu_metrics()
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/ |
| H A D | smu9_driver_if.h | 224 PPCLK_UCLK, enumerator
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| /linux/drivers/gpu/drm/amd/pm/powerplay/inc/ |
| H A D | smu11_driver_if.h | 322 PPCLK_UCLK, enumerator
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