1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Comedi driver for National Instruments PCI-DIO-32HS
4 *
5 * COMEDI - Linux Control and Measurement Device Interface
6 * Copyright (C) 1999,2002 David A. Schleef <ds@schleef.org>
7 */
8
9 /*
10 * Driver: ni_pcidio
11 * Description: National Instruments PCI-DIO32HS, PCI-6533
12 * Author: ds
13 * Status: works
14 * Devices: [National Instruments] PCI-DIO-32HS (ni_pcidio)
15 * [National Instruments] PXI-6533, PCI-6533 (pxi-6533)
16 * [National Instruments] PCI-6534 (pci-6534)
17 * Updated: Mon, 09 Jan 2012 14:27:23 +0000
18 *
19 * The DIO32HS board appears as one subdevice, with 32 channels. Each
20 * channel is individually I/O configurable. The channel order is 0=A0,
21 * 1=A1, 2=A2, ... 8=B0, 16=C0, 24=D0. The driver only supports simple
22 * digital I/O; no handshaking is supported.
23 *
24 * DMA mostly works for the PCI-DIO32HS, but only in timed input mode.
25 *
26 * The PCI-DIO-32HS/PCI-6533 has a configurable external trigger. Setting
27 * scan_begin_arg to 0 or CR_EDGE triggers on the leading edge. Setting
28 * scan_begin_arg to CR_INVERT or (CR_EDGE | CR_INVERT) triggers on the
29 * trailing edge.
30 *
31 * This driver could be easily modified to support AT-MIO32HS and AT-MIO96.
32 *
33 * The PCI-6534 requires a firmware upload after power-up to work, the
34 * firmware data and instructions for loading it with comedi_config
35 * it are contained in the comedi_nonfree_firmware tarball available from
36 * https://www.comedi.org
37 */
38
39 #define USE_DMA
40
41 #include <linux/module.h>
42 #include <linux/delay.h>
43 #include <linux/interrupt.h>
44 #include <linux/sched.h>
45 #include <linux/comedi/comedi_pci.h>
46
47 #include "mite.h"
48
49 /* defines for the PCI-DIO-32HS */
50
51 #define WINDOW_ADDRESS 4 /* W */
52 #define INTERRUPT_AND_WINDOW_STATUS 4 /* R */
53 #define INT_STATUS_1 BIT(0)
54 #define INT_STATUS_2 BIT(1)
55 #define WINDOW_ADDRESS_STATUS_MASK 0x7c
56
57 #define MASTER_DMA_AND_INTERRUPT_CONTROL 5 /* W */
58 #define INTERRUPT_LINE(x) ((x) & 3)
59 #define OPEN_INT BIT(2)
60 #define GROUP_STATUS 5 /* R */
61 #define DATA_LEFT BIT(0)
62 #define REQ BIT(2)
63 #define STOP_TRIG BIT(3)
64
65 #define GROUP_1_FLAGS 6 /* R */
66 #define GROUP_2_FLAGS 7 /* R */
67 #define TRANSFER_READY BIT(0)
68 #define COUNT_EXPIRED BIT(1)
69 #define WAITED BIT(5)
70 #define PRIMARY_TC BIT(6)
71 #define SECONDARY_TC BIT(7)
72 /* #define SerialRose */
73 /* #define ReqRose */
74 /* #define Paused */
75
76 #define GROUP_1_FIRST_CLEAR 6 /* W */
77 #define GROUP_2_FIRST_CLEAR 7 /* W */
78 #define CLEAR_WAITED BIT(3)
79 #define CLEAR_PRIMARY_TC BIT(4)
80 #define CLEAR_SECONDARY_TC BIT(5)
81 #define DMA_RESET BIT(6)
82 #define FIFO_RESET BIT(7)
83 #define CLEAR_ALL 0xf8
84
85 #define GROUP_1_FIFO 8 /* W */
86 #define GROUP_2_FIFO 12 /* W */
87
88 #define TRANSFER_COUNT 20
89 #define CHIP_ID_D 24
90 #define CHIP_ID_I 25
91 #define CHIP_ID_O 26
92 #define CHIP_VERSION 27
93 #define PORT_IO(x) (28 + (x))
94 #define PORT_PIN_DIRECTIONS(x) (32 + (x))
95 #define PORT_PIN_MASK(x) (36 + (x))
96 #define PORT_PIN_POLARITIES(x) (40 + (x))
97
98 #define MASTER_CLOCK_ROUTING 45
99 #define RTSI_CLOCKING(x) (((x) & 3) << 4)
100
101 #define GROUP_1_SECOND_CLEAR 46 /* W */
102 #define GROUP_2_SECOND_CLEAR 47 /* W */
103 #define CLEAR_EXPIRED BIT(0)
104
105 #define PORT_PATTERN(x) (48 + (x))
106
107 #define DATA_PATH 64
108 #define FIFO_ENABLE_A BIT(0)
109 #define FIFO_ENABLE_B BIT(1)
110 #define FIFO_ENABLE_C BIT(2)
111 #define FIFO_ENABLE_D BIT(3)
112 #define FUNNELING(x) (((x) & 3) << 4)
113 #define GROUP_DIRECTION BIT(7)
114
115 #define PROTOCOL_REGISTER_1 65
116 #define OP_MODE PROTOCOL_REGISTER_1
117 #define RUN_MODE(x) ((x) & 7)
118 #define NUMBERED BIT(3)
119
120 #define PROTOCOL_REGISTER_2 66
121 #define CLOCK_REG PROTOCOL_REGISTER_2
122 #define CLOCK_LINE(x) (((x) & 3) << 5)
123 #define INVERT_STOP_TRIG BIT(7)
124 #define DATA_LATCHING(x) (((x) & 3) << 5)
125
126 #define PROTOCOL_REGISTER_3 67
127 #define SEQUENCE PROTOCOL_REGISTER_3
128
129 #define PROTOCOL_REGISTER_14 68 /* 16 bit */
130 #define CLOCK_SPEED PROTOCOL_REGISTER_14
131
132 #define PROTOCOL_REGISTER_4 70
133 #define REQ_REG PROTOCOL_REGISTER_4
134 #define REQ_CONDITIONING(x) (((x) & 7) << 3)
135
136 #define PROTOCOL_REGISTER_5 71
137 #define BLOCK_MODE PROTOCOL_REGISTER_5
138
139 #define FIFO_Control 72
140 #define READY_LEVEL(x) ((x) & 7)
141
142 #define PROTOCOL_REGISTER_6 73
143 #define LINE_POLARITIES PROTOCOL_REGISTER_6
144 #define INVERT_ACK BIT(0)
145 #define INVERT_REQ BIT(1)
146 #define INVERT_CLOCK BIT(2)
147 #define INVERT_SERIAL BIT(3)
148 #define OPEN_ACK BIT(4)
149 #define OPEN_CLOCK BIT(5)
150
151 #define PROTOCOL_REGISTER_7 74
152 #define ACK_SER PROTOCOL_REGISTER_7
153 #define ACK_LINE(x) (((x) & 3) << 2)
154 #define EXCHANGE_PINS BIT(7)
155
156 #define INTERRUPT_CONTROL 75
157 /* bits same as flags */
158
159 #define DMA_LINE_CONTROL_GROUP1 76
160 #define DMA_LINE_CONTROL_GROUP2 108
161
162 /* channel zero is none */
primary_DMAChannel_bits(unsigned int channel)163 static inline unsigned int primary_DMAChannel_bits(unsigned int channel)
164 {
165 return channel & 0x3;
166 }
167
secondary_DMAChannel_bits(unsigned int channel)168 static inline unsigned int secondary_DMAChannel_bits(unsigned int channel)
169 {
170 return (channel << 2) & 0xc;
171 }
172
173 #define TRANSFER_SIZE_CONTROL 77
174 #define TRANSFER_WIDTH(x) ((x) & 3)
175 #define TRANSFER_LENGTH(x) (((x) & 3) << 3)
176 #define REQUIRE_R_LEVEL BIT(5)
177
178 #define PROTOCOL_REGISTER_15 79
179 #define DAQ_OPTIONS PROTOCOL_REGISTER_15
180 #define START_SOURCE(x) ((x) & 0x3)
181 #define INVERT_START BIT(2)
182 #define STOP_SOURCE(x) (((x) & 0x3) << 3)
183 #define REQ_START BIT(6)
184 #define PRE_START BIT(7)
185
186 #define PATTERN_DETECTION 81
187 #define DETECTION_METHOD BIT(0)
188 #define INVERT_MATCH BIT(1)
189 #define IE_PATTERN_DETECTION BIT(2)
190
191 #define PROTOCOL_REGISTER_9 82
192 #define REQ_DELAY PROTOCOL_REGISTER_9
193
194 #define PROTOCOL_REGISTER_10 83
195 #define REQ_NOT_DELAY PROTOCOL_REGISTER_10
196
197 #define PROTOCOL_REGISTER_11 84
198 #define ACK_DELAY PROTOCOL_REGISTER_11
199
200 #define PROTOCOL_REGISTER_12 85
201 #define ACK_NOT_DELAY PROTOCOL_REGISTER_12
202
203 #define PROTOCOL_REGISTER_13 86
204 #define DATA_1_DELAY PROTOCOL_REGISTER_13
205
206 #define PROTOCOL_REGISTER_8 88 /* 32 bit */
207 #define START_DELAY PROTOCOL_REGISTER_8
208
209 /* Firmware files for PCI-6524 */
210 #define FW_PCI_6534_MAIN "ni6534a.bin"
211 #define FW_PCI_6534_SCARAB_DI "niscrb01.bin"
212 #define FW_PCI_6534_SCARAB_DO "niscrb02.bin"
213 MODULE_FIRMWARE(FW_PCI_6534_MAIN);
214 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DI);
215 MODULE_FIRMWARE(FW_PCI_6534_SCARAB_DO);
216
217 enum pci_6534_firmware_registers { /* 16 bit */
218 Firmware_Control_Register = 0x100,
219 Firmware_Status_Register = 0x104,
220 Firmware_Data_Register = 0x108,
221 Firmware_Mask_Register = 0x10c,
222 Firmware_Debug_Register = 0x110,
223 };
224
225 /* main fpga registers (32 bit)*/
226 enum pci_6534_fpga_registers {
227 FPGA_Control1_Register = 0x200,
228 FPGA_Control2_Register = 0x204,
229 FPGA_Irq_Mask_Register = 0x208,
230 FPGA_Status_Register = 0x20c,
231 FPGA_Signature_Register = 0x210,
232 FPGA_SCALS_Counter_Register = 0x280, /*write-clear */
233 FPGA_SCAMS_Counter_Register = 0x284, /*write-clear */
234 FPGA_SCBLS_Counter_Register = 0x288, /*write-clear */
235 FPGA_SCBMS_Counter_Register = 0x28c, /*write-clear */
236 FPGA_Temp_Control_Register = 0x2a0,
237 FPGA_DAR_Register = 0x2a8,
238 FPGA_ELC_Read_Register = 0x2b8,
239 FPGA_ELC_Write_Register = 0x2bc,
240 };
241
242 enum FPGA_Control_Bits {
243 FPGA_Enable_Bit = 0x8000,
244 };
245
246 #define TIMER_BASE 50 /* nanoseconds */
247
248 #ifdef USE_DMA
249 #define INT_EN (COUNT_EXPIRED | WAITED | PRIMARY_TC | SECONDARY_TC)
250 #else
251 #define INT_EN (TRANSFER_READY | COUNT_EXPIRED | WAITED \
252 | PRIMARY_TC | SECONDARY_TC)
253 #endif
254
255 enum nidio_boardid {
256 BOARD_PCIDIO_32HS,
257 BOARD_PXI6533,
258 BOARD_PCI6534,
259 };
260
261 struct nidio_board {
262 const char *name;
263 unsigned int uses_firmware:1;
264 unsigned int dio_speed;
265 };
266
267 static const struct nidio_board nidio_boards[] = {
268 [BOARD_PCIDIO_32HS] = {
269 .name = "pci-dio-32hs",
270 .dio_speed = 50,
271 },
272 [BOARD_PXI6533] = {
273 .name = "pxi-6533",
274 .dio_speed = 50,
275 },
276 [BOARD_PCI6534] = {
277 .name = "pci-6534",
278 .uses_firmware = 1,
279 .dio_speed = 50,
280 },
281 };
282
283 struct nidio96_private {
284 struct mite *mite;
285 int boardtype;
286 int dio;
287 unsigned short OP_MODEBits;
288 struct mite_channel *di_mite_chan;
289 struct mite_ring *di_mite_ring;
290 spinlock_t mite_channel_lock;
291 };
292
ni_pcidio_request_di_mite_channel(struct comedi_device * dev)293 static int ni_pcidio_request_di_mite_channel(struct comedi_device *dev)
294 {
295 struct nidio96_private *devpriv = dev->private;
296 unsigned long flags;
297
298 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
299 BUG_ON(devpriv->di_mite_chan);
300 devpriv->di_mite_chan =
301 mite_request_channel_in_range(devpriv->mite,
302 devpriv->di_mite_ring, 1, 2);
303 if (!devpriv->di_mite_chan) {
304 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
305 dev_err(dev->class_dev, "failed to reserve mite dma channel\n");
306 return -EBUSY;
307 }
308 devpriv->di_mite_chan->dir = COMEDI_INPUT;
309 writeb(primary_DMAChannel_bits(devpriv->di_mite_chan->channel) |
310 secondary_DMAChannel_bits(devpriv->di_mite_chan->channel),
311 dev->mmio + DMA_LINE_CONTROL_GROUP1);
312 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
313 return 0;
314 }
315
ni_pcidio_release_di_mite_channel(struct comedi_device * dev)316 static void ni_pcidio_release_di_mite_channel(struct comedi_device *dev)
317 {
318 struct nidio96_private *devpriv = dev->private;
319 unsigned long flags;
320
321 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
322 if (devpriv->di_mite_chan) {
323 mite_release_channel(devpriv->di_mite_chan);
324 devpriv->di_mite_chan = NULL;
325 writeb(primary_DMAChannel_bits(0) |
326 secondary_DMAChannel_bits(0),
327 dev->mmio + DMA_LINE_CONTROL_GROUP1);
328 }
329 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
330 }
331
setup_mite_dma(struct comedi_device * dev,struct comedi_subdevice * s)332 static int setup_mite_dma(struct comedi_device *dev, struct comedi_subdevice *s)
333 {
334 struct nidio96_private *devpriv = dev->private;
335 int retval;
336 unsigned long flags;
337
338 retval = ni_pcidio_request_di_mite_channel(dev);
339 if (retval)
340 return retval;
341
342 /* write alloc the entire buffer */
343 comedi_buf_write_alloc(s, s->async->prealloc_bufsz);
344
345 spin_lock_irqsave(&devpriv->mite_channel_lock, flags);
346 if (devpriv->di_mite_chan) {
347 mite_prep_dma(devpriv->di_mite_chan, 32, 32);
348 mite_dma_arm(devpriv->di_mite_chan);
349 } else {
350 retval = -EIO;
351 }
352 spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
353
354 return retval;
355 }
356
ni_pcidio_poll(struct comedi_device * dev,struct comedi_subdevice * s)357 static int ni_pcidio_poll(struct comedi_device *dev, struct comedi_subdevice *s)
358 {
359 struct nidio96_private *devpriv = dev->private;
360 unsigned long irq_flags;
361 int count;
362
363 spin_lock_irqsave(&dev->spinlock, irq_flags);
364 spin_lock(&devpriv->mite_channel_lock);
365 if (devpriv->di_mite_chan)
366 mite_sync_dma(devpriv->di_mite_chan, s);
367 spin_unlock(&devpriv->mite_channel_lock);
368 count = comedi_buf_n_bytes_ready(s);
369 spin_unlock_irqrestore(&dev->spinlock, irq_flags);
370 return count;
371 }
372
nidio_interrupt(int irq,void * d)373 static irqreturn_t nidio_interrupt(int irq, void *d)
374 {
375 struct comedi_device *dev = d;
376 struct nidio96_private *devpriv = dev->private;
377 struct comedi_subdevice *s = dev->read_subdev;
378 struct comedi_async *async = s->async;
379 unsigned int auxdata;
380 int flags;
381 int status;
382 int work = 0;
383
384 /* interrupcions parasites */
385 if (!dev->attached) {
386 /* assume it's from another card */
387 return IRQ_NONE;
388 }
389
390 /* Lock to avoid race with comedi_poll */
391 spin_lock(&dev->spinlock);
392
393 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
394 flags = readb(dev->mmio + GROUP_1_FLAGS);
395
396 spin_lock(&devpriv->mite_channel_lock);
397 if (devpriv->di_mite_chan) {
398 mite_ack_linkc(devpriv->di_mite_chan, s, false);
399 /* XXX need to byteswap sync'ed dma */
400 }
401 spin_unlock(&devpriv->mite_channel_lock);
402
403 while (status & DATA_LEFT) {
404 work++;
405 if (work > 20) {
406 dev_dbg(dev->class_dev, "too much work in interrupt\n");
407 writeb(0x00,
408 dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
409 break;
410 }
411
412 flags &= INT_EN;
413
414 if (flags & TRANSFER_READY) {
415 while (flags & TRANSFER_READY) {
416 work++;
417 if (work > 100) {
418 dev_dbg(dev->class_dev,
419 "too much work in interrupt\n");
420 writeb(0x00, dev->mmio +
421 MASTER_DMA_AND_INTERRUPT_CONTROL
422 );
423 goto out;
424 }
425 auxdata = readl(dev->mmio + GROUP_1_FIFO);
426 comedi_buf_write_samples(s, &auxdata, 1);
427 flags = readb(dev->mmio + GROUP_1_FLAGS);
428 }
429 }
430
431 if (flags & COUNT_EXPIRED) {
432 writeb(CLEAR_EXPIRED, dev->mmio + GROUP_1_SECOND_CLEAR);
433 async->events |= COMEDI_CB_EOA;
434
435 writeb(0x00, dev->mmio + OP_MODE);
436 break;
437 } else if (flags & WAITED) {
438 writeb(CLEAR_WAITED, dev->mmio + GROUP_1_FIRST_CLEAR);
439 async->events |= COMEDI_CB_ERROR;
440 break;
441 } else if (flags & PRIMARY_TC) {
442 writeb(CLEAR_PRIMARY_TC,
443 dev->mmio + GROUP_1_FIRST_CLEAR);
444 async->events |= COMEDI_CB_EOA;
445 } else if (flags & SECONDARY_TC) {
446 writeb(CLEAR_SECONDARY_TC,
447 dev->mmio + GROUP_1_FIRST_CLEAR);
448 async->events |= COMEDI_CB_EOA;
449 }
450
451 flags = readb(dev->mmio + GROUP_1_FLAGS);
452 status = readb(dev->mmio + INTERRUPT_AND_WINDOW_STATUS);
453 }
454
455 out:
456 comedi_handle_events(dev, s);
457 #if 0
458 if (!tag)
459 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
460 #endif
461
462 spin_unlock(&dev->spinlock);
463 return IRQ_HANDLED;
464 }
465
ni_pcidio_insn_config(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)466 static int ni_pcidio_insn_config(struct comedi_device *dev,
467 struct comedi_subdevice *s,
468 struct comedi_insn *insn,
469 unsigned int *data)
470 {
471 int ret;
472
473 if (data[0] == INSN_CONFIG_GET_CMD_TIMING_CONSTRAINTS) {
474 const struct nidio_board *board = dev->board_ptr;
475
476 /* we don't care about actual channels */
477 data[1] = board->dio_speed;
478 data[2] = 0;
479 return 0;
480 }
481
482 ret = comedi_dio_insn_config(dev, s, insn, data, 0);
483 if (ret)
484 return ret;
485
486 writel(s->io_bits, dev->mmio + PORT_PIN_DIRECTIONS(0));
487
488 return insn->n;
489 }
490
ni_pcidio_insn_bits(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_insn * insn,unsigned int * data)491 static int ni_pcidio_insn_bits(struct comedi_device *dev,
492 struct comedi_subdevice *s,
493 struct comedi_insn *insn,
494 unsigned int *data)
495 {
496 if (comedi_dio_update_state(s, data))
497 writel(s->state, dev->mmio + PORT_IO(0));
498
499 data[1] = readl(dev->mmio + PORT_IO(0));
500
501 return insn->n;
502 }
503
ni_pcidio_ns_to_timer(int * nanosec,unsigned int flags)504 static int ni_pcidio_ns_to_timer(int *nanosec, unsigned int flags)
505 {
506 int divider, base;
507
508 base = TIMER_BASE;
509
510 switch (flags & CMDF_ROUND_MASK) {
511 case CMDF_ROUND_NEAREST:
512 default:
513 divider = DIV_ROUND_CLOSEST(*nanosec, base);
514 break;
515 case CMDF_ROUND_DOWN:
516 divider = (*nanosec) / base;
517 break;
518 case CMDF_ROUND_UP:
519 divider = DIV_ROUND_UP(*nanosec, base);
520 break;
521 }
522
523 *nanosec = base * divider;
524 return divider;
525 }
526
ni_pcidio_cmdtest(struct comedi_device * dev,struct comedi_subdevice * s,struct comedi_cmd * cmd)527 static int ni_pcidio_cmdtest(struct comedi_device *dev,
528 struct comedi_subdevice *s, struct comedi_cmd *cmd)
529 {
530 int err = 0;
531 unsigned int arg;
532
533 /* Step 1 : check if triggers are trivially valid */
534
535 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_INT);
536 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
537 TRIG_TIMER | TRIG_EXT);
538 err |= comedi_check_trigger_src(&cmd->convert_src, TRIG_NOW);
539 err |= comedi_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
540 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
541
542 if (err)
543 return 1;
544
545 /* Step 2a : make sure trigger sources are unique */
546
547 err |= comedi_check_trigger_is_unique(cmd->start_src);
548 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
549 err |= comedi_check_trigger_is_unique(cmd->stop_src);
550
551 /* Step 2b : and mutually compatible */
552
553 if (err)
554 return 2;
555
556 /* Step 3: check if arguments are trivially valid */
557
558 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
559
560 #define MAX_SPEED (TIMER_BASE) /* in nanoseconds */
561
562 if (cmd->scan_begin_src == TRIG_TIMER) {
563 err |= comedi_check_trigger_arg_min(&cmd->scan_begin_arg,
564 MAX_SPEED);
565 /* no minimum speed */
566 } else {
567 /* TRIG_EXT */
568 /* should be level/edge, hi/lo specification here */
569 if ((cmd->scan_begin_arg & ~(CR_EDGE | CR_INVERT)) != 0) {
570 cmd->scan_begin_arg &= (CR_EDGE | CR_INVERT);
571 err |= -EINVAL;
572 }
573 }
574
575 err |= comedi_check_trigger_arg_is(&cmd->convert_arg, 0);
576 err |= comedi_check_trigger_arg_is(&cmd->scan_end_arg,
577 cmd->chanlist_len);
578
579 if (cmd->stop_src == TRIG_COUNT)
580 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
581 else /* TRIG_NONE */
582 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
583
584 if (err)
585 return 3;
586
587 /* step 4: fix up any arguments */
588
589 if (cmd->scan_begin_src == TRIG_TIMER) {
590 arg = cmd->scan_begin_arg;
591 ni_pcidio_ns_to_timer(&arg, cmd->flags);
592 err |= comedi_check_trigger_arg_is(&cmd->scan_begin_arg, arg);
593 }
594
595 if (err)
596 return 4;
597
598 return 0;
599 }
600
ni_pcidio_inttrig(struct comedi_device * dev,struct comedi_subdevice * s,unsigned int trig_num)601 static int ni_pcidio_inttrig(struct comedi_device *dev,
602 struct comedi_subdevice *s,
603 unsigned int trig_num)
604 {
605 struct nidio96_private *devpriv = dev->private;
606 struct comedi_cmd *cmd = &s->async->cmd;
607
608 if (trig_num != cmd->start_arg)
609 return -EINVAL;
610
611 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
612 s->async->inttrig = NULL;
613
614 return 1;
615 }
616
ni_pcidio_cmd(struct comedi_device * dev,struct comedi_subdevice * s)617 static int ni_pcidio_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
618 {
619 struct nidio96_private *devpriv = dev->private;
620 struct comedi_cmd *cmd = &s->async->cmd;
621
622 /* XXX configure ports for input */
623 writel(0x0000, dev->mmio + PORT_PIN_DIRECTIONS(0));
624
625 if (1) {
626 /* enable fifos A B C D */
627 writeb(0x0f, dev->mmio + DATA_PATH);
628
629 /* set transfer width a 32 bits */
630 writeb(TRANSFER_WIDTH(0) | TRANSFER_LENGTH(0),
631 dev->mmio + TRANSFER_SIZE_CONTROL);
632 } else {
633 writeb(0x03, dev->mmio + DATA_PATH);
634 writeb(TRANSFER_WIDTH(3) | TRANSFER_LENGTH(0),
635 dev->mmio + TRANSFER_SIZE_CONTROL);
636 }
637
638 /* protocol configuration */
639 if (cmd->scan_begin_src == TRIG_TIMER) {
640 /* page 4-5, "input with internal REQs" */
641 writeb(0, dev->mmio + OP_MODE);
642 writeb(0x00, dev->mmio + CLOCK_REG);
643 writeb(1, dev->mmio + SEQUENCE);
644 writeb(0x04, dev->mmio + REQ_REG);
645 writeb(4, dev->mmio + BLOCK_MODE);
646 writeb(3, dev->mmio + LINE_POLARITIES);
647 writeb(0xc0, dev->mmio + ACK_SER);
648 writel(ni_pcidio_ns_to_timer(&cmd->scan_begin_arg,
649 CMDF_ROUND_NEAREST),
650 dev->mmio + START_DELAY);
651 writeb(1, dev->mmio + REQ_DELAY);
652 writeb(1, dev->mmio + REQ_NOT_DELAY);
653 writeb(1, dev->mmio + ACK_DELAY);
654 writeb(0x0b, dev->mmio + ACK_NOT_DELAY);
655 writeb(0x01, dev->mmio + DATA_1_DELAY);
656 /*
657 * manual, page 4-5:
658 * CLOCK_SPEED comment is incorrectly listed on DAQ_OPTIONS
659 */
660 writew(0, dev->mmio + CLOCK_SPEED);
661 writeb(0, dev->mmio + DAQ_OPTIONS);
662 } else {
663 /* TRIG_EXT */
664 /* page 4-5, "input with external REQs" */
665 writeb(0, dev->mmio + OP_MODE);
666 writeb(0x00, dev->mmio + CLOCK_REG);
667 writeb(0, dev->mmio + SEQUENCE);
668 writeb(0x00, dev->mmio + REQ_REG);
669 writeb(4, dev->mmio + BLOCK_MODE);
670 if (!(cmd->scan_begin_arg & CR_INVERT)) /* Leading Edge */
671 writeb(0, dev->mmio + LINE_POLARITIES);
672 else /* Trailing Edge */
673 writeb(2, dev->mmio + LINE_POLARITIES);
674 writeb(0x00, dev->mmio + ACK_SER);
675 writel(1, dev->mmio + START_DELAY);
676 writeb(1, dev->mmio + REQ_DELAY);
677 writeb(1, dev->mmio + REQ_NOT_DELAY);
678 writeb(1, dev->mmio + ACK_DELAY);
679 writeb(0x0C, dev->mmio + ACK_NOT_DELAY);
680 writeb(0x10, dev->mmio + DATA_1_DELAY);
681 writew(0, dev->mmio + CLOCK_SPEED);
682 writeb(0x60, dev->mmio + DAQ_OPTIONS);
683 }
684
685 if (cmd->stop_src == TRIG_COUNT) {
686 writel(cmd->stop_arg,
687 dev->mmio + TRANSFER_COUNT);
688 } else {
689 /* XXX */
690 }
691
692 #ifdef USE_DMA
693 writeb(CLEAR_PRIMARY_TC | CLEAR_SECONDARY_TC,
694 dev->mmio + GROUP_1_FIRST_CLEAR);
695
696 {
697 int retval = setup_mite_dma(dev, s);
698
699 if (retval)
700 return retval;
701 }
702 #else
703 writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP1);
704 #endif
705 writeb(0x00, dev->mmio + DMA_LINE_CONTROL_GROUP2);
706
707 /* clear and enable interrupts */
708 writeb(0xff, dev->mmio + GROUP_1_FIRST_CLEAR);
709 /* writeb(CLEAR_EXPIRED, dev->mmio+GROUP_1_SECOND_CLEAR); */
710
711 writeb(INT_EN, dev->mmio + INTERRUPT_CONTROL);
712 writeb(0x03, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
713
714 if (cmd->stop_src == TRIG_NONE) {
715 devpriv->OP_MODEBits = DATA_LATCHING(0) | RUN_MODE(7);
716 } else { /* TRIG_TIMER */
717 devpriv->OP_MODEBits = NUMBERED | RUN_MODE(7);
718 }
719 if (cmd->start_src == TRIG_NOW) {
720 /* start */
721 writeb(devpriv->OP_MODEBits, dev->mmio + OP_MODE);
722 s->async->inttrig = NULL;
723 } else {
724 /* TRIG_INT */
725 s->async->inttrig = ni_pcidio_inttrig;
726 }
727
728 return 0;
729 }
730
ni_pcidio_cancel(struct comedi_device * dev,struct comedi_subdevice * s)731 static int ni_pcidio_cancel(struct comedi_device *dev,
732 struct comedi_subdevice *s)
733 {
734 writeb(0x00, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
735 ni_pcidio_release_di_mite_channel(dev);
736
737 return 0;
738 }
739
ni_pcidio_change(struct comedi_device * dev,struct comedi_subdevice * s)740 static int ni_pcidio_change(struct comedi_device *dev,
741 struct comedi_subdevice *s)
742 {
743 struct nidio96_private *devpriv = dev->private;
744 int ret;
745
746 ret = mite_buf_change(devpriv->di_mite_ring, s);
747 if (ret < 0)
748 return ret;
749
750 memset(s->async->prealloc_buf, 0xaa, s->async->prealloc_bufsz);
751
752 return 0;
753 }
754
pci_6534_load_fpga(struct comedi_device * dev,const u8 * data,size_t data_len,unsigned long context)755 static int pci_6534_load_fpga(struct comedi_device *dev,
756 const u8 *data, size_t data_len,
757 unsigned long context)
758 {
759 static const int timeout = 1000;
760 int fpga_index = context;
761 int i;
762 size_t j;
763
764 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
765 writew(0xc0 | fpga_index, dev->mmio + Firmware_Control_Register);
766 for (i = 0;
767 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0 &&
768 i < timeout; ++i) {
769 udelay(1);
770 }
771 if (i == timeout) {
772 dev_warn(dev->class_dev,
773 "ni_pcidio: failed to load fpga %i, waiting for status 0x2\n",
774 fpga_index);
775 return -EIO;
776 }
777 writew(0x80 | fpga_index, dev->mmio + Firmware_Control_Register);
778 for (i = 0;
779 readw(dev->mmio + Firmware_Status_Register) != 0x3 &&
780 i < timeout; ++i) {
781 udelay(1);
782 }
783 if (i == timeout) {
784 dev_warn(dev->class_dev,
785 "ni_pcidio: failed to load fpga %i, waiting for status 0x3\n",
786 fpga_index);
787 return -EIO;
788 }
789 for (j = 0; j + 1 < data_len;) {
790 unsigned int value = data[j++];
791
792 value |= data[j++] << 8;
793 writew(value, dev->mmio + Firmware_Data_Register);
794 for (i = 0;
795 (readw(dev->mmio + Firmware_Status_Register) & 0x2) == 0
796 && i < timeout; ++i) {
797 udelay(1);
798 }
799 if (i == timeout) {
800 dev_warn(dev->class_dev,
801 "ni_pcidio: failed to load word into fpga %i\n",
802 fpga_index);
803 return -EIO;
804 }
805 if (need_resched())
806 schedule();
807 }
808 writew(0x0, dev->mmio + Firmware_Control_Register);
809 return 0;
810 }
811
pci_6534_reset_fpga(struct comedi_device * dev,int fpga_index)812 static int pci_6534_reset_fpga(struct comedi_device *dev, int fpga_index)
813 {
814 return pci_6534_load_fpga(dev, NULL, 0, fpga_index);
815 }
816
pci_6534_reset_fpgas(struct comedi_device * dev)817 static int pci_6534_reset_fpgas(struct comedi_device *dev)
818 {
819 int ret;
820 int i;
821
822 writew(0x0, dev->mmio + Firmware_Control_Register);
823 for (i = 0; i < 3; ++i) {
824 ret = pci_6534_reset_fpga(dev, i);
825 if (ret < 0)
826 break;
827 }
828 writew(0x0, dev->mmio + Firmware_Mask_Register);
829 return ret;
830 }
831
pci_6534_init_main_fpga(struct comedi_device * dev)832 static void pci_6534_init_main_fpga(struct comedi_device *dev)
833 {
834 writel(0, dev->mmio + FPGA_Control1_Register);
835 writel(0, dev->mmio + FPGA_Control2_Register);
836 writel(0, dev->mmio + FPGA_SCALS_Counter_Register);
837 writel(0, dev->mmio + FPGA_SCAMS_Counter_Register);
838 writel(0, dev->mmio + FPGA_SCBLS_Counter_Register);
839 writel(0, dev->mmio + FPGA_SCBMS_Counter_Register);
840 }
841
pci_6534_upload_firmware(struct comedi_device * dev)842 static int pci_6534_upload_firmware(struct comedi_device *dev)
843 {
844 struct nidio96_private *devpriv = dev->private;
845 static const char *const fw_file[3] = {
846 FW_PCI_6534_SCARAB_DI, /* loaded into scarab A for DI */
847 FW_PCI_6534_SCARAB_DO, /* loaded into scarab B for DO */
848 FW_PCI_6534_MAIN, /* loaded into main FPGA */
849 };
850 int ret;
851 int n;
852
853 ret = pci_6534_reset_fpgas(dev);
854 if (ret < 0)
855 return ret;
856 /* load main FPGA first, then the two scarabs */
857 for (n = 2; n >= 0; n--) {
858 ret = comedi_load_firmware(dev, &devpriv->mite->pcidev->dev,
859 fw_file[n],
860 pci_6534_load_fpga, n);
861 if (ret == 0 && n == 2)
862 pci_6534_init_main_fpga(dev);
863 if (ret < 0)
864 break;
865 }
866 return ret;
867 }
868
nidio_reset_board(struct comedi_device * dev)869 static void nidio_reset_board(struct comedi_device *dev)
870 {
871 writel(0, dev->mmio + PORT_IO(0));
872 writel(0, dev->mmio + PORT_PIN_DIRECTIONS(0));
873 writel(0, dev->mmio + PORT_PIN_MASK(0));
874
875 /* disable interrupts on board */
876 writeb(0, dev->mmio + MASTER_DMA_AND_INTERRUPT_CONTROL);
877 }
878
nidio_auto_attach(struct comedi_device * dev,unsigned long context)879 static int nidio_auto_attach(struct comedi_device *dev,
880 unsigned long context)
881 {
882 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
883 const struct nidio_board *board = NULL;
884 struct nidio96_private *devpriv;
885 struct comedi_subdevice *s;
886 int ret;
887 unsigned int irq;
888
889 if (context < ARRAY_SIZE(nidio_boards))
890 board = &nidio_boards[context];
891 if (!board)
892 return -ENODEV;
893 dev->board_ptr = board;
894 dev->board_name = board->name;
895
896 ret = comedi_pci_enable(dev);
897 if (ret)
898 return ret;
899
900 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
901 if (!devpriv)
902 return -ENOMEM;
903
904 spin_lock_init(&devpriv->mite_channel_lock);
905
906 devpriv->mite = mite_attach(dev, false); /* use win0 */
907 if (!devpriv->mite)
908 return -ENOMEM;
909
910 devpriv->di_mite_ring = mite_alloc_ring(devpriv->mite);
911 if (!devpriv->di_mite_ring)
912 return -ENOMEM;
913
914 if (board->uses_firmware) {
915 ret = pci_6534_upload_firmware(dev);
916 if (ret < 0)
917 return ret;
918 }
919
920 nidio_reset_board(dev);
921
922 ret = comedi_alloc_subdevices(dev, 1);
923 if (ret)
924 return ret;
925
926 dev_info(dev->class_dev, "%s rev=%d\n", dev->board_name,
927 readb(dev->mmio + CHIP_VERSION));
928
929 s = &dev->subdevices[0];
930
931 dev->read_subdev = s;
932 s->type = COMEDI_SUBD_DIO;
933 s->subdev_flags =
934 SDF_READABLE | SDF_WRITABLE | SDF_LSAMPL | SDF_PACKED |
935 SDF_CMD_READ;
936 s->n_chan = 32;
937 s->range_table = &range_digital;
938 s->maxdata = 1;
939 s->insn_config = &ni_pcidio_insn_config;
940 s->insn_bits = &ni_pcidio_insn_bits;
941 s->do_cmd = &ni_pcidio_cmd;
942 s->do_cmdtest = &ni_pcidio_cmdtest;
943 s->cancel = &ni_pcidio_cancel;
944 s->len_chanlist = 32; /* XXX */
945 s->buf_change = &ni_pcidio_change;
946 s->async_dma_dir = DMA_BIDIRECTIONAL;
947 s->poll = &ni_pcidio_poll;
948
949 irq = pcidev->irq;
950 if (irq) {
951 ret = request_irq(irq, nidio_interrupt, IRQF_SHARED,
952 dev->board_name, dev);
953 if (ret == 0)
954 dev->irq = irq;
955 }
956
957 return 0;
958 }
959
nidio_detach(struct comedi_device * dev)960 static void nidio_detach(struct comedi_device *dev)
961 {
962 struct nidio96_private *devpriv = dev->private;
963
964 if (dev->irq)
965 free_irq(dev->irq, dev);
966 if (devpriv) {
967 if (devpriv->di_mite_ring) {
968 mite_free_ring(devpriv->di_mite_ring);
969 devpriv->di_mite_ring = NULL;
970 }
971 mite_detach(devpriv->mite);
972 }
973 if (dev->mmio)
974 iounmap(dev->mmio);
975 comedi_pci_disable(dev);
976 }
977
978 static struct comedi_driver ni_pcidio_driver = {
979 .driver_name = "ni_pcidio",
980 .module = THIS_MODULE,
981 .auto_attach = nidio_auto_attach,
982 .detach = nidio_detach,
983 };
984
ni_pcidio_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)985 static int ni_pcidio_pci_probe(struct pci_dev *dev,
986 const struct pci_device_id *id)
987 {
988 return comedi_pci_auto_config(dev, &ni_pcidio_driver, id->driver_data);
989 }
990
991 static const struct pci_device_id ni_pcidio_pci_table[] = {
992 { PCI_VDEVICE(NI, 0x1150), BOARD_PCIDIO_32HS },
993 { PCI_VDEVICE(NI, 0x12b0), BOARD_PCI6534 },
994 { PCI_VDEVICE(NI, 0x1320), BOARD_PXI6533 },
995 { 0 }
996 };
997 MODULE_DEVICE_TABLE(pci, ni_pcidio_pci_table);
998
999 static struct pci_driver ni_pcidio_pci_driver = {
1000 .name = "ni_pcidio",
1001 .id_table = ni_pcidio_pci_table,
1002 .probe = ni_pcidio_pci_probe,
1003 .remove = comedi_pci_auto_unconfig,
1004 };
1005 module_comedi_pci_driver(ni_pcidio_driver, ni_pcidio_pci_driver);
1006
1007 MODULE_AUTHOR("Comedi https://www.comedi.org");
1008 MODULE_DESCRIPTION("Comedi low-level driver");
1009 MODULE_LICENSE("GPL");
1010