Home
last modified time | relevance | path

Searched refs:PORT_E (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_limits.h99 PORT_E, enumerator
H A Dintel_display_device.c585 …__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
638 …__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
682 ….__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E…
931 …__runtime_defaults.port_mask = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) | BIT(PORT_D) | BIT(PORT_E),
H A Dintel_crt.c1087 assert_port_valid(display, PORT_E); in intel_crt_init()
1089 crt->base.port = PORT_E; in intel_crt_init()
H A Dintel_bios.c2348 [PORT_E] = { DVO_PORT_HDMIE, DVO_PORT_DPE, DVO_PORT_CRT }, in dvo_port_to_port()
3021 else if (port == PORT_E) in init_vbt_missing_defaults()
3026 if (port != PORT_A && port != PORT_E) in init_vbt_missing_defaults()
3029 if (port != PORT_E) in init_vbt_missing_defaults()
H A Dintel_opregion.c413 if (port == PORT_E) { in intel_opregion_notify_encoder()
H A Dintel_hdcp.c471 case PORT_E: in intel_hdcp_get_repeater_ctl()
1217 (DISPLAY_VER(display) >= 12 || port < PORT_E); in is_hdcp_supported()
H A Dintel_dp_mst.c1840 if (DISPLAY_VER(display) < 11 && port == PORT_E) in intel_dp_mst_encoder_init()
/linux/drivers/gpu/drm/i915/gvt/
H A Dhandlers.c823 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
824 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) in ddi_buf_ctl_mmio_write()
842 u32 ddi_buf_ctl = vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_E)); in fdi_auto_training_started()
844 u32 tx_ctl = vgpu_vreg_t(vgpu, DP_TP_CTL(PORT_E)); in fdi_auto_training_started()
958 vgpu_vreg_t(vgpu, DP_TP_STATUS(PORT_E)) |= in update_fdi_rx_iir_status()
964 calc_index(offset, DP_TP_CTL(PORT_A), DP_TP_CTL(PORT_B), DP_TP_CTL(PORT_E))
2380 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write); in init_generic_mmio_info()
2386 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write); in init_generic_mmio_info()
2392 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL); in init_generic_mmio_info()
H A Ddisplay.c500 intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) { in emulate_monitor_status_change()