1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Macros for accessing system registers with older binutils. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 * Author: Catalin Marinas <catalin.marinas@arm.com> 7 */ 8 9 #ifndef __ASM_SYSREG_H 10 #define __ASM_SYSREG_H 11 12 #include <linux/bits.h> 13 #include <linux/stringify.h> 14 #include <linux/kasan-tags.h> 15 #include <linux/kconfig.h> 16 17 #include <asm/gpr-num.h> 18 19 #if ARM64_S390_COMMON == 1 20 21 /* 22 * ARMv8 ARM reserves the following encoding for system registers: 23 * (Ref: ARMv8 ARM, Section: "System instruction class encoding overview", 24 * C5.2, version:ARM DDI 0487A.f) 25 * [20-19] : Op0 26 * [18-16] : Op1 27 * [15-12] : CRn 28 * [11-8] : CRm 29 * [7-5] : Op2 30 */ 31 #define Op0_shift 19 32 #define Op0_mask 0x3 33 #define Op1_shift 16 34 #define Op1_mask 0x7 35 #define CRn_shift 12 36 #define CRn_mask 0xf 37 #define CRm_shift 8 38 #define CRm_mask 0xf 39 #define Op2_shift 5 40 #define Op2_mask 0x7 41 42 #define sys_reg(op0, op1, crn, crm, op2) \ 43 (((op0) << Op0_shift) | ((op1) << Op1_shift) | \ 44 ((crn) << CRn_shift) | ((crm) << CRm_shift) | \ 45 ((op2) << Op2_shift)) 46 47 #define sys_insn sys_reg 48 49 #define sys_reg_Op0(id) (((id) >> Op0_shift) & Op0_mask) 50 #define sys_reg_Op1(id) (((id) >> Op1_shift) & Op1_mask) 51 #define sys_reg_CRn(id) (((id) >> CRn_shift) & CRn_mask) 52 #define sys_reg_CRm(id) (((id) >> CRm_shift) & CRm_mask) 53 #define sys_reg_Op2(id) (((id) >> Op2_shift) & Op2_mask) 54 55 #endif /* ARM64_S390_COMMON == 1 */ 56 57 #ifndef CONFIG_BROKEN_GAS_INST 58 59 #ifdef __ASSEMBLER__ 60 // The space separator is omitted so that __emit_inst(x) can be parsed as 61 // either an assembler directive or an assembler macro argument. 62 #define __emit_inst(x) .inst(x) 63 #else 64 #define __emit_inst(x) ".inst " __stringify((x)) "\n\t" 65 #endif 66 67 #else /* CONFIG_BROKEN_GAS_INST */ 68 69 #ifdef __ASSEMBLER__ 70 #define __emit_inst(x) .long (x) 71 #else /* __ASSEMBLER__ */ 72 #define __emit_inst(x) ".long " __stringify(x) "\n\t" 73 #endif /* __ASSEMBLER__ */ 74 75 #endif /* CONFIG_BROKEN_GAS_INST */ 76 77 /* 78 * Instructions for modifying PSTATE fields. 79 * As per Arm ARM for v8-A, Section "C.5.1.3 op0 == 0b00, architectural hints, 80 * barriers and CLREX, and PSTATE access", ARM DDI 0487 C.a, system instructions 81 * for accessing PSTATE fields have the following encoding: 82 * Op0 = 0, CRn = 4 83 * Op1, Op2 encodes the PSTATE field modified and defines the constraints. 84 * CRm = Imm4 for the instruction. 85 * Rt = 0x1f 86 */ 87 #define pstate_field(op1, op2) ((op1) << Op1_shift | (op2) << Op2_shift) 88 #define PSTATE_Imm_shift CRm_shift 89 #define ENCODE_PSTATE(x, r) (0xd500401f | PSTATE_ ## r | ((!!x) << PSTATE_Imm_shift)) 90 #define SET_PSTATE(x, r) __emit_inst(ENCODE_PSTATE(x, r)) 91 92 #define PSTATE_PAN pstate_field(0, 4) 93 #define PSTATE_UAO pstate_field(0, 3) 94 #define PSTATE_SSBS pstate_field(3, 1) 95 #define PSTATE_DIT pstate_field(3, 2) 96 #define PSTATE_TCO pstate_field(3, 4) 97 98 #define SET_PSTATE_PAN(x) SET_PSTATE((x), PAN) 99 #define SET_PSTATE_UAO(x) SET_PSTATE((x), UAO) 100 #define SET_PSTATE_SSBS(x) SET_PSTATE((x), SSBS) 101 #define SET_PSTATE_DIT(x) SET_PSTATE((x), DIT) 102 #define SET_PSTATE_TCO(x) SET_PSTATE((x), TCO) 103 104 #define set_pstate_pan(x) asm volatile(SET_PSTATE_PAN(x)) 105 #define set_pstate_uao(x) asm volatile(SET_PSTATE_UAO(x)) 106 #define set_pstate_ssbs(x) asm volatile(SET_PSTATE_SSBS(x)) 107 #define set_pstate_dit(x) asm volatile(SET_PSTATE_DIT(x)) 108 109 /* Register-based PAN access, for save/restore purposes */ 110 #define SYS_PSTATE_PAN sys_reg(3, 0, 4, 2, 3) 111 112 #define __SYS_BARRIER_INSN(op0, op1, CRn, CRm, op2, Rt) \ 113 __emit_inst(0xd5000000 | \ 114 sys_insn((op0), (op1), (CRn), (CRm), (op2)) | \ 115 ((Rt) & 0x1f)) 116 117 #define SB_BARRIER_INSN __SYS_BARRIER_INSN(0, 3, 3, 0, 7, 31) 118 #define GSB_SYS_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 0, 31) 119 #define GSB_ACK_BARRIER_INSN __SYS_BARRIER_INSN(1, 0, 12, 0, 1, 31) 120 121 #if ARM64_S390_COMMON == 1 122 123 /* Data cache zero operations */ 124 #define SYS_DC_ISW sys_insn(1, 0, 7, 6, 2) 125 #define SYS_DC_IGSW sys_insn(1, 0, 7, 6, 4) 126 #define SYS_DC_IGDSW sys_insn(1, 0, 7, 6, 6) 127 #define SYS_DC_CSW sys_insn(1, 0, 7, 10, 2) 128 #define SYS_DC_CGSW sys_insn(1, 0, 7, 10, 4) 129 #define SYS_DC_CGDSW sys_insn(1, 0, 7, 10, 6) 130 #define SYS_DC_CISW sys_insn(1, 0, 7, 14, 2) 131 #define SYS_DC_CIGSW sys_insn(1, 0, 7, 14, 4) 132 #define SYS_DC_CIGDSW sys_insn(1, 0, 7, 14, 6) 133 134 #define SYS_IC_IALLUIS sys_insn(1, 0, 7, 1, 0) 135 #define SYS_IC_IALLU sys_insn(1, 0, 7, 5, 0) 136 #define SYS_IC_IVAU sys_insn(1, 3, 7, 5, 1) 137 138 #define SYS_DC_IVAC sys_insn(1, 0, 7, 6, 1) 139 #define SYS_DC_IGVAC sys_insn(1, 0, 7, 6, 3) 140 #define SYS_DC_IGDVAC sys_insn(1, 0, 7, 6, 5) 141 142 #define SYS_DC_CVAC sys_insn(1, 3, 7, 10, 1) 143 #define SYS_DC_CGVAC sys_insn(1, 3, 7, 10, 3) 144 #define SYS_DC_CGDVAC sys_insn(1, 3, 7, 10, 5) 145 146 #define SYS_DC_CVAU sys_insn(1, 3, 7, 11, 1) 147 148 #define SYS_DC_CVAP sys_insn(1, 3, 7, 12, 1) 149 #define SYS_DC_CGVAP sys_insn(1, 3, 7, 12, 3) 150 #define SYS_DC_CGDVAP sys_insn(1, 3, 7, 12, 5) 151 152 #define SYS_DC_CVADP sys_insn(1, 3, 7, 13, 1) 153 #define SYS_DC_CGVADP sys_insn(1, 3, 7, 13, 3) 154 #define SYS_DC_CGDVADP sys_insn(1, 3, 7, 13, 5) 155 156 #define SYS_DC_CIVAC sys_insn(1, 3, 7, 14, 1) 157 #define SYS_DC_CIGVAC sys_insn(1, 3, 7, 14, 3) 158 #define SYS_DC_CIGDVAC sys_insn(1, 3, 7, 14, 5) 159 160 #define SYS_DC_ZVA sys_insn(1, 3, 7, 4, 1) 161 #define SYS_DC_GVA sys_insn(1, 3, 7, 4, 3) 162 #define SYS_DC_GZVA sys_insn(1, 3, 7, 4, 4) 163 164 #define SYS_DC_CIVAPS sys_insn(1, 0, 7, 15, 1) 165 #define SYS_DC_CIGDVAPS sys_insn(1, 0, 7, 15, 5) 166 167 /* 168 * Automatically generated definitions for system registers, the 169 * manual encodings below are in the process of being converted to 170 * come from here. The header relies on the definition of sys_reg() 171 * earlier in this file. 172 */ 173 #include <asm/sysreg-defs.h> 174 175 /* 176 * System registers, organised loosely by encoding but grouped together 177 * where the architected name contains an index. e.g. ID_MMFR<n>_EL1. 178 */ 179 #define SYS_SVCR_SMSTOP_SM_EL0 sys_reg(0, 3, 4, 2, 3) 180 #define SYS_SVCR_SMSTART_SM_EL0 sys_reg(0, 3, 4, 3, 3) 181 #define SYS_SVCR_SMSTOP_SMZA_EL0 sys_reg(0, 3, 4, 6, 3) 182 183 #define SYS_DBGBVRn_EL1(n) sys_reg(2, 0, 0, n, 4) 184 #define SYS_DBGBCRn_EL1(n) sys_reg(2, 0, 0, n, 5) 185 #define SYS_DBGWVRn_EL1(n) sys_reg(2, 0, 0, n, 6) 186 #define SYS_DBGWCRn_EL1(n) sys_reg(2, 0, 0, n, 7) 187 #define SYS_MDRAR_EL1 sys_reg(2, 0, 1, 0, 0) 188 189 #define SYS_OSLSR_EL1 sys_reg(2, 0, 1, 1, 4) 190 #define OSLSR_EL1_OSLM_MASK (BIT(3) | BIT(0)) 191 #define OSLSR_EL1_OSLM_NI 0 192 #define OSLSR_EL1_OSLM_IMPLEMENTED BIT(3) 193 #define OSLSR_EL1_OSLK BIT(1) 194 195 #define SYS_OSDLR_EL1 sys_reg(2, 0, 1, 3, 4) 196 #define SYS_DBGPRCR_EL1 sys_reg(2, 0, 1, 4, 4) 197 #define SYS_DBGCLAIMSET_EL1 sys_reg(2, 0, 7, 8, 6) 198 #define SYS_DBGCLAIMCLR_EL1 sys_reg(2, 0, 7, 9, 6) 199 #define SYS_DBGAUTHSTATUS_EL1 sys_reg(2, 0, 7, 14, 6) 200 #define SYS_MDCCSR_EL0 sys_reg(2, 3, 0, 1, 0) 201 #define SYS_DBGDTR_EL0 sys_reg(2, 3, 0, 4, 0) 202 #define SYS_DBGDTRRX_EL0 sys_reg(2, 3, 0, 5, 0) 203 #define SYS_DBGDTRTX_EL0 sys_reg(2, 3, 0, 5, 0) 204 #define SYS_DBGVCR32_EL2 sys_reg(2, 4, 0, 7, 0) 205 206 #define SYS_BRBINF_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 0)) 207 #define SYS_BRBSRC_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 1)) 208 #define SYS_BRBTGT_EL1(n) sys_reg(2, 1, 8, (n & 15), (((n & 16) >> 2) | 2)) 209 210 #define SYS_TRCITECR_EL1 sys_reg(3, 0, 1, 2, 3) 211 #define SYS_TRCACATR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (2 | (m >> 3))) 212 #define SYS_TRCACVR(m) sys_reg(2, 1, 2, ((m & 7) << 1), (0 | (m >> 3))) 213 #define SYS_TRCAUTHSTATUS sys_reg(2, 1, 7, 14, 6) 214 #define SYS_TRCAUXCTLR sys_reg(2, 1, 0, 6, 0) 215 #define SYS_TRCBBCTLR sys_reg(2, 1, 0, 15, 0) 216 #define SYS_TRCCCCTLR sys_reg(2, 1, 0, 14, 0) 217 #define SYS_TRCCIDCCTLR0 sys_reg(2, 1, 3, 0, 2) 218 #define SYS_TRCCIDCCTLR1 sys_reg(2, 1, 3, 1, 2) 219 #define SYS_TRCCIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 0) 220 #define SYS_TRCCLAIMCLR sys_reg(2, 1, 7, 9, 6) 221 #define SYS_TRCCLAIMSET sys_reg(2, 1, 7, 8, 6) 222 #define SYS_TRCCNTCTLR(m) sys_reg(2, 1, 0, (4 | (m & 3)), 5) 223 #define SYS_TRCCNTRLDVR(m) sys_reg(2, 1, 0, (0 | (m & 3)), 5) 224 #define SYS_TRCCNTVR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 5) 225 #define SYS_TRCCONFIGR sys_reg(2, 1, 0, 4, 0) 226 #define SYS_TRCDEVARCH sys_reg(2, 1, 7, 15, 6) 227 #define SYS_TRCDEVID sys_reg(2, 1, 7, 2, 7) 228 #define SYS_TRCEVENTCTL0R sys_reg(2, 1, 0, 8, 0) 229 #define SYS_TRCEVENTCTL1R sys_reg(2, 1, 0, 9, 0) 230 #define SYS_TRCEXTINSELR(m) sys_reg(2, 1, 0, (8 | (m & 3)), 4) 231 #define SYS_TRCIDR0 sys_reg(2, 1, 0, 8, 7) 232 #define SYS_TRCIDR10 sys_reg(2, 1, 0, 2, 6) 233 #define SYS_TRCIDR11 sys_reg(2, 1, 0, 3, 6) 234 #define SYS_TRCIDR12 sys_reg(2, 1, 0, 4, 6) 235 #define SYS_TRCIDR13 sys_reg(2, 1, 0, 5, 6) 236 #define SYS_TRCIDR1 sys_reg(2, 1, 0, 9, 7) 237 #define SYS_TRCIDR2 sys_reg(2, 1, 0, 10, 7) 238 #define SYS_TRCIDR3 sys_reg(2, 1, 0, 11, 7) 239 #define SYS_TRCIDR4 sys_reg(2, 1, 0, 12, 7) 240 #define SYS_TRCIDR5 sys_reg(2, 1, 0, 13, 7) 241 #define SYS_TRCIDR6 sys_reg(2, 1, 0, 14, 7) 242 #define SYS_TRCIDR7 sys_reg(2, 1, 0, 15, 7) 243 #define SYS_TRCIDR8 sys_reg(2, 1, 0, 0, 6) 244 #define SYS_TRCIDR9 sys_reg(2, 1, 0, 1, 6) 245 #define SYS_TRCIMSPEC(m) sys_reg(2, 1, 0, (m & 7), 7) 246 #define SYS_TRCITEEDCR sys_reg(2, 1, 0, 2, 1) 247 #define SYS_TRCOSLSR sys_reg(2, 1, 1, 1, 4) 248 #define SYS_TRCPRGCTLR sys_reg(2, 1, 0, 1, 0) 249 #define SYS_TRCQCTLR sys_reg(2, 1, 0, 1, 1) 250 #define SYS_TRCRSCTLR(m) sys_reg(2, 1, 1, (m & 15), (0 | (m >> 4))) 251 #define SYS_TRCRSR sys_reg(2, 1, 0, 10, 0) 252 #define SYS_TRCSEQEVR(m) sys_reg(2, 1, 0, (m & 3), 4) 253 #define SYS_TRCSEQRSTEVR sys_reg(2, 1, 0, 6, 4) 254 #define SYS_TRCSEQSTR sys_reg(2, 1, 0, 7, 4) 255 #define SYS_TRCSSCCR(m) sys_reg(2, 1, 1, (m & 7), 2) 256 #define SYS_TRCSSCSR(m) sys_reg(2, 1, 1, (8 | (m & 7)), 2) 257 #define SYS_TRCSSPCICR(m) sys_reg(2, 1, 1, (m & 7), 3) 258 #define SYS_TRCSTALLCTLR sys_reg(2, 1, 0, 11, 0) 259 #define SYS_TRCSTATR sys_reg(2, 1, 0, 3, 0) 260 #define SYS_TRCSYNCPR sys_reg(2, 1, 0, 13, 0) 261 #define SYS_TRCTRACEIDR sys_reg(2, 1, 0, 0, 1) 262 #define SYS_TRCTSCTLR sys_reg(2, 1, 0, 12, 0) 263 #define SYS_TRCVICTLR sys_reg(2, 1, 0, 0, 2) 264 #define SYS_TRCVIIECTLR sys_reg(2, 1, 0, 1, 2) 265 #define SYS_TRCVIPCSSCTLR sys_reg(2, 1, 0, 3, 2) 266 #define SYS_TRCVISSCTLR sys_reg(2, 1, 0, 2, 2) 267 #define SYS_TRCVMIDCCTLR0 sys_reg(2, 1, 3, 2, 2) 268 #define SYS_TRCVMIDCCTLR1 sys_reg(2, 1, 3, 3, 2) 269 #define SYS_TRCVMIDCVR(m) sys_reg(2, 1, 3, ((m & 7) << 1), 1) 270 271 /* ETM */ 272 #define SYS_TRCOSLAR sys_reg(2, 1, 1, 0, 4) 273 274 #define SYS_MIDR_EL1 sys_reg(3, 0, 0, 0, 0) 275 #define SYS_MPIDR_EL1 sys_reg(3, 0, 0, 0, 5) 276 #define SYS_REVIDR_EL1 sys_reg(3, 0, 0, 0, 6) 277 278 #define SYS_ACTLR_EL1 sys_reg(3, 0, 1, 0, 1) 279 #define SYS_RGSR_EL1 sys_reg(3, 0, 1, 0, 5) 280 #define SYS_GCR_EL1 sys_reg(3, 0, 1, 0, 6) 281 282 #define SYS_APIAKEYLO_EL1 sys_reg(3, 0, 2, 1, 0) 283 #define SYS_APIAKEYHI_EL1 sys_reg(3, 0, 2, 1, 1) 284 #define SYS_APIBKEYLO_EL1 sys_reg(3, 0, 2, 1, 2) 285 #define SYS_APIBKEYHI_EL1 sys_reg(3, 0, 2, 1, 3) 286 287 #define SYS_APDAKEYLO_EL1 sys_reg(3, 0, 2, 2, 0) 288 #define SYS_APDAKEYHI_EL1 sys_reg(3, 0, 2, 2, 1) 289 #define SYS_APDBKEYLO_EL1 sys_reg(3, 0, 2, 2, 2) 290 #define SYS_APDBKEYHI_EL1 sys_reg(3, 0, 2, 2, 3) 291 292 #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) 293 #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) 294 295 #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) 296 297 #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) 298 299 #define SYS_AFSR0_EL1 sys_reg(3, 0, 5, 1, 0) 300 #define SYS_AFSR1_EL1 sys_reg(3, 0, 5, 1, 1) 301 #define SYS_ESR_EL1 sys_reg(3, 0, 5, 2, 0) 302 303 #define SYS_ERRIDR_EL1 sys_reg(3, 0, 5, 3, 0) 304 #define SYS_ERRSELR_EL1 sys_reg(3, 0, 5, 3, 1) 305 #define SYS_ERXFR_EL1 sys_reg(3, 0, 5, 4, 0) 306 #define SYS_ERXCTLR_EL1 sys_reg(3, 0, 5, 4, 1) 307 #define SYS_ERXSTATUS_EL1 sys_reg(3, 0, 5, 4, 2) 308 #define SYS_ERXADDR_EL1 sys_reg(3, 0, 5, 4, 3) 309 #define SYS_ERXPFGF_EL1 sys_reg(3, 0, 5, 4, 4) 310 #define SYS_ERXPFGCTL_EL1 sys_reg(3, 0, 5, 4, 5) 311 #define SYS_ERXPFGCDN_EL1 sys_reg(3, 0, 5, 4, 6) 312 #define SYS_ERXMISC0_EL1 sys_reg(3, 0, 5, 5, 0) 313 #define SYS_ERXMISC1_EL1 sys_reg(3, 0, 5, 5, 1) 314 #define SYS_ERXMISC2_EL1 sys_reg(3, 0, 5, 5, 2) 315 #define SYS_ERXMISC3_EL1 sys_reg(3, 0, 5, 5, 3) 316 #define SYS_TFSR_EL1 sys_reg(3, 0, 5, 6, 0) 317 #define SYS_TFSRE0_EL1 sys_reg(3, 0, 5, 6, 1) 318 319 #define SYS_PAR_EL1 sys_reg(3, 0, 7, 4, 0) 320 321 #define SYS_PAR_EL1_F BIT(0) 322 /* When PAR_EL1.F == 1 */ 323 #define SYS_PAR_EL1_FST GENMASK(6, 1) 324 #define SYS_PAR_EL1_PTW BIT(8) 325 #define SYS_PAR_EL1_S BIT(9) 326 #define SYS_PAR_EL1_AssuredOnly BIT(12) 327 #define SYS_PAR_EL1_TopLevel BIT(13) 328 #define SYS_PAR_EL1_Overlay BIT(14) 329 #define SYS_PAR_EL1_DirtyBit BIT(15) 330 #define SYS_PAR_EL1_F1_IMPDEF GENMASK_ULL(63, 48) 331 #define SYS_PAR_EL1_F1_RES0 (BIT(7) | BIT(10) | GENMASK_ULL(47, 16)) 332 #define SYS_PAR_EL1_RES1 BIT(11) 333 /* When PAR_EL1.F == 0 */ 334 #define SYS_PAR_EL1_SH GENMASK_ULL(8, 7) 335 #define SYS_PAR_EL1_NS BIT(9) 336 #define SYS_PAR_EL1_F0_IMPDEF BIT(10) 337 #define SYS_PAR_EL1_NSE BIT(11) 338 #define SYS_PAR_EL1_PA GENMASK_ULL(51, 12) 339 #define SYS_PAR_EL1_ATTR GENMASK_ULL(63, 56) 340 #define SYS_PAR_EL1_F0_RES0 (GENMASK_ULL(6, 1) | GENMASK_ULL(55, 52)) 341 342 /* Buffer error reporting */ 343 #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT 344 #define PMBSR_EL1_FAULT_FSC_MASK PMBSR_EL1_MSS_MASK 345 346 #define PMBSR_EL1_BUF_BSC_SHIFT PMBSR_EL1_MSS_SHIFT 347 #define PMBSR_EL1_BUF_BSC_MASK PMBSR_EL1_MSS_MASK 348 349 #define PMBSR_EL1_BUF_BSC_FULL 0x1UL 350 351 /*** End of Statistical Profiling Extension ***/ 352 353 #define TRBSR_EL1_BSC_MASK GENMASK(5, 0) 354 #define TRBSR_EL1_BSC_SHIFT 0 355 356 #define SYS_PMINTENSET_EL1 sys_reg(3, 0, 9, 14, 1) 357 #define SYS_PMINTENCLR_EL1 sys_reg(3, 0, 9, 14, 2) 358 359 #define SYS_PMMIR_EL1 sys_reg(3, 0, 9, 14, 6) 360 361 #define SYS_MAIR_EL1 sys_reg(3, 0, 10, 2, 0) 362 #define SYS_AMAIR_EL1 sys_reg(3, 0, 10, 3, 0) 363 364 #define SYS_VBAR_EL1 sys_reg(3, 0, 12, 0, 0) 365 #define SYS_DISR_EL1 sys_reg(3, 0, 12, 1, 1) 366 367 #define SYS_ICC_IAR0_EL1 sys_reg(3, 0, 12, 8, 0) 368 #define SYS_ICC_EOIR0_EL1 sys_reg(3, 0, 12, 8, 1) 369 #define SYS_ICC_HPPIR0_EL1 sys_reg(3, 0, 12, 8, 2) 370 #define SYS_ICC_BPR0_EL1 sys_reg(3, 0, 12, 8, 3) 371 #define SYS_ICC_AP0Rn_EL1(n) sys_reg(3, 0, 12, 8, 4 | n) 372 #define SYS_ICC_AP0R0_EL1 SYS_ICC_AP0Rn_EL1(0) 373 #define SYS_ICC_AP0R1_EL1 SYS_ICC_AP0Rn_EL1(1) 374 #define SYS_ICC_AP0R2_EL1 SYS_ICC_AP0Rn_EL1(2) 375 #define SYS_ICC_AP0R3_EL1 SYS_ICC_AP0Rn_EL1(3) 376 #define SYS_ICC_AP1Rn_EL1(n) sys_reg(3, 0, 12, 9, n) 377 #define SYS_ICC_AP1R0_EL1 SYS_ICC_AP1Rn_EL1(0) 378 #define SYS_ICC_AP1R1_EL1 SYS_ICC_AP1Rn_EL1(1) 379 #define SYS_ICC_AP1R2_EL1 SYS_ICC_AP1Rn_EL1(2) 380 #define SYS_ICC_AP1R3_EL1 SYS_ICC_AP1Rn_EL1(3) 381 #define SYS_ICC_DIR_EL1 sys_reg(3, 0, 12, 11, 1) 382 #define SYS_ICC_RPR_EL1 sys_reg(3, 0, 12, 11, 3) 383 #define SYS_ICC_SGI1R_EL1 sys_reg(3, 0, 12, 11, 5) 384 #define SYS_ICC_ASGI1R_EL1 sys_reg(3, 0, 12, 11, 6) 385 #define SYS_ICC_SGI0R_EL1 sys_reg(3, 0, 12, 11, 7) 386 #define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0) 387 #define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1) 388 #define SYS_ICC_HPPIR1_EL1 sys_reg(3, 0, 12, 12, 2) 389 #define SYS_ICC_BPR1_EL1 sys_reg(3, 0, 12, 12, 3) 390 #define SYS_ICC_CTLR_EL1 sys_reg(3, 0, 12, 12, 4) 391 #define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5) 392 #define SYS_ICC_IGRPEN0_EL1 sys_reg(3, 0, 12, 12, 6) 393 #define SYS_ICC_IGRPEN1_EL1 sys_reg(3, 0, 12, 12, 7) 394 395 #define SYS_ACCDATA_EL1 sys_reg(3, 0, 13, 0, 5) 396 397 #define SYS_CNTKCTL_EL1 sys_reg(3, 0, 14, 1, 0) 398 399 #define SYS_AIDR_EL1 sys_reg(3, 1, 0, 0, 7) 400 401 #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) 402 #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) 403 404 #define SYS_PMCR_EL0 sys_reg(3, 3, 9, 12, 0) 405 #define SYS_PMCNTENSET_EL0 sys_reg(3, 3, 9, 12, 1) 406 #define SYS_PMCNTENCLR_EL0 sys_reg(3, 3, 9, 12, 2) 407 #define SYS_PMOVSCLR_EL0 sys_reg(3, 3, 9, 12, 3) 408 #define SYS_PMSWINC_EL0 sys_reg(3, 3, 9, 12, 4) 409 #define SYS_PMCEID0_EL0 sys_reg(3, 3, 9, 12, 6) 410 #define SYS_PMCEID1_EL0 sys_reg(3, 3, 9, 12, 7) 411 #define SYS_PMCCNTR_EL0 sys_reg(3, 3, 9, 13, 0) 412 #define SYS_PMXEVTYPER_EL0 sys_reg(3, 3, 9, 13, 1) 413 #define SYS_PMXEVCNTR_EL0 sys_reg(3, 3, 9, 13, 2) 414 #define SYS_PMUSERENR_EL0 sys_reg(3, 3, 9, 14, 0) 415 #define SYS_PMOVSSET_EL0 sys_reg(3, 3, 9, 14, 3) 416 417 #define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2) 418 #define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3) 419 #define SYS_TPIDR2_EL0 sys_reg(3, 3, 13, 0, 5) 420 421 #define SYS_SCXTNUM_EL0 sys_reg(3, 3, 13, 0, 7) 422 423 /* Definitions for system register interface to AMU for ARMv8.4 onwards */ 424 #define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2)) 425 #define SYS_AMCR_EL0 SYS_AM_EL0(2, 0) 426 #define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1) 427 #define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2) 428 #define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3) 429 #define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4) 430 #define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5) 431 #define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0) 432 #define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1) 433 434 /* 435 * Group 0 of activity monitors (architected): 436 * op0 op1 CRn CRm op2 437 * Counter: 11 011 1101 010:n<3> n<2:0> 438 * Type: 11 011 1101 011:n<3> n<2:0> 439 * n: 0-15 440 * 441 * Group 1 of activity monitors (auxiliary): 442 * op0 op1 CRn CRm op2 443 * Counter: 11 011 1101 110:n<3> n<2:0> 444 * Type: 11 011 1101 111:n<3> n<2:0> 445 * n: 0-15 446 */ 447 448 #define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7) 449 #define SYS_AMEVTYPER0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7) 450 #define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7) 451 #define SYS_AMEVTYPER1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7) 452 453 /* AMU v1: Fixed (architecturally defined) activity monitors */ 454 #define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0) 455 #define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1) 456 #define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2) 457 #define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3) 458 459 #define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0) 460 461 #define SYS_CNTPCT_EL0 sys_reg(3, 3, 14, 0, 1) 462 #define SYS_CNTVCT_EL0 sys_reg(3, 3, 14, 0, 2) 463 #define SYS_CNTPCTSS_EL0 sys_reg(3, 3, 14, 0, 5) 464 #define SYS_CNTVCTSS_EL0 sys_reg(3, 3, 14, 0, 6) 465 466 #define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0) 467 #define SYS_CNTP_CTL_EL0 sys_reg(3, 3, 14, 2, 1) 468 #define SYS_CNTP_CVAL_EL0 sys_reg(3, 3, 14, 2, 2) 469 470 #define SYS_CNTV_TVAL_EL0 sys_reg(3, 3, 14, 3, 0) 471 #define SYS_CNTV_CTL_EL0 sys_reg(3, 3, 14, 3, 1) 472 #define SYS_CNTV_CVAL_EL0 sys_reg(3, 3, 14, 3, 2) 473 474 #define SYS_AARCH32_CNTP_TVAL sys_reg(0, 0, 14, 2, 0) 475 #define SYS_AARCH32_CNTP_CTL sys_reg(0, 0, 14, 2, 1) 476 #define SYS_AARCH32_CNTPCT sys_reg(0, 0, 0, 14, 0) 477 #define SYS_AARCH32_CNTVCT sys_reg(0, 1, 0, 14, 0) 478 #define SYS_AARCH32_CNTP_CVAL sys_reg(0, 2, 0, 14, 0) 479 #define SYS_AARCH32_CNTPCTSS sys_reg(0, 8, 0, 14, 0) 480 #define SYS_AARCH32_CNTVCTSS sys_reg(0, 9, 0, 14, 0) 481 482 #define __PMEV_op2(n) ((n) & 0x7) 483 #define __CNTR_CRm(n) (0x8 | (((n) >> 3) & 0x3)) 484 #define SYS_PMEVCNTSVRn_EL1(n) sys_reg(2, 0, 14, __CNTR_CRm(n), __PMEV_op2(n)) 485 #define SYS_PMEVCNTRn_EL0(n) sys_reg(3, 3, 14, __CNTR_CRm(n), __PMEV_op2(n)) 486 #define __TYPER_CRm(n) (0xc | (((n) >> 3) & 0x3)) 487 #define SYS_PMEVTYPERn_EL0(n) sys_reg(3, 3, 14, __TYPER_CRm(n), __PMEV_op2(n)) 488 489 #define SYS_PMCCFILTR_EL0 sys_reg(3, 3, 14, 15, 7) 490 491 #define SYS_SPMCGCRn_EL1(n) sys_reg(2, 0, 9, 13, ((n) & 1)) 492 493 #define __SPMEV_op2(n) ((n) & 0x7) 494 #define __SPMEV_crm(p, n) ((((p) & 7) << 1) | (((n) >> 3) & 1)) 495 #define SYS_SPMEVCNTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b000, n), __SPMEV_op2(n)) 496 #define SYS_SPMEVFILT2Rn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b011, n), __SPMEV_op2(n)) 497 #define SYS_SPMEVFILTRn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b010, n), __SPMEV_op2(n)) 498 #define SYS_SPMEVTYPERn_EL0(n) sys_reg(2, 3, 14, __SPMEV_crm(0b001, n), __SPMEV_op2(n)) 499 500 #define SYS_VPIDR_EL2 sys_reg(3, 4, 0, 0, 0) 501 #define SYS_VMPIDR_EL2 sys_reg(3, 4, 0, 0, 5) 502 503 #define SYS_ACTLR_EL2 sys_reg(3, 4, 1, 0, 1) 504 #define SYS_SCTLR2_EL2 sys_reg(3, 4, 1, 0, 3) 505 #define SYS_HCR_EL2 sys_reg(3, 4, 1, 1, 0) 506 #define SYS_MDCR_EL2 sys_reg(3, 4, 1, 1, 1) 507 #define SYS_CPTR_EL2 sys_reg(3, 4, 1, 1, 2) 508 #define SYS_HSTR_EL2 sys_reg(3, 4, 1, 1, 3) 509 #define SYS_HACR_EL2 sys_reg(3, 4, 1, 1, 7) 510 511 #define SYS_TTBR0_EL2 sys_reg(3, 4, 2, 0, 0) 512 #define SYS_TTBR1_EL2 sys_reg(3, 4, 2, 0, 1) 513 #define SYS_TCR_EL2 sys_reg(3, 4, 2, 0, 2) 514 #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) 515 516 #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) 517 #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) 518 #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) 519 #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0) 520 #define SYS_SPSR_abt sys_reg(3, 4, 4, 3, 1) 521 #define SYS_SPSR_und sys_reg(3, 4, 4, 3, 2) 522 #define SYS_SPSR_fiq sys_reg(3, 4, 4, 3, 3) 523 #define SYS_IFSR32_EL2 sys_reg(3, 4, 5, 0, 1) 524 #define SYS_AFSR0_EL2 sys_reg(3, 4, 5, 1, 0) 525 #define SYS_AFSR1_EL2 sys_reg(3, 4, 5, 1, 1) 526 #define SYS_ESR_EL2 sys_reg(3, 4, 5, 2, 0) 527 #define SYS_VSESR_EL2 sys_reg(3, 4, 5, 2, 3) 528 #define SYS_FPEXC32_EL2 sys_reg(3, 4, 5, 3, 0) 529 #define SYS_TFSR_EL2 sys_reg(3, 4, 5, 6, 0) 530 531 #define SYS_FAR_EL2 sys_reg(3, 4, 6, 0, 0) 532 #define SYS_HPFAR_EL2 sys_reg(3, 4, 6, 0, 4) 533 534 #define SYS_MAIR_EL2 sys_reg(3, 4, 10, 2, 0) 535 #define SYS_AMAIR_EL2 sys_reg(3, 4, 10, 3, 0) 536 537 #define SYS_VBAR_EL2 sys_reg(3, 4, 12, 0, 0) 538 #define SYS_RVBAR_EL2 sys_reg(3, 4, 12, 0, 1) 539 #define SYS_RMR_EL2 sys_reg(3, 4, 12, 0, 2) 540 #define SYS_VDISR_EL2 sys_reg(3, 4, 12, 1, 1) 541 #define __SYS__AP0Rx_EL2(x) sys_reg(3, 4, 12, 8, x) 542 #define SYS_ICH_AP0R0_EL2 __SYS__AP0Rx_EL2(0) 543 #define SYS_ICH_AP0R1_EL2 __SYS__AP0Rx_EL2(1) 544 #define SYS_ICH_AP0R2_EL2 __SYS__AP0Rx_EL2(2) 545 #define SYS_ICH_AP0R3_EL2 __SYS__AP0Rx_EL2(3) 546 547 #define __SYS__AP1Rx_EL2(x) sys_reg(3, 4, 12, 9, x) 548 #define SYS_ICH_AP1R0_EL2 __SYS__AP1Rx_EL2(0) 549 #define SYS_ICH_AP1R1_EL2 __SYS__AP1Rx_EL2(1) 550 #define SYS_ICH_AP1R2_EL2 __SYS__AP1Rx_EL2(2) 551 #define SYS_ICH_AP1R3_EL2 __SYS__AP1Rx_EL2(3) 552 553 #define SYS_ICH_VSEIR_EL2 sys_reg(3, 4, 12, 9, 4) 554 #define SYS_ICC_SRE_EL2 sys_reg(3, 4, 12, 9, 5) 555 #define SYS_ICH_EISR_EL2 sys_reg(3, 4, 12, 11, 3) 556 #define SYS_ICH_ELRSR_EL2 sys_reg(3, 4, 12, 11, 5) 557 558 #define __SYS__LR0_EL2(x) sys_reg(3, 4, 12, 12, x) 559 #define SYS_ICH_LR0_EL2 __SYS__LR0_EL2(0) 560 #define SYS_ICH_LR1_EL2 __SYS__LR0_EL2(1) 561 #define SYS_ICH_LR2_EL2 __SYS__LR0_EL2(2) 562 #define SYS_ICH_LR3_EL2 __SYS__LR0_EL2(3) 563 #define SYS_ICH_LR4_EL2 __SYS__LR0_EL2(4) 564 #define SYS_ICH_LR5_EL2 __SYS__LR0_EL2(5) 565 #define SYS_ICH_LR6_EL2 __SYS__LR0_EL2(6) 566 #define SYS_ICH_LR7_EL2 __SYS__LR0_EL2(7) 567 568 #define __SYS__LR8_EL2(x) sys_reg(3, 4, 12, 13, x) 569 #define SYS_ICH_LR8_EL2 __SYS__LR8_EL2(0) 570 #define SYS_ICH_LR9_EL2 __SYS__LR8_EL2(1) 571 #define SYS_ICH_LR10_EL2 __SYS__LR8_EL2(2) 572 #define SYS_ICH_LR11_EL2 __SYS__LR8_EL2(3) 573 #define SYS_ICH_LR12_EL2 __SYS__LR8_EL2(4) 574 #define SYS_ICH_LR13_EL2 __SYS__LR8_EL2(5) 575 #define SYS_ICH_LR14_EL2 __SYS__LR8_EL2(6) 576 #define SYS_ICH_LR15_EL2 __SYS__LR8_EL2(7) 577 578 #define SYS_CONTEXTIDR_EL2 sys_reg(3, 4, 13, 0, 1) 579 #define SYS_TPIDR_EL2 sys_reg(3, 4, 13, 0, 2) 580 #define SYS_SCXTNUM_EL2 sys_reg(3, 4, 13, 0, 7) 581 582 #define __AMEV_op2(m) (m & 0x7) 583 #define __AMEV_CRm(n, m) (n | ((m & 0x8) >> 3)) 584 #define __SYS__AMEVCNTVOFF0n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0x8, m), __AMEV_op2(m)) 585 #define SYS_AMEVCNTVOFF0n_EL2(m) __SYS__AMEVCNTVOFF0n_EL2(m) 586 #define __SYS__AMEVCNTVOFF1n_EL2(m) sys_reg(3, 4, 13, __AMEV_CRm(0xA, m), __AMEV_op2(m)) 587 #define SYS_AMEVCNTVOFF1n_EL2(m) __SYS__AMEVCNTVOFF1n_EL2(m) 588 589 #define SYS_CNTVOFF_EL2 sys_reg(3, 4, 14, 0, 3) 590 #define SYS_CNTHCTL_EL2 sys_reg(3, 4, 14, 1, 0) 591 #define SYS_CNTHP_TVAL_EL2 sys_reg(3, 4, 14, 2, 0) 592 #define SYS_CNTHP_CTL_EL2 sys_reg(3, 4, 14, 2, 1) 593 #define SYS_CNTHP_CVAL_EL2 sys_reg(3, 4, 14, 2, 2) 594 #define SYS_CNTHV_TVAL_EL2 sys_reg(3, 4, 14, 3, 0) 595 #define SYS_CNTHV_CTL_EL2 sys_reg(3, 4, 14, 3, 1) 596 #define SYS_CNTHV_CVAL_EL2 sys_reg(3, 4, 14, 3, 2) 597 598 /* VHE encodings for architectural EL0/1 system registers */ 599 #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) 600 #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) 601 #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) 602 #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) 603 #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) 604 #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) 605 #define SYS_ESR_EL12 sys_reg(3, 5, 5, 2, 0) 606 #define SYS_TFSR_EL12 sys_reg(3, 5, 5, 6, 0) 607 #define SYS_PMSCR_EL12 sys_reg(3, 5, 9, 9, 0) 608 #define SYS_MAIR_EL12 sys_reg(3, 5, 10, 2, 0) 609 #define SYS_AMAIR_EL12 sys_reg(3, 5, 10, 3, 0) 610 #define SYS_VBAR_EL12 sys_reg(3, 5, 12, 0, 0) 611 #define SYS_SCXTNUM_EL12 sys_reg(3, 5, 13, 0, 7) 612 #define SYS_CNTKCTL_EL12 sys_reg(3, 5, 14, 1, 0) 613 #define SYS_CNTP_TVAL_EL02 sys_reg(3, 5, 14, 2, 0) 614 #define SYS_CNTP_CTL_EL02 sys_reg(3, 5, 14, 2, 1) 615 #define SYS_CNTP_CVAL_EL02 sys_reg(3, 5, 14, 2, 2) 616 #define SYS_CNTV_TVAL_EL02 sys_reg(3, 5, 14, 3, 0) 617 #define SYS_CNTV_CTL_EL02 sys_reg(3, 5, 14, 3, 1) 618 #define SYS_CNTV_CVAL_EL02 sys_reg(3, 5, 14, 3, 2) 619 620 #define SYS_SP_EL2 sys_reg(3, 6, 4, 1, 0) 621 622 /* AT instructions */ 623 #define AT_Op0 1 624 #define AT_CRn 7 625 626 #define OP_AT_S1E1R sys_insn(AT_Op0, 0, AT_CRn, 8, 0) 627 #define OP_AT_S1E1W sys_insn(AT_Op0, 0, AT_CRn, 8, 1) 628 #define OP_AT_S1E0R sys_insn(AT_Op0, 0, AT_CRn, 8, 2) 629 #define OP_AT_S1E0W sys_insn(AT_Op0, 0, AT_CRn, 8, 3) 630 #define OP_AT_S1E1RP sys_insn(AT_Op0, 0, AT_CRn, 9, 0) 631 #define OP_AT_S1E1WP sys_insn(AT_Op0, 0, AT_CRn, 9, 1) 632 #define OP_AT_S1E1A sys_insn(AT_Op0, 0, AT_CRn, 9, 2) 633 #define OP_AT_S1E2R sys_insn(AT_Op0, 4, AT_CRn, 8, 0) 634 #define OP_AT_S1E2W sys_insn(AT_Op0, 4, AT_CRn, 8, 1) 635 #define OP_AT_S12E1R sys_insn(AT_Op0, 4, AT_CRn, 8, 4) 636 #define OP_AT_S12E1W sys_insn(AT_Op0, 4, AT_CRn, 8, 5) 637 #define OP_AT_S12E0R sys_insn(AT_Op0, 4, AT_CRn, 8, 6) 638 #define OP_AT_S12E0W sys_insn(AT_Op0, 4, AT_CRn, 8, 7) 639 #define OP_AT_S1E2A sys_insn(AT_Op0, 4, AT_CRn, 9, 2) 640 641 /* TLBI instructions */ 642 #define TLBI_Op0 1 643 644 #define TLBI_Op1_EL1 0 /* Accessible from EL1 or higher */ 645 #define TLBI_Op1_EL2 4 /* Accessible from EL2 or higher */ 646 647 #define TLBI_CRn_XS 8 /* Extra Slow (the common one) */ 648 #define TLBI_CRn_nXS 9 /* not Extra Slow (which nobody uses)*/ 649 650 #define TLBI_CRm_IPAIS 0 /* S2 Inner-Shareable */ 651 #define TLBI_CRm_nROS 1 /* non-Range, Outer-Sharable */ 652 #define TLBI_CRm_RIS 2 /* Range, Inner-Sharable */ 653 #define TLBI_CRm_nRIS 3 /* non-Range, Inner-Sharable */ 654 #define TLBI_CRm_IPAONS 4 /* S2 Outer and Non-Shareable */ 655 #define TLBI_CRm_ROS 5 /* Range, Outer-Sharable */ 656 #define TLBI_CRm_RNS 6 /* Range, Non-Sharable */ 657 #define TLBI_CRm_nRNS 7 /* non-Range, Non-Sharable */ 658 659 #define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0) 660 #define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1) 661 #define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2) 662 #define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3) 663 #define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5) 664 #define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7) 665 #define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1) 666 #define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3) 667 #define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5) 668 #define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7) 669 #define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0) 670 #define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1) 671 #define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2) 672 #define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3) 673 #define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5) 674 #define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7) 675 #define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1) 676 #define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3) 677 #define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5) 678 #define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7) 679 #define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1) 680 #define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3) 681 #define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5) 682 #define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7) 683 #define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0) 684 #define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1) 685 #define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2) 686 #define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3) 687 #define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5) 688 #define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7) 689 #define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0) 690 #define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1) 691 #define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2) 692 #define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3) 693 #define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5) 694 #define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7) 695 #define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1) 696 #define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3) 697 #define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5) 698 #define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7) 699 #define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0) 700 #define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1) 701 #define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2) 702 #define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3) 703 #define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5) 704 #define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7) 705 #define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1) 706 #define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3) 707 #define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5) 708 #define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7) 709 #define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1) 710 #define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3) 711 #define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5) 712 #define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7) 713 #define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0) 714 #define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1) 715 #define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2) 716 #define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3) 717 #define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5) 718 #define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7) 719 #define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1) 720 #define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2) 721 #define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5) 722 #define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6) 723 #define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0) 724 #define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1) 725 #define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4) 726 #define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5) 727 #define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6) 728 #define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1) 729 #define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5) 730 #define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0) 731 #define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1) 732 #define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4) 733 #define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5) 734 #define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6) 735 #define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0) 736 #define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1) 737 #define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2) 738 #define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3) 739 #define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4) 740 #define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5) 741 #define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6) 742 #define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7) 743 #define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1) 744 #define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5) 745 #define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1) 746 #define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5) 747 #define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0) 748 #define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1) 749 #define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4) 750 #define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5) 751 #define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6) 752 #define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1) 753 #define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2) 754 #define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5) 755 #define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6) 756 #define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0) 757 #define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1) 758 #define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4) 759 #define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5) 760 #define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6) 761 #define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1) 762 #define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5) 763 #define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0) 764 #define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1) 765 #define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4) 766 #define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5) 767 #define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6) 768 #define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0) 769 #define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1) 770 #define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2) 771 #define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3) 772 #define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4) 773 #define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5) 774 #define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6) 775 #define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7) 776 #define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1) 777 #define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5) 778 #define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1) 779 #define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5) 780 #define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0) 781 #define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1) 782 #define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4) 783 #define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5) 784 #define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6) 785 786 /* Misc instructions */ 787 #define OP_GCSPUSHX sys_insn(1, 0, 7, 7, 4) 788 #define OP_GCSPOPCX sys_insn(1, 0, 7, 7, 5) 789 #define OP_GCSPOPX sys_insn(1, 0, 7, 7, 6) 790 #define OP_GCSPUSHM sys_insn(1, 3, 7, 7, 0) 791 792 #define OP_BRB_IALL sys_insn(1, 1, 7, 2, 4) 793 #define OP_BRB_INJ sys_insn(1, 1, 7, 2, 5) 794 #define OP_CFP_RCTX sys_insn(1, 3, 7, 3, 4) 795 #define OP_DVP_RCTX sys_insn(1, 3, 7, 3, 5) 796 #define OP_COSP_RCTX sys_insn(1, 3, 7, 3, 6) 797 #define OP_CPP_RCTX sys_insn(1, 3, 7, 3, 7) 798 799 /* 800 * BRBE Instructions 801 */ 802 #define BRB_IALL_INSN __emit_inst(0xd5000000 | OP_BRB_IALL | (0x1f)) 803 #define BRB_INJ_INSN __emit_inst(0xd5000000 | OP_BRB_INJ | (0x1f)) 804 805 /* Common SCTLR_ELx flags. */ 806 #define SCTLR_ELx_ENTP2 (BIT(60)) 807 #define SCTLR_ELx_DSSBS (BIT(44)) 808 #define SCTLR_ELx_ATA (BIT(43)) 809 810 #define SCTLR_ELx_EE_SHIFT 25 811 #define SCTLR_ELx_ENIA_SHIFT 31 812 813 #define SCTLR_ELx_ITFSB (BIT(37)) 814 #define SCTLR_ELx_ENIA (BIT(SCTLR_ELx_ENIA_SHIFT)) 815 #define SCTLR_ELx_ENIB (BIT(30)) 816 #define SCTLR_ELx_LSMAOE (BIT(29)) 817 #define SCTLR_ELx_nTLSMD (BIT(28)) 818 #define SCTLR_ELx_ENDA (BIT(27)) 819 #define SCTLR_ELx_EE (BIT(SCTLR_ELx_EE_SHIFT)) 820 #define SCTLR_ELx_EIS (BIT(22)) 821 #define SCTLR_ELx_IESB (BIT(21)) 822 #define SCTLR_ELx_TSCXT (BIT(20)) 823 #define SCTLR_ELx_WXN (BIT(19)) 824 #define SCTLR_ELx_ENDB (BIT(13)) 825 #define SCTLR_ELx_I (BIT(12)) 826 #define SCTLR_ELx_EOS (BIT(11)) 827 #define SCTLR_ELx_SA (BIT(3)) 828 #define SCTLR_ELx_C (BIT(2)) 829 #define SCTLR_ELx_A (BIT(1)) 830 #define SCTLR_ELx_M (BIT(0)) 831 832 #endif /* ARM64_S390_COMMON == 1 */ 833 834 #define INIT_SCTLR_EL2_MMU_ON \ 835 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | SCTLR_ELx_I | \ 836 SCTLR_ELx_IESB | SCTLR_ELx_WXN | SCTLR_ELx_ITFSB | \ 837 SCTLR_ELx_EIS | SCTLR_ELx_EOS | SCTLR_EL2_RES1) 838 839 #define INIT_SCTLR_EL2_MMU_OFF (SCTLR_EL2_RES1) 840 841 /* SCTLR_EL1 specific flags. */ 842 #define INIT_SCTLR_EL1_MMU_OFF \ 843 (SCTLR_EL1_LSMAOE | SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | \ 844 SCTLR_EL1_TSCXT | SCTLR_EL1_EOS) 845 846 #define INIT_SCTLR_EL1_MMU_ON \ 847 (SCTLR_ELx_M | SCTLR_ELx_C | SCTLR_ELx_SA | \ 848 SCTLR_EL1_SA0 | SCTLR_EL1_SED | SCTLR_ELx_I | \ 849 SCTLR_EL1_DZE | SCTLR_EL1_UCT | SCTLR_EL1_nTWE | \ 850 SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \ 851 SCTLR_EL1_UCI | SCTLR_EL1_EPAN | SCTLR_EL1_LSMAOE | \ 852 SCTLR_EL1_nTLSMD | SCTLR_EL1_EIS | SCTLR_EL1_TSCXT | \ 853 SCTLR_EL1_EOS) 854 855 #if ARM64_S390_COMMON == 1 856 /* MAIR_ELx memory attributes (used by Linux) */ 857 #define MAIR_ATTR_DEVICE_nGnRnE UL(0x00) 858 #define MAIR_ATTR_DEVICE_nGnRE UL(0x04) 859 #define MAIR_ATTR_NORMAL_NC UL(0x44) 860 #define MAIR_ATTR_NORMAL_TAGGED UL(0xf0) 861 #define MAIR_ATTR_NORMAL UL(0xff) 862 #define MAIR_ATTR_MASK UL(0xff) 863 864 /* Position the attr at the correct index */ 865 #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) 866 867 /* id_aa64mmfr0 */ 868 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 0x0 869 #define ID_AA64MMFR0_EL1_TGRAN4_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT 870 #define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 0x7 871 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0 872 #define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7 873 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1 874 #define ID_AA64MMFR0_EL1_TGRAN16_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT 875 #define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf 876 877 #define ARM64_MIN_PARANGE_BITS 32 878 879 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT 0x0 880 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE 0x1 881 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN 0x2 882 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_LPA2 0x3 883 #define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX 0x7 884 885 #ifdef CONFIG_ARM64_PA_BITS_52 886 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_52 887 #else 888 #define ID_AA64MMFR0_EL1_PARANGE_MAX ID_AA64MMFR0_EL1_PARANGE_48 889 #endif 890 891 #if defined(CONFIG_ARM64_4K_PAGES) 892 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN4_SHIFT 893 #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN4_52_BIT 894 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN 895 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX 896 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT 897 #elif defined(CONFIG_ARM64_16K_PAGES) 898 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN16_SHIFT 899 #define ID_AA64MMFR0_EL1_TGRAN_LPA2 ID_AA64MMFR0_EL1_TGRAN16_52_BIT 900 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 901 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 902 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT 903 #elif defined(CONFIG_ARM64_64K_PAGES) 904 #define ID_AA64MMFR0_EL1_TGRAN_SHIFT ID_AA64MMFR0_EL1_TGRAN64_SHIFT 905 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 906 #define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 907 #define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT 908 #endif 909 910 #define CPACR_EL1_FPEN_EL1EN (BIT(20)) /* enable EL1 access */ 911 #define CPACR_EL1_FPEN_EL0EN (BIT(21)) /* enable EL0 access, if EL1EN set */ 912 913 #define CPACR_EL1_SMEN_EL1EN (BIT(24)) /* enable EL1 access */ 914 #define CPACR_EL1_SMEN_EL0EN (BIT(25)) /* enable EL0 access, if EL1EN set */ 915 916 #define CPACR_EL1_ZEN_EL1EN (BIT(16)) /* enable EL1 access */ 917 #define CPACR_EL1_ZEN_EL0EN (BIT(17)) /* enable EL0 access, if EL1EN set */ 918 919 /* GCR_EL1 Definitions */ 920 #define SYS_GCR_EL1_RRND (BIT(16)) 921 #define SYS_GCR_EL1_EXCL_MASK 0xffffUL 922 923 #ifdef CONFIG_KASAN_HW_TAGS 924 /* 925 * KASAN always uses a whole byte for its tags. With CONFIG_KASAN_HW_TAGS it 926 * only uses tags in the range 0xF0-0xFF, which we map to MTE tags 0x0-0xF. 927 */ 928 #define __MTE_TAG_MIN (KASAN_TAG_MIN & 0xf) 929 #define __MTE_TAG_MAX (KASAN_TAG_MAX & 0xf) 930 #define __MTE_TAG_INCL GENMASK(__MTE_TAG_MAX, __MTE_TAG_MIN) 931 #define KERNEL_GCR_EL1_EXCL (SYS_GCR_EL1_EXCL_MASK & ~__MTE_TAG_INCL) 932 #else 933 #define KERNEL_GCR_EL1_EXCL SYS_GCR_EL1_EXCL_MASK 934 #endif 935 936 #define KERNEL_GCR_EL1 (SYS_GCR_EL1_RRND | KERNEL_GCR_EL1_EXCL) 937 938 /* RGSR_EL1 Definitions */ 939 #define SYS_RGSR_EL1_TAG_MASK 0xfUL 940 #define SYS_RGSR_EL1_SEED_SHIFT 8 941 #define SYS_RGSR_EL1_SEED_MASK 0xffffUL 942 943 /* TFSR{,E0}_EL1 bit definitions */ 944 #define SYS_TFSR_EL1_TF0_SHIFT 0 945 #define SYS_TFSR_EL1_TF1_SHIFT 1 946 #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) 947 #define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) 948 949 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */ 950 #define SYS_MPIDR_SAFE_VAL (BIT(31)) 951 952 /* GIC Hypervisor interface registers */ 953 /* ICH_LR*_EL2 bit definitions */ 954 #define ICH_LR_VIRTUAL_ID_MASK ((1ULL << 32) - 1) 955 956 #define ICH_LR_EOI (1ULL << 41) 957 #define ICH_LR_GROUP (1ULL << 60) 958 #define ICH_LR_HW (1ULL << 61) 959 #define ICH_LR_STATE (3ULL << 62) 960 #define ICH_LR_PENDING_BIT (1ULL << 62) 961 #define ICH_LR_ACTIVE_BIT (1ULL << 63) 962 #define ICH_LR_PHYS_ID_SHIFT 32 963 #define ICH_LR_PHYS_ID_MASK (0x3ffULL << ICH_LR_PHYS_ID_SHIFT) 964 #define ICH_LR_PRIORITY_SHIFT 48 965 #define ICH_LR_PRIORITY_MASK (0xffULL << ICH_LR_PRIORITY_SHIFT) 966 967 /* 968 * Permission Indirection Extension (PIE) permission encodings. 969 * Encodings with the _O suffix, have overlays applied (Permission Overlay Extension). 970 */ 971 #define PIE_NONE_O UL(0x0) 972 #define PIE_R_O UL(0x1) 973 #define PIE_X_O UL(0x2) 974 #define PIE_RX_O UL(0x3) 975 #define PIE_RW_O UL(0x5) 976 #define PIE_RWnX_O UL(0x6) 977 #define PIE_RWX_O UL(0x7) 978 #define PIE_R UL(0x8) 979 #define PIE_GCS UL(0x9) 980 #define PIE_RX UL(0xa) 981 #define PIE_RW UL(0xc) 982 #define PIE_RWX UL(0xe) 983 #define PIE_MASK UL(0xf) 984 985 #define PIRx_ELx_BITS_PER_IDX 4 986 #define PIRx_ELx_PERM_SHIFT(idx) ((idx) * PIRx_ELx_BITS_PER_IDX) 987 #define PIRx_ELx_PERM_PREP(idx, perm) (((perm) & PIE_MASK) << PIRx_ELx_PERM_SHIFT(idx)) 988 989 /* 990 * Permission Overlay Extension (POE) permission encodings. 991 */ 992 #define POE_NONE UL(0x0) 993 #define POE_R UL(0x1) 994 #define POE_X UL(0x2) 995 #define POE_RX UL(0x3) 996 #define POE_W UL(0x4) 997 #define POE_RW UL(0x5) 998 #define POE_WX UL(0x6) 999 #define POE_RWX UL(0x7) 1000 #define POE_MASK UL(0xf) 1001 1002 #define POR_ELx_BITS_PER_IDX 4 1003 #define POR_ELx_PERM_SHIFT(idx) ((idx) * POR_ELx_BITS_PER_IDX) 1004 #define POR_ELx_PERM_GET(idx, reg) (((reg) >> POR_ELx_PERM_SHIFT(idx)) & POE_MASK) 1005 #define POR_ELx_PERM_PREP(idx, perm) (((perm) & POE_MASK) << POR_ELx_PERM_SHIFT(idx)) 1006 1007 /* 1008 * Definitions for Guarded Control Stack 1009 */ 1010 1011 #define GCS_CAP_ADDR_MASK GENMASK(63, 12) 1012 #define GCS_CAP_ADDR_SHIFT 12 1013 #define GCS_CAP_ADDR_WIDTH 52 1014 #define GCS_CAP_ADDR(x) FIELD_GET(GCS_CAP_ADDR_MASK, x) 1015 1016 #define GCS_CAP_TOKEN_MASK GENMASK(11, 0) 1017 #define GCS_CAP_TOKEN_SHIFT 0 1018 #define GCS_CAP_TOKEN_WIDTH 12 1019 #define GCS_CAP_TOKEN(x) FIELD_GET(GCS_CAP_TOKEN_MASK, x) 1020 1021 #define GCS_CAP_VALID_TOKEN 0x1 1022 #define GCS_CAP_IN_PROGRESS_TOKEN 0x5 1023 1024 #define GCS_CAP(x) ((((unsigned long)x) & GCS_CAP_ADDR_MASK) | \ 1025 GCS_CAP_VALID_TOKEN) 1026 /* 1027 * Definitions for GICv5 instructions for the Current Domain 1028 */ 1029 #define GICV5_OP_GIC_CDAFF sys_insn(1, 0, 12, 1, 3) 1030 #define GICV5_OP_GIC_CDDI sys_insn(1, 0, 12, 2, 0) 1031 #define GICV5_OP_GIC_CDDIS sys_insn(1, 0, 12, 1, 0) 1032 #define GICV5_OP_GIC_CDHM sys_insn(1, 0, 12, 2, 1) 1033 #define GICV5_OP_GIC_CDEN sys_insn(1, 0, 12, 1, 1) 1034 #define GICV5_OP_GIC_CDEOI sys_insn(1, 0, 12, 1, 7) 1035 #define GICV5_OP_GIC_CDPEND sys_insn(1, 0, 12, 1, 4) 1036 #define GICV5_OP_GIC_CDPRI sys_insn(1, 0, 12, 1, 2) 1037 #define GICV5_OP_GIC_CDRCFG sys_insn(1, 0, 12, 1, 5) 1038 #define GICV5_OP_GICR_CDIA sys_insn(1, 0, 12, 3, 0) 1039 #define GICV5_OP_GICR_CDNMIA sys_insn(1, 0, 12, 3, 1) 1040 1041 /* Definitions for GIC CDAFF */ 1042 #define GICV5_GIC_CDAFF_IAFFID_MASK GENMASK_ULL(47, 32) 1043 #define GICV5_GIC_CDAFF_TYPE_MASK GENMASK_ULL(31, 29) 1044 #define GICV5_GIC_CDAFF_IRM_MASK BIT_ULL(28) 1045 #define GICV5_GIC_CDAFF_ID_MASK GENMASK_ULL(23, 0) 1046 1047 /* Definitions for GIC CDDI */ 1048 #define GICV5_GIC_CDDI_TYPE_MASK GENMASK_ULL(31, 29) 1049 #define GICV5_GIC_CDDI_ID_MASK GENMASK_ULL(23, 0) 1050 1051 /* Definitions for GIC CDDIS */ 1052 #define GICV5_GIC_CDDIS_TYPE_MASK GENMASK_ULL(31, 29) 1053 #define GICV5_GIC_CDDIS_TYPE(r) FIELD_GET(GICV5_GIC_CDDIS_TYPE_MASK, r) 1054 #define GICV5_GIC_CDDIS_ID_MASK GENMASK_ULL(23, 0) 1055 #define GICV5_GIC_CDDIS_ID(r) FIELD_GET(GICV5_GIC_CDDIS_ID_MASK, r) 1056 1057 /* Definitions for GIC CDEN */ 1058 #define GICV5_GIC_CDEN_TYPE_MASK GENMASK_ULL(31, 29) 1059 #define GICV5_GIC_CDEN_ID_MASK GENMASK_ULL(23, 0) 1060 1061 /* Definitions for GIC CDHM */ 1062 #define GICV5_GIC_CDHM_HM_MASK BIT_ULL(32) 1063 #define GICV5_GIC_CDHM_TYPE_MASK GENMASK_ULL(31, 29) 1064 #define GICV5_GIC_CDHM_ID_MASK GENMASK_ULL(23, 0) 1065 1066 /* Definitions for GIC CDPEND */ 1067 #define GICV5_GIC_CDPEND_PENDING_MASK BIT_ULL(32) 1068 #define GICV5_GIC_CDPEND_TYPE_MASK GENMASK_ULL(31, 29) 1069 #define GICV5_GIC_CDPEND_ID_MASK GENMASK_ULL(23, 0) 1070 1071 /* Definitions for GIC CDPRI */ 1072 #define GICV5_GIC_CDPRI_PRIORITY_MASK GENMASK_ULL(39, 35) 1073 #define GICV5_GIC_CDPRI_TYPE_MASK GENMASK_ULL(31, 29) 1074 #define GICV5_GIC_CDPRI_ID_MASK GENMASK_ULL(23, 0) 1075 1076 /* Definitions for GIC CDRCFG */ 1077 #define GICV5_GIC_CDRCFG_TYPE_MASK GENMASK_ULL(31, 29) 1078 #define GICV5_GIC_CDRCFG_ID_MASK GENMASK_ULL(23, 0) 1079 1080 /* Definitions for GICR CDIA */ 1081 #define GICV5_GIC_CDIA_VALID_MASK BIT_ULL(32) 1082 #define GICV5_GICR_CDIA_VALID(r) FIELD_GET(GICV5_GIC_CDIA_VALID_MASK, r) 1083 #define GICV5_GIC_CDIA_TYPE_MASK GENMASK_ULL(31, 29) 1084 #define GICV5_GIC_CDIA_ID_MASK GENMASK_ULL(23, 0) 1085 1086 /* Definitions for GICR CDNMIA */ 1087 #define GICV5_GICR_CDNMIA_VALID_MASK BIT_ULL(32) 1088 #define GICV5_GICR_CDNMIA_VALID(r) FIELD_GET(GICV5_GICR_CDNMIA_VALID_MASK, r) 1089 #define GICV5_GICR_CDNMIA_TYPE_MASK GENMASK_ULL(31, 29) 1090 #define GICV5_GICR_CDNMIA_ID_MASK GENMASK_ULL(23, 0) 1091 1092 /* 1093 * Definitions for GICv5 instructions for the Virtual Domain 1094 */ 1095 #define GICV5_OP_GIC_VDPEND sys_insn(1, 4, 12, 1, 4) 1096 1097 /* Shift and mask definitions for GIC VDPEND */ 1098 #define GICV5_GIC_VDPEND_PENDING_MASK BIT_ULL(63) 1099 #define GICV5_GIC_VDPEND_VM_MASK GENMASK_ULL(47, 32) 1100 #define GICV5_GIC_VDPEND_TYPE_MASK GENMASK_ULL(31, 29) 1101 #define GICV5_GIC_VDPEND_ID_MASK GENMASK_ULL(23, 0) 1102 1103 #endif /* ARM64_S390_COMMON == 1 */ 1104 1105 #define gicr_insn(insn) read_sysreg_s(GICV5_OP_GICR_##insn) 1106 #define gic_insn(v, insn) write_sysreg_s(v, GICV5_OP_GIC_##insn) 1107 1108 #ifdef __ASSEMBLER__ 1109 1110 .macro mrs_s, rt, sreg 1111 __emit_inst(0xd5200000|(\sreg)|(.L__gpr_num_\rt)) 1112 .endm 1113 1114 .macro msr_s, sreg, rt 1115 __emit_inst(0xd5000000|(\sreg)|(.L__gpr_num_\rt)) 1116 .endm 1117 1118 .macro msr_hcr_el2, reg 1119 #if IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) 1120 dsb nsh 1121 #endif 1122 msr hcr_el2, \reg 1123 isb // Required by AMPERE_ERRATUM_AC04_CPU_23 1124 .endm 1125 #else 1126 1127 #include <linux/bitfield.h> 1128 #include <linux/build_bug.h> 1129 #include <linux/types.h> 1130 #include <asm/alternative.h> 1131 1132 #define DEFINE_MRS_S \ 1133 __DEFINE_ASM_GPR_NUMS \ 1134 " .macro mrs_s, rt, sreg\n" \ 1135 __emit_inst(0xd5200000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1136 " .endm\n" 1137 1138 #define DEFINE_MSR_S \ 1139 __DEFINE_ASM_GPR_NUMS \ 1140 " .macro msr_s, sreg, rt\n" \ 1141 __emit_inst(0xd5000000|(\\sreg)|(.L__gpr_num_\\rt)) \ 1142 " .endm\n" 1143 1144 #define UNDEFINE_MRS_S \ 1145 " .purgem mrs_s\n" 1146 1147 #define UNDEFINE_MSR_S \ 1148 " .purgem msr_s\n" 1149 1150 #define __mrs_s(v, r) \ 1151 DEFINE_MRS_S \ 1152 " mrs_s " v ", " __stringify(r) "\n" \ 1153 UNDEFINE_MRS_S 1154 1155 #define __msr_s(r, v) \ 1156 DEFINE_MSR_S \ 1157 " msr_s " __stringify(r) ", " v "\n" \ 1158 UNDEFINE_MSR_S 1159 1160 /* 1161 * Unlike read_cpuid, calls to read_sysreg are never expected to be 1162 * optimized away or replaced with synthetic values. 1163 */ 1164 #define read_sysreg(r) ({ \ 1165 u64 __val; \ 1166 asm volatile("mrs %0, " __stringify(r) : "=r" (__val)); \ 1167 __val; \ 1168 }) 1169 1170 /* 1171 * The "Z" constraint normally means a zero immediate, but when combined with 1172 * the "%x0" template means XZR. 1173 */ 1174 #define write_sysreg(v, r) do { \ 1175 u64 __val = (u64)(v); \ 1176 asm volatile("msr " __stringify(r) ", %x0" \ 1177 : : "rZ" (__val)); \ 1178 } while (0) 1179 1180 /* 1181 * For registers without architectural names, or simply unsupported by 1182 * GAS. 1183 * 1184 * __check_r forces warnings to be generated by the compiler when 1185 * evaluating r which wouldn't normally happen due to being passed to 1186 * the assembler via __stringify(r). 1187 */ 1188 #define read_sysreg_s(r) ({ \ 1189 u64 __val; \ 1190 u32 __maybe_unused __check_r = (u32)(r); \ 1191 asm volatile(__mrs_s("%0", r) : "=r" (__val)); \ 1192 __val; \ 1193 }) 1194 1195 /* 1196 * The "Z" constraint combined with the "%x0" template should be enough 1197 * to force XZR generation if (v) is a constant 0 value but LLVM does not 1198 * yet understand that modifier/constraint combo so a conditional is required 1199 * to nudge the compiler into using XZR as a source for a 0 constant value. 1200 */ 1201 #define write_sysreg_s(v, r) do { \ 1202 u64 __val = (u64)(v); \ 1203 u32 __maybe_unused __check_r = (u32)(r); \ 1204 if (__builtin_constant_p(__val) && __val == 0) \ 1205 asm volatile(__msr_s(r, "xzr")); \ 1206 else \ 1207 asm volatile(__msr_s(r, "%x0") : : "r" (__val)); \ 1208 } while (0) 1209 1210 /* 1211 * Modify bits in a sysreg. Bits in the clear mask are zeroed, then bits in the 1212 * set mask are set. Other bits are left as-is. 1213 */ 1214 #define sysreg_clear_set(sysreg, clear, set) do { \ 1215 u64 __scs_val = read_sysreg(sysreg); \ 1216 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1217 if (__scs_new != __scs_val) \ 1218 write_sysreg(__scs_new, sysreg); \ 1219 } while (0) 1220 1221 #define sysreg_clear_set_hcr(clear, set) do { \ 1222 u64 __scs_val = read_sysreg(hcr_el2); \ 1223 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1224 if (__scs_new != __scs_val) \ 1225 write_sysreg_hcr(__scs_new); \ 1226 } while (0) 1227 1228 #define sysreg_clear_set_s(sysreg, clear, set) do { \ 1229 u64 __scs_val = read_sysreg_s(sysreg); \ 1230 u64 __scs_new = (__scs_val & ~(u64)(clear)) | (set); \ 1231 if (__scs_new != __scs_val) \ 1232 write_sysreg_s(__scs_new, sysreg); \ 1233 } while (0) 1234 1235 #define write_sysreg_hcr(__val) do { \ 1236 if (IS_ENABLED(CONFIG_AMPERE_ERRATUM_AC04_CPU_23) && \ 1237 (!system_capabilities_finalized() || \ 1238 alternative_has_cap_unlikely(ARM64_WORKAROUND_AMPERE_AC04_CPU_23))) \ 1239 asm volatile("dsb nsh; msr hcr_el2, %x0; isb" \ 1240 : : "rZ" (__val)); \ 1241 else \ 1242 asm volatile("msr hcr_el2, %x0" \ 1243 : : "rZ" (__val)); \ 1244 } while (0) 1245 1246 #define read_sysreg_par() ({ \ 1247 u64 par; \ 1248 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1249 par = read_sysreg(par_el1); \ 1250 asm(ALTERNATIVE("nop", "dmb sy", ARM64_WORKAROUND_1508412)); \ 1251 par; \ 1252 }) 1253 1254 #if ARM64_S390_COMMON == 1 1255 1256 #define SYS_FIELD_VALUE(reg, field, val) reg##_##field##_##val 1257 1258 #define SYS_FIELD_GET(reg, field, val) \ 1259 FIELD_GET(reg##_##field##_MASK, val) 1260 1261 #define SYS_FIELD_PREP(reg, field, val) \ 1262 FIELD_PREP(reg##_##field##_MASK, val) 1263 1264 #define SYS_FIELD_PREP_ENUM(reg, field, val) \ 1265 FIELD_PREP(reg##_##field##_MASK, \ 1266 SYS_FIELD_VALUE(reg, field, val)) 1267 1268 #endif /* ARM64_S390_COMMON == 1 */ 1269 1270 #endif /* __ASSEMBLER__ */ 1271 1272 #endif /* __ASM_SYSREG_H */ 1273