xref: /linux/drivers/gpu/drm/amd/include/asic_reg/smu/smu_7_0_0_sh_mask.h (revision e5451c8f8330e03ad3cfa16048b4daf961af434f)
1 /*
2  * SMU_7_0_0 Register documentation
3  *
4  * Copyright (C) 2014  Advanced Micro Devices, Inc.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included
14  * in all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
20  * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
22  */
23 
24 #ifndef SMU_7_0_0_SH_MASK_H
25 #define SMU_7_0_0_SH_MASK_H
26 
27 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
28 #define GCK_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
29 #define GCK_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
30 #define GCK_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
31 #define CG_DCLK_CNTL__DCLK_DIVIDER_MASK 0x7f
32 #define CG_DCLK_CNTL__DCLK_DIVIDER__SHIFT 0x0
33 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN_MASK 0x100
34 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_EN__SHIFT 0x8
35 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG_MASK 0x200
36 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_TOG__SHIFT 0x9
37 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
38 #define CG_DCLK_CNTL__DCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
39 #define CG_DCLK_STATUS__DCLK_STATUS_MASK 0x1
40 #define CG_DCLK_STATUS__DCLK_STATUS__SHIFT 0x0
41 #define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG_MASK 0x2
42 #define CG_DCLK_STATUS__DCLK_DIR_CNTL_DONETOG__SHIFT 0x1
43 #define CG_VCLK_CNTL__VCLK_DIVIDER_MASK 0x7f
44 #define CG_VCLK_CNTL__VCLK_DIVIDER__SHIFT 0x0
45 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN_MASK 0x100
46 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_EN__SHIFT 0x8
47 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG_MASK 0x200
48 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_TOG__SHIFT 0x9
49 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
50 #define CG_VCLK_CNTL__VCLK_DIR_CNTL_DIVIDER__SHIFT 0xa
51 #define CG_VCLK_STATUS__VCLK_STATUS_MASK 0x1
52 #define CG_VCLK_STATUS__VCLK_STATUS__SHIFT 0x0
53 #define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG_MASK 0x2
54 #define CG_VCLK_STATUS__VCLK_DIR_CNTL_DONETOG__SHIFT 0x1
55 #define CG_ECLK_CNTL__ECLK_DIVIDER_MASK 0x7f
56 #define CG_ECLK_CNTL__ECLK_DIVIDER__SHIFT 0x0
57 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN_MASK 0x100
58 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_EN__SHIFT 0x8
59 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG_MASK 0x200
60 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_TOG__SHIFT 0x9
61 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
62 #define CG_ECLK_CNTL__ECLK_DIR_CNTL_DIVIDER__SHIFT 0xa
63 #define CG_ECLK_STATUS__ECLK_STATUS_MASK 0x1
64 #define CG_ECLK_STATUS__ECLK_STATUS__SHIFT 0x0
65 #define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG_MASK 0x2
66 #define CG_ECLK_STATUS__ECLK_DIR_CNTL_DONETOG__SHIFT 0x1
67 #define CG_ACLK_CNTL__ACLK_DIVIDER_MASK 0x7f
68 #define CG_ACLK_CNTL__ACLK_DIVIDER__SHIFT 0x0
69 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN_MASK 0x100
70 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_EN__SHIFT 0x8
71 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG_MASK 0x200
72 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_TOG__SHIFT 0x9
73 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER_MASK 0x1fc00
74 #define CG_ACLK_CNTL__ACLK_DIR_CNTL_DIVIDER__SHIFT 0xa
75 #define GCK_DFS_BYPASS_CNTL__BYPASSECLK_MASK 0x1
76 #define GCK_DFS_BYPASS_CNTL__BYPASSECLK__SHIFT 0x0
77 #define GCK_DFS_BYPASS_CNTL__BYPASSLCLK_MASK 0x2
78 #define GCK_DFS_BYPASS_CNTL__BYPASSLCLK__SHIFT 0x1
79 #define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK_MASK 0x4
80 #define GCK_DFS_BYPASS_CNTL__BYPASSEVCLK__SHIFT 0x2
81 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK 0x8
82 #define GCK_DFS_BYPASS_CNTL__BYPASSDCLK__SHIFT 0x3
83 #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK 0x10
84 #define GCK_DFS_BYPASS_CNTL__BYPASSVCLK__SHIFT 0x4
85 #define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK_MASK 0x20
86 #define GCK_DFS_BYPASS_CNTL__BYPASSDISPCLK__SHIFT 0x5
87 #define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK_MASK 0x40
88 #define GCK_DFS_BYPASS_CNTL__BYPASSDPREFCLK__SHIFT 0x6
89 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK_MASK 0x80
90 #define GCK_DFS_BYPASS_CNTL__BYPASSACLK__SHIFT 0x7
91 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK_MASK 0x100
92 #define GCK_DFS_BYPASS_CNTL__BYPASSADIVCLK__SHIFT 0x8
93 #define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK_MASK 0x200
94 #define GCK_DFS_BYPASS_CNTL__BYPASSPSPCLK__SHIFT 0x9
95 #define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK_MASK 0x400
96 #define GCK_DFS_BYPASS_CNTL__BYPASSSAMCLK__SHIFT 0xa
97 #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK_MASK 0x800
98 #define GCK_DFS_BYPASS_CNTL__BYPASSSCLK__SHIFT 0xb
99 #define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN_MASK 0x1000
100 #define GCK_DFS_BYPASS_CNTL__USE_SPLL_BYPASS_EN__SHIFT 0xc
101 #define CG_SPLL_FUNC_CNTL__SPLL_RESET_MASK 0x1
102 #define CG_SPLL_FUNC_CNTL__SPLL_RESET__SHIFT 0x0
103 #define CG_SPLL_FUNC_CNTL__SPLL_PWRON_MASK 0x2
104 #define CG_SPLL_FUNC_CNTL__SPLL_PWRON__SHIFT 0x1
105 #define CG_SPLL_FUNC_CNTL__SPLL_DIVEN_MASK 0x4
106 #define CG_SPLL_FUNC_CNTL__SPLL_DIVEN__SHIFT 0x2
107 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN_MASK 0x8
108 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_EN__SHIFT 0x3
109 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS_MASK 0x10
110 #define CG_SPLL_FUNC_CNTL__SPLL_BYPASS_THRU_DFS__SHIFT 0x4
111 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV_MASK 0x7e0
112 #define CG_SPLL_FUNC_CNTL__SPLL_REF_DIV__SHIFT 0x5
113 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE_MASK 0x800
114 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_UPDATE__SHIFT 0xb
115 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN_MASK 0x1000
116 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_EN__SHIFT 0xc
117 #define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON_MASK 0x2000
118 #define CG_SPLL_FUNC_CNTL__SPLL_BG_PWRON__SHIFT 0xd
119 #define CG_SPLL_FUNC_CNTL__SPLL_BGADJ_MASK 0x3c000
120 #define CG_SPLL_FUNC_CNTL__SPLL_BGADJ__SHIFT 0xe
121 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A_MASK 0x1fc0000
122 #define CG_SPLL_FUNC_CNTL__SPLL_PDIV_A__SHIFT 0x12
123 #define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS_MASK 0xe000000
124 #define CG_SPLL_FUNC_CNTL__SPLL_REG_BIAS__SHIFT 0x19
125 #define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN_MASK 0x10000000
126 #define CG_SPLL_FUNC_CNTL__SPLL_OTEST_LOCK_EN__SHIFT 0x1c
127 #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL_MASK 0x1ff
128 #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_SEL__SHIFT 0x0
129 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_MASK 0x800
130 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ__SHIFT 0xb
131 #define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG_MASK 0x400000
132 #define CG_SPLL_FUNC_CNTL_2__SPLL_BYPASS_CHG__SHIFT 0x16
133 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG_MASK 0x800000
134 #define CG_SPLL_FUNC_CNTL_2__SPLL_CTLREQ_CHG__SHIFT 0x17
135 #define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG_MASK 0x1000000
136 #define CG_SPLL_FUNC_CNTL_2__SPLL_RESET_CHG__SHIFT 0x18
137 #define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG_MASK 0x2000000
138 #define CG_SPLL_FUNC_CNTL_2__SPLL_BABY_STEP_CHG__SHIFT 0x19
139 #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE_MASK 0x4000000
140 #define CG_SPLL_FUNC_CNTL_2__SCLK_MUX_UPDATE__SHIFT 0x1a
141 #define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR_MASK 0x8000000
142 #define CG_SPLL_FUNC_CNTL_2__SPLL_UNLOCK_CLEAR__SHIFT 0x1b
143 #define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE_MASK 0x10000000
144 #define CG_SPLL_FUNC_CNTL_2__SPLL_CLKF_UPDATE__SHIFT 0x1c
145 #define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR_MASK 0x40000000
146 #define CG_SPLL_FUNC_CNTL_2__SPLL_TEST_UNLOCK_CLR__SHIFT 0x1e
147 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV_MASK 0x3ffffff
148 #define CG_SPLL_FUNC_CNTL_3__SPLL_FB_DIV__SHIFT 0x0
149 #define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN_MASK 0x10000000
150 #define CG_SPLL_FUNC_CNTL_3__SPLL_DITHEN__SHIFT 0x1c
151 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL_MASK 0xf
152 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_TEST_SEL__SHIFT 0x0
153 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL_MASK 0x60
154 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_SEL__SHIFT 0x5
155 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN_MASK 0x180
156 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EN__SHIFT 0x7
157 #define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN_MASK 0x200
158 #define CG_SPLL_FUNC_CNTL_4__SPLL_SSAMP_EN__SHIFT 0x9
159 #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_MASK 0x7fc00
160 #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE__SHIFT 0xa
161 #define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS_MASK 0x200000
162 #define CG_SPLL_FUNC_CNTL_4__TEST_FRAC_BYPASS__SHIFT 0x15
163 #define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK_MASK 0x800000
164 #define CG_SPLL_FUNC_CNTL_4__SPLL_ILOCK__SHIFT 0x17
165 #define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL_MASK 0x1000000
166 #define CG_SPLL_FUNC_CNTL_4__SPLL_FBCLK_SEL__SHIFT 0x18
167 #define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN_MASK 0x2000000
168 #define CG_SPLL_FUNC_CNTL_4__SPLL_VCTRLADC_EN__SHIFT 0x19
169 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT_MASK 0xc000000
170 #define CG_SPLL_FUNC_CNTL_4__SPLL_SCLK_EXT__SHIFT 0x1a
171 #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT_MASK 0x70000000
172 #define CG_SPLL_FUNC_CNTL_4__SPLL_SPARE_EXT__SHIFT 0x1c
173 #define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL_MASK 0x80000000
174 #define CG_SPLL_FUNC_CNTL_4__SPLL_VTOI_BIAS_CNTL__SHIFT 0x1f
175 #define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS_MASK 0x1
176 #define CG_SPLL_FUNC_CNTL_5__FBDIV_SSC_BYPASS__SHIFT 0x0
177 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN_MASK 0x2
178 #define CG_SPLL_FUNC_CNTL_5__RISEFBVCO_EN__SHIFT 0x1
179 #define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL_MASK 0xc
180 #define CG_SPLL_FUNC_CNTL_5__PFD_RESET_CNTRL__SHIFT 0x2
181 #define CG_SPLL_FUNC_CNTL_5__RESET_TIMER_MASK 0x30
182 #define CG_SPLL_FUNC_CNTL_5__RESET_TIMER__SHIFT 0x4
183 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL_MASK 0xc0
184 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_CNTRL__SHIFT 0x6
185 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN_MASK 0x100
186 #define CG_SPLL_FUNC_CNTL_5__FAST_LOCK_EN__SHIFT 0x8
187 #define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX_MASK 0x200
188 #define CG_SPLL_FUNC_CNTL_5__RESET_ANTI_MUX__SHIFT 0x9
189 #define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN_MASK 0x400
190 #define CG_SPLL_FUNC_CNTL_5__REFCLK_BYPASS_EN__SHIFT 0xa
191 #define CG_SPLL_FUNC_CNTL_5__PLLBYPASS_MASK 0x800
192 #define CG_SPLL_FUNC_CNTL_5__PLLBYPASS__SHIFT 0xb
193 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT_MASK 0xff
194 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX0_CLKOFF_CNT__SHIFT 0x0
195 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT_MASK 0xff00
196 #define CG_SPLL_FUNC_CNTL_6__SCLKMUX1_CLKOFF_CNT__SHIFT 0x8
197 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN_MASK 0x10000
198 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_EN__SHIFT 0x10
199 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN_MASK 0x1e0000
200 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_IN__SHIFT 0x11
201 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT_MASK 0x1e00000
202 #define CG_SPLL_FUNC_CNTL_6__SPLL_VCTL_CNTRL_OUT__SHIFT 0x15
203 #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR_MASK 0xfe000000
204 #define CG_SPLL_FUNC_CNTL_6__SPLL_LF_CNTR__SHIFT 0x19
205 #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL_MASK 0xfff
206 #define CG_SPLL_FUNC_CNTL_7__SPLL_BW_CNTRL__SHIFT 0x0
207 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL_MASK 0x1
208 #define SPLL_CNTL_MODE__SPLL_SW_DIR_CONTROL__SHIFT 0x0
209 #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV_MASK 0x2
210 #define SPLL_CNTL_MODE__SPLL_LEGACY_PDIV__SHIFT 0x1
211 #define SPLL_CNTL_MODE__SPLL_TEST_MASK 0x4
212 #define SPLL_CNTL_MODE__SPLL_TEST__SHIFT 0x2
213 #define SPLL_CNTL_MODE__SPLL_FASTEN_MASK 0x8
214 #define SPLL_CNTL_MODE__SPLL_FASTEN__SHIFT 0x3
215 #define SPLL_CNTL_MODE__SPLL_ENSAT_MASK 0x10
216 #define SPLL_CNTL_MODE__SPLL_ENSAT__SHIFT 0x4
217 #define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV_MASK 0xc00
218 #define SPLL_CNTL_MODE__SPLL_TEST_CLK_EXT_DIV__SHIFT 0xa
219 #define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT_MASK 0xff000
220 #define SPLL_CNTL_MODE__SPLL_CTLREQ_DLY_CNT__SHIFT 0xc
221 #define SPLL_CNTL_MODE__SPLL_RESET_EN_MASK 0x10000000
222 #define SPLL_CNTL_MODE__SPLL_RESET_EN__SHIFT 0x1c
223 #define SPLL_CNTL_MODE__SPLL_VCO_MODE_MASK 0x60000000
224 #define SPLL_CNTL_MODE__SPLL_VCO_MODE__SHIFT 0x1d
225 #define CG_SPLL_SPREAD_SPECTRUM__SSEN_MASK 0x1
226 #define CG_SPLL_SPREAD_SPECTRUM__SSEN__SHIFT 0x0
227 #define CG_SPLL_SPREAD_SPECTRUM__CLKS_MASK 0xfff0
228 #define CG_SPLL_SPREAD_SPECTRUM__CLKS__SHIFT 0x4
229 #define CG_SPLL_SPREAD_SPECTRUM_2__CLKV_MASK 0x3ffffff
230 #define CG_SPLL_SPREAD_SPECTRUM_2__CLKV__SHIFT 0x0
231 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL_MASK 0xff00
232 #define MPLL_BYPASSCLK_SEL__MPLL_CLKOUT_SEL__SHIFT 0x8
233 #define CG_CLKPIN_CNTL__XTALIN_DIVIDE_MASK 0x2
234 #define CG_CLKPIN_CNTL__XTALIN_DIVIDE__SHIFT 0x1
235 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK_MASK 0x4
236 #define CG_CLKPIN_CNTL__BCLK_AS_XCLK__SHIFT 0x2
237 #define CG_CLKPIN_CNTL_2__ENABLE_XCLK_MASK 0x1
238 #define CG_CLKPIN_CNTL_2__ENABLE_XCLK__SHIFT 0x0
239 #define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN_MASK 0x8
240 #define CG_CLKPIN_CNTL_2__FORCE_BIF_REFCLK_EN__SHIFT 0x3
241 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK_MASK 0x100
242 #define CG_CLKPIN_CNTL_2__MUX_TCLK_TO_XCLK__SHIFT 0x8
243 #define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN_MASK 0x4000
244 #define CG_CLKPIN_CNTL_2__XO_IN_OSCIN_EN__SHIFT 0xe
245 #define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE_MASK 0x8000
246 #define CG_CLKPIN_CNTL_2__XO_IN_ICORE_CLK_OE__SHIFT 0xf
247 #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN_MASK 0x10000
248 #define CG_CLKPIN_CNTL_2__XO_IN_CML_RXEN__SHIFT 0x10
249 #define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE_MASK 0x20000
250 #define CG_CLKPIN_CNTL_2__XO_IN_BIDIR_CML_OE__SHIFT 0x11
251 #define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN_MASK 0x40000
252 #define CG_CLKPIN_CNTL_2__XO_IN2_OSCIN_EN__SHIFT 0x12
253 #define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE_MASK 0x80000
254 #define CG_CLKPIN_CNTL_2__XO_IN2_ICORE_CLK_OE__SHIFT 0x13
255 #define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN_MASK 0x100000
256 #define CG_CLKPIN_CNTL_2__XO_IN2_CML_RXEN__SHIFT 0x14
257 #define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE_MASK 0x200000
258 #define CG_CLKPIN_CNTL_2__XO_IN2_BIDIR_CML_OE__SHIFT 0x15
259 #define CG_CLKPIN_CNTL_2__CML_CTRL_MASK 0xc00000
260 #define CG_CLKPIN_CNTL_2__CML_CTRL__SHIFT 0x16
261 #define CG_CLKPIN_CNTL_2__CLK_SPARE_MASK 0xff000000
262 #define CG_CLKPIN_CNTL_2__CLK_SPARE__SHIFT 0x18
263 #define THM_CLK_CNTL__CMON_CLK_SEL_MASK 0xff
264 #define THM_CLK_CNTL__CMON_CLK_SEL__SHIFT 0x0
265 #define THM_CLK_CNTL__TMON_CLK_SEL_MASK 0xff00
266 #define THM_CLK_CNTL__TMON_CLK_SEL__SHIFT 0x8
267 #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN_MASK 0x10000
268 #define THM_CLK_CNTL__CTF_CLK_SHUTOFF_EN__SHIFT 0x10
269 #define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL_MASK 0xff
270 #define MISC_CLK_CTRL__DEEP_SLEEP_CLK_SEL__SHIFT 0x0
271 #define MISC_CLK_CTRL__ZCLK_SEL_MASK 0xff00
272 #define MISC_CLK_CTRL__ZCLK_SEL__SHIFT 0x8
273 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL_MASK 0xff0000
274 #define MISC_CLK_CTRL__DFT_SMS_PG_CLK_SEL__SHIFT 0x10
275 #define GCK_PLL_TEST_CNTL__TST_SRC_SEL_MASK 0x1f
276 #define GCK_PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
277 #define GCK_PLL_TEST_CNTL__TST_REF_SEL_MASK 0x3e0
278 #define GCK_PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x5
279 #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x1fc00
280 #define GCK_PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0xa
281 #define GCK_PLL_TEST_CNTL__TST_RESET_MASK 0x20000
282 #define GCK_PLL_TEST_CNTL__TST_RESET__SHIFT 0x11
283 #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE_MASK 0x40000
284 #define GCK_PLL_TEST_CNTL__TST_CLK_SEL_MODE__SHIFT 0x12
285 #define GCK_PLL_TEST_CNTL_2__TEST_COUNT_MASK 0xfffe0000
286 #define GCK_PLL_TEST_CNTL_2__TEST_COUNT__SHIFT 0x11
287 #define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL_MASK 0x7
288 #define GCK_ADFS_CLK_BYPASS_CNTL1__ECLK_BYPASS_CNTL__SHIFT 0x0
289 #define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL_MASK 0x38
290 #define GCK_ADFS_CLK_BYPASS_CNTL1__SCLK_BYPASS_CNTL__SHIFT 0x3
291 #define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL_MASK 0x1c0
292 #define GCK_ADFS_CLK_BYPASS_CNTL1__LCLK_BYPASS_CNTL__SHIFT 0x6
293 #define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL_MASK 0xe00
294 #define GCK_ADFS_CLK_BYPASS_CNTL1__DCLK_BYPASS_CNTL__SHIFT 0x9
295 #define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL_MASK 0x7000
296 #define GCK_ADFS_CLK_BYPASS_CNTL1__VCLK_BYPASS_CNTL__SHIFT 0xc
297 #define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL_MASK 0x38000
298 #define GCK_ADFS_CLK_BYPASS_CNTL1__DISPCLK_BYPASS_CNTL__SHIFT 0xf
299 #define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL_MASK 0x1c0000
300 #define GCK_ADFS_CLK_BYPASS_CNTL1__DRREFCLK_BYPASS_CNTL__SHIFT 0x12
301 #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL_MASK 0xe00000
302 #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_BYPASS_CNTL__SHIFT 0x15
303 #define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL_MASK 0x7000000
304 #define GCK_ADFS_CLK_BYPASS_CNTL1__SAMCLK_BYPASS_CNTL__SHIFT 0x18
305 #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL_MASK 0x38000000
306 #define GCK_ADFS_CLK_BYPASS_CNTL1__ACLK_DIV_BYPASS_CNTL__SHIFT 0x1b
307 #define SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
308 #define SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
309 #define SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
310 #define SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
311 #define SMC_IND_INDEX_0__SMC_IND_ADDR_MASK 0xffffffff
312 #define SMC_IND_INDEX_0__SMC_IND_ADDR__SHIFT 0x0
313 #define SMC_IND_DATA_0__SMC_IND_DATA_MASK 0xffffffff
314 #define SMC_IND_DATA_0__SMC_IND_DATA__SHIFT 0x0
315 #define SMC_IND_INDEX_1__SMC_IND_ADDR_MASK 0xffffffff
316 #define SMC_IND_INDEX_1__SMC_IND_ADDR__SHIFT 0x0
317 #define SMC_IND_DATA_1__SMC_IND_DATA_MASK 0xffffffff
318 #define SMC_IND_DATA_1__SMC_IND_DATA__SHIFT 0x0
319 #define SMC_IND_INDEX_2__SMC_IND_ADDR_MASK 0xffffffff
320 #define SMC_IND_INDEX_2__SMC_IND_ADDR__SHIFT 0x0
321 #define SMC_IND_DATA_2__SMC_IND_DATA_MASK 0xffffffff
322 #define SMC_IND_DATA_2__SMC_IND_DATA__SHIFT 0x0
323 #define SMC_IND_INDEX_3__SMC_IND_ADDR_MASK 0xffffffff
324 #define SMC_IND_INDEX_3__SMC_IND_ADDR__SHIFT 0x0
325 #define SMC_IND_DATA_3__SMC_IND_DATA_MASK 0xffffffff
326 #define SMC_IND_DATA_3__SMC_IND_DATA__SHIFT 0x0
327 #define SMC_IND_INDEX_4__SMC_IND_ADDR_MASK 0xffffffff
328 #define SMC_IND_INDEX_4__SMC_IND_ADDR__SHIFT 0x0
329 #define SMC_IND_DATA_4__SMC_IND_DATA_MASK 0xffffffff
330 #define SMC_IND_DATA_4__SMC_IND_DATA__SHIFT 0x0
331 #define SMC_IND_INDEX_5__SMC_IND_ADDR_MASK 0xffffffff
332 #define SMC_IND_INDEX_5__SMC_IND_ADDR__SHIFT 0x0
333 #define SMC_IND_DATA_5__SMC_IND_DATA_MASK 0xffffffff
334 #define SMC_IND_DATA_5__SMC_IND_DATA__SHIFT 0x0
335 #define SMC_IND_INDEX_6__SMC_IND_ADDR_MASK 0xffffffff
336 #define SMC_IND_INDEX_6__SMC_IND_ADDR__SHIFT 0x0
337 #define SMC_IND_DATA_6__SMC_IND_DATA_MASK 0xffffffff
338 #define SMC_IND_DATA_6__SMC_IND_DATA__SHIFT 0x0
339 #define SMC_IND_INDEX_7__SMC_IND_ADDR_MASK 0xffffffff
340 #define SMC_IND_INDEX_7__SMC_IND_ADDR__SHIFT 0x0
341 #define SMC_IND_DATA_7__SMC_IND_DATA_MASK 0xffffffff
342 #define SMC_IND_DATA_7__SMC_IND_DATA__SHIFT 0x0
343 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0_MASK 0x1
344 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_0__SHIFT 0x0
345 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1_MASK 0x2
346 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_1__SHIFT 0x1
347 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2_MASK 0x4
348 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_2__SHIFT 0x2
349 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3_MASK 0x8
350 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_3__SHIFT 0x3
351 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4_MASK 0x10
352 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_4__SHIFT 0x4
353 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5_MASK 0x20
354 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_5__SHIFT 0x5
355 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6_MASK 0x40
356 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_6__SHIFT 0x6
357 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7_MASK 0x80
358 #define SMC_IND_ACCESS_CNTL__AUTO_INCREMENT_IND_7__SHIFT 0x7
359 #define SMC_MESSAGE_0__SMC_MSG_MASK 0xffff
360 #define SMC_MESSAGE_0__SMC_MSG__SHIFT 0x0
361 #define SMC_RESP_0__SMC_RESP_MASK 0xffff
362 #define SMC_RESP_0__SMC_RESP__SHIFT 0x0
363 #define SMC_MESSAGE_1__SMC_MSG_MASK 0xffff
364 #define SMC_MESSAGE_1__SMC_MSG__SHIFT 0x0
365 #define SMC_RESP_1__SMC_RESP_MASK 0xffff
366 #define SMC_RESP_1__SMC_RESP__SHIFT 0x0
367 #define SMC_MESSAGE_2__SMC_MSG_MASK 0xffff
368 #define SMC_MESSAGE_2__SMC_MSG__SHIFT 0x0
369 #define SMC_RESP_2__SMC_RESP_MASK 0xffff
370 #define SMC_RESP_2__SMC_RESP__SHIFT 0x0
371 #define SMC_MESSAGE_3__SMC_MSG_MASK 0xffff
372 #define SMC_MESSAGE_3__SMC_MSG__SHIFT 0x0
373 #define SMC_RESP_3__SMC_RESP_MASK 0xffff
374 #define SMC_RESP_3__SMC_RESP__SHIFT 0x0
375 #define SMC_MESSAGE_4__SMC_MSG_MASK 0xffff
376 #define SMC_MESSAGE_4__SMC_MSG__SHIFT 0x0
377 #define SMC_RESP_4__SMC_RESP_MASK 0xffff
378 #define SMC_RESP_4__SMC_RESP__SHIFT 0x0
379 #define SMC_MESSAGE_5__SMC_MSG_MASK 0xffff
380 #define SMC_MESSAGE_5__SMC_MSG__SHIFT 0x0
381 #define SMC_RESP_5__SMC_RESP_MASK 0xffff
382 #define SMC_RESP_5__SMC_RESP__SHIFT 0x0
383 #define SMC_MESSAGE_6__SMC_MSG_MASK 0xffff
384 #define SMC_MESSAGE_6__SMC_MSG__SHIFT 0x0
385 #define SMC_RESP_6__SMC_RESP_MASK 0xffff
386 #define SMC_RESP_6__SMC_RESP__SHIFT 0x0
387 #define SMC_MESSAGE_7__SMC_MSG_MASK 0xffff
388 #define SMC_MESSAGE_7__SMC_MSG__SHIFT 0x0
389 #define SMC_RESP_7__SMC_RESP_MASK 0xffff
390 #define SMC_RESP_7__SMC_RESP__SHIFT 0x0
391 #define SMC_MSG_ARG_0__SMC_MSG_ARG_MASK 0xffffffff
392 #define SMC_MSG_ARG_0__SMC_MSG_ARG__SHIFT 0x0
393 #define SMC_MSG_ARG_1__SMC_MSG_ARG_MASK 0xffffffff
394 #define SMC_MSG_ARG_1__SMC_MSG_ARG__SHIFT 0x0
395 #define SMC_MSG_ARG_2__SMC_MSG_ARG_MASK 0xffffffff
396 #define SMC_MSG_ARG_2__SMC_MSG_ARG__SHIFT 0x0
397 #define SMC_MSG_ARG_3__SMC_MSG_ARG_MASK 0xffffffff
398 #define SMC_MSG_ARG_3__SMC_MSG_ARG__SHIFT 0x0
399 #define SMC_MSG_ARG_4__SMC_MSG_ARG_MASK 0xffffffff
400 #define SMC_MSG_ARG_4__SMC_MSG_ARG__SHIFT 0x0
401 #define SMC_MSG_ARG_5__SMC_MSG_ARG_MASK 0xffffffff
402 #define SMC_MSG_ARG_5__SMC_MSG_ARG__SHIFT 0x0
403 #define SMC_MSG_ARG_6__SMC_MSG_ARG_MASK 0xffffffff
404 #define SMC_MSG_ARG_6__SMC_MSG_ARG__SHIFT 0x0
405 #define SMC_MSG_ARG_7__SMC_MSG_ARG_MASK 0xffffffff
406 #define SMC_MSG_ARG_7__SMC_MSG_ARG__SHIFT 0x0
407 #define SMC_MESSAGE_8__SMC_MSG_MASK 0xffff
408 #define SMC_MESSAGE_8__SMC_MSG__SHIFT 0x0
409 #define SMC_RESP_8__SMC_RESP_MASK 0xffff
410 #define SMC_RESP_8__SMC_RESP__SHIFT 0x0
411 #define SMC_MESSAGE_9__SMC_MSG_MASK 0xffff
412 #define SMC_MESSAGE_9__SMC_MSG__SHIFT 0x0
413 #define SMC_RESP_9__SMC_RESP_MASK 0xffff
414 #define SMC_RESP_9__SMC_RESP__SHIFT 0x0
415 #define SMC_MESSAGE_10__SMC_MSG_MASK 0xffff
416 #define SMC_MESSAGE_10__SMC_MSG__SHIFT 0x0
417 #define SMC_RESP_10__SMC_RESP_MASK 0xffff
418 #define SMC_RESP_10__SMC_RESP__SHIFT 0x0
419 #define SMC_MESSAGE_11__SMC_MSG_MASK 0xffff
420 #define SMC_MESSAGE_11__SMC_MSG__SHIFT 0x0
421 #define SMC_RESP_11__SMC_RESP_MASK 0xffff
422 #define SMC_RESP_11__SMC_RESP__SHIFT 0x0
423 #define SMC_MSG_ARG_8__SMC_MSG_ARG_MASK 0xffffffff
424 #define SMC_MSG_ARG_8__SMC_MSG_ARG__SHIFT 0x0
425 #define SMC_MSG_ARG_9__SMC_MSG_ARG_MASK 0xffffffff
426 #define SMC_MSG_ARG_9__SMC_MSG_ARG__SHIFT 0x0
427 #define SMC_MSG_ARG_10__SMC_MSG_ARG_MASK 0xffffffff
428 #define SMC_MSG_ARG_10__SMC_MSG_ARG__SHIFT 0x0
429 #define SMC_MSG_ARG_11__SMC_MSG_ARG_MASK 0xffffffff
430 #define SMC_MSG_ARG_11__SMC_MSG_ARG__SHIFT 0x0
431 #define SMC_SYSCON_RESET_CNTL__rst_reg_MASK 0x1
432 #define SMC_SYSCON_RESET_CNTL__rst_reg__SHIFT 0x0
433 #define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override_MASK 0x2
434 #define SMC_SYSCON_RESET_CNTL__srbm_soft_rst_override__SHIFT 0x1
435 #define SMC_SYSCON_RESET_CNTL__RegReset_MASK 0x40000000
436 #define SMC_SYSCON_RESET_CNTL__RegReset__SHIFT 0x1e
437 #define SMC_SYSCON_CLOCK_CNTL_0__ck_disable_MASK 0x1
438 #define SMC_SYSCON_CLOCK_CNTL_0__ck_disable__SHIFT 0x0
439 #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en_MASK 0x2
440 #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_en__SHIFT 0x1
441 #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout_MASK 0xffff00
442 #define SMC_SYSCON_CLOCK_CNTL_0__auto_cg_timeout__SHIFT 0x8
443 #define SMC_SYSCON_CLOCK_CNTL_0__cken_MASK 0x1000000
444 #define SMC_SYSCON_CLOCK_CNTL_0__cken__SHIFT 0x18
445 #define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable_MASK 0x1
446 #define SMC_SYSCON_CLOCK_CNTL_1__auto_ck_disable__SHIFT 0x0
447 #define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq_MASK 0xffffffff
448 #define SMC_SYSCON_CLOCK_CNTL_2__wake_on_irq__SHIFT 0x0
449 #define SMC_SYSCON_MSG_ARG_0__smc_msg_arg_MASK 0xffffffff
450 #define SMC_SYSCON_MSG_ARG_0__smc_msg_arg__SHIFT 0x0
451 #define SMC_PC_C__smc_pc_c_MASK 0xffffffff
452 #define SMC_PC_C__smc_pc_c__SHIFT 0x0
453 #define SMC_SCRATCH9__SCRATCH_VALUE_MASK 0xffffffff
454 #define SMC_SCRATCH9__SCRATCH_VALUE__SHIFT 0x0
455 #define CG_FPS_CNT__FPS_CNT_MASK 0xff
456 #define CG_FPS_CNT__FPS_CNT__SHIFT 0x0
457 #define SMU_SMC_IND_INDEX__SMC_IND_ADDR_MASK 0xffffffff
458 #define SMU_SMC_IND_INDEX__SMC_IND_ADDR__SHIFT 0x0
459 #define SMU_SMC_IND_DATA__SMC_IND_DATA_MASK 0xffffffff
460 #define SMU_SMC_IND_DATA__SMC_IND_DATA__SHIFT 0x0
461 #define RCU_UC_EVENTS__RCU_TST_jpc_rep_req_MASK 0x1
462 #define RCU_UC_EVENTS__RCU_TST_jpc_rep_req__SHIFT 0x0
463 #define RCU_UC_EVENTS__TST_RCU_jpc_rep_done_MASK 0x2
464 #define RCU_UC_EVENTS__TST_RCU_jpc_rep_done__SHIFT 0x1
465 #define RCU_UC_EVENTS__drv_rst_mode_MASK 0x4
466 #define RCU_UC_EVENTS__drv_rst_mode__SHIFT 0x2
467 #define RCU_UC_EVENTS__TP_Tester_MASK 0x40
468 #define RCU_UC_EVENTS__TP_Tester__SHIFT 0x6
469 #define RCU_UC_EVENTS__boot_seq_done_MASK 0x80
470 #define RCU_UC_EVENTS__boot_seq_done__SHIFT 0x7
471 #define RCU_UC_EVENTS__sclk_deep_sleep_exit_MASK 0x100
472 #define RCU_UC_EVENTS__sclk_deep_sleep_exit__SHIFT 0x8
473 #define RCU_UC_EVENTS__BREAK_PT1_ACTIVE_MASK 0x200
474 #define RCU_UC_EVENTS__BREAK_PT1_ACTIVE__SHIFT 0x9
475 #define RCU_UC_EVENTS__BREAK_PT2_ACTIVE_MASK 0x400
476 #define RCU_UC_EVENTS__BREAK_PT2_ACTIVE__SHIFT 0xa
477 #define RCU_UC_EVENTS__FCH_HALT_MASK 0x800
478 #define RCU_UC_EVENTS__FCH_HALT__SHIFT 0xb
479 #define RCU_UC_EVENTS__RCU_GIO_fch_lockdown_MASK 0x2000
480 #define RCU_UC_EVENTS__RCU_GIO_fch_lockdown__SHIFT 0xd
481 #define RCU_UC_EVENTS__INTERRUPTS_ENABLED_MASK 0x10000
482 #define RCU_UC_EVENTS__INTERRUPTS_ENABLED__SHIFT 0x10
483 #define RCU_UC_EVENTS__RCU_DtmCnt0_Done_MASK 0x20000
484 #define RCU_UC_EVENTS__RCU_DtmCnt0_Done__SHIFT 0x11
485 #define RCU_UC_EVENTS__RCU_DtmCnt1_Done_MASK 0x40000
486 #define RCU_UC_EVENTS__RCU_DtmCnt1_Done__SHIFT 0x12
487 #define RCU_UC_EVENTS__RCU_DtmCnt2_Done_MASK 0x80000
488 #define RCU_UC_EVENTS__RCU_DtmCnt2_Done__SHIFT 0x13
489 #define RCU_UC_EVENTS__irq31_sel_MASK 0x3000000
490 #define RCU_UC_EVENTS__irq31_sel__SHIFT 0x18
491 #define RCU_MISC_CTRL__REG_DRV_RST_MODE_MASK 0x2
492 #define RCU_MISC_CTRL__REG_DRV_RST_MODE__SHIFT 0x1
493 #define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS_MASK 0x8
494 #define RCU_MISC_CTRL__REG_RCU_MEMREP_DIS__SHIFT 0x3
495 #define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE_MASK 0x10
496 #define RCU_MISC_CTRL__REG_CC_FUSE_DISABLE__SHIFT 0x4
497 #define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE_MASK 0x20
498 #define RCU_MISC_CTRL__REG_SAMU_FUSE_DISABLE__SHIFT 0x5
499 #define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE_MASK 0x100
500 #define RCU_MISC_CTRL__REG_CC_SRBM_RD_DISABLE__SHIFT 0x8
501 #define RCU_MISC_CTRL__BREAK_PT1_DONE_MASK 0x10000
502 #define RCU_MISC_CTRL__BREAK_PT1_DONE__SHIFT 0x10
503 #define RCU_MISC_CTRL__BREAK_PT2_DONE_MASK 0x20000
504 #define RCU_MISC_CTRL__BREAK_PT2_DONE__SHIFT 0x11
505 #define RCU_MISC_CTRL__SAMU_START_MASK 0x400000
506 #define RCU_MISC_CTRL__SAMU_START__SHIFT 0x16
507 #define RCU_MISC_CTRL__RST_PULSE_WIDTH_MASK 0xff800000
508 #define RCU_MISC_CTRL__RST_PULSE_WIDTH__SHIFT 0x17
509 #define CC_RCU_FUSES__GPU_DIS_MASK 0x2
510 #define CC_RCU_FUSES__GPU_DIS__SHIFT 0x1
511 #define CC_RCU_FUSES__DEBUG_DISABLE_MASK 0x4
512 #define CC_RCU_FUSES__DEBUG_DISABLE__SHIFT 0x2
513 #define CC_RCU_FUSES__EFUSE_RD_DISABLE_MASK 0x10
514 #define CC_RCU_FUSES__EFUSE_RD_DISABLE__SHIFT 0x4
515 #define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS_MASK 0x20
516 #define CC_RCU_FUSES__CG_RST_GLB_REQ_DIS__SHIFT 0x5
517 #define CC_RCU_FUSES__DRV_RST_MODE_MASK 0x40
518 #define CC_RCU_FUSES__DRV_RST_MODE__SHIFT 0x6
519 #define CC_RCU_FUSES__ROM_DIS_MASK 0x80
520 #define CC_RCU_FUSES__ROM_DIS__SHIFT 0x7
521 #define CC_RCU_FUSES__JPC_REP_DISABLE_MASK 0x100
522 #define CC_RCU_FUSES__JPC_REP_DISABLE__SHIFT 0x8
523 #define CC_RCU_FUSES__RCU_BREAK_POINT1_MASK 0x200
524 #define CC_RCU_FUSES__RCU_BREAK_POINT1__SHIFT 0x9
525 #define CC_RCU_FUSES__RCU_BREAK_POINT2_MASK 0x400
526 #define CC_RCU_FUSES__RCU_BREAK_POINT2__SHIFT 0xa
527 #define CC_RCU_FUSES__PHY_FUSE_VALID_MASK 0x4000
528 #define CC_RCU_FUSES__PHY_FUSE_VALID__SHIFT 0xe
529 #define CC_RCU_FUSES__SMU_IOC_MST_DISABLE_MASK 0x8000
530 #define CC_RCU_FUSES__SMU_IOC_MST_DISABLE__SHIFT 0xf
531 #define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE_MASK 0x10000
532 #define CC_RCU_FUSES__FCH_LOCKOUT_ENABLE__SHIFT 0x10
533 #define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE_MASK 0x20000
534 #define CC_RCU_FUSES__FCH_XFIRE_FILTER_ENABLE__SHIFT 0x11
535 #define CC_RCU_FUSES__XFIRE_DISABLE_MASK 0x40000
536 #define CC_RCU_FUSES__XFIRE_DISABLE__SHIFT 0x12
537 #define CC_RCU_FUSES__SAMU_FUSE_DISABLE_MASK 0x80000
538 #define CC_RCU_FUSES__SAMU_FUSE_DISABLE__SHIFT 0x13
539 #define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE_MASK 0x100000
540 #define CC_RCU_FUSES__BIF_RST_POLLING_DISABLE__SHIFT 0x14
541 #define CC_RCU_FUSES__MEM_HARDREP_EN_MASK 0x400000
542 #define CC_RCU_FUSES__MEM_HARDREP_EN__SHIFT 0x16
543 #define CC_RCU_FUSES__PCIE_INIT_DISABLE_MASK 0x800000
544 #define CC_RCU_FUSES__PCIE_INIT_DISABLE__SHIFT 0x17
545 #define CC_RCU_FUSES__DSMU_DISABLE_MASK 0x1000000
546 #define CC_RCU_FUSES__DSMU_DISABLE__SHIFT 0x18
547 #define CC_RCU_FUSES__RCU_SPARE_MASK 0x7e000000
548 #define CC_RCU_FUSES__RCU_SPARE__SHIFT 0x19
549 #define CC_RCU_FUSES__PSP_ENABLE_MASK 0x80000000
550 #define CC_RCU_FUSES__PSP_ENABLE__SHIFT 0x1f
551 #define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE_MASK 0x2
552 #define CC_SMU_MISC_FUSES__IOMMU_V2_DISABLE__SHIFT 0x1
553 #define CC_SMU_MISC_FUSES__MinSClkDid_MASK 0x1fc
554 #define CC_SMU_MISC_FUSES__MinSClkDid__SHIFT 0x2
555 #define CC_SMU_MISC_FUSES__MISC_SPARE_MASK 0x600
556 #define CC_SMU_MISC_FUSES__MISC_SPARE__SHIFT 0x9
557 #define CC_SMU_MISC_FUSES__PostResetGnbClkDid_MASK 0x3f800
558 #define CC_SMU_MISC_FUSES__PostResetGnbClkDid__SHIFT 0xb
559 #define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half_MASK 0x40000
560 #define CC_SMU_MISC_FUSES__L2IMU_tn2_dtc_half__SHIFT 0x12
561 #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half_MASK 0x80000
562 #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_half__SHIFT 0x13
563 #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half_MASK 0x100000
564 #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_half__SHIFT 0x14
565 #define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half_MASK 0x200000
566 #define CC_SMU_MISC_FUSES__L2IMU_tn2_pdc_half__SHIFT 0x15
567 #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis_MASK 0x400000
568 #define CC_SMU_MISC_FUSES__L2IMU_tn2_ptc_dis__SHIFT 0x16
569 #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis_MASK 0x800000
570 #define CC_SMU_MISC_FUSES__L2IMU_tn2_itc_dis__SHIFT 0x17
571 #define CC_SMU_MISC_FUSES__VCE_DISABLE_MASK 0x8000000
572 #define CC_SMU_MISC_FUSES__VCE_DISABLE__SHIFT 0x1b
573 #define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE_MASK 0x10000000
574 #define CC_SMU_MISC_FUSES__IOC_IOMMU_DISABLE__SHIFT 0x1c
575 #define CC_SMU_MISC_FUSES__GNB_SPARE_MASK 0x60000000
576 #define CC_SMU_MISC_FUSES__GNB_SPARE__SHIFT 0x1d
577 #define CC_SCLK_VID_FUSES__SClkVid0_MASK 0xff
578 #define CC_SCLK_VID_FUSES__SClkVid0__SHIFT 0x0
579 #define CC_SCLK_VID_FUSES__SClkVid1_MASK 0xff00
580 #define CC_SCLK_VID_FUSES__SClkVid1__SHIFT 0x8
581 #define CC_SCLK_VID_FUSES__SClkVid2_MASK 0xff0000
582 #define CC_SCLK_VID_FUSES__SClkVid2__SHIFT 0x10
583 #define CC_SCLK_VID_FUSES__SClkVid3_MASK 0xff000000
584 #define CC_SCLK_VID_FUSES__SClkVid3__SHIFT 0x18
585 #define CC_GIO_IOCCFG_FUSES__NB_REV_ID_MASK 0x7fe
586 #define CC_GIO_IOCCFG_FUSES__NB_REV_ID__SHIFT 0x1
587 #define CC_GIO_IOC_FUSES__IOC_FUSES_MASK 0x3fffe
588 #define CC_GIO_IOC_FUSES__IOC_FUSES__SHIFT 0x1
589 #define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2_MASK 0x3e
590 #define CC_SMU_TST_EFUSE1_MISC__RF_RM_6_2__SHIFT 0x1
591 #define CC_SMU_TST_EFUSE1_MISC__RME_MASK 0x40
592 #define CC_SMU_TST_EFUSE1_MISC__RME__SHIFT 0x6
593 #define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE_MASK 0x80
594 #define CC_SMU_TST_EFUSE1_MISC__MBIST_DISABLE__SHIFT 0x7
595 #define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE_MASK 0x100
596 #define CC_SMU_TST_EFUSE1_MISC__HARD_REPAIR_DISABLE__SHIFT 0x8
597 #define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE_MASK 0x200
598 #define CC_SMU_TST_EFUSE1_MISC__SOFT_REPAIR_DISABLE__SHIFT 0x9
599 #define CC_SMU_TST_EFUSE1_MISC__GPU_DIS_MASK 0x400
600 #define CC_SMU_TST_EFUSE1_MISC__GPU_DIS__SHIFT 0xa
601 #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE_MASK 0x800
602 #define CC_SMU_TST_EFUSE1_MISC__SMS_PWRDWN_DISABLE__SHIFT 0xb
603 #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA_MASK 0x1000
604 #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISA__SHIFT 0xc
605 #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB_MASK 0x2000
606 #define CC_SMU_TST_EFUSE1_MISC__CRBBMP1500_DISB__SHIFT 0xd
607 #define CC_SMU_TST_EFUSE1_MISC__RM_RF8_MASK 0x4000
608 #define CC_SMU_TST_EFUSE1_MISC__RM_RF8__SHIFT 0xe
609 #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1_MASK 0x400000
610 #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE1__SHIFT 0x16
611 #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2_MASK 0x800000
612 #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE2__SHIFT 0x17
613 #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3_MASK 0x1000000
614 #define CC_SMU_TST_EFUSE1_MISC__DFT_SPARE3__SHIFT 0x18
615 #define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE_MASK 0x2000000
616 #define CC_SMU_TST_EFUSE1_MISC__VCE_DISABLE__SHIFT 0x19
617 #define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE_MASK 0x4000000
618 #define CC_SMU_TST_EFUSE1_MISC__DCE_SCAN_DISABLE__SHIFT 0x1a
619 #define CC_TST_ID_STRAPS__DEVICE_ID_MASK 0xffff0
620 #define CC_TST_ID_STRAPS__DEVICE_ID__SHIFT 0x4
621 #define CC_TST_ID_STRAPS__MAJOR_REV_ID_MASK 0xf00000
622 #define CC_TST_ID_STRAPS__MAJOR_REV_ID__SHIFT 0x14
623 #define CC_TST_ID_STRAPS__MINOR_REV_ID_MASK 0xf000000
624 #define CC_TST_ID_STRAPS__MINOR_REV_ID__SHIFT 0x18
625 #define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT_MASK 0x2
626 #define CC_FCTRL_FUSES__EXT_EFUSE_MACRO_PRESENT__SHIFT 0x1
627 #define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ_MASK 0xffffffff
628 #define SMU_MAIN_PLL_OP_FREQ__PLL_OP_FREQ__SHIFT 0x0
629 #define SMU_STATUS__SMU_DONE_MASK 0x1
630 #define SMU_STATUS__SMU_DONE__SHIFT 0x0
631 #define SMU_STATUS__SMU_PASS_MASK 0x2
632 #define SMU_STATUS__SMU_PASS__SHIFT 0x1
633 #define SMU_FIRMWARE__SMU_IN_PROG_MASK 0x1
634 #define SMU_FIRMWARE__SMU_IN_PROG__SHIFT 0x0
635 #define SMU_FIRMWARE__SMU_RD_DONE_MASK 0x6
636 #define SMU_FIRMWARE__SMU_RD_DONE__SHIFT 0x1
637 #define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN_MASK 0x8
638 #define SMU_FIRMWARE__SMU_SRAM_RD_BLOCK_EN__SHIFT 0x3
639 #define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN_MASK 0x10
640 #define SMU_FIRMWARE__SMU_SRAM_WR_BLOCK_EN__SHIFT 0x4
641 #define SMU_FIRMWARE__SMU_counter_MASK 0xf00
642 #define SMU_FIRMWARE__SMU_counter__SHIFT 0x8
643 #define SMU_FIRMWARE__SMU_MODE_MASK 0x10000
644 #define SMU_FIRMWARE__SMU_MODE__SHIFT 0x10
645 #define SMU_FIRMWARE__SMU_SEL_MASK 0x20000
646 #define SMU_FIRMWARE__SMU_SEL__SHIFT 0x11
647 #define SMU_INPUT_DATA__START_ADDR_MASK 0x7fffffff
648 #define SMU_INPUT_DATA__START_ADDR__SHIFT 0x0
649 #define SMU_INPUT_DATA__AUTO_START_MASK 0x80000000
650 #define SMU_INPUT_DATA__AUTO_START__SHIFT 0x1f
651 #define SMU_EFUSE_0__EFUSE_DATA_MASK 0xffffffff
652 #define SMU_EFUSE_0__EFUSE_DATA__SHIFT 0x0
653 #define DPM_TABLE_1__SystemFlags_MASK 0xffffffff
654 #define DPM_TABLE_1__SystemFlags__SHIFT 0x0
655 #define DPM_TABLE_2__GraphicsPIDController_Ki_MASK 0xffffffff
656 #define DPM_TABLE_2__GraphicsPIDController_Ki__SHIFT 0x0
657 #define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim_MASK 0xffffffff
658 #define DPM_TABLE_3__GraphicsPIDController_LFWindupUpperLim__SHIFT 0x0
659 #define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim_MASK 0xffffffff
660 #define DPM_TABLE_4__GraphicsPIDController_LFWindupLowerLim__SHIFT 0x0
661 #define DPM_TABLE_5__GraphicsPIDController_StatePrecision_MASK 0xffffffff
662 #define DPM_TABLE_5__GraphicsPIDController_StatePrecision__SHIFT 0x0
663 #define DPM_TABLE_6__GraphicsPIDController_LfPrecision_MASK 0xffffffff
664 #define DPM_TABLE_6__GraphicsPIDController_LfPrecision__SHIFT 0x0
665 #define DPM_TABLE_7__GraphicsPIDController_LfOffset_MASK 0xffffffff
666 #define DPM_TABLE_7__GraphicsPIDController_LfOffset__SHIFT 0x0
667 #define DPM_TABLE_8__GraphicsPIDController_MaxState_MASK 0xffffffff
668 #define DPM_TABLE_8__GraphicsPIDController_MaxState__SHIFT 0x0
669 #define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction_MASK 0xffffffff
670 #define DPM_TABLE_9__GraphicsPIDController_MaxLfFraction__SHIFT 0x0
671 #define DPM_TABLE_10__GraphicsPIDController_StateShift_MASK 0xffffffff
672 #define DPM_TABLE_10__GraphicsPIDController_StateShift__SHIFT 0x0
673 #define DPM_TABLE_11__GioPIDController_Ki_MASK 0xffffffff
674 #define DPM_TABLE_11__GioPIDController_Ki__SHIFT 0x0
675 #define DPM_TABLE_12__GioPIDController_LFWindupUpperLim_MASK 0xffffffff
676 #define DPM_TABLE_12__GioPIDController_LFWindupUpperLim__SHIFT 0x0
677 #define DPM_TABLE_13__GioPIDController_LFWindupLowerLim_MASK 0xffffffff
678 #define DPM_TABLE_13__GioPIDController_LFWindupLowerLim__SHIFT 0x0
679 #define DPM_TABLE_14__GioPIDController_StatePrecision_MASK 0xffffffff
680 #define DPM_TABLE_14__GioPIDController_StatePrecision__SHIFT 0x0
681 #define DPM_TABLE_15__GioPIDController_LfPrecision_MASK 0xffffffff
682 #define DPM_TABLE_15__GioPIDController_LfPrecision__SHIFT 0x0
683 #define DPM_TABLE_16__GioPIDController_LfOffset_MASK 0xffffffff
684 #define DPM_TABLE_16__GioPIDController_LfOffset__SHIFT 0x0
685 #define DPM_TABLE_17__GioPIDController_MaxState_MASK 0xffffffff
686 #define DPM_TABLE_17__GioPIDController_MaxState__SHIFT 0x0
687 #define DPM_TABLE_18__GioPIDController_MaxLfFraction_MASK 0xffffffff
688 #define DPM_TABLE_18__GioPIDController_MaxLfFraction__SHIFT 0x0
689 #define DPM_TABLE_19__GioPIDController_StateShift_MASK 0xffffffff
690 #define DPM_TABLE_19__GioPIDController_StateShift__SHIFT 0x0
691 #define DPM_TABLE_20__VceLevelCount_MASK 0xff
692 #define DPM_TABLE_20__VceLevelCount__SHIFT 0x0
693 #define DPM_TABLE_20__UvdLevelCount_MASK 0xff00
694 #define DPM_TABLE_20__UvdLevelCount__SHIFT 0x8
695 #define DPM_TABLE_20__GIOLevelCount_MASK 0xff0000
696 #define DPM_TABLE_20__GIOLevelCount__SHIFT 0x10
697 #define DPM_TABLE_20__GraphicsDpmLevelCount_MASK 0xff000000
698 #define DPM_TABLE_20__GraphicsDpmLevelCount__SHIFT 0x18
699 #define DPM_TABLE_21__FpsHighThreshold_MASK 0xffff
700 #define DPM_TABLE_21__FpsHighThreshold__SHIFT 0x0
701 #define DPM_TABLE_21__SamuLevelCount_MASK 0xff0000
702 #define DPM_TABLE_21__SamuLevelCount__SHIFT 0x10
703 #define DPM_TABLE_21__AcpLevelCount_MASK 0xff000000
704 #define DPM_TABLE_21__AcpLevelCount__SHIFT 0x18
705 #define DPM_TABLE_22__GraphicsLevel_0_MinVddNb_MASK 0xffffffff
706 #define DPM_TABLE_22__GraphicsLevel_0_MinVddNb__SHIFT 0x0
707 #define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency_MASK 0xffffffff
708 #define DPM_TABLE_23__GraphicsLevel_0_SclkFrequency__SHIFT 0x0
709 #define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel_MASK 0xffff
710 #define DPM_TABLE_24__GraphicsLevel_0_ActivityLevel__SHIFT 0x0
711 #define DPM_TABLE_24__GraphicsLevel_0_VidOffset_MASK 0xff0000
712 #define DPM_TABLE_24__GraphicsLevel_0_VidOffset__SHIFT 0x10
713 #define DPM_TABLE_24__GraphicsLevel_0_Vid_MASK 0xff000000
714 #define DPM_TABLE_24__GraphicsLevel_0_Vid__SHIFT 0x18
715 #define DPM_TABLE_25__GraphicsLevel_0_SclkDid_MASK 0xff
716 #define DPM_TABLE_25__GraphicsLevel_0_SclkDid__SHIFT 0x0
717 #define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1_MASK 0xff00
718 #define DPM_TABLE_25__GraphicsLevel_0_ForceNbPs1__SHIFT 0x8
719 #define DPM_TABLE_25__GraphicsLevel_0_GnbSlow_MASK 0xff0000
720 #define DPM_TABLE_25__GraphicsLevel_0_GnbSlow__SHIFT 0x10
721 #define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle_MASK 0xff000000
722 #define DPM_TABLE_25__GraphicsLevel_0_PowerThrottle__SHIFT 0x18
723 #define DPM_TABLE_26__GraphicsLevel_0_UpHyst_MASK 0xff
724 #define DPM_TABLE_26__GraphicsLevel_0_UpHyst__SHIFT 0x0
725 #define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle_MASK 0xff00
726 #define DPM_TABLE_26__GraphicsLevel_0_EnabledForThrottle__SHIFT 0x8
727 #define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity_MASK 0xff0000
728 #define DPM_TABLE_26__GraphicsLevel_0_EnabledForActivity__SHIFT 0x10
729 #define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark_MASK 0xff000000
730 #define DPM_TABLE_26__GraphicsLevel_0_DisplayWatermark__SHIFT 0x18
731 #define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl_MASK 0xff
732 #define DPM_TABLE_27__GraphicsLevel_0_ClkBypassCntl__SHIFT 0x0
733 #define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId_MASK 0xff00
734 #define DPM_TABLE_27__GraphicsLevel_0_DeepSleepDivId__SHIFT 0x8
735 #define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst_MASK 0xff0000
736 #define DPM_TABLE_27__GraphicsLevel_0_VoltageDownHyst__SHIFT 0x10
737 #define DPM_TABLE_27__GraphicsLevel_0_DownHyst_MASK 0xff000000
738 #define DPM_TABLE_27__GraphicsLevel_0_DownHyst__SHIFT 0x18
739 #define DPM_TABLE_28__GraphicsLevel_0_reserved_MASK 0xffffffff
740 #define DPM_TABLE_28__GraphicsLevel_0_reserved__SHIFT 0x0
741 #define DPM_TABLE_29__GraphicsLevel_1_MinVddNb_MASK 0xffffffff
742 #define DPM_TABLE_29__GraphicsLevel_1_MinVddNb__SHIFT 0x0
743 #define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency_MASK 0xffffffff
744 #define DPM_TABLE_30__GraphicsLevel_1_SclkFrequency__SHIFT 0x0
745 #define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel_MASK 0xffff
746 #define DPM_TABLE_31__GraphicsLevel_1_ActivityLevel__SHIFT 0x0
747 #define DPM_TABLE_31__GraphicsLevel_1_VidOffset_MASK 0xff0000
748 #define DPM_TABLE_31__GraphicsLevel_1_VidOffset__SHIFT 0x10
749 #define DPM_TABLE_31__GraphicsLevel_1_Vid_MASK 0xff000000
750 #define DPM_TABLE_31__GraphicsLevel_1_Vid__SHIFT 0x18
751 #define DPM_TABLE_32__GraphicsLevel_1_SclkDid_MASK 0xff
752 #define DPM_TABLE_32__GraphicsLevel_1_SclkDid__SHIFT 0x0
753 #define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1_MASK 0xff00
754 #define DPM_TABLE_32__GraphicsLevel_1_ForceNbPs1__SHIFT 0x8
755 #define DPM_TABLE_32__GraphicsLevel_1_GnbSlow_MASK 0xff0000
756 #define DPM_TABLE_32__GraphicsLevel_1_GnbSlow__SHIFT 0x10
757 #define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle_MASK 0xff000000
758 #define DPM_TABLE_32__GraphicsLevel_1_PowerThrottle__SHIFT 0x18
759 #define DPM_TABLE_33__GraphicsLevel_1_UpHyst_MASK 0xff
760 #define DPM_TABLE_33__GraphicsLevel_1_UpHyst__SHIFT 0x0
761 #define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle_MASK 0xff00
762 #define DPM_TABLE_33__GraphicsLevel_1_EnabledForThrottle__SHIFT 0x8
763 #define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity_MASK 0xff0000
764 #define DPM_TABLE_33__GraphicsLevel_1_EnabledForActivity__SHIFT 0x10
765 #define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark_MASK 0xff000000
766 #define DPM_TABLE_33__GraphicsLevel_1_DisplayWatermark__SHIFT 0x18
767 #define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl_MASK 0xff
768 #define DPM_TABLE_34__GraphicsLevel_1_ClkBypassCntl__SHIFT 0x0
769 #define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId_MASK 0xff00
770 #define DPM_TABLE_34__GraphicsLevel_1_DeepSleepDivId__SHIFT 0x8
771 #define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst_MASK 0xff0000
772 #define DPM_TABLE_34__GraphicsLevel_1_VoltageDownHyst__SHIFT 0x10
773 #define DPM_TABLE_34__GraphicsLevel_1_DownHyst_MASK 0xff000000
774 #define DPM_TABLE_34__GraphicsLevel_1_DownHyst__SHIFT 0x18
775 #define DPM_TABLE_35__GraphicsLevel_1_reserved_MASK 0xffffffff
776 #define DPM_TABLE_35__GraphicsLevel_1_reserved__SHIFT 0x0
777 #define DPM_TABLE_36__GraphicsLevel_2_MinVddNb_MASK 0xffffffff
778 #define DPM_TABLE_36__GraphicsLevel_2_MinVddNb__SHIFT 0x0
779 #define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency_MASK 0xffffffff
780 #define DPM_TABLE_37__GraphicsLevel_2_SclkFrequency__SHIFT 0x0
781 #define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel_MASK 0xffff
782 #define DPM_TABLE_38__GraphicsLevel_2_ActivityLevel__SHIFT 0x0
783 #define DPM_TABLE_38__GraphicsLevel_2_VidOffset_MASK 0xff0000
784 #define DPM_TABLE_38__GraphicsLevel_2_VidOffset__SHIFT 0x10
785 #define DPM_TABLE_38__GraphicsLevel_2_Vid_MASK 0xff000000
786 #define DPM_TABLE_38__GraphicsLevel_2_Vid__SHIFT 0x18
787 #define DPM_TABLE_39__GraphicsLevel_2_SclkDid_MASK 0xff
788 #define DPM_TABLE_39__GraphicsLevel_2_SclkDid__SHIFT 0x0
789 #define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1_MASK 0xff00
790 #define DPM_TABLE_39__GraphicsLevel_2_ForceNbPs1__SHIFT 0x8
791 #define DPM_TABLE_39__GraphicsLevel_2_GnbSlow_MASK 0xff0000
792 #define DPM_TABLE_39__GraphicsLevel_2_GnbSlow__SHIFT 0x10
793 #define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle_MASK 0xff000000
794 #define DPM_TABLE_39__GraphicsLevel_2_PowerThrottle__SHIFT 0x18
795 #define DPM_TABLE_40__GraphicsLevel_2_UpHyst_MASK 0xff
796 #define DPM_TABLE_40__GraphicsLevel_2_UpHyst__SHIFT 0x0
797 #define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle_MASK 0xff00
798 #define DPM_TABLE_40__GraphicsLevel_2_EnabledForThrottle__SHIFT 0x8
799 #define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity_MASK 0xff0000
800 #define DPM_TABLE_40__GraphicsLevel_2_EnabledForActivity__SHIFT 0x10
801 #define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark_MASK 0xff000000
802 #define DPM_TABLE_40__GraphicsLevel_2_DisplayWatermark__SHIFT 0x18
803 #define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl_MASK 0xff
804 #define DPM_TABLE_41__GraphicsLevel_2_ClkBypassCntl__SHIFT 0x0
805 #define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId_MASK 0xff00
806 #define DPM_TABLE_41__GraphicsLevel_2_DeepSleepDivId__SHIFT 0x8
807 #define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst_MASK 0xff0000
808 #define DPM_TABLE_41__GraphicsLevel_2_VoltageDownHyst__SHIFT 0x10
809 #define DPM_TABLE_41__GraphicsLevel_2_DownHyst_MASK 0xff000000
810 #define DPM_TABLE_41__GraphicsLevel_2_DownHyst__SHIFT 0x18
811 #define DPM_TABLE_42__GraphicsLevel_2_reserved_MASK 0xffffffff
812 #define DPM_TABLE_42__GraphicsLevel_2_reserved__SHIFT 0x0
813 #define DPM_TABLE_43__GraphicsLevel_3_MinVddNb_MASK 0xffffffff
814 #define DPM_TABLE_43__GraphicsLevel_3_MinVddNb__SHIFT 0x0
815 #define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency_MASK 0xffffffff
816 #define DPM_TABLE_44__GraphicsLevel_3_SclkFrequency__SHIFT 0x0
817 #define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel_MASK 0xffff
818 #define DPM_TABLE_45__GraphicsLevel_3_ActivityLevel__SHIFT 0x0
819 #define DPM_TABLE_45__GraphicsLevel_3_VidOffset_MASK 0xff0000
820 #define DPM_TABLE_45__GraphicsLevel_3_VidOffset__SHIFT 0x10
821 #define DPM_TABLE_45__GraphicsLevel_3_Vid_MASK 0xff000000
822 #define DPM_TABLE_45__GraphicsLevel_3_Vid__SHIFT 0x18
823 #define DPM_TABLE_46__GraphicsLevel_3_SclkDid_MASK 0xff
824 #define DPM_TABLE_46__GraphicsLevel_3_SclkDid__SHIFT 0x0
825 #define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1_MASK 0xff00
826 #define DPM_TABLE_46__GraphicsLevel_3_ForceNbPs1__SHIFT 0x8
827 #define DPM_TABLE_46__GraphicsLevel_3_GnbSlow_MASK 0xff0000
828 #define DPM_TABLE_46__GraphicsLevel_3_GnbSlow__SHIFT 0x10
829 #define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle_MASK 0xff000000
830 #define DPM_TABLE_46__GraphicsLevel_3_PowerThrottle__SHIFT 0x18
831 #define DPM_TABLE_47__GraphicsLevel_3_UpHyst_MASK 0xff
832 #define DPM_TABLE_47__GraphicsLevel_3_UpHyst__SHIFT 0x0
833 #define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle_MASK 0xff00
834 #define DPM_TABLE_47__GraphicsLevel_3_EnabledForThrottle__SHIFT 0x8
835 #define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity_MASK 0xff0000
836 #define DPM_TABLE_47__GraphicsLevel_3_EnabledForActivity__SHIFT 0x10
837 #define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark_MASK 0xff000000
838 #define DPM_TABLE_47__GraphicsLevel_3_DisplayWatermark__SHIFT 0x18
839 #define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl_MASK 0xff
840 #define DPM_TABLE_48__GraphicsLevel_3_ClkBypassCntl__SHIFT 0x0
841 #define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId_MASK 0xff00
842 #define DPM_TABLE_48__GraphicsLevel_3_DeepSleepDivId__SHIFT 0x8
843 #define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst_MASK 0xff0000
844 #define DPM_TABLE_48__GraphicsLevel_3_VoltageDownHyst__SHIFT 0x10
845 #define DPM_TABLE_48__GraphicsLevel_3_DownHyst_MASK 0xff000000
846 #define DPM_TABLE_48__GraphicsLevel_3_DownHyst__SHIFT 0x18
847 #define DPM_TABLE_49__GraphicsLevel_3_reserved_MASK 0xffffffff
848 #define DPM_TABLE_49__GraphicsLevel_3_reserved__SHIFT 0x0
849 #define DPM_TABLE_50__GraphicsLevel_4_MinVddNb_MASK 0xffffffff
850 #define DPM_TABLE_50__GraphicsLevel_4_MinVddNb__SHIFT 0x0
851 #define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency_MASK 0xffffffff
852 #define DPM_TABLE_51__GraphicsLevel_4_SclkFrequency__SHIFT 0x0
853 #define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel_MASK 0xffff
854 #define DPM_TABLE_52__GraphicsLevel_4_ActivityLevel__SHIFT 0x0
855 #define DPM_TABLE_52__GraphicsLevel_4_VidOffset_MASK 0xff0000
856 #define DPM_TABLE_52__GraphicsLevel_4_VidOffset__SHIFT 0x10
857 #define DPM_TABLE_52__GraphicsLevel_4_Vid_MASK 0xff000000
858 #define DPM_TABLE_52__GraphicsLevel_4_Vid__SHIFT 0x18
859 #define DPM_TABLE_53__GraphicsLevel_4_SclkDid_MASK 0xff
860 #define DPM_TABLE_53__GraphicsLevel_4_SclkDid__SHIFT 0x0
861 #define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1_MASK 0xff00
862 #define DPM_TABLE_53__GraphicsLevel_4_ForceNbPs1__SHIFT 0x8
863 #define DPM_TABLE_53__GraphicsLevel_4_GnbSlow_MASK 0xff0000
864 #define DPM_TABLE_53__GraphicsLevel_4_GnbSlow__SHIFT 0x10
865 #define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle_MASK 0xff000000
866 #define DPM_TABLE_53__GraphicsLevel_4_PowerThrottle__SHIFT 0x18
867 #define DPM_TABLE_54__GraphicsLevel_4_UpHyst_MASK 0xff
868 #define DPM_TABLE_54__GraphicsLevel_4_UpHyst__SHIFT 0x0
869 #define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle_MASK 0xff00
870 #define DPM_TABLE_54__GraphicsLevel_4_EnabledForThrottle__SHIFT 0x8
871 #define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity_MASK 0xff0000
872 #define DPM_TABLE_54__GraphicsLevel_4_EnabledForActivity__SHIFT 0x10
873 #define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark_MASK 0xff000000
874 #define DPM_TABLE_54__GraphicsLevel_4_DisplayWatermark__SHIFT 0x18
875 #define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl_MASK 0xff
876 #define DPM_TABLE_55__GraphicsLevel_4_ClkBypassCntl__SHIFT 0x0
877 #define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId_MASK 0xff00
878 #define DPM_TABLE_55__GraphicsLevel_4_DeepSleepDivId__SHIFT 0x8
879 #define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst_MASK 0xff0000
880 #define DPM_TABLE_55__GraphicsLevel_4_VoltageDownHyst__SHIFT 0x10
881 #define DPM_TABLE_55__GraphicsLevel_4_DownHyst_MASK 0xff000000
882 #define DPM_TABLE_55__GraphicsLevel_4_DownHyst__SHIFT 0x18
883 #define DPM_TABLE_56__GraphicsLevel_4_reserved_MASK 0xffffffff
884 #define DPM_TABLE_56__GraphicsLevel_4_reserved__SHIFT 0x0
885 #define DPM_TABLE_57__GraphicsLevel_5_MinVddNb_MASK 0xffffffff
886 #define DPM_TABLE_57__GraphicsLevel_5_MinVddNb__SHIFT 0x0
887 #define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency_MASK 0xffffffff
888 #define DPM_TABLE_58__GraphicsLevel_5_SclkFrequency__SHIFT 0x0
889 #define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel_MASK 0xffff
890 #define DPM_TABLE_59__GraphicsLevel_5_ActivityLevel__SHIFT 0x0
891 #define DPM_TABLE_59__GraphicsLevel_5_VidOffset_MASK 0xff0000
892 #define DPM_TABLE_59__GraphicsLevel_5_VidOffset__SHIFT 0x10
893 #define DPM_TABLE_59__GraphicsLevel_5_Vid_MASK 0xff000000
894 #define DPM_TABLE_59__GraphicsLevel_5_Vid__SHIFT 0x18
895 #define DPM_TABLE_60__GraphicsLevel_5_SclkDid_MASK 0xff
896 #define DPM_TABLE_60__GraphicsLevel_5_SclkDid__SHIFT 0x0
897 #define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1_MASK 0xff00
898 #define DPM_TABLE_60__GraphicsLevel_5_ForceNbPs1__SHIFT 0x8
899 #define DPM_TABLE_60__GraphicsLevel_5_GnbSlow_MASK 0xff0000
900 #define DPM_TABLE_60__GraphicsLevel_5_GnbSlow__SHIFT 0x10
901 #define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle_MASK 0xff000000
902 #define DPM_TABLE_60__GraphicsLevel_5_PowerThrottle__SHIFT 0x18
903 #define DPM_TABLE_61__GraphicsLevel_5_UpHyst_MASK 0xff
904 #define DPM_TABLE_61__GraphicsLevel_5_UpHyst__SHIFT 0x0
905 #define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle_MASK 0xff00
906 #define DPM_TABLE_61__GraphicsLevel_5_EnabledForThrottle__SHIFT 0x8
907 #define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity_MASK 0xff0000
908 #define DPM_TABLE_61__GraphicsLevel_5_EnabledForActivity__SHIFT 0x10
909 #define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark_MASK 0xff000000
910 #define DPM_TABLE_61__GraphicsLevel_5_DisplayWatermark__SHIFT 0x18
911 #define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl_MASK 0xff
912 #define DPM_TABLE_62__GraphicsLevel_5_ClkBypassCntl__SHIFT 0x0
913 #define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId_MASK 0xff00
914 #define DPM_TABLE_62__GraphicsLevel_5_DeepSleepDivId__SHIFT 0x8
915 #define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst_MASK 0xff0000
916 #define DPM_TABLE_62__GraphicsLevel_5_VoltageDownHyst__SHIFT 0x10
917 #define DPM_TABLE_62__GraphicsLevel_5_DownHyst_MASK 0xff000000
918 #define DPM_TABLE_62__GraphicsLevel_5_DownHyst__SHIFT 0x18
919 #define DPM_TABLE_63__GraphicsLevel_5_reserved_MASK 0xffffffff
920 #define DPM_TABLE_63__GraphicsLevel_5_reserved__SHIFT 0x0
921 #define DPM_TABLE_64__GraphicsLevel_6_MinVddNb_MASK 0xffffffff
922 #define DPM_TABLE_64__GraphicsLevel_6_MinVddNb__SHIFT 0x0
923 #define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency_MASK 0xffffffff
924 #define DPM_TABLE_65__GraphicsLevel_6_SclkFrequency__SHIFT 0x0
925 #define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel_MASK 0xffff
926 #define DPM_TABLE_66__GraphicsLevel_6_ActivityLevel__SHIFT 0x0
927 #define DPM_TABLE_66__GraphicsLevel_6_VidOffset_MASK 0xff0000
928 #define DPM_TABLE_66__GraphicsLevel_6_VidOffset__SHIFT 0x10
929 #define DPM_TABLE_66__GraphicsLevel_6_Vid_MASK 0xff000000
930 #define DPM_TABLE_66__GraphicsLevel_6_Vid__SHIFT 0x18
931 #define DPM_TABLE_67__GraphicsLevel_6_SclkDid_MASK 0xff
932 #define DPM_TABLE_67__GraphicsLevel_6_SclkDid__SHIFT 0x0
933 #define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1_MASK 0xff00
934 #define DPM_TABLE_67__GraphicsLevel_6_ForceNbPs1__SHIFT 0x8
935 #define DPM_TABLE_67__GraphicsLevel_6_GnbSlow_MASK 0xff0000
936 #define DPM_TABLE_67__GraphicsLevel_6_GnbSlow__SHIFT 0x10
937 #define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle_MASK 0xff000000
938 #define DPM_TABLE_67__GraphicsLevel_6_PowerThrottle__SHIFT 0x18
939 #define DPM_TABLE_68__GraphicsLevel_6_UpHyst_MASK 0xff
940 #define DPM_TABLE_68__GraphicsLevel_6_UpHyst__SHIFT 0x0
941 #define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle_MASK 0xff00
942 #define DPM_TABLE_68__GraphicsLevel_6_EnabledForThrottle__SHIFT 0x8
943 #define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity_MASK 0xff0000
944 #define DPM_TABLE_68__GraphicsLevel_6_EnabledForActivity__SHIFT 0x10
945 #define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark_MASK 0xff000000
946 #define DPM_TABLE_68__GraphicsLevel_6_DisplayWatermark__SHIFT 0x18
947 #define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl_MASK 0xff
948 #define DPM_TABLE_69__GraphicsLevel_6_ClkBypassCntl__SHIFT 0x0
949 #define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId_MASK 0xff00
950 #define DPM_TABLE_69__GraphicsLevel_6_DeepSleepDivId__SHIFT 0x8
951 #define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst_MASK 0xff0000
952 #define DPM_TABLE_69__GraphicsLevel_6_VoltageDownHyst__SHIFT 0x10
953 #define DPM_TABLE_69__GraphicsLevel_6_DownHyst_MASK 0xff000000
954 #define DPM_TABLE_69__GraphicsLevel_6_DownHyst__SHIFT 0x18
955 #define DPM_TABLE_70__GraphicsLevel_6_reserved_MASK 0xffffffff
956 #define DPM_TABLE_70__GraphicsLevel_6_reserved__SHIFT 0x0
957 #define DPM_TABLE_71__GraphicsLevel_7_MinVddNb_MASK 0xffffffff
958 #define DPM_TABLE_71__GraphicsLevel_7_MinVddNb__SHIFT 0x0
959 #define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency_MASK 0xffffffff
960 #define DPM_TABLE_72__GraphicsLevel_7_SclkFrequency__SHIFT 0x0
961 #define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel_MASK 0xffff
962 #define DPM_TABLE_73__GraphicsLevel_7_ActivityLevel__SHIFT 0x0
963 #define DPM_TABLE_73__GraphicsLevel_7_VidOffset_MASK 0xff0000
964 #define DPM_TABLE_73__GraphicsLevel_7_VidOffset__SHIFT 0x10
965 #define DPM_TABLE_73__GraphicsLevel_7_Vid_MASK 0xff000000
966 #define DPM_TABLE_73__GraphicsLevel_7_Vid__SHIFT 0x18
967 #define DPM_TABLE_74__GraphicsLevel_7_SclkDid_MASK 0xff
968 #define DPM_TABLE_74__GraphicsLevel_7_SclkDid__SHIFT 0x0
969 #define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1_MASK 0xff00
970 #define DPM_TABLE_74__GraphicsLevel_7_ForceNbPs1__SHIFT 0x8
971 #define DPM_TABLE_74__GraphicsLevel_7_GnbSlow_MASK 0xff0000
972 #define DPM_TABLE_74__GraphicsLevel_7_GnbSlow__SHIFT 0x10
973 #define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle_MASK 0xff000000
974 #define DPM_TABLE_74__GraphicsLevel_7_PowerThrottle__SHIFT 0x18
975 #define DPM_TABLE_75__GraphicsLevel_7_UpHyst_MASK 0xff
976 #define DPM_TABLE_75__GraphicsLevel_7_UpHyst__SHIFT 0x0
977 #define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle_MASK 0xff00
978 #define DPM_TABLE_75__GraphicsLevel_7_EnabledForThrottle__SHIFT 0x8
979 #define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity_MASK 0xff0000
980 #define DPM_TABLE_75__GraphicsLevel_7_EnabledForActivity__SHIFT 0x10
981 #define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark_MASK 0xff000000
982 #define DPM_TABLE_75__GraphicsLevel_7_DisplayWatermark__SHIFT 0x18
983 #define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl_MASK 0xff
984 #define DPM_TABLE_76__GraphicsLevel_7_ClkBypassCntl__SHIFT 0x0
985 #define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId_MASK 0xff00
986 #define DPM_TABLE_76__GraphicsLevel_7_DeepSleepDivId__SHIFT 0x8
987 #define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst_MASK 0xff0000
988 #define DPM_TABLE_76__GraphicsLevel_7_VoltageDownHyst__SHIFT 0x10
989 #define DPM_TABLE_76__GraphicsLevel_7_DownHyst_MASK 0xff000000
990 #define DPM_TABLE_76__GraphicsLevel_7_DownHyst__SHIFT 0x18
991 #define DPM_TABLE_77__GraphicsLevel_7_reserved_MASK 0xffffffff
992 #define DPM_TABLE_77__GraphicsLevel_7_reserved__SHIFT 0x0
993 #define DPM_TABLE_78__ACPILevel_Flags_MASK 0xffffffff
994 #define DPM_TABLE_78__ACPILevel_Flags__SHIFT 0x0
995 #define DPM_TABLE_79__ACPILevel_MinVddNb_MASK 0xffffffff
996 #define DPM_TABLE_79__ACPILevel_MinVddNb__SHIFT 0x0
997 #define DPM_TABLE_80__ACPILevel_SclkFrequency_MASK 0xffffffff
998 #define DPM_TABLE_80__ACPILevel_SclkFrequency__SHIFT 0x0
999 #define DPM_TABLE_81__ACPILevel_DisplayWatermark_MASK 0xff
1000 #define DPM_TABLE_81__ACPILevel_DisplayWatermark__SHIFT 0x0
1001 #define DPM_TABLE_81__ACPILevel_ForceNbPs1_MASK 0xff00
1002 #define DPM_TABLE_81__ACPILevel_ForceNbPs1__SHIFT 0x8
1003 #define DPM_TABLE_81__ACPILevel_GnbSlow_MASK 0xff0000
1004 #define DPM_TABLE_81__ACPILevel_GnbSlow__SHIFT 0x10
1005 #define DPM_TABLE_81__ACPILevel_SclkDid_MASK 0xff000000
1006 #define DPM_TABLE_81__ACPILevel_SclkDid__SHIFT 0x18
1007 #define DPM_TABLE_82__ACPILevel_padding_2_MASK 0xff
1008 #define DPM_TABLE_82__ACPILevel_padding_2__SHIFT 0x0
1009 #define DPM_TABLE_82__ACPILevel_padding_1_MASK 0xff00
1010 #define DPM_TABLE_82__ACPILevel_padding_1__SHIFT 0x8
1011 #define DPM_TABLE_82__ACPILevel_padding_0_MASK 0xff0000
1012 #define DPM_TABLE_82__ACPILevel_padding_0__SHIFT 0x10
1013 #define DPM_TABLE_82__ACPILevel_DeepSleepDivId_MASK 0xff000000
1014 #define DPM_TABLE_82__ACPILevel_DeepSleepDivId__SHIFT 0x18
1015 #define DPM_TABLE_83__UvdLevel_0_VclkFrequency_MASK 0xffffffff
1016 #define DPM_TABLE_83__UvdLevel_0_VclkFrequency__SHIFT 0x0
1017 #define DPM_TABLE_84__UvdLevel_0_DclkFrequency_MASK 0xffffffff
1018 #define DPM_TABLE_84__UvdLevel_0_DclkFrequency__SHIFT 0x0
1019 #define DPM_TABLE_85__UvdLevel_0_DclkDivider_MASK 0xff
1020 #define DPM_TABLE_85__UvdLevel_0_DclkDivider__SHIFT 0x0
1021 #define DPM_TABLE_85__UvdLevel_0_VclkDivider_MASK 0xff00
1022 #define DPM_TABLE_85__UvdLevel_0_VclkDivider__SHIFT 0x8
1023 #define DPM_TABLE_85__UvdLevel_0_MinVddNb_MASK 0xffff0000
1024 #define DPM_TABLE_85__UvdLevel_0_MinVddNb__SHIFT 0x10
1025 #define DPM_TABLE_86__UvdLevel_0_padding_1_MASK 0xff
1026 #define DPM_TABLE_86__UvdLevel_0_padding_1__SHIFT 0x0
1027 #define DPM_TABLE_86__UvdLevel_0_padding_0_MASK 0xff00
1028 #define DPM_TABLE_86__UvdLevel_0_padding_0__SHIFT 0x8
1029 #define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl_MASK 0xff0000
1030 #define DPM_TABLE_86__UvdLevel_0_DClkBypassCntl__SHIFT 0x10
1031 #define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl_MASK 0xff000000
1032 #define DPM_TABLE_86__UvdLevel_0_VClkBypassCntl__SHIFT 0x18
1033 #define DPM_TABLE_87__UvdLevel_1_VclkFrequency_MASK 0xffffffff
1034 #define DPM_TABLE_87__UvdLevel_1_VclkFrequency__SHIFT 0x0
1035 #define DPM_TABLE_88__UvdLevel_1_DclkFrequency_MASK 0xffffffff
1036 #define DPM_TABLE_88__UvdLevel_1_DclkFrequency__SHIFT 0x0
1037 #define DPM_TABLE_89__UvdLevel_1_DclkDivider_MASK 0xff
1038 #define DPM_TABLE_89__UvdLevel_1_DclkDivider__SHIFT 0x0
1039 #define DPM_TABLE_89__UvdLevel_1_VclkDivider_MASK 0xff00
1040 #define DPM_TABLE_89__UvdLevel_1_VclkDivider__SHIFT 0x8
1041 #define DPM_TABLE_89__UvdLevel_1_MinVddNb_MASK 0xffff0000
1042 #define DPM_TABLE_89__UvdLevel_1_MinVddNb__SHIFT 0x10
1043 #define DPM_TABLE_90__UvdLevel_1_padding_1_MASK 0xff
1044 #define DPM_TABLE_90__UvdLevel_1_padding_1__SHIFT 0x0
1045 #define DPM_TABLE_90__UvdLevel_1_padding_0_MASK 0xff00
1046 #define DPM_TABLE_90__UvdLevel_1_padding_0__SHIFT 0x8
1047 #define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl_MASK 0xff0000
1048 #define DPM_TABLE_90__UvdLevel_1_DClkBypassCntl__SHIFT 0x10
1049 #define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl_MASK 0xff000000
1050 #define DPM_TABLE_90__UvdLevel_1_VClkBypassCntl__SHIFT 0x18
1051 #define DPM_TABLE_91__UvdLevel_2_VclkFrequency_MASK 0xffffffff
1052 #define DPM_TABLE_91__UvdLevel_2_VclkFrequency__SHIFT 0x0
1053 #define DPM_TABLE_92__UvdLevel_2_DclkFrequency_MASK 0xffffffff
1054 #define DPM_TABLE_92__UvdLevel_2_DclkFrequency__SHIFT 0x0
1055 #define DPM_TABLE_93__UvdLevel_2_DclkDivider_MASK 0xff
1056 #define DPM_TABLE_93__UvdLevel_2_DclkDivider__SHIFT 0x0
1057 #define DPM_TABLE_93__UvdLevel_2_VclkDivider_MASK 0xff00
1058 #define DPM_TABLE_93__UvdLevel_2_VclkDivider__SHIFT 0x8
1059 #define DPM_TABLE_93__UvdLevel_2_MinVddNb_MASK 0xffff0000
1060 #define DPM_TABLE_93__UvdLevel_2_MinVddNb__SHIFT 0x10
1061 #define DPM_TABLE_94__UvdLevel_2_padding_1_MASK 0xff
1062 #define DPM_TABLE_94__UvdLevel_2_padding_1__SHIFT 0x0
1063 #define DPM_TABLE_94__UvdLevel_2_padding_0_MASK 0xff00
1064 #define DPM_TABLE_94__UvdLevel_2_padding_0__SHIFT 0x8
1065 #define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl_MASK 0xff0000
1066 #define DPM_TABLE_94__UvdLevel_2_DClkBypassCntl__SHIFT 0x10
1067 #define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl_MASK 0xff000000
1068 #define DPM_TABLE_94__UvdLevel_2_VClkBypassCntl__SHIFT 0x18
1069 #define DPM_TABLE_95__UvdLevel_3_VclkFrequency_MASK 0xffffffff
1070 #define DPM_TABLE_95__UvdLevel_3_VclkFrequency__SHIFT 0x0
1071 #define DPM_TABLE_96__UvdLevel_3_DclkFrequency_MASK 0xffffffff
1072 #define DPM_TABLE_96__UvdLevel_3_DclkFrequency__SHIFT 0x0
1073 #define DPM_TABLE_97__UvdLevel_3_DclkDivider_MASK 0xff
1074 #define DPM_TABLE_97__UvdLevel_3_DclkDivider__SHIFT 0x0
1075 #define DPM_TABLE_97__UvdLevel_3_VclkDivider_MASK 0xff00
1076 #define DPM_TABLE_97__UvdLevel_3_VclkDivider__SHIFT 0x8
1077 #define DPM_TABLE_97__UvdLevel_3_MinVddNb_MASK 0xffff0000
1078 #define DPM_TABLE_97__UvdLevel_3_MinVddNb__SHIFT 0x10
1079 #define DPM_TABLE_98__UvdLevel_3_padding_1_MASK 0xff
1080 #define DPM_TABLE_98__UvdLevel_3_padding_1__SHIFT 0x0
1081 #define DPM_TABLE_98__UvdLevel_3_padding_0_MASK 0xff00
1082 #define DPM_TABLE_98__UvdLevel_3_padding_0__SHIFT 0x8
1083 #define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl_MASK 0xff0000
1084 #define DPM_TABLE_98__UvdLevel_3_DClkBypassCntl__SHIFT 0x10
1085 #define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl_MASK 0xff000000
1086 #define DPM_TABLE_98__UvdLevel_3_VClkBypassCntl__SHIFT 0x18
1087 #define DPM_TABLE_99__UvdLevel_4_VclkFrequency_MASK 0xffffffff
1088 #define DPM_TABLE_99__UvdLevel_4_VclkFrequency__SHIFT 0x0
1089 #define DPM_TABLE_100__UvdLevel_4_DclkFrequency_MASK 0xffffffff
1090 #define DPM_TABLE_100__UvdLevel_4_DclkFrequency__SHIFT 0x0
1091 #define DPM_TABLE_101__UvdLevel_4_DclkDivider_MASK 0xff
1092 #define DPM_TABLE_101__UvdLevel_4_DclkDivider__SHIFT 0x0
1093 #define DPM_TABLE_101__UvdLevel_4_VclkDivider_MASK 0xff00
1094 #define DPM_TABLE_101__UvdLevel_4_VclkDivider__SHIFT 0x8
1095 #define DPM_TABLE_101__UvdLevel_4_MinVddNb_MASK 0xffff0000
1096 #define DPM_TABLE_101__UvdLevel_4_MinVddNb__SHIFT 0x10
1097 #define DPM_TABLE_102__UvdLevel_4_padding_1_MASK 0xff
1098 #define DPM_TABLE_102__UvdLevel_4_padding_1__SHIFT 0x0
1099 #define DPM_TABLE_102__UvdLevel_4_padding_0_MASK 0xff00
1100 #define DPM_TABLE_102__UvdLevel_4_padding_0__SHIFT 0x8
1101 #define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl_MASK 0xff0000
1102 #define DPM_TABLE_102__UvdLevel_4_DClkBypassCntl__SHIFT 0x10
1103 #define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl_MASK 0xff000000
1104 #define DPM_TABLE_102__UvdLevel_4_VClkBypassCntl__SHIFT 0x18
1105 #define DPM_TABLE_103__UvdLevel_5_VclkFrequency_MASK 0xffffffff
1106 #define DPM_TABLE_103__UvdLevel_5_VclkFrequency__SHIFT 0x0
1107 #define DPM_TABLE_104__UvdLevel_5_DclkFrequency_MASK 0xffffffff
1108 #define DPM_TABLE_104__UvdLevel_5_DclkFrequency__SHIFT 0x0
1109 #define DPM_TABLE_105__UvdLevel_5_DclkDivider_MASK 0xff
1110 #define DPM_TABLE_105__UvdLevel_5_DclkDivider__SHIFT 0x0
1111 #define DPM_TABLE_105__UvdLevel_5_VclkDivider_MASK 0xff00
1112 #define DPM_TABLE_105__UvdLevel_5_VclkDivider__SHIFT 0x8
1113 #define DPM_TABLE_105__UvdLevel_5_MinVddNb_MASK 0xffff0000
1114 #define DPM_TABLE_105__UvdLevel_5_MinVddNb__SHIFT 0x10
1115 #define DPM_TABLE_106__UvdLevel_5_padding_1_MASK 0xff
1116 #define DPM_TABLE_106__UvdLevel_5_padding_1__SHIFT 0x0
1117 #define DPM_TABLE_106__UvdLevel_5_padding_0_MASK 0xff00
1118 #define DPM_TABLE_106__UvdLevel_5_padding_0__SHIFT 0x8
1119 #define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl_MASK 0xff0000
1120 #define DPM_TABLE_106__UvdLevel_5_DClkBypassCntl__SHIFT 0x10
1121 #define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl_MASK 0xff000000
1122 #define DPM_TABLE_106__UvdLevel_5_VClkBypassCntl__SHIFT 0x18
1123 #define DPM_TABLE_107__UvdLevel_6_VclkFrequency_MASK 0xffffffff
1124 #define DPM_TABLE_107__UvdLevel_6_VclkFrequency__SHIFT 0x0
1125 #define DPM_TABLE_108__UvdLevel_6_DclkFrequency_MASK 0xffffffff
1126 #define DPM_TABLE_108__UvdLevel_6_DclkFrequency__SHIFT 0x0
1127 #define DPM_TABLE_109__UvdLevel_6_DclkDivider_MASK 0xff
1128 #define DPM_TABLE_109__UvdLevel_6_DclkDivider__SHIFT 0x0
1129 #define DPM_TABLE_109__UvdLevel_6_VclkDivider_MASK 0xff00
1130 #define DPM_TABLE_109__UvdLevel_6_VclkDivider__SHIFT 0x8
1131 #define DPM_TABLE_109__UvdLevel_6_MinVddNb_MASK 0xffff0000
1132 #define DPM_TABLE_109__UvdLevel_6_MinVddNb__SHIFT 0x10
1133 #define DPM_TABLE_110__UvdLevel_6_padding_1_MASK 0xff
1134 #define DPM_TABLE_110__UvdLevel_6_padding_1__SHIFT 0x0
1135 #define DPM_TABLE_110__UvdLevel_6_padding_0_MASK 0xff00
1136 #define DPM_TABLE_110__UvdLevel_6_padding_0__SHIFT 0x8
1137 #define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl_MASK 0xff0000
1138 #define DPM_TABLE_110__UvdLevel_6_DClkBypassCntl__SHIFT 0x10
1139 #define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl_MASK 0xff000000
1140 #define DPM_TABLE_110__UvdLevel_6_VClkBypassCntl__SHIFT 0x18
1141 #define DPM_TABLE_111__UvdLevel_7_VclkFrequency_MASK 0xffffffff
1142 #define DPM_TABLE_111__UvdLevel_7_VclkFrequency__SHIFT 0x0
1143 #define DPM_TABLE_112__UvdLevel_7_DclkFrequency_MASK 0xffffffff
1144 #define DPM_TABLE_112__UvdLevel_7_DclkFrequency__SHIFT 0x0
1145 #define DPM_TABLE_113__UvdLevel_7_DclkDivider_MASK 0xff
1146 #define DPM_TABLE_113__UvdLevel_7_DclkDivider__SHIFT 0x0
1147 #define DPM_TABLE_113__UvdLevel_7_VclkDivider_MASK 0xff00
1148 #define DPM_TABLE_113__UvdLevel_7_VclkDivider__SHIFT 0x8
1149 #define DPM_TABLE_113__UvdLevel_7_MinVddNb_MASK 0xffff0000
1150 #define DPM_TABLE_113__UvdLevel_7_MinVddNb__SHIFT 0x10
1151 #define DPM_TABLE_114__UvdLevel_7_padding_1_MASK 0xff
1152 #define DPM_TABLE_114__UvdLevel_7_padding_1__SHIFT 0x0
1153 #define DPM_TABLE_114__UvdLevel_7_padding_0_MASK 0xff00
1154 #define DPM_TABLE_114__UvdLevel_7_padding_0__SHIFT 0x8
1155 #define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl_MASK 0xff0000
1156 #define DPM_TABLE_114__UvdLevel_7_DClkBypassCntl__SHIFT 0x10
1157 #define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl_MASK 0xff000000
1158 #define DPM_TABLE_114__UvdLevel_7_VClkBypassCntl__SHIFT 0x18
1159 #define DPM_TABLE_115__VceLevel_0_Frequency_MASK 0xffffffff
1160 #define DPM_TABLE_115__VceLevel_0_Frequency__SHIFT 0x0
1161 #define DPM_TABLE_116__VceLevel_0_ClkBypassCntl_MASK 0xff
1162 #define DPM_TABLE_116__VceLevel_0_ClkBypassCntl__SHIFT 0x0
1163 #define DPM_TABLE_116__VceLevel_0_Divider_MASK 0xff00
1164 #define DPM_TABLE_116__VceLevel_0_Divider__SHIFT 0x8
1165 #define DPM_TABLE_116__VceLevel_0_MinVoltage_MASK 0xffff0000
1166 #define DPM_TABLE_116__VceLevel_0_MinVoltage__SHIFT 0x10
1167 #define DPM_TABLE_117__VceLevel_0_Reserved_MASK 0xffffffff
1168 #define DPM_TABLE_117__VceLevel_0_Reserved__SHIFT 0x0
1169 #define DPM_TABLE_118__VceLevel_1_Frequency_MASK 0xffffffff
1170 #define DPM_TABLE_118__VceLevel_1_Frequency__SHIFT 0x0
1171 #define DPM_TABLE_119__VceLevel_1_ClkBypassCntl_MASK 0xff
1172 #define DPM_TABLE_119__VceLevel_1_ClkBypassCntl__SHIFT 0x0
1173 #define DPM_TABLE_119__VceLevel_1_Divider_MASK 0xff00
1174 #define DPM_TABLE_119__VceLevel_1_Divider__SHIFT 0x8
1175 #define DPM_TABLE_119__VceLevel_1_MinVoltage_MASK 0xffff0000
1176 #define DPM_TABLE_119__VceLevel_1_MinVoltage__SHIFT 0x10
1177 #define DPM_TABLE_120__VceLevel_1_Reserved_MASK 0xffffffff
1178 #define DPM_TABLE_120__VceLevel_1_Reserved__SHIFT 0x0
1179 #define DPM_TABLE_121__VceLevel_2_Frequency_MASK 0xffffffff
1180 #define DPM_TABLE_121__VceLevel_2_Frequency__SHIFT 0x0
1181 #define DPM_TABLE_122__VceLevel_2_ClkBypassCntl_MASK 0xff
1182 #define DPM_TABLE_122__VceLevel_2_ClkBypassCntl__SHIFT 0x0
1183 #define DPM_TABLE_122__VceLevel_2_Divider_MASK 0xff00
1184 #define DPM_TABLE_122__VceLevel_2_Divider__SHIFT 0x8
1185 #define DPM_TABLE_122__VceLevel_2_MinVoltage_MASK 0xffff0000
1186 #define DPM_TABLE_122__VceLevel_2_MinVoltage__SHIFT 0x10
1187 #define DPM_TABLE_123__VceLevel_2_Reserved_MASK 0xffffffff
1188 #define DPM_TABLE_123__VceLevel_2_Reserved__SHIFT 0x0
1189 #define DPM_TABLE_124__VceLevel_3_Frequency_MASK 0xffffffff
1190 #define DPM_TABLE_124__VceLevel_3_Frequency__SHIFT 0x0
1191 #define DPM_TABLE_125__VceLevel_3_ClkBypassCntl_MASK 0xff
1192 #define DPM_TABLE_125__VceLevel_3_ClkBypassCntl__SHIFT 0x0
1193 #define DPM_TABLE_125__VceLevel_3_Divider_MASK 0xff00
1194 #define DPM_TABLE_125__VceLevel_3_Divider__SHIFT 0x8
1195 #define DPM_TABLE_125__VceLevel_3_MinVoltage_MASK 0xffff0000
1196 #define DPM_TABLE_125__VceLevel_3_MinVoltage__SHIFT 0x10
1197 #define DPM_TABLE_126__VceLevel_3_Reserved_MASK 0xffffffff
1198 #define DPM_TABLE_126__VceLevel_3_Reserved__SHIFT 0x0
1199 #define DPM_TABLE_127__VceLevel_4_Frequency_MASK 0xffffffff
1200 #define DPM_TABLE_127__VceLevel_4_Frequency__SHIFT 0x0
1201 #define DPM_TABLE_128__VceLevel_4_ClkBypassCntl_MASK 0xff
1202 #define DPM_TABLE_128__VceLevel_4_ClkBypassCntl__SHIFT 0x0
1203 #define DPM_TABLE_128__VceLevel_4_Divider_MASK 0xff00
1204 #define DPM_TABLE_128__VceLevel_4_Divider__SHIFT 0x8
1205 #define DPM_TABLE_128__VceLevel_4_MinVoltage_MASK 0xffff0000
1206 #define DPM_TABLE_128__VceLevel_4_MinVoltage__SHIFT 0x10
1207 #define DPM_TABLE_129__VceLevel_4_Reserved_MASK 0xffffffff
1208 #define DPM_TABLE_129__VceLevel_4_Reserved__SHIFT 0x0
1209 #define DPM_TABLE_130__VceLevel_5_Frequency_MASK 0xffffffff
1210 #define DPM_TABLE_130__VceLevel_5_Frequency__SHIFT 0x0
1211 #define DPM_TABLE_131__VceLevel_5_ClkBypassCntl_MASK 0xff
1212 #define DPM_TABLE_131__VceLevel_5_ClkBypassCntl__SHIFT 0x0
1213 #define DPM_TABLE_131__VceLevel_5_Divider_MASK 0xff00
1214 #define DPM_TABLE_131__VceLevel_5_Divider__SHIFT 0x8
1215 #define DPM_TABLE_131__VceLevel_5_MinVoltage_MASK 0xffff0000
1216 #define DPM_TABLE_131__VceLevel_5_MinVoltage__SHIFT 0x10
1217 #define DPM_TABLE_132__VceLevel_5_Reserved_MASK 0xffffffff
1218 #define DPM_TABLE_132__VceLevel_5_Reserved__SHIFT 0x0
1219 #define DPM_TABLE_133__VceLevel_6_Frequency_MASK 0xffffffff
1220 #define DPM_TABLE_133__VceLevel_6_Frequency__SHIFT 0x0
1221 #define DPM_TABLE_134__VceLevel_6_ClkBypassCntl_MASK 0xff
1222 #define DPM_TABLE_134__VceLevel_6_ClkBypassCntl__SHIFT 0x0
1223 #define DPM_TABLE_134__VceLevel_6_Divider_MASK 0xff00
1224 #define DPM_TABLE_134__VceLevel_6_Divider__SHIFT 0x8
1225 #define DPM_TABLE_134__VceLevel_6_MinVoltage_MASK 0xffff0000
1226 #define DPM_TABLE_134__VceLevel_6_MinVoltage__SHIFT 0x10
1227 #define DPM_TABLE_135__VceLevel_6_Reserved_MASK 0xffffffff
1228 #define DPM_TABLE_135__VceLevel_6_Reserved__SHIFT 0x0
1229 #define DPM_TABLE_136__VceLevel_7_Frequency_MASK 0xffffffff
1230 #define DPM_TABLE_136__VceLevel_7_Frequency__SHIFT 0x0
1231 #define DPM_TABLE_137__VceLevel_7_ClkBypassCntl_MASK 0xff
1232 #define DPM_TABLE_137__VceLevel_7_ClkBypassCntl__SHIFT 0x0
1233 #define DPM_TABLE_137__VceLevel_7_Divider_MASK 0xff00
1234 #define DPM_TABLE_137__VceLevel_7_Divider__SHIFT 0x8
1235 #define DPM_TABLE_137__VceLevel_7_MinVoltage_MASK 0xffff0000
1236 #define DPM_TABLE_137__VceLevel_7_MinVoltage__SHIFT 0x10
1237 #define DPM_TABLE_138__VceLevel_7_Reserved_MASK 0xffffffff
1238 #define DPM_TABLE_138__VceLevel_7_Reserved__SHIFT 0x0
1239 #define DPM_TABLE_139__AcpLevel_0_Frequency_MASK 0xffffffff
1240 #define DPM_TABLE_139__AcpLevel_0_Frequency__SHIFT 0x0
1241 #define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl_MASK 0xff
1242 #define DPM_TABLE_140__AcpLevel_0_ClkBypassCntl__SHIFT 0x0
1243 #define DPM_TABLE_140__AcpLevel_0_Divider_MASK 0xff00
1244 #define DPM_TABLE_140__AcpLevel_0_Divider__SHIFT 0x8
1245 #define DPM_TABLE_140__AcpLevel_0_MinVoltage_MASK 0xffff0000
1246 #define DPM_TABLE_140__AcpLevel_0_MinVoltage__SHIFT 0x10
1247 #define DPM_TABLE_141__AcpLevel_0_Reserved_MASK 0xffffffff
1248 #define DPM_TABLE_141__AcpLevel_0_Reserved__SHIFT 0x0
1249 #define DPM_TABLE_142__AcpLevel_1_Frequency_MASK 0xffffffff
1250 #define DPM_TABLE_142__AcpLevel_1_Frequency__SHIFT 0x0
1251 #define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl_MASK 0xff
1252 #define DPM_TABLE_143__AcpLevel_1_ClkBypassCntl__SHIFT 0x0
1253 #define DPM_TABLE_143__AcpLevel_1_Divider_MASK 0xff00
1254 #define DPM_TABLE_143__AcpLevel_1_Divider__SHIFT 0x8
1255 #define DPM_TABLE_143__AcpLevel_1_MinVoltage_MASK 0xffff0000
1256 #define DPM_TABLE_143__AcpLevel_1_MinVoltage__SHIFT 0x10
1257 #define DPM_TABLE_144__AcpLevel_1_Reserved_MASK 0xffffffff
1258 #define DPM_TABLE_144__AcpLevel_1_Reserved__SHIFT 0x0
1259 #define DPM_TABLE_145__AcpLevel_2_Frequency_MASK 0xffffffff
1260 #define DPM_TABLE_145__AcpLevel_2_Frequency__SHIFT 0x0
1261 #define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl_MASK 0xff
1262 #define DPM_TABLE_146__AcpLevel_2_ClkBypassCntl__SHIFT 0x0
1263 #define DPM_TABLE_146__AcpLevel_2_Divider_MASK 0xff00
1264 #define DPM_TABLE_146__AcpLevel_2_Divider__SHIFT 0x8
1265 #define DPM_TABLE_146__AcpLevel_2_MinVoltage_MASK 0xffff0000
1266 #define DPM_TABLE_146__AcpLevel_2_MinVoltage__SHIFT 0x10
1267 #define DPM_TABLE_147__AcpLevel_2_Reserved_MASK 0xffffffff
1268 #define DPM_TABLE_147__AcpLevel_2_Reserved__SHIFT 0x0
1269 #define DPM_TABLE_148__AcpLevel_3_Frequency_MASK 0xffffffff
1270 #define DPM_TABLE_148__AcpLevel_3_Frequency__SHIFT 0x0
1271 #define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl_MASK 0xff
1272 #define DPM_TABLE_149__AcpLevel_3_ClkBypassCntl__SHIFT 0x0
1273 #define DPM_TABLE_149__AcpLevel_3_Divider_MASK 0xff00
1274 #define DPM_TABLE_149__AcpLevel_3_Divider__SHIFT 0x8
1275 #define DPM_TABLE_149__AcpLevel_3_MinVoltage_MASK 0xffff0000
1276 #define DPM_TABLE_149__AcpLevel_3_MinVoltage__SHIFT 0x10
1277 #define DPM_TABLE_150__AcpLevel_3_Reserved_MASK 0xffffffff
1278 #define DPM_TABLE_150__AcpLevel_3_Reserved__SHIFT 0x0
1279 #define DPM_TABLE_151__AcpLevel_4_Frequency_MASK 0xffffffff
1280 #define DPM_TABLE_151__AcpLevel_4_Frequency__SHIFT 0x0
1281 #define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl_MASK 0xff
1282 #define DPM_TABLE_152__AcpLevel_4_ClkBypassCntl__SHIFT 0x0
1283 #define DPM_TABLE_152__AcpLevel_4_Divider_MASK 0xff00
1284 #define DPM_TABLE_152__AcpLevel_4_Divider__SHIFT 0x8
1285 #define DPM_TABLE_152__AcpLevel_4_MinVoltage_MASK 0xffff0000
1286 #define DPM_TABLE_152__AcpLevel_4_MinVoltage__SHIFT 0x10
1287 #define DPM_TABLE_153__AcpLevel_4_Reserved_MASK 0xffffffff
1288 #define DPM_TABLE_153__AcpLevel_4_Reserved__SHIFT 0x0
1289 #define DPM_TABLE_154__AcpLevel_5_Frequency_MASK 0xffffffff
1290 #define DPM_TABLE_154__AcpLevel_5_Frequency__SHIFT 0x0
1291 #define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl_MASK 0xff
1292 #define DPM_TABLE_155__AcpLevel_5_ClkBypassCntl__SHIFT 0x0
1293 #define DPM_TABLE_155__AcpLevel_5_Divider_MASK 0xff00
1294 #define DPM_TABLE_155__AcpLevel_5_Divider__SHIFT 0x8
1295 #define DPM_TABLE_155__AcpLevel_5_MinVoltage_MASK 0xffff0000
1296 #define DPM_TABLE_155__AcpLevel_5_MinVoltage__SHIFT 0x10
1297 #define DPM_TABLE_156__AcpLevel_5_Reserved_MASK 0xffffffff
1298 #define DPM_TABLE_156__AcpLevel_5_Reserved__SHIFT 0x0
1299 #define DPM_TABLE_157__AcpLevel_6_Frequency_MASK 0xffffffff
1300 #define DPM_TABLE_157__AcpLevel_6_Frequency__SHIFT 0x0
1301 #define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl_MASK 0xff
1302 #define DPM_TABLE_158__AcpLevel_6_ClkBypassCntl__SHIFT 0x0
1303 #define DPM_TABLE_158__AcpLevel_6_Divider_MASK 0xff00
1304 #define DPM_TABLE_158__AcpLevel_6_Divider__SHIFT 0x8
1305 #define DPM_TABLE_158__AcpLevel_6_MinVoltage_MASK 0xffff0000
1306 #define DPM_TABLE_158__AcpLevel_6_MinVoltage__SHIFT 0x10
1307 #define DPM_TABLE_159__AcpLevel_6_Reserved_MASK 0xffffffff
1308 #define DPM_TABLE_159__AcpLevel_6_Reserved__SHIFT 0x0
1309 #define DPM_TABLE_160__AcpLevel_7_Frequency_MASK 0xffffffff
1310 #define DPM_TABLE_160__AcpLevel_7_Frequency__SHIFT 0x0
1311 #define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl_MASK 0xff
1312 #define DPM_TABLE_161__AcpLevel_7_ClkBypassCntl__SHIFT 0x0
1313 #define DPM_TABLE_161__AcpLevel_7_Divider_MASK 0xff00
1314 #define DPM_TABLE_161__AcpLevel_7_Divider__SHIFT 0x8
1315 #define DPM_TABLE_161__AcpLevel_7_MinVoltage_MASK 0xffff0000
1316 #define DPM_TABLE_161__AcpLevel_7_MinVoltage__SHIFT 0x10
1317 #define DPM_TABLE_162__AcpLevel_7_Reserved_MASK 0xffffffff
1318 #define DPM_TABLE_162__AcpLevel_7_Reserved__SHIFT 0x0
1319 #define DPM_TABLE_163__SamuLevel_0_Frequency_MASK 0xffffffff
1320 #define DPM_TABLE_163__SamuLevel_0_Frequency__SHIFT 0x0
1321 #define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl_MASK 0xff
1322 #define DPM_TABLE_164__SamuLevel_0_ClkBypassCntl__SHIFT 0x0
1323 #define DPM_TABLE_164__SamuLevel_0_Divider_MASK 0xff00
1324 #define DPM_TABLE_164__SamuLevel_0_Divider__SHIFT 0x8
1325 #define DPM_TABLE_164__SamuLevel_0_MinVoltage_MASK 0xffff0000
1326 #define DPM_TABLE_164__SamuLevel_0_MinVoltage__SHIFT 0x10
1327 #define DPM_TABLE_165__SamuLevel_0_Reserved_MASK 0xffffffff
1328 #define DPM_TABLE_165__SamuLevel_0_Reserved__SHIFT 0x0
1329 #define DPM_TABLE_166__SamuLevel_1_Frequency_MASK 0xffffffff
1330 #define DPM_TABLE_166__SamuLevel_1_Frequency__SHIFT 0x0
1331 #define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl_MASK 0xff
1332 #define DPM_TABLE_167__SamuLevel_1_ClkBypassCntl__SHIFT 0x0
1333 #define DPM_TABLE_167__SamuLevel_1_Divider_MASK 0xff00
1334 #define DPM_TABLE_167__SamuLevel_1_Divider__SHIFT 0x8
1335 #define DPM_TABLE_167__SamuLevel_1_MinVoltage_MASK 0xffff0000
1336 #define DPM_TABLE_167__SamuLevel_1_MinVoltage__SHIFT 0x10
1337 #define DPM_TABLE_168__SamuLevel_1_Reserved_MASK 0xffffffff
1338 #define DPM_TABLE_168__SamuLevel_1_Reserved__SHIFT 0x0
1339 #define DPM_TABLE_169__SamuLevel_2_Frequency_MASK 0xffffffff
1340 #define DPM_TABLE_169__SamuLevel_2_Frequency__SHIFT 0x0
1341 #define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl_MASK 0xff
1342 #define DPM_TABLE_170__SamuLevel_2_ClkBypassCntl__SHIFT 0x0
1343 #define DPM_TABLE_170__SamuLevel_2_Divider_MASK 0xff00
1344 #define DPM_TABLE_170__SamuLevel_2_Divider__SHIFT 0x8
1345 #define DPM_TABLE_170__SamuLevel_2_MinVoltage_MASK 0xffff0000
1346 #define DPM_TABLE_170__SamuLevel_2_MinVoltage__SHIFT 0x10
1347 #define DPM_TABLE_171__SamuLevel_2_Reserved_MASK 0xffffffff
1348 #define DPM_TABLE_171__SamuLevel_2_Reserved__SHIFT 0x0
1349 #define DPM_TABLE_172__SamuLevel_3_Frequency_MASK 0xffffffff
1350 #define DPM_TABLE_172__SamuLevel_3_Frequency__SHIFT 0x0
1351 #define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl_MASK 0xff
1352 #define DPM_TABLE_173__SamuLevel_3_ClkBypassCntl__SHIFT 0x0
1353 #define DPM_TABLE_173__SamuLevel_3_Divider_MASK 0xff00
1354 #define DPM_TABLE_173__SamuLevel_3_Divider__SHIFT 0x8
1355 #define DPM_TABLE_173__SamuLevel_3_MinVoltage_MASK 0xffff0000
1356 #define DPM_TABLE_173__SamuLevel_3_MinVoltage__SHIFT 0x10
1357 #define DPM_TABLE_174__SamuLevel_3_Reserved_MASK 0xffffffff
1358 #define DPM_TABLE_174__SamuLevel_3_Reserved__SHIFT 0x0
1359 #define DPM_TABLE_175__SamuLevel_4_Frequency_MASK 0xffffffff
1360 #define DPM_TABLE_175__SamuLevel_4_Frequency__SHIFT 0x0
1361 #define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl_MASK 0xff
1362 #define DPM_TABLE_176__SamuLevel_4_ClkBypassCntl__SHIFT 0x0
1363 #define DPM_TABLE_176__SamuLevel_4_Divider_MASK 0xff00
1364 #define DPM_TABLE_176__SamuLevel_4_Divider__SHIFT 0x8
1365 #define DPM_TABLE_176__SamuLevel_4_MinVoltage_MASK 0xffff0000
1366 #define DPM_TABLE_176__SamuLevel_4_MinVoltage__SHIFT 0x10
1367 #define DPM_TABLE_177__SamuLevel_4_Reserved_MASK 0xffffffff
1368 #define DPM_TABLE_177__SamuLevel_4_Reserved__SHIFT 0x0
1369 #define DPM_TABLE_178__SamuLevel_5_Frequency_MASK 0xffffffff
1370 #define DPM_TABLE_178__SamuLevel_5_Frequency__SHIFT 0x0
1371 #define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl_MASK 0xff
1372 #define DPM_TABLE_179__SamuLevel_5_ClkBypassCntl__SHIFT 0x0
1373 #define DPM_TABLE_179__SamuLevel_5_Divider_MASK 0xff00
1374 #define DPM_TABLE_179__SamuLevel_5_Divider__SHIFT 0x8
1375 #define DPM_TABLE_179__SamuLevel_5_MinVoltage_MASK 0xffff0000
1376 #define DPM_TABLE_179__SamuLevel_5_MinVoltage__SHIFT 0x10
1377 #define DPM_TABLE_180__SamuLevel_5_Reserved_MASK 0xffffffff
1378 #define DPM_TABLE_180__SamuLevel_5_Reserved__SHIFT 0x0
1379 #define DPM_TABLE_181__SamuLevel_6_Frequency_MASK 0xffffffff
1380 #define DPM_TABLE_181__SamuLevel_6_Frequency__SHIFT 0x0
1381 #define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl_MASK 0xff
1382 #define DPM_TABLE_182__SamuLevel_6_ClkBypassCntl__SHIFT 0x0
1383 #define DPM_TABLE_182__SamuLevel_6_Divider_MASK 0xff00
1384 #define DPM_TABLE_182__SamuLevel_6_Divider__SHIFT 0x8
1385 #define DPM_TABLE_182__SamuLevel_6_MinVoltage_MASK 0xffff0000
1386 #define DPM_TABLE_182__SamuLevel_6_MinVoltage__SHIFT 0x10
1387 #define DPM_TABLE_183__SamuLevel_6_Reserved_MASK 0xffffffff
1388 #define DPM_TABLE_183__SamuLevel_6_Reserved__SHIFT 0x0
1389 #define DPM_TABLE_184__SamuLevel_7_Frequency_MASK 0xffffffff
1390 #define DPM_TABLE_184__SamuLevel_7_Frequency__SHIFT 0x0
1391 #define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl_MASK 0xff
1392 #define DPM_TABLE_185__SamuLevel_7_ClkBypassCntl__SHIFT 0x0
1393 #define DPM_TABLE_185__SamuLevel_7_Divider_MASK 0xff00
1394 #define DPM_TABLE_185__SamuLevel_7_Divider__SHIFT 0x8
1395 #define DPM_TABLE_185__SamuLevel_7_MinVoltage_MASK 0xffff0000
1396 #define DPM_TABLE_185__SamuLevel_7_MinVoltage__SHIFT 0x10
1397 #define DPM_TABLE_186__SamuLevel_7_Reserved_MASK 0xffffffff
1398 #define DPM_TABLE_186__SamuLevel_7_Reserved__SHIFT 0x0
1399 #define DPM_TABLE_187__SamuBootLevel_MASK 0xff
1400 #define DPM_TABLE_187__SamuBootLevel__SHIFT 0x0
1401 #define DPM_TABLE_187__AcpBootLevel_MASK 0xff00
1402 #define DPM_TABLE_187__AcpBootLevel__SHIFT 0x8
1403 #define DPM_TABLE_187__VceBootLevel_MASK 0xff0000
1404 #define DPM_TABLE_187__VceBootLevel__SHIFT 0x10
1405 #define DPM_TABLE_187__UvdBootLevel_MASK 0xff000000
1406 #define DPM_TABLE_187__UvdBootLevel__SHIFT 0x18
1407 #define DPM_TABLE_188__SAMUInterval_MASK 0xff
1408 #define DPM_TABLE_188__SAMUInterval__SHIFT 0x0
1409 #define DPM_TABLE_188__ACPInterval_MASK 0xff00
1410 #define DPM_TABLE_188__ACPInterval__SHIFT 0x8
1411 #define DPM_TABLE_188__VCEInterval_MASK 0xff0000
1412 #define DPM_TABLE_188__VCEInterval__SHIFT 0x10
1413 #define DPM_TABLE_188__UVDInterval_MASK 0xff000000
1414 #define DPM_TABLE_188__UVDInterval__SHIFT 0x18
1415 #define DPM_TABLE_189__GraphicsVoltageChangeEnable_MASK 0xff
1416 #define DPM_TABLE_189__GraphicsVoltageChangeEnable__SHIFT 0x0
1417 #define DPM_TABLE_189__GraphicsThermThrottleEnable_MASK 0xff00
1418 #define DPM_TABLE_189__GraphicsThermThrottleEnable__SHIFT 0x8
1419 #define DPM_TABLE_189__GraphicsInterval_MASK 0xff0000
1420 #define DPM_TABLE_189__GraphicsInterval__SHIFT 0x10
1421 #define DPM_TABLE_189__GraphicsBootLevel_MASK 0xff000000
1422 #define DPM_TABLE_189__GraphicsBootLevel__SHIFT 0x18
1423 #define DPM_TABLE_190__FpsLowThreshold_MASK 0xffff
1424 #define DPM_TABLE_190__FpsLowThreshold__SHIFT 0x0
1425 #define DPM_TABLE_190__GraphicsClkSlowDivider_MASK 0xff0000
1426 #define DPM_TABLE_190__GraphicsClkSlowDivider__SHIFT 0x10
1427 #define DPM_TABLE_190__GraphicsClkSlowEnable_MASK 0xff000000
1428 #define DPM_TABLE_190__GraphicsClkSlowEnable__SHIFT 0x18
1429 #define DPM_TABLE_191__DisplayCac_MASK 0xffffffff
1430 #define DPM_TABLE_191__DisplayCac__SHIFT 0x0
1431 #define SOFT_REGISTERS_TABLE_1__RefClockFrequency_MASK 0xffffffff
1432 #define SOFT_REGISTERS_TABLE_1__RefClockFrequency__SHIFT 0x0
1433 #define SOFT_REGISTERS_TABLE_2__PmTimerPeriod_MASK 0xffffffff
1434 #define SOFT_REGISTERS_TABLE_2__PmTimerPeriod__SHIFT 0x0
1435 #define SOFT_REGISTERS_TABLE_3__FeatureEnables_MASK 0xffffffff
1436 #define SOFT_REGISTERS_TABLE_3__FeatureEnables__SHIFT 0x0
1437 #define SOFT_REGISTERS_TABLE_4__HandshakeDisables_MASK 0xffffffff
1438 #define SOFT_REGISTERS_TABLE_4__HandshakeDisables__SHIFT 0x0
1439 #define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config_MASK 0xff
1440 #define SOFT_REGISTERS_TABLE_5__DisplayPhy4Config__SHIFT 0x0
1441 #define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config_MASK 0xff00
1442 #define SOFT_REGISTERS_TABLE_5__DisplayPhy3Config__SHIFT 0x8
1443 #define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config_MASK 0xff0000
1444 #define SOFT_REGISTERS_TABLE_5__DisplayPhy2Config__SHIFT 0x10
1445 #define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config_MASK 0xff000000
1446 #define SOFT_REGISTERS_TABLE_5__DisplayPhy1Config__SHIFT 0x18
1447 #define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config_MASK 0xff
1448 #define SOFT_REGISTERS_TABLE_6__DisplayPhy8Config__SHIFT 0x0
1449 #define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config_MASK 0xff00
1450 #define SOFT_REGISTERS_TABLE_6__DisplayPhy7Config__SHIFT 0x8
1451 #define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config_MASK 0xff0000
1452 #define SOFT_REGISTERS_TABLE_6__DisplayPhy6Config__SHIFT 0x10
1453 #define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config_MASK 0xff000000
1454 #define SOFT_REGISTERS_TABLE_6__DisplayPhy5Config__SHIFT 0x18
1455 #define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity_MASK 0xffffffff
1456 #define SOFT_REGISTERS_TABLE_7__AverageGraphicsActivity__SHIFT 0x0
1457 #define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity_MASK 0xffffffff
1458 #define SOFT_REGISTERS_TABLE_8__AverageMemoryActivity__SHIFT 0x0
1459 #define SOFT_REGISTERS_TABLE_9__AverageGioActivity_MASK 0xffffffff
1460 #define SOFT_REGISTERS_TABLE_9__AverageGioActivity__SHIFT 0x0
1461 #define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels_MASK 0xff
1462 #define SOFT_REGISTERS_TABLE_10__PCIeDpmEnabledLevels__SHIFT 0x0
1463 #define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels_MASK 0xff00
1464 #define SOFT_REGISTERS_TABLE_10__LClkDpmEnabledLevels__SHIFT 0x8
1465 #define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels_MASK 0xff0000
1466 #define SOFT_REGISTERS_TABLE_10__MClkDpmEnabledLevels__SHIFT 0x10
1467 #define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels_MASK 0xff000000
1468 #define SOFT_REGISTERS_TABLE_10__SClkDpmEnabledLevels__SHIFT 0x18
1469 #define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels_MASK 0xff
1470 #define SOFT_REGISTERS_TABLE_11__VCEDpmEnabledLevels__SHIFT 0x0
1471 #define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels_MASK 0xff00
1472 #define SOFT_REGISTERS_TABLE_11__ACPDpmEnabledLevels__SHIFT 0x8
1473 #define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels_MASK 0xff0000
1474 #define SOFT_REGISTERS_TABLE_11__SAMUDpmEnabledLevels__SHIFT 0x10
1475 #define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels_MASK 0xff000000
1476 #define SOFT_REGISTERS_TABLE_11__UVDDpmEnabledLevels__SHIFT 0x18
1477 #define SOFT_REGISTERS_TABLE_12__Reserved_0_MASK 0xffffffff
1478 #define SOFT_REGISTERS_TABLE_12__Reserved_0__SHIFT 0x0
1479 #define SOFT_REGISTERS_TABLE_13__Reserved_1_MASK 0xffffffff
1480 #define SOFT_REGISTERS_TABLE_13__Reserved_1__SHIFT 0x0
1481 #define SOFT_REGISTERS_TABLE_14__Reserved_2_MASK 0xffffffff
1482 #define SOFT_REGISTERS_TABLE_14__Reserved_2__SHIFT 0x0
1483 #define SOFT_REGISTERS_TABLE_15__Reserved_3_MASK 0xffffffff
1484 #define SOFT_REGISTERS_TABLE_15__Reserved_3__SHIFT 0x0
1485 #define SOFT_REGISTERS_TABLE_16__Reserved_4_MASK 0xffffffff
1486 #define SOFT_REGISTERS_TABLE_16__Reserved_4__SHIFT 0x0
1487 #define SOFT_REGISTERS_TABLE_17__Reserved_5_MASK 0xffffffff
1488 #define SOFT_REGISTERS_TABLE_17__Reserved_5__SHIFT 0x0
1489 #define SOFT_REGISTERS_TABLE_18__Reserved_6_MASK 0xffffffff
1490 #define SOFT_REGISTERS_TABLE_18__Reserved_6__SHIFT 0x0
1491 #define SOFT_REGISTERS_TABLE_19__Reserved_7_MASK 0xffffffff
1492 #define SOFT_REGISTERS_TABLE_19__Reserved_7__SHIFT 0x0
1493 #define SOFT_REGISTERS_TABLE_20__Reserved_8_MASK 0xffffffff
1494 #define SOFT_REGISTERS_TABLE_20__Reserved_8__SHIFT 0x0
1495 #define SOFT_REGISTERS_TABLE_21__Reserved_9_MASK 0xffffffff
1496 #define SOFT_REGISTERS_TABLE_21__Reserved_9__SHIFT 0x0
1497 #define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1498 #define SMU_LCLK_DPM_STATE_0_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1499 #define SMU_LCLK_DPM_STATE_0_CNTL_0__VID_MASK 0xff00
1500 #define SMU_LCLK_DPM_STATE_0_CNTL_0__VID__SHIFT 0x8
1501 #define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1502 #define SMU_LCLK_DPM_STATE_0_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1503 #define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID_MASK 0xff000000
1504 #define SMU_LCLK_DPM_STATE_0_CNTL_0__STATE_VALID__SHIFT 0x18
1505 #define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1506 #define SMU_LCLK_DPM_STATE_1_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1507 #define SMU_LCLK_DPM_STATE_1_CNTL_0__VID_MASK 0xff00
1508 #define SMU_LCLK_DPM_STATE_1_CNTL_0__VID__SHIFT 0x8
1509 #define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1510 #define SMU_LCLK_DPM_STATE_1_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1511 #define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID_MASK 0xff000000
1512 #define SMU_LCLK_DPM_STATE_1_CNTL_0__STATE_VALID__SHIFT 0x18
1513 #define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1514 #define SMU_LCLK_DPM_STATE_2_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1515 #define SMU_LCLK_DPM_STATE_2_CNTL_0__VID_MASK 0xff00
1516 #define SMU_LCLK_DPM_STATE_2_CNTL_0__VID__SHIFT 0x8
1517 #define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1518 #define SMU_LCLK_DPM_STATE_2_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1519 #define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID_MASK 0xff000000
1520 #define SMU_LCLK_DPM_STATE_2_CNTL_0__STATE_VALID__SHIFT 0x18
1521 #define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1522 #define SMU_LCLK_DPM_STATE_3_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1523 #define SMU_LCLK_DPM_STATE_3_CNTL_0__VID_MASK 0xff00
1524 #define SMU_LCLK_DPM_STATE_3_CNTL_0__VID__SHIFT 0x8
1525 #define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1526 #define SMU_LCLK_DPM_STATE_3_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1527 #define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID_MASK 0xff000000
1528 #define SMU_LCLK_DPM_STATE_3_CNTL_0__STATE_VALID__SHIFT 0x18
1529 #define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1530 #define SMU_LCLK_DPM_STATE_4_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1531 #define SMU_LCLK_DPM_STATE_4_CNTL_0__VID_MASK 0xff00
1532 #define SMU_LCLK_DPM_STATE_4_CNTL_0__VID__SHIFT 0x8
1533 #define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1534 #define SMU_LCLK_DPM_STATE_4_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1535 #define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID_MASK 0xff000000
1536 #define SMU_LCLK_DPM_STATE_4_CNTL_0__STATE_VALID__SHIFT 0x18
1537 #define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1538 #define SMU_LCLK_DPM_STATE_5_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1539 #define SMU_LCLK_DPM_STATE_5_CNTL_0__VID_MASK 0xff00
1540 #define SMU_LCLK_DPM_STATE_5_CNTL_0__VID__SHIFT 0x8
1541 #define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1542 #define SMU_LCLK_DPM_STATE_5_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1543 #define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID_MASK 0xff000000
1544 #define SMU_LCLK_DPM_STATE_5_CNTL_0__STATE_VALID__SHIFT 0x18
1545 #define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1546 #define SMU_LCLK_DPM_STATE_6_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1547 #define SMU_LCLK_DPM_STATE_6_CNTL_0__VID_MASK 0xff00
1548 #define SMU_LCLK_DPM_STATE_6_CNTL_0__VID__SHIFT 0x8
1549 #define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1550 #define SMU_LCLK_DPM_STATE_6_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1551 #define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID_MASK 0xff000000
1552 #define SMU_LCLK_DPM_STATE_6_CNTL_0__STATE_VALID__SHIFT 0x18
1553 #define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD_MASK 0xff
1554 #define SMU_LCLK_DPM_STATE_7_CNTL_0__LOW_VOLTAGE_REQ_THRESHOLD__SHIFT 0x0
1555 #define SMU_LCLK_DPM_STATE_7_CNTL_0__VID_MASK 0xff00
1556 #define SMU_LCLK_DPM_STATE_7_CNTL_0__VID__SHIFT 0x8
1557 #define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER_MASK 0xff0000
1558 #define SMU_LCLK_DPM_STATE_7_CNTL_0__CLK_DIVIDER__SHIFT 0x10
1559 #define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID_MASK 0xff000000
1560 #define SMU_LCLK_DPM_STATE_7_CNTL_0__STATE_VALID__SHIFT 0x18
1561 #define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1562 #define SMU_LCLK_DPM_STATE_0_CNTL_1__MIN_VDDNB__SHIFT 0x0
1563 #define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1564 #define SMU_LCLK_DPM_STATE_1_CNTL_1__MIN_VDDNB__SHIFT 0x0
1565 #define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1566 #define SMU_LCLK_DPM_STATE_2_CNTL_1__MIN_VDDNB__SHIFT 0x0
1567 #define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1568 #define SMU_LCLK_DPM_STATE_3_CNTL_1__MIN_VDDNB__SHIFT 0x0
1569 #define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1570 #define SMU_LCLK_DPM_STATE_4_CNTL_1__MIN_VDDNB__SHIFT 0x0
1571 #define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1572 #define SMU_LCLK_DPM_STATE_5_CNTL_1__MIN_VDDNB__SHIFT 0x0
1573 #define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1574 #define SMU_LCLK_DPM_STATE_6_CNTL_1__MIN_VDDNB__SHIFT 0x0
1575 #define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB_MASK 0xffffffff
1576 #define SMU_LCLK_DPM_STATE_7_CNTL_1__MIN_VDDNB__SHIFT 0x0
1577 #define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1578 #define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1579 #define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1580 #define SMU_LCLK_DPM_STATE_0_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1581 #define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1582 #define SMU_LCLK_DPM_STATE_0_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1583 #define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1584 #define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1585 #define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1586 #define SMU_LCLK_DPM_STATE_1_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1587 #define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1588 #define SMU_LCLK_DPM_STATE_1_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1589 #define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1590 #define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1591 #define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1592 #define SMU_LCLK_DPM_STATE_2_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1593 #define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1594 #define SMU_LCLK_DPM_STATE_2_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1595 #define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1596 #define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1597 #define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1598 #define SMU_LCLK_DPM_STATE_3_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1599 #define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1600 #define SMU_LCLK_DPM_STATE_3_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1601 #define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1602 #define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1603 #define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1604 #define SMU_LCLK_DPM_STATE_4_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1605 #define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1606 #define SMU_LCLK_DPM_STATE_4_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1607 #define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1608 #define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1609 #define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1610 #define SMU_LCLK_DPM_STATE_5_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1611 #define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1612 #define SMU_LCLK_DPM_STATE_5_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1613 #define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1614 #define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1615 #define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1616 #define SMU_LCLK_DPM_STATE_6_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1617 #define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1618 #define SMU_LCLK_DPM_STATE_6_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1619 #define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN_MASK 0xff
1620 #define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_DOWN__SHIFT 0x0
1621 #define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP_MASK 0xff00
1622 #define SMU_LCLK_DPM_STATE_7_CNTL_2__HYSTERESIS_UP__SHIFT 0x8
1623 #define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER_MASK 0xffff0000
1624 #define SMU_LCLK_DPM_STATE_7_CNTL_2__RESIDENCY_COUNTER__SHIFT 0x10
1625 #define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1626 #define SMU_LCLK_DPM_STATE_0_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1627 #define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1628 #define SMU_LCLK_DPM_STATE_1_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1629 #define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1630 #define SMU_LCLK_DPM_STATE_2_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1631 #define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1632 #define SMU_LCLK_DPM_STATE_3_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1633 #define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1634 #define SMU_LCLK_DPM_STATE_4_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1635 #define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1636 #define SMU_LCLK_DPM_STATE_5_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1637 #define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1638 #define SMU_LCLK_DPM_STATE_6_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1639 #define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY_MASK 0xffffffff
1640 #define SMU_LCLK_DPM_STATE_7_CNTL_3__LCLK_FREQUENCY__SHIFT 0x0
1641 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1642 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1643 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1644 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1645 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1646 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1647 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1648 #define SMU_LCLK_DPM_STATE_0_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1649 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1650 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1651 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1652 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1653 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1654 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1655 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1656 #define SMU_LCLK_DPM_STATE_1_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1657 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1658 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1659 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1660 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1661 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1662 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1663 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1664 #define SMU_LCLK_DPM_STATE_2_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1665 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1666 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1667 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1668 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1669 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1670 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1671 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1672 #define SMU_LCLK_DPM_STATE_3_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1673 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1674 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1675 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1676 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1677 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1678 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1679 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1680 #define SMU_LCLK_DPM_STATE_4_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1681 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1682 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1683 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1684 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1685 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1686 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1687 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1688 #define SMU_LCLK_DPM_STATE_5_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1689 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1690 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1691 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1692 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1693 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1694 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1695 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1696 #define SMU_LCLK_DPM_STATE_6_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1697 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED_MASK 0xff
1698 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__RESERVED__SHIFT 0x0
1699 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL_MASK 0xff00
1700 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__LCLKBYPASSCNTL__SHIFT 0x8
1701 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE_MASK 0xff0000
1702 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ENABLED_FOR_THROTTLE__SHIFT 0x10
1703 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD_MASK 0xff000000
1704 #define SMU_LCLK_DPM_STATE_7_ACTIVITY_THRESHOLD__ACTIVITY_THRESHOLD__SHIFT 0x18
1705 #define GIO_PID_CONTROLLER_CNTL_0__K_I_MASK 0xffffffff
1706 #define GIO_PID_CONTROLLER_CNTL_0__K_I__SHIFT 0x0
1707 #define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM_MASK 0xffffffff
1708 #define GIO_PID_CONTROLLER_CNTL_1__LF_WINDUP_UPPER_LIM__SHIFT 0x0
1709 #define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM_MASK 0xffffffff
1710 #define GIO_PID_CONTROLLER_CNTL_2__LF_WINDUP_LOWER_LIM__SHIFT 0x0
1711 #define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION_MASK 0xffffffff
1712 #define GIO_PID_CONTROLLER_CNTL_3__STATE_PRECISION__SHIFT 0x0
1713 #define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION_MASK 0xffffffff
1714 #define GIO_PID_CONTROLLER_CNTL_4__LF_PRECISION__SHIFT 0x0
1715 #define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET_MASK 0xffffffff
1716 #define GIO_PID_CONTROLLER_CNTL_5__LF_OFFSET__SHIFT 0x0
1717 #define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE_MASK 0xffffffff
1718 #define GIO_PID_CONTROLLER_CNTL_6__MAX_STATE__SHIFT 0x0
1719 #define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION_MASK 0xffffffff
1720 #define GIO_PID_CONTROLLER_CNTL_7__MAX_LF_FRACTION__SHIFT 0x0
1721 #define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT_MASK 0xffffffff
1722 #define GIO_PID_CONTROLLER_CNTL_8__STATE_SHIFT__SHIFT 0x0
1723 #define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT_MASK 0xffffffff
1724 #define SMU_LCLK_DPM_LEVEL_COUNT__LCLK_DPM_LEVEL_COUNT__SHIFT 0x0
1725 #define SMU_LCLK_DPM_CNTL__RESERVED_MASK 0xff
1726 #define SMU_LCLK_DPM_CNTL__RESERVED__SHIFT 0x0
1727 #define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE_MASK 0xff00
1728 #define SMU_LCLK_DPM_CNTL__LCLK_DPM_BOOT_STATE__SHIFT 0x8
1729 #define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN_MASK 0xff0000
1730 #define SMU_LCLK_DPM_CNTL__VOLTAGE_CHG_EN__SHIFT 0x10
1731 #define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN_MASK 0xff000000
1732 #define SMU_LCLK_DPM_CNTL__LCLK_DPM_EN__SHIFT 0x18
1733 #define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE_MASK 0xff
1734 #define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__CURRENT_STATE__SHIFT 0x0
1735 #define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE_MASK 0xff00
1736 #define SMU_LCLK_DPM_CURRENT_AND_TARGET_STATE__TARGET_STATE__SHIFT 0x8
1737 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN_MASK 0xff
1738 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_THERMAL_THROTTLING_EN__SHIFT 0x0
1739 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL_MASK 0xff00
1740 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TEMPERATURE_SEL__SHIFT 0x8
1741 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE_MASK 0xff0000
1742 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__LCLK_TT_MODE__SHIFT 0x10
1743 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE_MASK 0xff000000
1744 #define SMU_LCLK_DPM_THERMAL_THROTTLING_CNTL__TT_HTC_ACTIVE__SHIFT 0x18
1745 #define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD_MASK 0xffff
1746 #define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__LOW_THRESHOLD__SHIFT 0x0
1747 #define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD_MASK 0xffff0000
1748 #define SMU_LCLK_DPM_THERMAL_THROTTLING_THRESHOLDS__HIGH_THRESHOLD__SHIFT 0x10
1749 #define PM_FUSES_1__BapmPstateVid_3_MASK 0xff
1750 #define PM_FUSES_1__BapmPstateVid_3__SHIFT 0x0
1751 #define PM_FUSES_1__BapmPstateVid_2_MASK 0xff00
1752 #define PM_FUSES_1__BapmPstateVid_2__SHIFT 0x8
1753 #define PM_FUSES_1__BapmPstateVid_1_MASK 0xff0000
1754 #define PM_FUSES_1__BapmPstateVid_1__SHIFT 0x10
1755 #define PM_FUSES_1__BapmPstateVid_0_MASK 0xff000000
1756 #define PM_FUSES_1__BapmPstateVid_0__SHIFT 0x18
1757 #define PM_FUSES_2__BapmPstateVid_7_MASK 0xff
1758 #define PM_FUSES_2__BapmPstateVid_7__SHIFT 0x0
1759 #define PM_FUSES_2__BapmPstateVid_6_MASK 0xff00
1760 #define PM_FUSES_2__BapmPstateVid_6__SHIFT 0x8
1761 #define PM_FUSES_2__BapmPstateVid_5_MASK 0xff0000
1762 #define PM_FUSES_2__BapmPstateVid_5__SHIFT 0x10
1763 #define PM_FUSES_2__BapmPstateVid_4_MASK 0xff000000
1764 #define PM_FUSES_2__BapmPstateVid_4__SHIFT 0x18
1765 #define PM_FUSES_3__BapmVddNbVidHiSidd_3_MASK 0xff
1766 #define PM_FUSES_3__BapmVddNbVidHiSidd_3__SHIFT 0x0
1767 #define PM_FUSES_3__BapmVddNbVidHiSidd_2_MASK 0xff00
1768 #define PM_FUSES_3__BapmVddNbVidHiSidd_2__SHIFT 0x8
1769 #define PM_FUSES_3__BapmVddNbVidHiSidd_1_MASK 0xff0000
1770 #define PM_FUSES_3__BapmVddNbVidHiSidd_1__SHIFT 0x10
1771 #define PM_FUSES_3__BapmVddNbVidHiSidd_0_MASK 0xff000000
1772 #define PM_FUSES_3__BapmVddNbVidHiSidd_0__SHIFT 0x18
1773 #define PM_FUSES_4__BapmVddNbVidLoSidd_2_MASK 0xff
1774 #define PM_FUSES_4__BapmVddNbVidLoSidd_2__SHIFT 0x0
1775 #define PM_FUSES_4__BapmVddNbVidLoSidd_1_MASK 0xff00
1776 #define PM_FUSES_4__BapmVddNbVidLoSidd_1__SHIFT 0x8
1777 #define PM_FUSES_4__BapmVddNbVidLoSidd_0_MASK 0xff0000
1778 #define PM_FUSES_4__BapmVddNbVidLoSidd_0__SHIFT 0x10
1779 #define PM_FUSES_4__BapmVddNbVidHiSidd_4_MASK 0xff000000
1780 #define PM_FUSES_4__BapmVddNbVidHiSidd_4__SHIFT 0x18
1781 #define PM_FUSES_5__CpuIdModel_MASK 0xff
1782 #define PM_FUSES_5__CpuIdModel__SHIFT 0x0
1783 #define PM_FUSES_5__SviLoadLineEn_MASK 0xff00
1784 #define PM_FUSES_5__SviLoadLineEn__SHIFT 0x8
1785 #define PM_FUSES_5__BapmVddNbVidLoSidd_4_MASK 0xff0000
1786 #define PM_FUSES_5__BapmVddNbVidLoSidd_4__SHIFT 0x10
1787 #define PM_FUSES_5__BapmVddNbVidLoSidd_3_MASK 0xff000000
1788 #define PM_FUSES_5__BapmVddNbVidLoSidd_3__SHIFT 0x18
1789 #define PM_FUSES_6__SviLoadLineTrimVddNb_MASK 0xff
1790 #define PM_FUSES_6__SviLoadLineTrimVddNb__SHIFT 0x0
1791 #define PM_FUSES_6__SviLoadLineTrimVdd_MASK 0xff00
1792 #define PM_FUSES_6__SviLoadLineTrimVdd__SHIFT 0x8
1793 #define PM_FUSES_6__SviLoadLineVddNb_MASK 0xff0000
1794 #define PM_FUSES_6__SviLoadLineVddNb__SHIFT 0x10
1795 #define PM_FUSES_6__SviLoadLineVdd_MASK 0xff000000
1796 #define PM_FUSES_6__SviLoadLineVdd__SHIFT 0x18
1797 #define PM_FUSES_7__BAPMTI_TjOffset_0_MASK 0xffff
1798 #define PM_FUSES_7__BAPMTI_TjOffset_0__SHIFT 0x0
1799 #define PM_FUSES_7__SviLoadLineOffsetVddNb_MASK 0xff0000
1800 #define PM_FUSES_7__SviLoadLineOffsetVddNb__SHIFT 0x10
1801 #define PM_FUSES_7__SviLoadLineOffsetVdd_MASK 0xff000000
1802 #define PM_FUSES_7__SviLoadLineOffsetVdd__SHIFT 0x18
1803 #define PM_FUSES_8__BAPMTI_TjOffset_2_MASK 0xffff
1804 #define PM_FUSES_8__BAPMTI_TjOffset_2__SHIFT 0x0
1805 #define PM_FUSES_8__BAPMTI_TjOffset_1_MASK 0xffff0000
1806 #define PM_FUSES_8__BAPMTI_TjOffset_1__SHIFT 0x10
1807 #define PM_FUSES_9__BAPMTI_TjHyst_1_MASK 0xffff
1808 #define PM_FUSES_9__BAPMTI_TjHyst_1__SHIFT 0x0
1809 #define PM_FUSES_9__BAPMTI_TjHyst_0_MASK 0xffff0000
1810 #define PM_FUSES_9__BAPMTI_TjHyst_0__SHIFT 0x10
1811 #define PM_FUSES_10__BAPMTI_TjMax_1_MASK 0xff
1812 #define PM_FUSES_10__BAPMTI_TjMax_1__SHIFT 0x0
1813 #define PM_FUSES_10__BAPMTI_TjMax_0_MASK 0xff00
1814 #define PM_FUSES_10__BAPMTI_TjMax_0__SHIFT 0x8
1815 #define PM_FUSES_10__BAPMTI_GpuTjHyst_MASK 0xffff0000
1816 #define PM_FUSES_10__BAPMTI_GpuTjHyst__SHIFT 0x10
1817 #define PM_FUSES_11__LhtcTmpLmt_MASK 0xff
1818 #define PM_FUSES_11__LhtcTmpLmt__SHIFT 0x0
1819 #define PM_FUSES_11__LhtcPstateLimit_MASK 0xff00
1820 #define PM_FUSES_11__LhtcPstateLimit__SHIFT 0x8
1821 #define PM_FUSES_11__LhtcHystLmt_MASK 0xff0000
1822 #define PM_FUSES_11__LhtcHystLmt__SHIFT 0x10
1823 #define PM_FUSES_11__BAPMTI_GpuTjMax_MASK 0xff000000
1824 #define PM_FUSES_11__BAPMTI_GpuTjMax__SHIFT 0x18
1825 #define PM_FUSES_12__MaxPwrCpu_1_MASK 0xff
1826 #define PM_FUSES_12__MaxPwrCpu_1__SHIFT 0x0
1827 #define PM_FUSES_12__MaxPwrCpu_0_MASK 0xff00
1828 #define PM_FUSES_12__MaxPwrCpu_0__SHIFT 0x8
1829 #define PM_FUSES_12__NomPwrCpu_1_MASK 0xff0000
1830 #define PM_FUSES_12__NomPwrCpu_1__SHIFT 0x10
1831 #define PM_FUSES_12__NomPwrCpu_0_MASK 0xff000000
1832 #define PM_FUSES_12__NomPwrCpu_0__SHIFT 0x18
1833 #define PM_FUSES_13__NomPwrGpu_MASK 0xffff
1834 #define PM_FUSES_13__NomPwrGpu__SHIFT 0x0
1835 #define PM_FUSES_13__MidPwrCpu_1_MASK 0xff0000
1836 #define PM_FUSES_13__MidPwrCpu_1__SHIFT 0x10
1837 #define PM_FUSES_13__MidPwrCpu_0_MASK 0xff000000
1838 #define PM_FUSES_13__MidPwrCpu_0__SHIFT 0x18
1839 #define PM_FUSES_14__MinPwrGpu_MASK 0xffff
1840 #define PM_FUSES_14__MinPwrGpu__SHIFT 0x0
1841 #define PM_FUSES_14__MaxPwrGpu_MASK 0xffff0000
1842 #define PM_FUSES_14__MaxPwrGpu__SHIFT 0x10
1843 #define PM_FUSES_15__PCIe3PhyOffset_MASK 0xff
1844 #define PM_FUSES_15__PCIe3PhyOffset__SHIFT 0x0
1845 #define PM_FUSES_15__PCIe2PhyOffset_MASK 0xff00
1846 #define PM_FUSES_15__PCIe2PhyOffset__SHIFT 0x8
1847 #define PM_FUSES_15__PCIe1PhyOffset_MASK 0xff0000
1848 #define PM_FUSES_15__PCIe1PhyOffset__SHIFT 0x10
1849 #define PM_FUSES_15__MidPwrTempHyst_MASK 0xff000000
1850 #define PM_FUSES_15__MidPwrTempHyst__SHIFT 0x18
1851 #define PM_FUSES_16__TDC_VDD_PkgLimit_MASK 0xffff
1852 #define PM_FUSES_16__TDC_VDD_PkgLimit__SHIFT 0x0
1853 #define PM_FUSES_16__DCE2PhyOffset_MASK 0xff0000
1854 #define PM_FUSES_16__DCE2PhyOffset__SHIFT 0x10
1855 #define PM_FUSES_16__DCE1PhyOffset_MASK 0xff000000
1856 #define PM_FUSES_16__DCE1PhyOffset__SHIFT 0x18
1857 #define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc_MASK 0xff
1858 #define PM_FUSES_17__TDC_VDDNB_ThrottleReleaseLimitPerc__SHIFT 0x0
1859 #define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc_MASK 0xff00
1860 #define PM_FUSES_17__TDC_VDD_ThrottleReleaseLimitPerc__SHIFT 0x8
1861 #define PM_FUSES_17__TDC_VDDNB_PkgLimit_MASK 0xffff0000
1862 #define PM_FUSES_17__TDC_VDDNB_PkgLimit__SHIFT 0x10
1863 #define PM_FUSES_18__TdcWaterfallCtl_MASK 0xff
1864 #define PM_FUSES_18__TdcWaterfallCtl__SHIFT 0x0
1865 #define PM_FUSES_18__TdpAgeRate_MASK 0xff00
1866 #define PM_FUSES_18__TdpAgeRate__SHIFT 0x8
1867 #define PM_FUSES_18__TdpAgeValue_MASK 0xff0000
1868 #define PM_FUSES_18__TdpAgeValue__SHIFT 0x10
1869 #define PM_FUSES_18__TDC_MAWt_MASK 0xff000000
1870 #define PM_FUSES_18__TDC_MAWt__SHIFT 0x18
1871 #define PM_FUSES_19__BapmLhtcCap_MASK 0xff
1872 #define PM_FUSES_19__BapmLhtcCap__SHIFT 0x0
1873 #define PM_FUSES_19__BapmFuseOverride_MASK 0xff00
1874 #define PM_FUSES_19__BapmFuseOverride__SHIFT 0x8
1875 #define PM_FUSES_19__SmuCoolingIndex_MASK 0xff0000
1876 #define PM_FUSES_19__SmuCoolingIndex__SHIFT 0x10
1877 #define PM_FUSES_19__SmuSocIndex_MASK 0xff000000
1878 #define PM_FUSES_19__SmuSocIndex__SHIFT 0x18
1879 #define PM_FUSES_20__SamClkDid_3_MASK 0xff
1880 #define PM_FUSES_20__SamClkDid_3__SHIFT 0x0
1881 #define PM_FUSES_20__SamClkDid_2_MASK 0xff00
1882 #define PM_FUSES_20__SamClkDid_2__SHIFT 0x8
1883 #define PM_FUSES_20__SamClkDid_1_MASK 0xff0000
1884 #define PM_FUSES_20__SamClkDid_1__SHIFT 0x10
1885 #define PM_FUSES_20__SamClkDid_0_MASK 0xff000000
1886 #define PM_FUSES_20__SamClkDid_0__SHIFT 0x18
1887 #define PM_FUSES_21__AmbientTempBase_MASK 0xff
1888 #define PM_FUSES_21__AmbientTempBase__SHIFT 0x0
1889 #define PM_FUSES_21__LPMLTemperatureMax_MASK 0xff00
1890 #define PM_FUSES_21__LPMLTemperatureMax__SHIFT 0x8
1891 #define PM_FUSES_21__LPMLTemperatureMin_MASK 0xff0000
1892 #define PM_FUSES_21__LPMLTemperatureMin__SHIFT 0x10
1893 #define PM_FUSES_21__SamClkDid_4_MASK 0xff000000
1894 #define PM_FUSES_21__SamClkDid_4__SHIFT 0x18
1895 #define PM_FUSES_22__LPMLTemperatureScaler_3_MASK 0xff
1896 #define PM_FUSES_22__LPMLTemperatureScaler_3__SHIFT 0x0
1897 #define PM_FUSES_22__LPMLTemperatureScaler_2_MASK 0xff00
1898 #define PM_FUSES_22__LPMLTemperatureScaler_2__SHIFT 0x8
1899 #define PM_FUSES_22__LPMLTemperatureScaler_1_MASK 0xff0000
1900 #define PM_FUSES_22__LPMLTemperatureScaler_1__SHIFT 0x10
1901 #define PM_FUSES_22__LPMLTemperatureScaler_0_MASK 0xff000000
1902 #define PM_FUSES_22__LPMLTemperatureScaler_0__SHIFT 0x18
1903 #define PM_FUSES_23__LPMLTemperatureScaler_7_MASK 0xff
1904 #define PM_FUSES_23__LPMLTemperatureScaler_7__SHIFT 0x0
1905 #define PM_FUSES_23__LPMLTemperatureScaler_6_MASK 0xff00
1906 #define PM_FUSES_23__LPMLTemperatureScaler_6__SHIFT 0x8
1907 #define PM_FUSES_23__LPMLTemperatureScaler_5_MASK 0xff0000
1908 #define PM_FUSES_23__LPMLTemperatureScaler_5__SHIFT 0x10
1909 #define PM_FUSES_23__LPMLTemperatureScaler_4_MASK 0xff000000
1910 #define PM_FUSES_23__LPMLTemperatureScaler_4__SHIFT 0x18
1911 #define PM_FUSES_24__LPMLTemperatureScaler_11_MASK 0xff
1912 #define PM_FUSES_24__LPMLTemperatureScaler_11__SHIFT 0x0
1913 #define PM_FUSES_24__LPMLTemperatureScaler_10_MASK 0xff00
1914 #define PM_FUSES_24__LPMLTemperatureScaler_10__SHIFT 0x8
1915 #define PM_FUSES_24__LPMLTemperatureScaler_9_MASK 0xff0000
1916 #define PM_FUSES_24__LPMLTemperatureScaler_9__SHIFT 0x10
1917 #define PM_FUSES_24__LPMLTemperatureScaler_8_MASK 0xff000000
1918 #define PM_FUSES_24__LPMLTemperatureScaler_8__SHIFT 0x18
1919 #define PM_FUSES_25__LPMLTemperatureScaler_15_MASK 0xff
1920 #define PM_FUSES_25__LPMLTemperatureScaler_15__SHIFT 0x0
1921 #define PM_FUSES_25__LPMLTemperatureScaler_14_MASK 0xff00
1922 #define PM_FUSES_25__LPMLTemperatureScaler_14__SHIFT 0x8
1923 #define PM_FUSES_25__LPMLTemperatureScaler_13_MASK 0xff0000
1924 #define PM_FUSES_25__LPMLTemperatureScaler_13__SHIFT 0x10
1925 #define PM_FUSES_25__LPMLTemperatureScaler_12_MASK 0xff000000
1926 #define PM_FUSES_25__LPMLTemperatureScaler_12__SHIFT 0x18
1927 #define PM_FUSES_26__GnbLPML_3_MASK 0xff
1928 #define PM_FUSES_26__GnbLPML_3__SHIFT 0x0
1929 #define PM_FUSES_26__GnbLPML_2_MASK 0xff00
1930 #define PM_FUSES_26__GnbLPML_2__SHIFT 0x8
1931 #define PM_FUSES_26__GnbLPML_1_MASK 0xff0000
1932 #define PM_FUSES_26__GnbLPML_1__SHIFT 0x10
1933 #define PM_FUSES_26__GnbLPML_0_MASK 0xff000000
1934 #define PM_FUSES_26__GnbLPML_0__SHIFT 0x18
1935 #define PM_FUSES_27__GnbLPML_7_MASK 0xff
1936 #define PM_FUSES_27__GnbLPML_7__SHIFT 0x0
1937 #define PM_FUSES_27__GnbLPML_6_MASK 0xff00
1938 #define PM_FUSES_27__GnbLPML_6__SHIFT 0x8
1939 #define PM_FUSES_27__GnbLPML_5_MASK 0xff0000
1940 #define PM_FUSES_27__GnbLPML_5__SHIFT 0x10
1941 #define PM_FUSES_27__GnbLPML_4_MASK 0xff000000
1942 #define PM_FUSES_27__GnbLPML_4__SHIFT 0x18
1943 #define PM_FUSES_28__GnbLPML_11_MASK 0xff
1944 #define PM_FUSES_28__GnbLPML_11__SHIFT 0x0
1945 #define PM_FUSES_28__GnbLPML_10_MASK 0xff00
1946 #define PM_FUSES_28__GnbLPML_10__SHIFT 0x8
1947 #define PM_FUSES_28__GnbLPML_9_MASK 0xff0000
1948 #define PM_FUSES_28__GnbLPML_9__SHIFT 0x10
1949 #define PM_FUSES_28__GnbLPML_8_MASK 0xff000000
1950 #define PM_FUSES_28__GnbLPML_8__SHIFT 0x18
1951 #define PM_FUSES_29__GnbLPML_15_MASK 0xff
1952 #define PM_FUSES_29__GnbLPML_15__SHIFT 0x0
1953 #define PM_FUSES_29__GnbLPML_14_MASK 0xff00
1954 #define PM_FUSES_29__GnbLPML_14__SHIFT 0x8
1955 #define PM_FUSES_29__GnbLPML_13_MASK 0xff0000
1956 #define PM_FUSES_29__GnbLPML_13__SHIFT 0x10
1957 #define PM_FUSES_29__GnbLPML_12_MASK 0xff000000
1958 #define PM_FUSES_29__GnbLPML_12__SHIFT 0x18
1959 #define PM_FUSES_30__NbVid_3_MASK 0xff
1960 #define PM_FUSES_30__NbVid_3__SHIFT 0x0
1961 #define PM_FUSES_30__NbVid_2_MASK 0xff00
1962 #define PM_FUSES_30__NbVid_2__SHIFT 0x8
1963 #define PM_FUSES_30__NbVid_1_MASK 0xff0000
1964 #define PM_FUSES_30__NbVid_1__SHIFT 0x10
1965 #define PM_FUSES_30__NbVid_0_MASK 0xff000000
1966 #define PM_FUSES_30__NbVid_0__SHIFT 0x18
1967 #define PM_FUSES_31__CpuVid_3_MASK 0xff
1968 #define PM_FUSES_31__CpuVid_3__SHIFT 0x0
1969 #define PM_FUSES_31__CpuVid_2_MASK 0xff00
1970 #define PM_FUSES_31__CpuVid_2__SHIFT 0x8
1971 #define PM_FUSES_31__CpuVid_1_MASK 0xff0000
1972 #define PM_FUSES_31__CpuVid_1__SHIFT 0x10
1973 #define PM_FUSES_31__CpuVid_0_MASK 0xff000000
1974 #define PM_FUSES_31__CpuVid_0__SHIFT 0x18
1975 #define PM_FUSES_32__CpuVid_7_MASK 0xff
1976 #define PM_FUSES_32__CpuVid_7__SHIFT 0x0
1977 #define PM_FUSES_32__CpuVid_6_MASK 0xff00
1978 #define PM_FUSES_32__CpuVid_6__SHIFT 0x8
1979 #define PM_FUSES_32__CpuVid_5_MASK 0xff0000
1980 #define PM_FUSES_32__CpuVid_5__SHIFT 0x10
1981 #define PM_FUSES_32__CpuVid_4_MASK 0xff000000
1982 #define PM_FUSES_32__CpuVid_4__SHIFT 0x18
1983 #define PM_FUSES_33__Tdp2Watt_MASK 0xffff
1984 #define PM_FUSES_33__Tdp2Watt__SHIFT 0x0
1985 #define PM_FUSES_33__GnbLPMLMinVid_MASK 0xff0000
1986 #define PM_FUSES_33__GnbLPMLMinVid__SHIFT 0x10
1987 #define PM_FUSES_33__GnbLPMLMaxVid_MASK 0xff000000
1988 #define PM_FUSES_33__GnbLPMLMaxVid__SHIFT 0x18
1989 #define PM_FUSES_34__Lpml_3_MASK 0xff
1990 #define PM_FUSES_34__Lpml_3__SHIFT 0x0
1991 #define PM_FUSES_34__Lpml_2_MASK 0xff00
1992 #define PM_FUSES_34__Lpml_2__SHIFT 0x8
1993 #define PM_FUSES_34__Lpml_1_MASK 0xff0000
1994 #define PM_FUSES_34__Lpml_1__SHIFT 0x10
1995 #define PM_FUSES_34__Lpml_0_MASK 0xff000000
1996 #define PM_FUSES_34__Lpml_0__SHIFT 0x18
1997 #define PM_FUSES_35__Lpml_7_MASK 0xff
1998 #define PM_FUSES_35__Lpml_7__SHIFT 0x0
1999 #define PM_FUSES_35__Lpml_6_MASK 0xff00
2000 #define PM_FUSES_35__Lpml_6__SHIFT 0x8
2001 #define PM_FUSES_35__Lpml_5_MASK 0xff0000
2002 #define PM_FUSES_35__Lpml_5__SHIFT 0x10
2003 #define PM_FUSES_35__Lpml_4_MASK 0xff000000
2004 #define PM_FUSES_35__Lpml_4__SHIFT 0x18
2005 #define PM_FUSES_36__Lpmv_3_MASK 0xff
2006 #define PM_FUSES_36__Lpmv_3__SHIFT 0x0
2007 #define PM_FUSES_36__Lpmv_2_MASK 0xff00
2008 #define PM_FUSES_36__Lpmv_2__SHIFT 0x8
2009 #define PM_FUSES_36__Lpmv_1_MASK 0xff0000
2010 #define PM_FUSES_36__Lpmv_1__SHIFT 0x10
2011 #define PM_FUSES_36__Lpmv_0_MASK 0xff000000
2012 #define PM_FUSES_36__Lpmv_0__SHIFT 0x18
2013 #define PM_FUSES_37__Lpmv_7_MASK 0xff
2014 #define PM_FUSES_37__Lpmv_7__SHIFT 0x0
2015 #define PM_FUSES_37__Lpmv_6_MASK 0xff00
2016 #define PM_FUSES_37__Lpmv_6__SHIFT 0x8
2017 #define PM_FUSES_37__Lpmv_5_MASK 0xff0000
2018 #define PM_FUSES_37__Lpmv_5__SHIFT 0x10
2019 #define PM_FUSES_37__Lpmv_4_MASK 0xff000000
2020 #define PM_FUSES_37__Lpmv_4__SHIFT 0x18
2021 #define PM_FUSES_38__EClkDid_3_MASK 0xff
2022 #define PM_FUSES_38__EClkDid_3__SHIFT 0x0
2023 #define PM_FUSES_38__EClkDid_2_MASK 0xff00
2024 #define PM_FUSES_38__EClkDid_2__SHIFT 0x8
2025 #define PM_FUSES_38__EClkDid_1_MASK 0xff0000
2026 #define PM_FUSES_38__EClkDid_1__SHIFT 0x10
2027 #define PM_FUSES_38__EClkDid_0_MASK 0xff000000
2028 #define PM_FUSES_38__EClkDid_0__SHIFT 0x18
2029 #define PM_FUSES_39__CoreDis_MASK 0xff
2030 #define PM_FUSES_39__CoreDis__SHIFT 0x0
2031 #define PM_FUSES_39__C6CstatePower_MASK 0xff00
2032 #define PM_FUSES_39__C6CstatePower__SHIFT 0x8
2033 #define PM_FUSES_39__BoostLock_MASK 0xff0000
2034 #define PM_FUSES_39__BoostLock__SHIFT 0x10
2035 #define PM_FUSES_39__EClkDid_4_MASK 0xff000000
2036 #define PM_FUSES_39__EClkDid_4__SHIFT 0x18
2037 #define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd_MASK 0xffff
2038 #define PM_FUSES_40__BapmVddNbBaseLeakageLoSidd__SHIFT 0x0
2039 #define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd_MASK 0xffff0000
2040 #define PM_FUSES_40__BapmVddNbBaseLeakageHiSidd__SHIFT 0x10
2041 #define PM_FUSES_41__VddNbVid_3_MASK 0xff
2042 #define PM_FUSES_41__VddNbVid_3__SHIFT 0x0
2043 #define PM_FUSES_41__VddNbVid_2_MASK 0xff00
2044 #define PM_FUSES_41__VddNbVid_2__SHIFT 0x8
2045 #define PM_FUSES_41__VddNbVid_1_MASK 0xff0000
2046 #define PM_FUSES_41__VddNbVid_1__SHIFT 0x10
2047 #define PM_FUSES_41__VddNbVid_0_MASK 0xff000000
2048 #define PM_FUSES_41__VddNbVid_0__SHIFT 0x18
2049 #define PM_FUSES_42__VddNbVidOffset_2_MASK 0xff
2050 #define PM_FUSES_42__VddNbVidOffset_2__SHIFT 0x0
2051 #define PM_FUSES_42__VddNbVidOffset_1_MASK 0xff00
2052 #define PM_FUSES_42__VddNbVidOffset_1__SHIFT 0x8
2053 #define PM_FUSES_42__VddNbVidOffset_0_MASK 0xff0000
2054 #define PM_FUSES_42__VddNbVidOffset_0__SHIFT 0x10
2055 #define PM_FUSES_42__VddNbVid_4_MASK 0xff000000
2056 #define PM_FUSES_42__VddNbVid_4__SHIFT 0x18
2057 #define PM_FUSES_43__BapmDisable_MASK 0xff
2058 #define PM_FUSES_43__BapmDisable__SHIFT 0x0
2059 #define PM_FUSES_43__CoreTdpLimit0_MASK 0xff00
2060 #define PM_FUSES_43__CoreTdpLimit0__SHIFT 0x8
2061 #define PM_FUSES_43__VddNbVidOffset_4_MASK 0xff0000
2062 #define PM_FUSES_43__VddNbVidOffset_4__SHIFT 0x10
2063 #define PM_FUSES_43__VddNbVidOffset_3_MASK 0xff000000
2064 #define PM_FUSES_43__VddNbVidOffset_3__SHIFT 0x18
2065 #define PM_FUSES_44__LpmlL2_3_MASK 0xff
2066 #define PM_FUSES_44__LpmlL2_3__SHIFT 0x0
2067 #define PM_FUSES_44__LpmlL2_2_MASK 0xff00
2068 #define PM_FUSES_44__LpmlL2_2__SHIFT 0x8
2069 #define PM_FUSES_44__LpmlL2_1_MASK 0xff0000
2070 #define PM_FUSES_44__LpmlL2_1__SHIFT 0x10
2071 #define PM_FUSES_44__LpmlL2_0_MASK 0xff000000
2072 #define PM_FUSES_44__LpmlL2_0__SHIFT 0x18
2073 #define PM_FUSES_45__LpmlL2_7_MASK 0xff
2074 #define PM_FUSES_45__LpmlL2_7__SHIFT 0x0
2075 #define PM_FUSES_45__LpmlL2_6_MASK 0xff00
2076 #define PM_FUSES_45__LpmlL2_6__SHIFT 0x8
2077 #define PM_FUSES_45__LpmlL2_5_MASK 0xff0000
2078 #define PM_FUSES_45__LpmlL2_5__SHIFT 0x10
2079 #define PM_FUSES_45__LpmlL2_4_MASK 0xff000000
2080 #define PM_FUSES_45__LpmlL2_4__SHIFT 0x18
2081 #define PM_FUSES_46__CoolPdmTc_MASK 0xff
2082 #define PM_FUSES_46__CoolPdmTc__SHIFT 0x0
2083 #define PM_FUSES_46__BaseCpcTdpLimit2_MASK 0xff00
2084 #define PM_FUSES_46__BaseCpcTdpLimit2__SHIFT 0x8
2085 #define PM_FUSES_46__BaseCpcTdpLimit1_MASK 0xff0000
2086 #define PM_FUSES_46__BaseCpcTdpLimit1__SHIFT 0x10
2087 #define PM_FUSES_46__BaseCpcTdpLimit_MASK 0xff000000
2088 #define PM_FUSES_46__BaseCpcTdpLimit__SHIFT 0x18
2089 #define PM_FUSES_47__CoolPdmThr2_MASK 0xff
2090 #define PM_FUSES_47__CoolPdmThr2__SHIFT 0x0
2091 #define PM_FUSES_47__CoolPdmThr1_MASK 0xff00
2092 #define PM_FUSES_47__CoolPdmThr1__SHIFT 0x8
2093 #define PM_FUSES_47__GpuPdmTc_MASK 0xff0000
2094 #define PM_FUSES_47__GpuPdmTc__SHIFT 0x10
2095 #define PM_FUSES_47__HeatPdmTc_MASK 0xff000000
2096 #define PM_FUSES_47__HeatPdmTc__SHIFT 0x18
2097 #define PM_FUSES_48__PkgPwr_MAWt_MASK 0xff
2098 #define PM_FUSES_48__PkgPwr_MAWt__SHIFT 0x0
2099 #define PM_FUSES_48__GpuActThr_MASK 0xff00
2100 #define PM_FUSES_48__GpuActThr__SHIFT 0x8
2101 #define PM_FUSES_48__HeatPdmThr2_MASK 0xff0000
2102 #define PM_FUSES_48__HeatPdmThr2__SHIFT 0x10
2103 #define PM_FUSES_48__HeatPdmThr1_MASK 0xff000000
2104 #define PM_FUSES_48__HeatPdmThr1__SHIFT 0x18
2105 #define PM_FUSES_49__SocketTdp_MASK 0xffff
2106 #define PM_FUSES_49__SocketTdp__SHIFT 0x0
2107 #define PM_FUSES_49__GpuPdmMult_MASK 0xffff0000
2108 #define PM_FUSES_49__GpuPdmMult__SHIFT 0x10
2109 #define PM_FUSES_50__Reserved2_MASK 0xffff
2110 #define PM_FUSES_50__Reserved2__SHIFT 0x0
2111 #define PM_FUSES_50__Reserved1_MASK 0xff0000
2112 #define PM_FUSES_50__Reserved1__SHIFT 0x10
2113 #define PM_FUSES_50__NumBoostStates_MASK 0xff000000
2114 #define PM_FUSES_50__NumBoostStates__SHIFT 0x18
2115 #define PM_FUSES_51__FUSE_DATA_MASK 0xffffffff
2116 #define PM_FUSES_51__FUSE_DATA__SHIFT 0x0
2117 #define PM_FUSES_52__FUSE_DATA_MASK 0xffffffff
2118 #define PM_FUSES_52__FUSE_DATA__SHIFT 0x0
2119 #define PM_FUSES_53__FUSE_DATA_MASK 0xffffffff
2120 #define PM_FUSES_53__FUSE_DATA__SHIFT 0x0
2121 #define PM_FUSES_54__FUSE_DATA_MASK 0xffffffff
2122 #define PM_FUSES_54__FUSE_DATA__SHIFT 0x0
2123 #define PM_FUSES_55__FUSE_DATA_MASK 0xffffffff
2124 #define PM_FUSES_55__FUSE_DATA__SHIFT 0x0
2125 #define PM_FUSES_56__FUSE_DATA_MASK 0xffffffff
2126 #define PM_FUSES_56__FUSE_DATA__SHIFT 0x0
2127 #define PM_FUSES_57__FUSE_DATA_MASK 0xffffffff
2128 #define PM_FUSES_57__FUSE_DATA__SHIFT 0x0
2129 #define PM_FUSES_58__FUSE_DATA_MASK 0xffffffff
2130 #define PM_FUSES_58__FUSE_DATA__SHIFT 0x0
2131 #define PM_FUSES_59__FUSE_DATA_MASK 0xffffffff
2132 #define PM_FUSES_59__FUSE_DATA__SHIFT 0x0
2133 #define PM_FUSES_60__FUSE_DATA_MASK 0xffffffff
2134 #define PM_FUSES_60__FUSE_DATA__SHIFT 0x0
2135 #define PM_FUSES_61__FUSE_DATA_MASK 0xffffffff
2136 #define PM_FUSES_61__FUSE_DATA__SHIFT 0x0
2137 #define PM_FUSES_62__FUSE_DATA_MASK 0xffffffff
2138 #define PM_FUSES_62__FUSE_DATA__SHIFT 0x0
2139 #define PM_FUSES_63__FUSE_DATA_MASK 0xffffffff
2140 #define PM_FUSES_63__FUSE_DATA__SHIFT 0x0
2141 #define PM_FUSES_64__FUSE_DATA_MASK 0xffffffff
2142 #define PM_FUSES_64__FUSE_DATA__SHIFT 0x0
2143 #define PM_FUSES_65__FUSE_DATA_MASK 0xffffffff
2144 #define PM_FUSES_65__FUSE_DATA__SHIFT 0x0
2145 #define FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK 0x1
2146 #define FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT 0x0
2147 #define FIRMWARE_FLAGS__RESERVED_MASK 0xfffffe
2148 #define FIRMWARE_FLAGS__RESERVED__SHIFT 0x1
2149 #define FIRMWARE_FLAGS__TEST_COUNT_MASK 0xff000000
2150 #define FIRMWARE_FLAGS__TEST_COUNT__SHIFT 0x18
2151 #define TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
2152 #define TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
2153 #define TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
2154 #define TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
2155 #define TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
2156 #define TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
2157 #define CURRENT_GNB_TEMP__TEMP_MASK 0x7ff
2158 #define CURRENT_GNB_TEMP__TEMP__SHIFT 0x0
2159 #define CURRENT_GLOBAL_TEMP__TEMP_MASK 0x7ff
2160 #define CURRENT_GLOBAL_TEMP__TEMP__SHIFT 0x0
2161 #define FEATURE_STATUS__SCLK_DPM_ON_MASK 0x1
2162 #define FEATURE_STATUS__SCLK_DPM_ON__SHIFT 0x0
2163 #define FEATURE_STATUS__MCLK_DPM_ON_MASK 0x2
2164 #define FEATURE_STATUS__MCLK_DPM_ON__SHIFT 0x1
2165 #define FEATURE_STATUS__LCLK_DPM_ON_MASK 0x4
2166 #define FEATURE_STATUS__LCLK_DPM_ON__SHIFT 0x2
2167 #define FEATURE_STATUS__UVD_DPM_ON_MASK 0x8
2168 #define FEATURE_STATUS__UVD_DPM_ON__SHIFT 0x3
2169 #define FEATURE_STATUS__VCE_DPM_ON_MASK 0x10
2170 #define FEATURE_STATUS__VCE_DPM_ON__SHIFT 0x4
2171 #define FEATURE_STATUS__ACP_DPM_ON_MASK 0x20
2172 #define FEATURE_STATUS__ACP_DPM_ON__SHIFT 0x5
2173 #define FEATURE_STATUS__SAMU_DPM_ON_MASK 0x40
2174 #define FEATURE_STATUS__SAMU_DPM_ON__SHIFT 0x6
2175 #define FEATURE_STATUS__PCIE_DPM_ON_MASK 0x80
2176 #define FEATURE_STATUS__PCIE_DPM_ON__SHIFT 0x7
2177 #define FEATURE_STATUS__BAPM_ON_MASK 0x100
2178 #define FEATURE_STATUS__BAPM_ON__SHIFT 0x8
2179 #define FEATURE_STATUS__LPMX_ON_MASK 0x200
2180 #define FEATURE_STATUS__LPMX_ON__SHIFT 0x9
2181 #define FEATURE_STATUS__NBDPM_ON_MASK 0x400
2182 #define FEATURE_STATUS__NBDPM_ON__SHIFT 0xa
2183 #define FEATURE_STATUS__LHTC_ON_MASK 0x800
2184 #define FEATURE_STATUS__LHTC_ON__SHIFT 0xb
2185 #define FEATURE_STATUS__VPC_ON_MASK 0x1000
2186 #define FEATURE_STATUS__VPC_ON__SHIFT 0xc
2187 #define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON_MASK 0x2000
2188 #define FEATURE_STATUS__VOLTAGE_CONTROLLER_ON__SHIFT 0xd
2189 #define FEATURE_STATUS__TDC_LIMIT_ON_MASK 0x4000
2190 #define FEATURE_STATUS__TDC_LIMIT_ON__SHIFT 0xe
2191 #define FEATURE_STATUS__GPU_CAC_ON_MASK 0x8000
2192 #define FEATURE_STATUS__GPU_CAC_ON__SHIFT 0xf
2193 #define FEATURE_STATUS__AVS_ON_MASK 0x10000
2194 #define FEATURE_STATUS__AVS_ON__SHIFT 0x10
2195 #define FEATURE_STATUS__SPMI_ON_MASK 0x20000
2196 #define FEATURE_STATUS__SPMI_ON__SHIFT 0x11
2197 #define FEATURE_STATUS__SCLK_DPM_FORCED_MASK 0x40000
2198 #define FEATURE_STATUS__SCLK_DPM_FORCED__SHIFT 0x12
2199 #define FEATURE_STATUS__MCLK_DPM_FORCED_MASK 0x80000
2200 #define FEATURE_STATUS__MCLK_DPM_FORCED__SHIFT 0x13
2201 #define FEATURE_STATUS__LCLK_DPM_FORCED_MASK 0x100000
2202 #define FEATURE_STATUS__LCLK_DPM_FORCED__SHIFT 0x14
2203 #define FEATURE_STATUS__PCIE_DPM_FORCED_MASK 0x200000
2204 #define FEATURE_STATUS__PCIE_DPM_FORCED__SHIFT 0x15
2205 #define FEATURE_STATUS__CLK_MON_ON_MASK 0x400000
2206 #define FEATURE_STATUS__CLK_MON_ON__SHIFT 0x16
2207 #define FEATURE_STATUS__RESERVED_MASK 0xff800000
2208 #define FEATURE_STATUS__RESERVED__SHIFT 0x17
2209 #define PCIE_PLL_RECONF__RECONF_WAIT_MASK 0xff
2210 #define PCIE_PLL_RECONF__RECONF_WAIT__SHIFT 0x0
2211 #define PCIE_PLL_RECONF__RECONF_WRAPPER_MASK 0xff00
2212 #define PCIE_PLL_RECONF__RECONF_WRAPPER__SHIFT 0x8
2213 #define PCIE_PLL_RECONF__SB_RELOCATE_EN_MASK 0xff0000
2214 #define PCIE_PLL_RECONF__SB_RELOCATE_EN__SHIFT 0x10
2215 #define PCIE_PLL_RECONF__SB_NEW_PORT_MASK 0xff000000
2216 #define PCIE_PLL_RECONF__SB_NEW_PORT__SHIFT 0x18
2217 #define PM_INTERVAL_CNTL_0__LCLK_DPM_MASK 0xff
2218 #define PM_INTERVAL_CNTL_0__LCLK_DPM__SHIFT 0x0
2219 #define PM_INTERVAL_CNTL_0__THERMAL_CNTL_MASK 0xff00
2220 #define PM_INTERVAL_CNTL_0__THERMAL_CNTL__SHIFT 0x8
2221 #define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL_MASK 0xff0000
2222 #define PM_INTERVAL_CNTL_0__VOLTAGE_CNTL__SHIFT 0x10
2223 #define PM_INTERVAL_CNTL_0__LOADLINE_MASK 0xff000000
2224 #define PM_INTERVAL_CNTL_0__LOADLINE__SHIFT 0x18
2225 #define PM_INTERVAL_CNTL_1__NB_DPM_MASK 0xff
2226 #define PM_INTERVAL_CNTL_1__NB_DPM__SHIFT 0x0
2227 #define PM_INTERVAL_CNTL_1__AVS_PERIOD_MASK 0xff00
2228 #define PM_INTERVAL_CNTL_1__AVS_PERIOD__SHIFT 0x8
2229 #define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD_MASK 0xff0000
2230 #define PM_INTERVAL_CNTL_1__PKGPWR_PERIOD__SHIFT 0x10
2231 #define PM_INTERVAL_CNTL_1__TDP_CNTL_MASK 0xff000000
2232 #define PM_INTERVAL_CNTL_1__TDP_CNTL__SHIFT 0x18
2233 #define PM_INTERVAL_CNTL_2__BAPM_PERIOD_MASK 0xff
2234 #define PM_INTERVAL_CNTL_2__BAPM_PERIOD__SHIFT 0x0
2235 #define PM_INTERVAL_CNTL_2__HTC_PERIOD_MASK 0xff00
2236 #define PM_INTERVAL_CNTL_2__HTC_PERIOD__SHIFT 0x8
2237 #define PM_INTERVAL_CNTL_2__TDC_PERIOD_MASK 0xff0000
2238 #define PM_INTERVAL_CNTL_2__TDC_PERIOD__SHIFT 0x10
2239 #define PM_INTERVAL_CNTL_2__LPMX_PERIOD_MASK 0xff000000
2240 #define PM_INTERVAL_CNTL_2__LPMX_PERIOD__SHIFT 0x18
2241 #define VPC_INTERVAL_CNTL__VPC_PERIOD_MASK 0xffffffff
2242 #define VPC_INTERVAL_CNTL__VPC_PERIOD__SHIFT 0x0
2243 #define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit_MASK 0xffffffff
2244 #define DISP_PHY_TDP_LIMIT__DisplayPhyTdpLimit__SHIFT 0x0
2245 #define FCH_PWR_CREDIT__FchPwrCredit_MASK 0xffffffff
2246 #define FCH_PWR_CREDIT__FchPwrCredit__SHIFT 0x0
2247 #define PKGPWR_MV_AVG__Avg_Pkg_Pwr_MASK 0xffffffff
2248 #define PKGPWR_MV_AVG__Avg_Pkg_Pwr__SHIFT 0x0
2249 #define PACKAGE_POWER__Pkg_power_MASK 0xffffffff
2250 #define PACKAGE_POWER__Pkg_power__SHIFT 0x0
2251 #define PKG_PWR_CNTL__CpcGpuPerfPri_MASK 0x1
2252 #define PKG_PWR_CNTL__CpcGpuPerfPri__SHIFT 0x0
2253 #define PKG_PWR_CNTL__PkgPwrLimit_MASK 0x1fffe
2254 #define PKG_PWR_CNTL__PkgPwrLimit__SHIFT 0x1
2255 #define PKG_PWR_CNTL__FchPwrCreditScale_MASK 0x7e0000
2256 #define PKG_PWR_CNTL__FchPwrCreditScale__SHIFT 0x11
2257 #define PKG_PWR_CNTL__PkgHystCoeff_MASK 0x1f800000
2258 #define PKG_PWR_CNTL__PkgHystCoeff__SHIFT 0x17
2259 #define PKG_PWR_CNTL__RESERVED_MASK 0xe0000000
2260 #define PKG_PWR_CNTL__RESERVED__SHIFT 0x1d
2261 #define PKG_PWR_STATUS__GnbMinLimitSetFlag_MASK 0x1
2262 #define PKG_PWR_STATUS__GnbMinLimitSetFlag__SHIFT 0x0
2263 #define PKG_PWR_STATUS__PstateLimitSetFlag_MASK 0x2
2264 #define PKG_PWR_STATUS__PstateLimitSetFlag__SHIFT 0x1
2265 #define PKG_PWR_STATUS__PkgPwrLimit_base_MASK 0x3fffc
2266 #define PKG_PWR_STATUS__PkgPwrLimit_base__SHIFT 0x2
2267 #define PKG_PWR_STATUS__RESERVED_MASK 0xfc0000
2268 #define PKG_PWR_STATUS__RESERVED__SHIFT 0x12
2269 #define PKG_PWR_STATUS__PkgPwr_MAWt_MASK 0xff000000
2270 #define PKG_PWR_STATUS__PkgPwr_MAWt__SHIFT 0x18
2271 #define DISP_PHY_CONFIG__Corner_MASK 0xff
2272 #define DISP_PHY_CONFIG__Corner__SHIFT 0x0
2273 #define DISP_PHY_CONFIG__DispPHYConfig_MASK 0xff00
2274 #define DISP_PHY_CONFIG__DispPHYConfig__SHIFT 0x8
2275 #define GPU_TDP_LIMIT__Gpu_Tdp_Limit_MASK 0xffff
2276 #define GPU_TDP_LIMIT__Gpu_Tdp_Limit__SHIFT 0x0
2277 #define GPU_TDP_LIMIT__Reserved_MASK 0xffff0000
2278 #define GPU_TDP_LIMIT__Reserved__SHIFT 0x10
2279 #define EXT_API_IN_DATA_0_0__byte0_MASK 0xff
2280 #define EXT_API_IN_DATA_0_0__byte0__SHIFT 0x0
2281 #define EXT_API_IN_DATA_0_0__byte1_MASK 0xff00
2282 #define EXT_API_IN_DATA_0_0__byte1__SHIFT 0x8
2283 #define EXT_API_IN_DATA_0_0__byte2_MASK 0xff0000
2284 #define EXT_API_IN_DATA_0_0__byte2__SHIFT 0x10
2285 #define EXT_API_IN_DATA_0_0__byte3_MASK 0xff000000
2286 #define EXT_API_IN_DATA_0_0__byte3__SHIFT 0x18
2287 #define EXT_API_IN_DATA_0_1__byte0_MASK 0xff
2288 #define EXT_API_IN_DATA_0_1__byte0__SHIFT 0x0
2289 #define EXT_API_IN_DATA_0_1__byte1_MASK 0xff00
2290 #define EXT_API_IN_DATA_0_1__byte1__SHIFT 0x8
2291 #define EXT_API_IN_DATA_0_1__byte2_MASK 0xff0000
2292 #define EXT_API_IN_DATA_0_1__byte2__SHIFT 0x10
2293 #define EXT_API_IN_DATA_0_1__byte3_MASK 0xff000000
2294 #define EXT_API_IN_DATA_0_1__byte3__SHIFT 0x18
2295 #define EXT_API_IN_DATA_0_2__byte0_MASK 0xff
2296 #define EXT_API_IN_DATA_0_2__byte0__SHIFT 0x0
2297 #define EXT_API_IN_DATA_0_2__byte1_MASK 0xff00
2298 #define EXT_API_IN_DATA_0_2__byte1__SHIFT 0x8
2299 #define EXT_API_IN_DATA_0_2__byte2_MASK 0xff0000
2300 #define EXT_API_IN_DATA_0_2__byte2__SHIFT 0x10
2301 #define EXT_API_IN_DATA_0_2__byte3_MASK 0xff000000
2302 #define EXT_API_IN_DATA_0_2__byte3__SHIFT 0x18
2303 #define EXT_API_IN_DATA_0_3__byte0_MASK 0xff
2304 #define EXT_API_IN_DATA_0_3__byte0__SHIFT 0x0
2305 #define EXT_API_IN_DATA_0_3__byte1_MASK 0xff00
2306 #define EXT_API_IN_DATA_0_3__byte1__SHIFT 0x8
2307 #define EXT_API_IN_DATA_0_3__byte2_MASK 0xff0000
2308 #define EXT_API_IN_DATA_0_3__byte2__SHIFT 0x10
2309 #define EXT_API_IN_DATA_0_3__byte3_MASK 0xff000000
2310 #define EXT_API_IN_DATA_0_3__byte3__SHIFT 0x18
2311 #define EXT_API_OUT_DATA_0_0__byte0_MASK 0xff
2312 #define EXT_API_OUT_DATA_0_0__byte0__SHIFT 0x0
2313 #define EXT_API_OUT_DATA_0_0__byte1_MASK 0xff00
2314 #define EXT_API_OUT_DATA_0_0__byte1__SHIFT 0x8
2315 #define EXT_API_OUT_DATA_0_0__byte2_MASK 0xff0000
2316 #define EXT_API_OUT_DATA_0_0__byte2__SHIFT 0x10
2317 #define EXT_API_OUT_DATA_0_0__byte3_MASK 0xff000000
2318 #define EXT_API_OUT_DATA_0_0__byte3__SHIFT 0x18
2319 #define EXT_API_OUT_DATA_0_1__byte0_MASK 0xff
2320 #define EXT_API_OUT_DATA_0_1__byte0__SHIFT 0x0
2321 #define EXT_API_OUT_DATA_0_1__byte1_MASK 0xff00
2322 #define EXT_API_OUT_DATA_0_1__byte1__SHIFT 0x8
2323 #define EXT_API_OUT_DATA_0_1__byte2_MASK 0xff0000
2324 #define EXT_API_OUT_DATA_0_1__byte2__SHIFT 0x10
2325 #define EXT_API_OUT_DATA_0_1__byte3_MASK 0xff000000
2326 #define EXT_API_OUT_DATA_0_1__byte3__SHIFT 0x18
2327 #define EXT_API_OUT_DATA_0_2__byte0_MASK 0xff
2328 #define EXT_API_OUT_DATA_0_2__byte0__SHIFT 0x0
2329 #define EXT_API_OUT_DATA_0_2__byte1_MASK 0xff00
2330 #define EXT_API_OUT_DATA_0_2__byte1__SHIFT 0x8
2331 #define EXT_API_OUT_DATA_0_2__byte2_MASK 0xff0000
2332 #define EXT_API_OUT_DATA_0_2__byte2__SHIFT 0x10
2333 #define EXT_API_OUT_DATA_0_2__byte3_MASK 0xff000000
2334 #define EXT_API_OUT_DATA_0_2__byte3__SHIFT 0x18
2335 #define EXT_API_OUT_DATA_0_3__byte0_MASK 0xff
2336 #define EXT_API_OUT_DATA_0_3__byte0__SHIFT 0x0
2337 #define EXT_API_OUT_DATA_0_3__byte1_MASK 0xff00
2338 #define EXT_API_OUT_DATA_0_3__byte1__SHIFT 0x8
2339 #define EXT_API_OUT_DATA_0_3__byte2_MASK 0xff0000
2340 #define EXT_API_OUT_DATA_0_3__byte2__SHIFT 0x10
2341 #define EXT_API_OUT_DATA_0_3__byte3_MASK 0xff000000
2342 #define EXT_API_OUT_DATA_0_3__byte3__SHIFT 0x18
2343 #define BAPM_PARAMETERS__MaxPwrCpu_1_MASK 0xff
2344 #define BAPM_PARAMETERS__MaxPwrCpu_1__SHIFT 0x0
2345 #define BAPM_PARAMETERS__NomPwrCpu_1_MASK 0xff00
2346 #define BAPM_PARAMETERS__NomPwrCpu_1__SHIFT 0x8
2347 #define BAPM_PARAMETERS__MaxPwrCpu_0_MASK 0xff0000
2348 #define BAPM_PARAMETERS__MaxPwrCpu_0__SHIFT 0x10
2349 #define BAPM_PARAMETERS__NomPwrCpu_0_MASK 0xff000000
2350 #define BAPM_PARAMETERS__NomPwrCpu_0__SHIFT 0x18
2351 #define BAPM_PARAMETERS_2__MaxPwrGpu_MASK 0xffff
2352 #define BAPM_PARAMETERS_2__MaxPwrGpu__SHIFT 0x0
2353 #define BAPM_PARAMETERS_2__NomPwrGpu_MASK 0xffff0000
2354 #define BAPM_PARAMETERS_2__NomPwrGpu__SHIFT 0x10
2355 #define BAPM_PARAMETERS_3__TjOffset_MASK 0xff
2356 #define BAPM_PARAMETERS_3__TjOffset__SHIFT 0x0
2357 #define BAPM_PARAMETERS_3__EnergyCntNorm_MASK 0x3ff00
2358 #define BAPM_PARAMETERS_3__EnergyCntNorm__SHIFT 0x8
2359 #define BAPM_PARAMETERS_3__Reserved_MASK 0xfffc0000
2360 #define BAPM_PARAMETERS_3__Reserved__SHIFT 0x12
2361 #define BAPM_PARAMETERS_4__MinPwrGpu_MASK 0xffff
2362 #define BAPM_PARAMETERS_4__MinPwrGpu__SHIFT 0x0
2363 #define BAPM_PARAMETERS_4__MidPwrCpu_1_MASK 0xff0000
2364 #define BAPM_PARAMETERS_4__MidPwrCpu_1__SHIFT 0x10
2365 #define BAPM_PARAMETERS_4__MidPwrCpu_0_MASK 0xff000000
2366 #define BAPM_PARAMETERS_4__MidPwrCpu_0__SHIFT 0x18
2367 #define SMU_SVI_TELEMETRY__Iddspike_OCP_MASK 0xffff
2368 #define SMU_SVI_TELEMETRY__Iddspike_OCP__SHIFT 0x0
2369 #define SMU_SVI_TELEMETRY__IddNbspike_OCP_MASK 0xffff0000
2370 #define SMU_SVI_TELEMETRY__IddNbspike_OCP__SHIFT 0x10
2371 #define BAPM_STATUS__THROTTLE_MASK 0xff
2372 #define BAPM_STATUS__THROTTLE__SHIFT 0x0
2373 #define BAPM_STATUS__THROTTLE_LAST_MASK 0xff00
2374 #define BAPM_STATUS__THROTTLE_LAST__SHIFT 0x8
2375 #define BAPM_STATUS__COUNT_CORE1_MASK 0xff0000
2376 #define BAPM_STATUS__COUNT_CORE1__SHIFT 0x10
2377 #define BAPM_STATUS__COUNT_CORE0_MASK 0xff000000
2378 #define BAPM_STATUS__COUNT_CORE0__SHIFT 0x18
2379 #define SMU_HTC_STATUS__HTC_ACTIVE_MASK 0x1
2380 #define SMU_HTC_STATUS__HTC_ACTIVE__SHIFT 0x0
2381 #define SMU_HTC_STATUS__Reserved_MASK 0xfffffffe
2382 #define SMU_HTC_STATUS__Reserved__SHIFT 0x1
2383 #define SMU_VPC_STATUS__AllCpuIdleLast_MASK 0x1
2384 #define SMU_VPC_STATUS__AllCpuIdleLast__SHIFT 0x0
2385 #define SMU_VPC_STATUS__Reserved_MASK 0xfffffffe
2386 #define SMU_VPC_STATUS__Reserved__SHIFT 0x1
2387 #define ENTITY_TEMPERATURES_1__CORE0_MASK 0xffffffff
2388 #define ENTITY_TEMPERATURES_1__CORE0__SHIFT 0x0
2389 #define ENTITY_TEMPERATURES_2__CORE1_MASK 0xffffffff
2390 #define ENTITY_TEMPERATURES_2__CORE1__SHIFT 0x0
2391 #define ENTITY_TEMPERATURES_3__GPU_MASK 0xffffffff
2392 #define ENTITY_TEMPERATURES_3__GPU__SHIFT 0x0
2393 #define CU_POWER__CU0_POWER_MASK 0xffff
2394 #define CU_POWER__CU0_POWER__SHIFT 0x0
2395 #define CU_POWER__CU1_POWER_MASK 0xffff0000
2396 #define CU_POWER__CU1_POWER__SHIFT 0x10
2397 #define GPU_POWER__IGPU_POWER_MASK 0xffff
2398 #define GPU_POWER__IGPU_POWER__SHIFT 0x0
2399 #define GPU_POWER__DGPU_POWER_MASK 0xffff0000
2400 #define GPU_POWER__DGPU_POWER__SHIFT 0x10
2401 #define NTE_POWER__NTE0_POWER_MASK 0xffff
2402 #define NTE_POWER__NTE0_POWER__SHIFT 0x0
2403 #define NTE_POWER__NTE1_POWER_MASK 0xffff0000
2404 #define NTE_POWER__NTE1_POWER__SHIFT 0x10
2405 #define TDC_STATUS__VDD_Boost_MASK 0xff
2406 #define TDC_STATUS__VDD_Boost__SHIFT 0x0
2407 #define TDC_STATUS__VDD_Throttle_MASK 0xff00
2408 #define TDC_STATUS__VDD_Throttle__SHIFT 0x8
2409 #define TDC_STATUS__VDDNB_Boost_MASK 0xff0000
2410 #define TDC_STATUS__VDDNB_Boost__SHIFT 0x10
2411 #define TDC_STATUS__VDDNB_Throttle_MASK 0xff000000
2412 #define TDC_STATUS__VDDNB_Throttle__SHIFT 0x18
2413 #define TDC_MV_AVERAGE__IDD_MASK 0xffff
2414 #define TDC_MV_AVERAGE__IDD__SHIFT 0x0
2415 #define TDC_MV_AVERAGE__IDDNB_MASK 0xffff0000
2416 #define TDC_MV_AVERAGE__IDDNB__SHIFT 0x10
2417 #define PM_CONFIG__Enable_VPC_Accumulators_MASK 0x1
2418 #define PM_CONFIG__Enable_VPC_Accumulators__SHIFT 0x0
2419 #define PM_CONFIG__Enable_BAPM_MASK 0x2
2420 #define PM_CONFIG__Enable_BAPM__SHIFT 0x1
2421 #define PM_CONFIG__Enable_TDC_Limit_MASK 0x4
2422 #define PM_CONFIG__Enable_TDC_Limit__SHIFT 0x2
2423 #define PM_CONFIG__Enable_LPMx_MASK 0x8
2424 #define PM_CONFIG__Enable_LPMx__SHIFT 0x3
2425 #define PM_CONFIG__Enable_HTC_Limit_MASK 0x10
2426 #define PM_CONFIG__Enable_HTC_Limit__SHIFT 0x4
2427 #define PM_CONFIG__Enable_NBDPM_MASK 0x20
2428 #define PM_CONFIG__Enable_NBDPM__SHIFT 0x5
2429 #define PM_CONFIG__Enable_LoadLine_MASK 0x40
2430 #define PM_CONFIG__Enable_LoadLine__SHIFT 0x6
2431 #define PM_CONFIG__Reserved_MASK 0xff80
2432 #define PM_CONFIG__Reserved__SHIFT 0x7
2433 #define PM_CONFIG__Override_VPC_Current_MASK 0x10000
2434 #define PM_CONFIG__Override_VPC_Current__SHIFT 0x10
2435 #define PM_CONFIG__Reserved1_MASK 0x60000
2436 #define PM_CONFIG__Reserved1__SHIFT 0x11
2437 #define PM_CONFIG__Override_Calc_Temp_MASK 0x80000
2438 #define PM_CONFIG__Override_Calc_Temp__SHIFT 0x13
2439 #define PM_CONFIG__Enable_Hybrid_Boost_MASK 0x100000
2440 #define PM_CONFIG__Enable_Hybrid_Boost__SHIFT 0x14
2441 #define PM_CONFIG__Reserved2_MASK 0xe00000
2442 #define PM_CONFIG__Reserved2__SHIFT 0x15
2443 #define PM_CONFIG__PSTATE_AllCpusIdle_MASK 0x7000000
2444 #define PM_CONFIG__PSTATE_AllCpusIdle__SHIFT 0x18
2445 #define PM_CONFIG__NBPSTATE_AllCpusIdle_MASK 0x8000000
2446 #define PM_CONFIG__NBPSTATE_AllCpusIdle__SHIFT 0x1b
2447 #define PM_CONFIG__Reserved3_MASK 0x10000000
2448 #define PM_CONFIG__Reserved3__SHIFT 0x1c
2449 #define PM_CONFIG__SVI_Mode_MASK 0x20000000
2450 #define PM_CONFIG__SVI_Mode__SHIFT 0x1d
2451 #define PM_CONFIG__Enable_PDM_MASK 0x40000000
2452 #define PM_CONFIG__Enable_PDM__SHIFT 0x1e
2453 #define PM_CONFIG__Enable_PKG_PWR_LIMIT_MASK 0x80000000
2454 #define PM_CONFIG__Enable_PKG_PWR_LIMIT__SHIFT 0x1f
2455 #define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
2456 #define TE0_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
2457 #define TE0_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
2458 #define TE0_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
2459 #define TE0_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
2460 #define TE0_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
2461 #define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
2462 #define TE1_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
2463 #define TE1_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
2464 #define TE1_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
2465 #define TE1_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
2466 #define TE1_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
2467 #define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR_MASK 0x3f
2468 #define TE2_TEMPERATURE_READ_ADDR__CSR_ADDR__SHIFT 0x0
2469 #define TE2_TEMPERATURE_READ_ADDR__TCEN_ID_MASK 0x3c0
2470 #define TE2_TEMPERATURE_READ_ADDR__TCEN_ID__SHIFT 0x6
2471 #define TE2_TEMPERATURE_READ_ADDR__RESERVED_MASK 0xfffffc00
2472 #define TE2_TEMPERATURE_READ_ADDR__RESERVED__SHIFT 0xa
2473 #define NB_DPM_CONFIG_1__Dpm0PgNbPsLo_MASK 0xff
2474 #define NB_DPM_CONFIG_1__Dpm0PgNbPsLo__SHIFT 0x0
2475 #define NB_DPM_CONFIG_1__Dpm0PgNbPsHi_MASK 0xff00
2476 #define NB_DPM_CONFIG_1__Dpm0PgNbPsHi__SHIFT 0x8
2477 #define NB_DPM_CONFIG_1__DpmXNbPsLo_MASK 0xff0000
2478 #define NB_DPM_CONFIG_1__DpmXNbPsLo__SHIFT 0x10
2479 #define NB_DPM_CONFIG_1__DpmXNbPsHi_MASK 0xff000000
2480 #define NB_DPM_CONFIG_1__DpmXNbPsHi__SHIFT 0x18
2481 #define NB_DPM_CONFIG_2__Hysteresis_MASK 0xff
2482 #define NB_DPM_CONFIG_2__Hysteresis__SHIFT 0x0
2483 #define NB_DPM_CONFIG_2__SkipPG_MASK 0xff00
2484 #define NB_DPM_CONFIG_2__SkipPG__SHIFT 0x8
2485 #define NB_DPM_CONFIG_2__SkipDPM0_MASK 0xff0000
2486 #define NB_DPM_CONFIG_2__SkipDPM0__SHIFT 0x10
2487 #define NB_DPM_CONFIG_2__EnablePSI1_MASK 0xff000000
2488 #define NB_DPM_CONFIG_2__EnablePSI1__SHIFT 0x18
2489 #define NB_DPM_CONFIG_3__RESERVED_MASK 0xffffff
2490 #define NB_DPM_CONFIG_3__RESERVED__SHIFT 0x0
2491 #define NB_DPM_CONFIG_3__EnableDpmPstatePoll_MASK 0xff000000
2492 #define NB_DPM_CONFIG_3__EnableDpmPstatePoll__SHIFT 0x18
2493 #define SMU_IDD_OVERRIDE__IDD_MASK 0xffff
2494 #define SMU_IDD_OVERRIDE__IDD__SHIFT 0x0
2495 #define SMU_IDD_OVERRIDE__IDDNB_MASK 0xffff0000
2496 #define SMU_IDD_OVERRIDE__IDDNB__SHIFT 0x10
2497 #define AVS_CONFIG__AvsEnabledForPstates_MASK 0xff
2498 #define AVS_CONFIG__AvsEnabledForPstates__SHIFT 0x0
2499 #define AVS_CONFIG__AvsOverrideEnabled_MASK 0x100
2500 #define AVS_CONFIG__AvsOverrideEnabled__SHIFT 0x8
2501 #define AVS_CONFIG__AvsPsmTempCompensation_MASK 0x200
2502 #define AVS_CONFIG__AvsPsmTempCompensation__SHIFT 0x9
2503 #define AVS_CONFIG__RESERVED1_MASK 0xfc00
2504 #define AVS_CONFIG__RESERVED1__SHIFT 0xa
2505 #define AVS_CONFIG__AvsOverrideOffset_MASK 0xff0000
2506 #define AVS_CONFIG__AvsOverrideOffset__SHIFT 0x10
2507 #define AVS_CONFIG__RESERVED_MASK 0xff000000
2508 #define AVS_CONFIG__RESERVED__SHIFT 0x18
2509 #define TDC_VRM_LIMIT__IDD_MASK 0xffff
2510 #define TDC_VRM_LIMIT__IDD__SHIFT 0x0
2511 #define TDC_VRM_LIMIT__IDDNB_MASK 0xffff0000
2512 #define TDC_VRM_LIMIT__IDDNB__SHIFT 0x10
2513 #define CU0_PSM_CONFIG__Psm4_MASK 0xff
2514 #define CU0_PSM_CONFIG__Psm4__SHIFT 0x0
2515 #define CU0_PSM_CONFIG__Psm3_MASK 0xff00
2516 #define CU0_PSM_CONFIG__Psm3__SHIFT 0x8
2517 #define CU0_PSM_CONFIG__Psm2_MASK 0xff0000
2518 #define CU0_PSM_CONFIG__Psm2__SHIFT 0x10
2519 #define CU0_PSM_CONFIG__Psm1_MASK 0xff000000
2520 #define CU0_PSM_CONFIG__Psm1__SHIFT 0x18
2521 #define CU1_PSM_CONFIG__Psm4_MASK 0xff
2522 #define CU1_PSM_CONFIG__Psm4__SHIFT 0x0
2523 #define CU1_PSM_CONFIG__Psm3_MASK 0xff00
2524 #define CU1_PSM_CONFIG__Psm3__SHIFT 0x8
2525 #define CU1_PSM_CONFIG__Psm2_MASK 0xff0000
2526 #define CU1_PSM_CONFIG__Psm2__SHIFT 0x10
2527 #define CU1_PSM_CONFIG__Psm1_MASK 0xff000000
2528 #define CU1_PSM_CONFIG__Psm1__SHIFT 0x18
2529 #define SPMI_CONFIG__SpmiTestCode_MASK 0xff
2530 #define SPMI_CONFIG__SpmiTestCode__SHIFT 0x0
2531 #define SPMI_CONFIG__SpmiTestData_MASK 0xff00
2532 #define SPMI_CONFIG__SpmiTestData__SHIFT 0x8
2533 #define SPMI_CONFIG__RESERVED_MASK 0xffff0000
2534 #define SPMI_CONFIG__RESERVED__SHIFT 0x10
2535 #define SPMI_SMC_CHAIN_ADDR__Addr_MASK 0xffffffff
2536 #define SPMI_SMC_CHAIN_ADDR__Addr__SHIFT 0x0
2537 #define SPMI_STATUS__OpDone_MASK 0xff
2538 #define SPMI_STATUS__OpDone__SHIFT 0x0
2539 #define SPMI_STATUS__OpFailed_MASK 0xff00
2540 #define SPMI_STATUS__OpFailed__SHIFT 0x8
2541 #define AVSNB_CONFIG__AvsEnabledForPstates_MASK 0xf
2542 #define AVSNB_CONFIG__AvsEnabledForPstates__SHIFT 0x0
2543 #define AVSNB_CONFIG__RESERVED0_MASK 0xf0
2544 #define AVSNB_CONFIG__RESERVED0__SHIFT 0x4
2545 #define AVSNB_CONFIG__AvsOverrideEnabled_MASK 0x100
2546 #define AVSNB_CONFIG__AvsOverrideEnabled__SHIFT 0x8
2547 #define AVSNB_CONFIG__AvsPsmTempCompensation_MASK 0x200
2548 #define AVSNB_CONFIG__AvsPsmTempCompensation__SHIFT 0x9
2549 #define AVSNB_CONFIG__RESERVED1_MASK 0xfc00
2550 #define AVSNB_CONFIG__RESERVED1__SHIFT 0xa
2551 #define AVSNB_CONFIG__AvsOverrideOffset_MASK 0xff0000
2552 #define AVSNB_CONFIG__AvsOverrideOffset__SHIFT 0x10
2553 #define AVSNB_CONFIG__RESERVED_MASK 0xff000000
2554 #define AVSNB_CONFIG__RESERVED__SHIFT 0x18
2555 #define HTC_CONFIG__CSR_ADDR_MASK 0x3f
2556 #define HTC_CONFIG__CSR_ADDR__SHIFT 0x0
2557 #define HTC_CONFIG__TCEN_ID_MASK 0x3c0
2558 #define HTC_CONFIG__TCEN_ID__SHIFT 0x6
2559 #define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT_MASK 0xff0000
2560 #define HTC_CONFIG__HTC_ACTIVE_PSTATE_LIMIT__SHIFT 0x10
2561 #define HTC_CONFIG__Reserved_MASK 0xff000000
2562 #define HTC_CONFIG__Reserved__SHIFT 0x18
2563 #define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
2564 #define AVS_CU0_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
2565 #define AVS_CU0_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
2566 #define AVS_CU0_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
2567 #define AVS_CU0_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
2568 #define AVS_CU0_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
2569 #define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
2570 #define AVS_CU1_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
2571 #define AVS_CU1_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
2572 #define AVS_CU1_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
2573 #define AVS_CU1_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
2574 #define AVS_CU1_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
2575 #define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
2576 #define AVS_GNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
2577 #define AVS_GNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
2578 #define AVS_GNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
2579 #define AVS_GNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
2580 #define AVS_GNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
2581 #define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr_MASK 0x3f
2582 #define AVS_UNB_TEMPERATURE_SENSOR__CsrAddr__SHIFT 0x0
2583 #define AVS_UNB_TEMPERATURE_SENSOR__TcenID_MASK 0x3c0
2584 #define AVS_UNB_TEMPERATURE_SENSOR__TcenID__SHIFT 0x6
2585 #define AVS_UNB_TEMPERATURE_SENSOR__RESERVED_MASK 0xfffffc00
2586 #define AVS_UNB_TEMPERATURE_SENSOR__RESERVED__SHIFT 0xa
2587 #define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS_MASK 0xffffffff
2588 #define SMU_MONITOR_PORT80_MMIO_ADDR__MMIO_ADDRESS__SHIFT 0x0
2589 #define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI_MASK 0xffffffff
2590 #define SMU_MONITOR_PORT80_MEMBASE_HI__MEMORY_BASE_HI__SHIFT 0x0
2591 #define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO_MASK 0xffffffff
2592 #define SMU_MONITOR_PORT80_MEMBASE_LO__MEMORY_BASE_LO__SHIFT 0x0
2593 #define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION_MASK 0xffff
2594 #define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_POSITION__SHIFT 0x0
2595 #define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE_MASK 0xffff0000
2596 #define SMU_MONITOR_PORT80_MEMSETUP__MEMORY_BUFFER_SIZE__SHIFT 0x10
2597 #define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW_MASK 0x1
2598 #define SMU_MONITOR_PORT80_CTRL__ENABLE_DRAM_SHADOW__SHIFT 0x0
2599 #define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW_MASK 0x2
2600 #define SMU_MONITOR_PORT80_CTRL__ENABLE_CSR_SHADOW__SHIFT 0x1
2601 #define SMU_MONITOR_PORT80_CTRL__RESERVED_MASK 0xfffc
2602 #define SMU_MONITOR_PORT80_CTRL__RESERVED__SHIFT 0x2
2603 #define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL_MASK 0xffff0000
2604 #define SMU_MONITOR_PORT80_CTRL__POLLING_INTERVAL__SHIFT 0x10
2605 #define SMU_TCEN_ALIVE__CORE_TCEN_ID_MASK 0xff
2606 #define SMU_TCEN_ALIVE__CORE_TCEN_ID__SHIFT 0x0
2607 #define SMU_TCEN_ALIVE__GNB_TCEN_ID_MASK 0xff00
2608 #define SMU_TCEN_ALIVE__GNB_TCEN_ID__SHIFT 0x8
2609 #define SMU_TCEN_ALIVE__RESERVED_MASK 0xffff0000
2610 #define SMU_TCEN_ALIVE__RESERVED__SHIFT 0x10
2611 #define PDM_STATUS__PDM_ENABLED_MASK 0x1
2612 #define PDM_STATUS__PDM_ENABLED__SHIFT 0x0
2613 #define PDM_STATUS__NewCpcTdpLimit_MASK 0x1fffe
2614 #define PDM_STATUS__NewCpcTdpLimit__SHIFT 0x1
2615 #define PDM_STATUS__NoofConnectedCores_MASK 0x1e0000
2616 #define PDM_STATUS__NoofConnectedCores__SHIFT 0x11
2617 #define PDM_STATUS__Reserved_MASK 0xffe00000
2618 #define PDM_STATUS__Reserved__SHIFT 0x15
2619 #define PDM_CNTL_1__BaseCoreTdpLimit0_MASK 0xff
2620 #define PDM_CNTL_1__BaseCoreTdpLimit0__SHIFT 0x0
2621 #define PDM_CNTL_1__BaseCoreTdpLimit1_MASK 0xff00
2622 #define PDM_CNTL_1__BaseCoreTdpLimit1__SHIFT 0x8
2623 #define PDM_CNTL_1__BaseCoreTdpLimit2_MASK 0xff0000
2624 #define PDM_CNTL_1__BaseCoreTdpLimit2__SHIFT 0x10
2625 #define PDM_CNTL_1__GpuPdmMult_MASK 0xff000000
2626 #define PDM_CNTL_1__GpuPdmMult__SHIFT 0x18
2627 #define PDM_CNTL_2__HeatPdmTc_MASK 0xff
2628 #define PDM_CNTL_2__HeatPdmTc__SHIFT 0x0
2629 #define PDM_CNTL_2__CoolPdmTc_MASK 0xff00
2630 #define PDM_CNTL_2__CoolPdmTc__SHIFT 0x8
2631 #define PDM_CNTL_2__GpuPdmTc_MASK 0xff0000
2632 #define PDM_CNTL_2__GpuPdmTc__SHIFT 0x10
2633 #define PDM_CNTL_2__GpuActThr_MASK 0xff000000
2634 #define PDM_CNTL_2__GpuActThr__SHIFT 0x18
2635 #define PDM_CNTL_3__HeatPdmThr1_MASK 0xff
2636 #define PDM_CNTL_3__HeatPdmThr1__SHIFT 0x0
2637 #define PDM_CNTL_3__HeatPdmThr2_MASK 0xff00
2638 #define PDM_CNTL_3__HeatPdmThr2__SHIFT 0x8
2639 #define PDM_CNTL_3__CoolPdmThr1_MASK 0xff0000
2640 #define PDM_CNTL_3__CoolPdmThr1__SHIFT 0x10
2641 #define PDM_CNTL_3__CoolPdmThr2_MASK 0xff000000
2642 #define PDM_CNTL_3__CoolPdmThr2__SHIFT 0x18
2643 #define SMU_PM_STATUS_0__DATA_MASK 0xffffffff
2644 #define SMU_PM_STATUS_0__DATA__SHIFT 0x0
2645 #define SMU_PM_STATUS_1__DATA_MASK 0xffffffff
2646 #define SMU_PM_STATUS_1__DATA__SHIFT 0x0
2647 #define SMU_PM_STATUS_2__DATA_MASK 0xffffffff
2648 #define SMU_PM_STATUS_2__DATA__SHIFT 0x0
2649 #define SMU_PM_STATUS_3__DATA_MASK 0xffffffff
2650 #define SMU_PM_STATUS_3__DATA__SHIFT 0x0
2651 #define SMU_PM_STATUS_4__DATA_MASK 0xffffffff
2652 #define SMU_PM_STATUS_4__DATA__SHIFT 0x0
2653 #define SMU_PM_STATUS_5__DATA_MASK 0xffffffff
2654 #define SMU_PM_STATUS_5__DATA__SHIFT 0x0
2655 #define SMU_PM_STATUS_6__DATA_MASK 0xffffffff
2656 #define SMU_PM_STATUS_6__DATA__SHIFT 0x0
2657 #define SMU_PM_STATUS_7__DATA_MASK 0xffffffff
2658 #define SMU_PM_STATUS_7__DATA__SHIFT 0x0
2659 #define SMU_PM_STATUS_8__DATA_MASK 0xffffffff
2660 #define SMU_PM_STATUS_8__DATA__SHIFT 0x0
2661 #define SMU_PM_STATUS_9__DATA_MASK 0xffffffff
2662 #define SMU_PM_STATUS_9__DATA__SHIFT 0x0
2663 #define SMU_PM_STATUS_10__DATA_MASK 0xffffffff
2664 #define SMU_PM_STATUS_10__DATA__SHIFT 0x0
2665 #define SMU_PM_STATUS_11__DATA_MASK 0xffffffff
2666 #define SMU_PM_STATUS_11__DATA__SHIFT 0x0
2667 #define SMU_PM_STATUS_12__DATA_MASK 0xffffffff
2668 #define SMU_PM_STATUS_12__DATA__SHIFT 0x0
2669 #define SMU_PM_STATUS_13__DATA_MASK 0xffffffff
2670 #define SMU_PM_STATUS_13__DATA__SHIFT 0x0
2671 #define SMU_PM_STATUS_14__DATA_MASK 0xffffffff
2672 #define SMU_PM_STATUS_14__DATA__SHIFT 0x0
2673 #define SMU_PM_STATUS_15__DATA_MASK 0xffffffff
2674 #define SMU_PM_STATUS_15__DATA__SHIFT 0x0
2675 #define SMU_PM_STATUS_16__DATA_MASK 0xffffffff
2676 #define SMU_PM_STATUS_16__DATA__SHIFT 0x0
2677 #define SMU_PM_STATUS_17__DATA_MASK 0xffffffff
2678 #define SMU_PM_STATUS_17__DATA__SHIFT 0x0
2679 #define SMU_PM_STATUS_18__DATA_MASK 0xffffffff
2680 #define SMU_PM_STATUS_18__DATA__SHIFT 0x0
2681 #define SMU_PM_STATUS_19__DATA_MASK 0xffffffff
2682 #define SMU_PM_STATUS_19__DATA__SHIFT 0x0
2683 #define SMU_PM_STATUS_20__DATA_MASK 0xffffffff
2684 #define SMU_PM_STATUS_20__DATA__SHIFT 0x0
2685 #define SMU_PM_STATUS_21__DATA_MASK 0xffffffff
2686 #define SMU_PM_STATUS_21__DATA__SHIFT 0x0
2687 #define SMU_PM_STATUS_22__DATA_MASK 0xffffffff
2688 #define SMU_PM_STATUS_22__DATA__SHIFT 0x0
2689 #define SMU_PM_STATUS_23__DATA_MASK 0xffffffff
2690 #define SMU_PM_STATUS_23__DATA__SHIFT 0x0
2691 #define SMU_PM_STATUS_24__DATA_MASK 0xffffffff
2692 #define SMU_PM_STATUS_24__DATA__SHIFT 0x0
2693 #define SMU_PM_STATUS_25__DATA_MASK 0xffffffff
2694 #define SMU_PM_STATUS_25__DATA__SHIFT 0x0
2695 #define SMU_PM_STATUS_26__DATA_MASK 0xffffffff
2696 #define SMU_PM_STATUS_26__DATA__SHIFT 0x0
2697 #define SMU_PM_STATUS_27__DATA_MASK 0xffffffff
2698 #define SMU_PM_STATUS_27__DATA__SHIFT 0x0
2699 #define SMU_PM_STATUS_28__DATA_MASK 0xffffffff
2700 #define SMU_PM_STATUS_28__DATA__SHIFT 0x0
2701 #define SMU_PM_STATUS_29__DATA_MASK 0xffffffff
2702 #define SMU_PM_STATUS_29__DATA__SHIFT 0x0
2703 #define SMU_PM_STATUS_30__DATA_MASK 0xffffffff
2704 #define SMU_PM_STATUS_30__DATA__SHIFT 0x0
2705 #define SMU_PM_STATUS_31__DATA_MASK 0xffffffff
2706 #define SMU_PM_STATUS_31__DATA__SHIFT 0x0
2707 #define SMU_PM_STATUS_32__DATA_MASK 0xffffffff
2708 #define SMU_PM_STATUS_32__DATA__SHIFT 0x0
2709 #define SMU_PM_STATUS_33__DATA_MASK 0xffffffff
2710 #define SMU_PM_STATUS_33__DATA__SHIFT 0x0
2711 #define SMU_PM_STATUS_34__DATA_MASK 0xffffffff
2712 #define SMU_PM_STATUS_34__DATA__SHIFT 0x0
2713 #define SMU_PM_STATUS_35__DATA_MASK 0xffffffff
2714 #define SMU_PM_STATUS_35__DATA__SHIFT 0x0
2715 #define SMU_PM_STATUS_36__DATA_MASK 0xffffffff
2716 #define SMU_PM_STATUS_36__DATA__SHIFT 0x0
2717 #define SMU_PM_STATUS_37__DATA_MASK 0xffffffff
2718 #define SMU_PM_STATUS_37__DATA__SHIFT 0x0
2719 #define SMU_PM_STATUS_38__DATA_MASK 0xffffffff
2720 #define SMU_PM_STATUS_38__DATA__SHIFT 0x0
2721 #define SMU_PM_STATUS_39__DATA_MASK 0xffffffff
2722 #define SMU_PM_STATUS_39__DATA__SHIFT 0x0
2723 #define SMU_PM_STATUS_40__DATA_MASK 0xffffffff
2724 #define SMU_PM_STATUS_40__DATA__SHIFT 0x0
2725 #define SMU_PM_STATUS_41__DATA_MASK 0xffffffff
2726 #define SMU_PM_STATUS_41__DATA__SHIFT 0x0
2727 #define SMU_PM_STATUS_42__DATA_MASK 0xffffffff
2728 #define SMU_PM_STATUS_42__DATA__SHIFT 0x0
2729 #define SMU_PM_STATUS_43__DATA_MASK 0xffffffff
2730 #define SMU_PM_STATUS_43__DATA__SHIFT 0x0
2731 #define SMU_PM_STATUS_44__DATA_MASK 0xffffffff
2732 #define SMU_PM_STATUS_44__DATA__SHIFT 0x0
2733 #define SMU_PM_STATUS_45__DATA_MASK 0xffffffff
2734 #define SMU_PM_STATUS_45__DATA__SHIFT 0x0
2735 #define SMU_PM_STATUS_46__DATA_MASK 0xffffffff
2736 #define SMU_PM_STATUS_46__DATA__SHIFT 0x0
2737 #define SMU_PM_STATUS_47__DATA_MASK 0xffffffff
2738 #define SMU_PM_STATUS_47__DATA__SHIFT 0x0
2739 #define SMU_PM_STATUS_48__DATA_MASK 0xffffffff
2740 #define SMU_PM_STATUS_48__DATA__SHIFT 0x0
2741 #define SMU_PM_STATUS_49__DATA_MASK 0xffffffff
2742 #define SMU_PM_STATUS_49__DATA__SHIFT 0x0
2743 #define SMU_PM_STATUS_50__DATA_MASK 0xffffffff
2744 #define SMU_PM_STATUS_50__DATA__SHIFT 0x0
2745 #define SMU_PM_STATUS_51__DATA_MASK 0xffffffff
2746 #define SMU_PM_STATUS_51__DATA__SHIFT 0x0
2747 #define SMU_PM_STATUS_52__DATA_MASK 0xffffffff
2748 #define SMU_PM_STATUS_52__DATA__SHIFT 0x0
2749 #define SMU_PM_STATUS_53__DATA_MASK 0xffffffff
2750 #define SMU_PM_STATUS_53__DATA__SHIFT 0x0
2751 #define SMU_PM_STATUS_54__DATA_MASK 0xffffffff
2752 #define SMU_PM_STATUS_54__DATA__SHIFT 0x0
2753 #define SMU_PM_STATUS_55__DATA_MASK 0xffffffff
2754 #define SMU_PM_STATUS_55__DATA__SHIFT 0x0
2755 #define SMU_PM_STATUS_56__DATA_MASK 0xffffffff
2756 #define SMU_PM_STATUS_56__DATA__SHIFT 0x0
2757 #define SMU_PM_STATUS_57__DATA_MASK 0xffffffff
2758 #define SMU_PM_STATUS_57__DATA__SHIFT 0x0
2759 #define SMU_PM_STATUS_58__DATA_MASK 0xffffffff
2760 #define SMU_PM_STATUS_58__DATA__SHIFT 0x0
2761 #define SMU_PM_STATUS_59__DATA_MASK 0xffffffff
2762 #define SMU_PM_STATUS_59__DATA__SHIFT 0x0
2763 #define SMU_PM_STATUS_60__DATA_MASK 0xffffffff
2764 #define SMU_PM_STATUS_60__DATA__SHIFT 0x0
2765 #define SMU_PM_STATUS_61__DATA_MASK 0xffffffff
2766 #define SMU_PM_STATUS_61__DATA__SHIFT 0x0
2767 #define SMU_PM_STATUS_62__DATA_MASK 0xffffffff
2768 #define SMU_PM_STATUS_62__DATA__SHIFT 0x0
2769 #define SMU_PM_STATUS_63__DATA_MASK 0xffffffff
2770 #define SMU_PM_STATUS_63__DATA__SHIFT 0x0
2771 #define SMU_PM_STATUS_64__DATA_MASK 0xffffffff
2772 #define SMU_PM_STATUS_64__DATA__SHIFT 0x0
2773 #define SMU_PM_STATUS_65__DATA_MASK 0xffffffff
2774 #define SMU_PM_STATUS_65__DATA__SHIFT 0x0
2775 #define SMU_PM_STATUS_66__DATA_MASK 0xffffffff
2776 #define SMU_PM_STATUS_66__DATA__SHIFT 0x0
2777 #define SMU_PM_STATUS_67__DATA_MASK 0xffffffff
2778 #define SMU_PM_STATUS_67__DATA__SHIFT 0x0
2779 #define SMU_PM_STATUS_68__DATA_MASK 0xffffffff
2780 #define SMU_PM_STATUS_68__DATA__SHIFT 0x0
2781 #define SMU_PM_STATUS_69__DATA_MASK 0xffffffff
2782 #define SMU_PM_STATUS_69__DATA__SHIFT 0x0
2783 #define SMU_PM_STATUS_70__DATA_MASK 0xffffffff
2784 #define SMU_PM_STATUS_70__DATA__SHIFT 0x0
2785 #define SMU_PM_STATUS_71__DATA_MASK 0xffffffff
2786 #define SMU_PM_STATUS_71__DATA__SHIFT 0x0
2787 #define SMU_PM_STATUS_72__DATA_MASK 0xffffffff
2788 #define SMU_PM_STATUS_72__DATA__SHIFT 0x0
2789 #define SMU_PM_STATUS_73__DATA_MASK 0xffffffff
2790 #define SMU_PM_STATUS_73__DATA__SHIFT 0x0
2791 #define SMU_PM_STATUS_74__DATA_MASK 0xffffffff
2792 #define SMU_PM_STATUS_74__DATA__SHIFT 0x0
2793 #define SMU_PM_STATUS_75__DATA_MASK 0xffffffff
2794 #define SMU_PM_STATUS_75__DATA__SHIFT 0x0
2795 #define SMU_PM_STATUS_76__DATA_MASK 0xffffffff
2796 #define SMU_PM_STATUS_76__DATA__SHIFT 0x0
2797 #define SMU_PM_STATUS_77__DATA_MASK 0xffffffff
2798 #define SMU_PM_STATUS_77__DATA__SHIFT 0x0
2799 #define SMU_PM_STATUS_78__DATA_MASK 0xffffffff
2800 #define SMU_PM_STATUS_78__DATA__SHIFT 0x0
2801 #define SMU_PM_STATUS_79__DATA_MASK 0xffffffff
2802 #define SMU_PM_STATUS_79__DATA__SHIFT 0x0
2803 #define SMU_PM_STATUS_80__DATA_MASK 0xffffffff
2804 #define SMU_PM_STATUS_80__DATA__SHIFT 0x0
2805 #define SMU_PM_STATUS_81__DATA_MASK 0xffffffff
2806 #define SMU_PM_STATUS_81__DATA__SHIFT 0x0
2807 #define SMU_PM_STATUS_82__DATA_MASK 0xffffffff
2808 #define SMU_PM_STATUS_82__DATA__SHIFT 0x0
2809 #define SMU_PM_STATUS_83__DATA_MASK 0xffffffff
2810 #define SMU_PM_STATUS_83__DATA__SHIFT 0x0
2811 #define SMU_PM_STATUS_84__DATA_MASK 0xffffffff
2812 #define SMU_PM_STATUS_84__DATA__SHIFT 0x0
2813 #define SMU_PM_STATUS_85__DATA_MASK 0xffffffff
2814 #define SMU_PM_STATUS_85__DATA__SHIFT 0x0
2815 #define SMU_PM_STATUS_86__DATA_MASK 0xffffffff
2816 #define SMU_PM_STATUS_86__DATA__SHIFT 0x0
2817 #define SMU_PM_STATUS_87__DATA_MASK 0xffffffff
2818 #define SMU_PM_STATUS_87__DATA__SHIFT 0x0
2819 #define SMU_PM_STATUS_88__DATA_MASK 0xffffffff
2820 #define SMU_PM_STATUS_88__DATA__SHIFT 0x0
2821 #define SMU_PM_STATUS_89__DATA_MASK 0xffffffff
2822 #define SMU_PM_STATUS_89__DATA__SHIFT 0x0
2823 #define SMU_PM_STATUS_90__DATA_MASK 0xffffffff
2824 #define SMU_PM_STATUS_90__DATA__SHIFT 0x0
2825 #define SMU_PM_STATUS_91__DATA_MASK 0xffffffff
2826 #define SMU_PM_STATUS_91__DATA__SHIFT 0x0
2827 #define SMU_PM_STATUS_92__DATA_MASK 0xffffffff
2828 #define SMU_PM_STATUS_92__DATA__SHIFT 0x0
2829 #define SMU_PM_STATUS_93__DATA_MASK 0xffffffff
2830 #define SMU_PM_STATUS_93__DATA__SHIFT 0x0
2831 #define SMU_PM_STATUS_94__DATA_MASK 0xffffffff
2832 #define SMU_PM_STATUS_94__DATA__SHIFT 0x0
2833 #define SMU_PM_STATUS_95__DATA_MASK 0xffffffff
2834 #define SMU_PM_STATUS_95__DATA__SHIFT 0x0
2835 #define SMU_PM_STATUS_96__DATA_MASK 0xffffffff
2836 #define SMU_PM_STATUS_96__DATA__SHIFT 0x0
2837 #define SMU_PM_STATUS_97__DATA_MASK 0xffffffff
2838 #define SMU_PM_STATUS_97__DATA__SHIFT 0x0
2839 #define SMU_PM_STATUS_98__DATA_MASK 0xffffffff
2840 #define SMU_PM_STATUS_98__DATA__SHIFT 0x0
2841 #define SMU_PM_STATUS_99__DATA_MASK 0xffffffff
2842 #define SMU_PM_STATUS_99__DATA__SHIFT 0x0
2843 #define SMU_PM_STATUS_100__DATA_MASK 0xffffffff
2844 #define SMU_PM_STATUS_100__DATA__SHIFT 0x0
2845 #define SMU_PM_STATUS_101__DATA_MASK 0xffffffff
2846 #define SMU_PM_STATUS_101__DATA__SHIFT 0x0
2847 #define SMU_PM_STATUS_102__DATA_MASK 0xffffffff
2848 #define SMU_PM_STATUS_102__DATA__SHIFT 0x0
2849 #define SMU_PM_STATUS_103__DATA_MASK 0xffffffff
2850 #define SMU_PM_STATUS_103__DATA__SHIFT 0x0
2851 #define SMU_PM_STATUS_104__DATA_MASK 0xffffffff
2852 #define SMU_PM_STATUS_104__DATA__SHIFT 0x0
2853 #define SMU_PM_STATUS_105__DATA_MASK 0xffffffff
2854 #define SMU_PM_STATUS_105__DATA__SHIFT 0x0
2855 #define SMU_PM_STATUS_106__DATA_MASK 0xffffffff
2856 #define SMU_PM_STATUS_106__DATA__SHIFT 0x0
2857 #define SMU_PM_STATUS_107__DATA_MASK 0xffffffff
2858 #define SMU_PM_STATUS_107__DATA__SHIFT 0x0
2859 #define SMU_PM_STATUS_108__DATA_MASK 0xffffffff
2860 #define SMU_PM_STATUS_108__DATA__SHIFT 0x0
2861 #define SMU_PM_STATUS_109__DATA_MASK 0xffffffff
2862 #define SMU_PM_STATUS_109__DATA__SHIFT 0x0
2863 #define SMU_PM_STATUS_110__DATA_MASK 0xffffffff
2864 #define SMU_PM_STATUS_110__DATA__SHIFT 0x0
2865 #define SMU_PM_STATUS_111__DATA_MASK 0xffffffff
2866 #define SMU_PM_STATUS_111__DATA__SHIFT 0x0
2867 #define SMU_PM_STATUS_112__DATA_MASK 0xffffffff
2868 #define SMU_PM_STATUS_112__DATA__SHIFT 0x0
2869 #define SMU_PM_STATUS_113__DATA_MASK 0xffffffff
2870 #define SMU_PM_STATUS_113__DATA__SHIFT 0x0
2871 #define SMU_PM_STATUS_114__DATA_MASK 0xffffffff
2872 #define SMU_PM_STATUS_114__DATA__SHIFT 0x0
2873 #define SMU_PM_STATUS_115__DATA_MASK 0xffffffff
2874 #define SMU_PM_STATUS_115__DATA__SHIFT 0x0
2875 #define SMU_PM_STATUS_116__DATA_MASK 0xffffffff
2876 #define SMU_PM_STATUS_116__DATA__SHIFT 0x0
2877 #define SMU_PM_STATUS_117__DATA_MASK 0xffffffff
2878 #define SMU_PM_STATUS_117__DATA__SHIFT 0x0
2879 #define SMU_PM_STATUS_118__DATA_MASK 0xffffffff
2880 #define SMU_PM_STATUS_118__DATA__SHIFT 0x0
2881 #define SMU_PM_STATUS_119__DATA_MASK 0xffffffff
2882 #define SMU_PM_STATUS_119__DATA__SHIFT 0x0
2883 #define SMU_PM_STATUS_120__DATA_MASK 0xffffffff
2884 #define SMU_PM_STATUS_120__DATA__SHIFT 0x0
2885 #define SMU_PM_STATUS_121__DATA_MASK 0xffffffff
2886 #define SMU_PM_STATUS_121__DATA__SHIFT 0x0
2887 #define SMU_PM_STATUS_122__DATA_MASK 0xffffffff
2888 #define SMU_PM_STATUS_122__DATA__SHIFT 0x0
2889 #define SMU_PM_STATUS_123__DATA_MASK 0xffffffff
2890 #define SMU_PM_STATUS_123__DATA__SHIFT 0x0
2891 #define SMU_PM_STATUS_124__DATA_MASK 0xffffffff
2892 #define SMU_PM_STATUS_124__DATA__SHIFT 0x0
2893 #define SMU_PM_STATUS_125__DATA_MASK 0xffffffff
2894 #define SMU_PM_STATUS_125__DATA__SHIFT 0x0
2895 #define SMU_PM_STATUS_126__DATA_MASK 0xffffffff
2896 #define SMU_PM_STATUS_126__DATA__SHIFT 0x0
2897 #define SMU_PM_STATUS_127__DATA_MASK 0xffffffff
2898 #define SMU_PM_STATUS_127__DATA__SHIFT 0x0
2899 #define CG_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x1
2900 #define CG_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0
2901 #define CG_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x2
2902 #define CG_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1
2903 #define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x4
2904 #define CG_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2
2905 #define CG_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x8
2906 #define CG_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3
2907 #define CG_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x10
2908 #define CG_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4
2909 #define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x20
2910 #define CG_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5
2911 #define CG_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0xff
2912 #define CG_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0
2913 #define CG_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0xff00
2914 #define CG_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8
2915 #define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD_MASK 0xff0000
2916 #define CG_THERMAL_INT_CTRL__GNB_TEMP_THRESHOLD__SHIFT 0x10
2917 #define CG_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x1000000
2918 #define CG_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18
2919 #define CG_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x2000000
2920 #define CG_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19
2921 #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x4000000
2922 #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a
2923 #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK_MASK 0x8000000
2924 #define CG_THERMAL_INT_CTRL__THERM_TRIGGER_CNB_MASK__SHIFT 0x1b
2925 #define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA_MASK 0x10000000
2926 #define CG_THERMAL_INT_CTRL__THERM_GNB_HW_ENA__SHIFT 0x1c
2927 #define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x1
2928 #define CG_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0
2929 #define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x2
2930 #define CG_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1
2931 #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x4
2932 #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2
2933 #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT_MASK 0x8
2934 #define CG_THERMAL_INT_STATUS__THERM_TRIGGER_CNB_DETECT__SHIFT 0x3
2935 #define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN_MASK 0x1
2936 #define GENERAL_PWRMGT__GLOBAL_PWRMGT_EN__SHIFT 0x0
2937 #define GENERAL_PWRMGT__STATIC_PM_EN_MASK 0x2
2938 #define GENERAL_PWRMGT__STATIC_PM_EN__SHIFT 0x1
2939 #define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS_MASK 0x4
2940 #define GENERAL_PWRMGT__THERMAL_PROTECTION_DIS__SHIFT 0x2
2941 #define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE_MASK 0x8
2942 #define GENERAL_PWRMGT__THERMAL_PROTECTION_TYPE__SHIFT 0x3
2943 #define GENERAL_PWRMGT__SW_SMIO_INDEX_MASK 0x40
2944 #define GENERAL_PWRMGT__SW_SMIO_INDEX__SHIFT 0x6
2945 #define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI_MASK 0x100
2946 #define GENERAL_PWRMGT__LOW_VOLT_D2_ACPI__SHIFT 0x8
2947 #define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI_MASK 0x200
2948 #define GENERAL_PWRMGT__LOW_VOLT_D3_ACPI__SHIFT 0x9
2949 #define GENERAL_PWRMGT__VOLT_PWRMGT_EN_MASK 0x400
2950 #define GENERAL_PWRMGT__VOLT_PWRMGT_EN__SHIFT 0xa
2951 #define GENERAL_PWRMGT__SPARE11_MASK 0x800
2952 #define GENERAL_PWRMGT__SPARE11__SHIFT 0xb
2953 #define GENERAL_PWRMGT__GPU_COUNTER_ACPI_MASK 0x4000
2954 #define GENERAL_PWRMGT__GPU_COUNTER_ACPI__SHIFT 0xe
2955 #define GENERAL_PWRMGT__GPU_COUNTER_CLK_MASK 0x8000
2956 #define GENERAL_PWRMGT__GPU_COUNTER_CLK__SHIFT 0xf
2957 #define GENERAL_PWRMGT__GPU_COUNTER_OFF_MASK 0x10000
2958 #define GENERAL_PWRMGT__GPU_COUNTER_OFF__SHIFT 0x10
2959 #define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF_MASK 0x20000
2960 #define GENERAL_PWRMGT__GPU_COUNTER_INTF_OFF__SHIFT 0x11
2961 #define GENERAL_PWRMGT__SPARE18_MASK 0x40000
2962 #define GENERAL_PWRMGT__SPARE18__SHIFT 0x12
2963 #define GENERAL_PWRMGT__ACPI_D3_VID_MASK 0x180000
2964 #define GENERAL_PWRMGT__ACPI_D3_VID__SHIFT 0x13
2965 #define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN_MASK 0x800000
2966 #define GENERAL_PWRMGT__DYN_SPREAD_SPECTRUM_EN__SHIFT 0x17
2967 #define GENERAL_PWRMGT__SPARE27_MASK 0x8000000
2968 #define GENERAL_PWRMGT__SPARE27__SHIFT 0x1b
2969 #define GENERAL_PWRMGT__SPARE_MASK 0xf0000000
2970 #define GENERAL_PWRMGT__SPARE__SHIFT 0x1c
2971 #define CNB_PWRMGT_CNTL__GNB_SLOW_MODE_MASK 0x3
2972 #define CNB_PWRMGT_CNTL__GNB_SLOW_MODE__SHIFT 0x0
2973 #define CNB_PWRMGT_CNTL__GNB_SLOW_MASK 0x4
2974 #define CNB_PWRMGT_CNTL__GNB_SLOW__SHIFT 0x2
2975 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1_MASK 0x8
2976 #define CNB_PWRMGT_CNTL__FORCE_NB_PS1__SHIFT 0x3
2977 #define CNB_PWRMGT_CNTL__DPM_ENABLED_MASK 0x10
2978 #define CNB_PWRMGT_CNTL__DPM_ENABLED__SHIFT 0x4
2979 #define CNB_PWRMGT_CNTL__SPARE_MASK 0xffffffe0
2980 #define CNB_PWRMGT_CNTL__SPARE__SHIFT 0x5
2981 #define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF_MASK 0x1
2982 #define SCLK_PWRMGT_CNTL__SCLK_PWRMGT_OFF__SHIFT 0x0
2983 #define SCLK_PWRMGT_CNTL__SCLK_LOW_D1_MASK 0x2
2984 #define SCLK_PWRMGT_CNTL__SCLK_LOW_D1__SHIFT 0x1
2985 #define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN_MASK 0x4
2986 #define SCLK_PWRMGT_CNTL__DYN_PWR_DOWN_EN__SHIFT 0x2
2987 #define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT_MASK 0x10
2988 #define SCLK_PWRMGT_CNTL__RESET_BUSY_CNT__SHIFT 0x4
2989 #define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT_MASK 0x20
2990 #define SCLK_PWRMGT_CNTL__RESET_SCLK_CNT__SHIFT 0x5
2991 #define SCLK_PWRMGT_CNTL__RESERVED_0_MASK 0x40
2992 #define SCLK_PWRMGT_CNTL__RESERVED_0__SHIFT 0x6
2993 #define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN_MASK 0x80
2994 #define SCLK_PWRMGT_CNTL__DYN_GFX_CLK_OFF_EN__SHIFT 0x7
2995 #define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON_MASK 0x100
2996 #define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_ON__SHIFT 0x8
2997 #define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF_MASK 0x200
2998 #define SCLK_PWRMGT_CNTL__GFX_CLK_REQUEST_OFF__SHIFT 0x9
2999 #define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF_MASK 0x400
3000 #define SCLK_PWRMGT_CNTL__GFX_CLK_FORCE_OFF__SHIFT 0xa
3001 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1_MASK 0x800
3002 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D1__SHIFT 0xb
3003 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2_MASK 0x1000
3004 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D2__SHIFT 0xc
3005 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3_MASK 0x2000
3006 #define SCLK_PWRMGT_CNTL__GFX_CLK_OFF_ACPI_D3__SHIFT 0xd
3007 #define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN_MASK 0x4000
3008 #define SCLK_PWRMGT_CNTL__DYN_LIGHT_SLEEP_EN__SHIFT 0xe
3009 #define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP_MASK 0x8000
3010 #define SCLK_PWRMGT_CNTL__AUTO_SCLK_PULSE_SKIP__SHIFT 0xf
3011 #define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER_MASK 0x1f0000
3012 #define SCLK_PWRMGT_CNTL__LIGHT_SLEEP_COUNTER__SHIFT 0x10
3013 #define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN_MASK 0x200000
3014 #define SCLK_PWRMGT_CNTL__DYNAMIC_PM_EN__SHIFT 0x15
3015 #define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL_MASK 0x400000
3016 #define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_CNTL__SHIFT 0x16
3017 #define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN_MASK 0x800000
3018 #define SCLK_PWRMGT_CNTL__DPM_DYN_PWR_DOWN_EN__SHIFT 0x17
3019 #define SCLK_PWRMGT_CNTL__RESERVED_3_MASK 0x1000000
3020 #define SCLK_PWRMGT_CNTL__RESERVED_3__SHIFT 0x18
3021 #define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN_MASK 0x2000000
3022 #define SCLK_PWRMGT_CNTL__VOLTAGE_UPDATE_EN__SHIFT 0x19
3023 #define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT_MASK 0x10000000
3024 #define SCLK_PWRMGT_CNTL__FORCE_PM0_INTERRUPT__SHIFT 0x1c
3025 #define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT_MASK 0x20000000
3026 #define SCLK_PWRMGT_CNTL__FORCE_PM1_INTERRUPT__SHIFT 0x1d
3027 #define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN_MASK 0x40000000
3028 #define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_EN__SHIFT 0x1e
3029 #define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE_MASK 0x80000000
3030 #define SCLK_PWRMGT_CNTL__GFX_VOLTAGE_CHANGE_MODE__SHIFT 0x1f
3031 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE_MASK 0xf
3032 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARGET_STATE__SHIFT 0x0
3033 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE_MASK 0xf0
3034 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURRENT_STATE__SHIFT 0x4
3035 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX_MASK 0xf00
3036 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_MCLK_INDEX__SHIFT 0x8
3037 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX_MASK 0xf000
3038 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_MCLK_INDEX__SHIFT 0xc
3039 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX_MASK 0x1f0000
3040 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_SCLK_INDEX__SHIFT 0x10
3041 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX_MASK 0x3e00000
3042 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_SCLK_INDEX__SHIFT 0x15
3043 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX_MASK 0x1c000000
3044 #define TARGET_AND_CURRENT_PROFILE_INDEX__CURR_LCLK_INDEX__SHIFT 0x1a
3045 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX_MASK 0xe0000000
3046 #define TARGET_AND_CURRENT_PROFILE_INDEX__TARG_LCLK_INDEX__SHIFT 0x1d
3047 #define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3048 #define CG_FREQ_TRAN_VOTING_0__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3049 #define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3050 #define CG_FREQ_TRAN_VOTING_0__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3051 #define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3052 #define CG_FREQ_TRAN_VOTING_0__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3053 #define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3054 #define CG_FREQ_TRAN_VOTING_0__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3055 #define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3056 #define CG_FREQ_TRAN_VOTING_0__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3057 #define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3058 #define CG_FREQ_TRAN_VOTING_0__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3059 #define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3060 #define CG_FREQ_TRAN_VOTING_0__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3061 #define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3062 #define CG_FREQ_TRAN_VOTING_0__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3063 #define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3064 #define CG_FREQ_TRAN_VOTING_0__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3065 #define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3066 #define CG_FREQ_TRAN_VOTING_0__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3067 #define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3068 #define CG_FREQ_TRAN_VOTING_0__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3069 #define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3070 #define CG_FREQ_TRAN_VOTING_0__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3071 #define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3072 #define CG_FREQ_TRAN_VOTING_0__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3073 #define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3074 #define CG_FREQ_TRAN_VOTING_0__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3075 #define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3076 #define CG_FREQ_TRAN_VOTING_0__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3077 #define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3078 #define CG_FREQ_TRAN_VOTING_0__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3079 #define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3080 #define CG_FREQ_TRAN_VOTING_0__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3081 #define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3082 #define CG_FREQ_TRAN_VOTING_0__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3083 #define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3084 #define CG_FREQ_TRAN_VOTING_0__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3085 #define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3086 #define CG_FREQ_TRAN_VOTING_0__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3087 #define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3088 #define CG_FREQ_TRAN_VOTING_0__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3089 #define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3090 #define CG_FREQ_TRAN_VOTING_0__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3091 #define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3092 #define CG_FREQ_TRAN_VOTING_0__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3093 #define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3094 #define CG_FREQ_TRAN_VOTING_0__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3095 #define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3096 #define CG_FREQ_TRAN_VOTING_0__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3097 #define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3098 #define CG_FREQ_TRAN_VOTING_0__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3099 #define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3100 #define CG_FREQ_TRAN_VOTING_0__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3101 #define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3102 #define CG_FREQ_TRAN_VOTING_0__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3103 #define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3104 #define CG_FREQ_TRAN_VOTING_0__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3105 #define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3106 #define CG_FREQ_TRAN_VOTING_0__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3107 #define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3108 #define CG_FREQ_TRAN_VOTING_0__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3109 #define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3110 #define CG_FREQ_TRAN_VOTING_1__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3111 #define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3112 #define CG_FREQ_TRAN_VOTING_1__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3113 #define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3114 #define CG_FREQ_TRAN_VOTING_1__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3115 #define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3116 #define CG_FREQ_TRAN_VOTING_1__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3117 #define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3118 #define CG_FREQ_TRAN_VOTING_1__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3119 #define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3120 #define CG_FREQ_TRAN_VOTING_1__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3121 #define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3122 #define CG_FREQ_TRAN_VOTING_1__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3123 #define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3124 #define CG_FREQ_TRAN_VOTING_1__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3125 #define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3126 #define CG_FREQ_TRAN_VOTING_1__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3127 #define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3128 #define CG_FREQ_TRAN_VOTING_1__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3129 #define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3130 #define CG_FREQ_TRAN_VOTING_1__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3131 #define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3132 #define CG_FREQ_TRAN_VOTING_1__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3133 #define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3134 #define CG_FREQ_TRAN_VOTING_1__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3135 #define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3136 #define CG_FREQ_TRAN_VOTING_1__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3137 #define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3138 #define CG_FREQ_TRAN_VOTING_1__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3139 #define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3140 #define CG_FREQ_TRAN_VOTING_1__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3141 #define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3142 #define CG_FREQ_TRAN_VOTING_1__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3143 #define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3144 #define CG_FREQ_TRAN_VOTING_1__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3145 #define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3146 #define CG_FREQ_TRAN_VOTING_1__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3147 #define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3148 #define CG_FREQ_TRAN_VOTING_1__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3149 #define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3150 #define CG_FREQ_TRAN_VOTING_1__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3151 #define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3152 #define CG_FREQ_TRAN_VOTING_1__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3153 #define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3154 #define CG_FREQ_TRAN_VOTING_1__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3155 #define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3156 #define CG_FREQ_TRAN_VOTING_1__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3157 #define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3158 #define CG_FREQ_TRAN_VOTING_1__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3159 #define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3160 #define CG_FREQ_TRAN_VOTING_1__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3161 #define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3162 #define CG_FREQ_TRAN_VOTING_1__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3163 #define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3164 #define CG_FREQ_TRAN_VOTING_1__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3165 #define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3166 #define CG_FREQ_TRAN_VOTING_1__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3167 #define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3168 #define CG_FREQ_TRAN_VOTING_1__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3169 #define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3170 #define CG_FREQ_TRAN_VOTING_1__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3171 #define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3172 #define CG_FREQ_TRAN_VOTING_2__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3173 #define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3174 #define CG_FREQ_TRAN_VOTING_2__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3175 #define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3176 #define CG_FREQ_TRAN_VOTING_2__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3177 #define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3178 #define CG_FREQ_TRAN_VOTING_2__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3179 #define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3180 #define CG_FREQ_TRAN_VOTING_2__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3181 #define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3182 #define CG_FREQ_TRAN_VOTING_2__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3183 #define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3184 #define CG_FREQ_TRAN_VOTING_2__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3185 #define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3186 #define CG_FREQ_TRAN_VOTING_2__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3187 #define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3188 #define CG_FREQ_TRAN_VOTING_2__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3189 #define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3190 #define CG_FREQ_TRAN_VOTING_2__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3191 #define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3192 #define CG_FREQ_TRAN_VOTING_2__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3193 #define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3194 #define CG_FREQ_TRAN_VOTING_2__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3195 #define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3196 #define CG_FREQ_TRAN_VOTING_2__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3197 #define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3198 #define CG_FREQ_TRAN_VOTING_2__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3199 #define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3200 #define CG_FREQ_TRAN_VOTING_2__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3201 #define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3202 #define CG_FREQ_TRAN_VOTING_2__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3203 #define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3204 #define CG_FREQ_TRAN_VOTING_2__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3205 #define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3206 #define CG_FREQ_TRAN_VOTING_2__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3207 #define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3208 #define CG_FREQ_TRAN_VOTING_2__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3209 #define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3210 #define CG_FREQ_TRAN_VOTING_2__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3211 #define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3212 #define CG_FREQ_TRAN_VOTING_2__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3213 #define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3214 #define CG_FREQ_TRAN_VOTING_2__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3215 #define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3216 #define CG_FREQ_TRAN_VOTING_2__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3217 #define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3218 #define CG_FREQ_TRAN_VOTING_2__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3219 #define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3220 #define CG_FREQ_TRAN_VOTING_2__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3221 #define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3222 #define CG_FREQ_TRAN_VOTING_2__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3223 #define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3224 #define CG_FREQ_TRAN_VOTING_2__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3225 #define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3226 #define CG_FREQ_TRAN_VOTING_2__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3227 #define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3228 #define CG_FREQ_TRAN_VOTING_2__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3229 #define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3230 #define CG_FREQ_TRAN_VOTING_2__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3231 #define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3232 #define CG_FREQ_TRAN_VOTING_2__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3233 #define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3234 #define CG_FREQ_TRAN_VOTING_3__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3235 #define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3236 #define CG_FREQ_TRAN_VOTING_3__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3237 #define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3238 #define CG_FREQ_TRAN_VOTING_3__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3239 #define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3240 #define CG_FREQ_TRAN_VOTING_3__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3241 #define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3242 #define CG_FREQ_TRAN_VOTING_3__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3243 #define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3244 #define CG_FREQ_TRAN_VOTING_3__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3245 #define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3246 #define CG_FREQ_TRAN_VOTING_3__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3247 #define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3248 #define CG_FREQ_TRAN_VOTING_3__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3249 #define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3250 #define CG_FREQ_TRAN_VOTING_3__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3251 #define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3252 #define CG_FREQ_TRAN_VOTING_3__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3253 #define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3254 #define CG_FREQ_TRAN_VOTING_3__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3255 #define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3256 #define CG_FREQ_TRAN_VOTING_3__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3257 #define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3258 #define CG_FREQ_TRAN_VOTING_3__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3259 #define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3260 #define CG_FREQ_TRAN_VOTING_3__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3261 #define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3262 #define CG_FREQ_TRAN_VOTING_3__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3263 #define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3264 #define CG_FREQ_TRAN_VOTING_3__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3265 #define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3266 #define CG_FREQ_TRAN_VOTING_3__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3267 #define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3268 #define CG_FREQ_TRAN_VOTING_3__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3269 #define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3270 #define CG_FREQ_TRAN_VOTING_3__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3271 #define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3272 #define CG_FREQ_TRAN_VOTING_3__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3273 #define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3274 #define CG_FREQ_TRAN_VOTING_3__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3275 #define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3276 #define CG_FREQ_TRAN_VOTING_3__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3277 #define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3278 #define CG_FREQ_TRAN_VOTING_3__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3279 #define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3280 #define CG_FREQ_TRAN_VOTING_3__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3281 #define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3282 #define CG_FREQ_TRAN_VOTING_3__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3283 #define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3284 #define CG_FREQ_TRAN_VOTING_3__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3285 #define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3286 #define CG_FREQ_TRAN_VOTING_3__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3287 #define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3288 #define CG_FREQ_TRAN_VOTING_3__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3289 #define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3290 #define CG_FREQ_TRAN_VOTING_3__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3291 #define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3292 #define CG_FREQ_TRAN_VOTING_3__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3293 #define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3294 #define CG_FREQ_TRAN_VOTING_3__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3295 #define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3296 #define CG_FREQ_TRAN_VOTING_4__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3297 #define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3298 #define CG_FREQ_TRAN_VOTING_4__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3299 #define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3300 #define CG_FREQ_TRAN_VOTING_4__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3301 #define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3302 #define CG_FREQ_TRAN_VOTING_4__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3303 #define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3304 #define CG_FREQ_TRAN_VOTING_4__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3305 #define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3306 #define CG_FREQ_TRAN_VOTING_4__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3307 #define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3308 #define CG_FREQ_TRAN_VOTING_4__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3309 #define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3310 #define CG_FREQ_TRAN_VOTING_4__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3311 #define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3312 #define CG_FREQ_TRAN_VOTING_4__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3313 #define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3314 #define CG_FREQ_TRAN_VOTING_4__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3315 #define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3316 #define CG_FREQ_TRAN_VOTING_4__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3317 #define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3318 #define CG_FREQ_TRAN_VOTING_4__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3319 #define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3320 #define CG_FREQ_TRAN_VOTING_4__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3321 #define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3322 #define CG_FREQ_TRAN_VOTING_4__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3323 #define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3324 #define CG_FREQ_TRAN_VOTING_4__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3325 #define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3326 #define CG_FREQ_TRAN_VOTING_4__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3327 #define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3328 #define CG_FREQ_TRAN_VOTING_4__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3329 #define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3330 #define CG_FREQ_TRAN_VOTING_4__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3331 #define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3332 #define CG_FREQ_TRAN_VOTING_4__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3333 #define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3334 #define CG_FREQ_TRAN_VOTING_4__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3335 #define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3336 #define CG_FREQ_TRAN_VOTING_4__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3337 #define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3338 #define CG_FREQ_TRAN_VOTING_4__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3339 #define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3340 #define CG_FREQ_TRAN_VOTING_4__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3341 #define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3342 #define CG_FREQ_TRAN_VOTING_4__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3343 #define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3344 #define CG_FREQ_TRAN_VOTING_4__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3345 #define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3346 #define CG_FREQ_TRAN_VOTING_4__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3347 #define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3348 #define CG_FREQ_TRAN_VOTING_4__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3349 #define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3350 #define CG_FREQ_TRAN_VOTING_4__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3351 #define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3352 #define CG_FREQ_TRAN_VOTING_4__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3353 #define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3354 #define CG_FREQ_TRAN_VOTING_4__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3355 #define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3356 #define CG_FREQ_TRAN_VOTING_4__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3357 #define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3358 #define CG_FREQ_TRAN_VOTING_5__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3359 #define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3360 #define CG_FREQ_TRAN_VOTING_5__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3361 #define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3362 #define CG_FREQ_TRAN_VOTING_5__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3363 #define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3364 #define CG_FREQ_TRAN_VOTING_5__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3365 #define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3366 #define CG_FREQ_TRAN_VOTING_5__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3367 #define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3368 #define CG_FREQ_TRAN_VOTING_5__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3369 #define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3370 #define CG_FREQ_TRAN_VOTING_5__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3371 #define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3372 #define CG_FREQ_TRAN_VOTING_5__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3373 #define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3374 #define CG_FREQ_TRAN_VOTING_5__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3375 #define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3376 #define CG_FREQ_TRAN_VOTING_5__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3377 #define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3378 #define CG_FREQ_TRAN_VOTING_5__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3379 #define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3380 #define CG_FREQ_TRAN_VOTING_5__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3381 #define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3382 #define CG_FREQ_TRAN_VOTING_5__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3383 #define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3384 #define CG_FREQ_TRAN_VOTING_5__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3385 #define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3386 #define CG_FREQ_TRAN_VOTING_5__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3387 #define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3388 #define CG_FREQ_TRAN_VOTING_5__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3389 #define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3390 #define CG_FREQ_TRAN_VOTING_5__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3391 #define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3392 #define CG_FREQ_TRAN_VOTING_5__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3393 #define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3394 #define CG_FREQ_TRAN_VOTING_5__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3395 #define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3396 #define CG_FREQ_TRAN_VOTING_5__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3397 #define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3398 #define CG_FREQ_TRAN_VOTING_5__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3399 #define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3400 #define CG_FREQ_TRAN_VOTING_5__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3401 #define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3402 #define CG_FREQ_TRAN_VOTING_5__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3403 #define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3404 #define CG_FREQ_TRAN_VOTING_5__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3405 #define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3406 #define CG_FREQ_TRAN_VOTING_5__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3407 #define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3408 #define CG_FREQ_TRAN_VOTING_5__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3409 #define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3410 #define CG_FREQ_TRAN_VOTING_5__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3411 #define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3412 #define CG_FREQ_TRAN_VOTING_5__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3413 #define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3414 #define CG_FREQ_TRAN_VOTING_5__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3415 #define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3416 #define CG_FREQ_TRAN_VOTING_5__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3417 #define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3418 #define CG_FREQ_TRAN_VOTING_5__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3419 #define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3420 #define CG_FREQ_TRAN_VOTING_6__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3421 #define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3422 #define CG_FREQ_TRAN_VOTING_6__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3423 #define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3424 #define CG_FREQ_TRAN_VOTING_6__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3425 #define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3426 #define CG_FREQ_TRAN_VOTING_6__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3427 #define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3428 #define CG_FREQ_TRAN_VOTING_6__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3429 #define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3430 #define CG_FREQ_TRAN_VOTING_6__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3431 #define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3432 #define CG_FREQ_TRAN_VOTING_6__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3433 #define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3434 #define CG_FREQ_TRAN_VOTING_6__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3435 #define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3436 #define CG_FREQ_TRAN_VOTING_6__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3437 #define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3438 #define CG_FREQ_TRAN_VOTING_6__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3439 #define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3440 #define CG_FREQ_TRAN_VOTING_6__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3441 #define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3442 #define CG_FREQ_TRAN_VOTING_6__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3443 #define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3444 #define CG_FREQ_TRAN_VOTING_6__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3445 #define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3446 #define CG_FREQ_TRAN_VOTING_6__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3447 #define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3448 #define CG_FREQ_TRAN_VOTING_6__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3449 #define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3450 #define CG_FREQ_TRAN_VOTING_6__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3451 #define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3452 #define CG_FREQ_TRAN_VOTING_6__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3453 #define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3454 #define CG_FREQ_TRAN_VOTING_6__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3455 #define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3456 #define CG_FREQ_TRAN_VOTING_6__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3457 #define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3458 #define CG_FREQ_TRAN_VOTING_6__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3459 #define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3460 #define CG_FREQ_TRAN_VOTING_6__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3461 #define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3462 #define CG_FREQ_TRAN_VOTING_6__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3463 #define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3464 #define CG_FREQ_TRAN_VOTING_6__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3465 #define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3466 #define CG_FREQ_TRAN_VOTING_6__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3467 #define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3468 #define CG_FREQ_TRAN_VOTING_6__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3469 #define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3470 #define CG_FREQ_TRAN_VOTING_6__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3471 #define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3472 #define CG_FREQ_TRAN_VOTING_6__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3473 #define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3474 #define CG_FREQ_TRAN_VOTING_6__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3475 #define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3476 #define CG_FREQ_TRAN_VOTING_6__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3477 #define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3478 #define CG_FREQ_TRAN_VOTING_6__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3479 #define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3480 #define CG_FREQ_TRAN_VOTING_6__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3481 #define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN_MASK 0x1
3482 #define CG_FREQ_TRAN_VOTING_7__BIF_FREQ_THROTTLING_VOTE_EN__SHIFT 0x0
3483 #define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN_MASK 0x2
3484 #define CG_FREQ_TRAN_VOTING_7__HDP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1
3485 #define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN_MASK 0x4
3486 #define CG_FREQ_TRAN_VOTING_7__ROM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x2
3487 #define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN_MASK 0x8
3488 #define CG_FREQ_TRAN_VOTING_7__IH_SEM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x3
3489 #define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x10
3490 #define CG_FREQ_TRAN_VOTING_7__PDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x4
3491 #define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN_MASK 0x20
3492 #define CG_FREQ_TRAN_VOTING_7__DRM_FREQ_THROTTLING_VOTE_EN__SHIFT 0x5
3493 #define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN_MASK 0x40
3494 #define CG_FREQ_TRAN_VOTING_7__IDCT_FREQ_THROTTLING_VOTE_EN__SHIFT 0x6
3495 #define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN_MASK 0x80
3496 #define CG_FREQ_TRAN_VOTING_7__ACP_FREQ_THROTTLING_VOTE_EN__SHIFT 0x7
3497 #define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN_MASK 0x100
3498 #define CG_FREQ_TRAN_VOTING_7__SDMA_FREQ_THROTTLING_VOTE_EN__SHIFT 0x8
3499 #define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN_MASK 0x200
3500 #define CG_FREQ_TRAN_VOTING_7__UVD_FREQ_THROTTLING_VOTE_EN__SHIFT 0x9
3501 #define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN_MASK 0x400
3502 #define CG_FREQ_TRAN_VOTING_7__VCE_FREQ_THROTTLING_VOTE_EN__SHIFT 0xa
3503 #define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN_MASK 0x800
3504 #define CG_FREQ_TRAN_VOTING_7__DC_AZ_FREQ_THROTTLING_VOTE_EN__SHIFT 0xb
3505 #define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN_MASK 0x1000
3506 #define CG_FREQ_TRAN_VOTING_7__SAM_FREQ_THROTTLING_VOTE_EN__SHIFT 0xc
3507 #define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN_MASK 0x2000
3508 #define CG_FREQ_TRAN_VOTING_7__AVP_FREQ_THROTTLING_VOTE_EN__SHIFT 0xd
3509 #define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN_MASK 0x4000
3510 #define CG_FREQ_TRAN_VOTING_7__GRBM_0_FREQ_THROTTLING_VOTE_EN__SHIFT 0xe
3511 #define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN_MASK 0x8000
3512 #define CG_FREQ_TRAN_VOTING_7__GRBM_1_FREQ_THROTTLING_VOTE_EN__SHIFT 0xf
3513 #define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN_MASK 0x10000
3514 #define CG_FREQ_TRAN_VOTING_7__GRBM_2_FREQ_THROTTLING_VOTE_EN__SHIFT 0x10
3515 #define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN_MASK 0x20000
3516 #define CG_FREQ_TRAN_VOTING_7__GRBM_3_FREQ_THROTTLING_VOTE_EN__SHIFT 0x11
3517 #define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN_MASK 0x40000
3518 #define CG_FREQ_TRAN_VOTING_7__GRBM_4_FREQ_THROTTLING_VOTE_EN__SHIFT 0x12
3519 #define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN_MASK 0x80000
3520 #define CG_FREQ_TRAN_VOTING_7__GRBM_5_FREQ_THROTTLING_VOTE_EN__SHIFT 0x13
3521 #define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN_MASK 0x100000
3522 #define CG_FREQ_TRAN_VOTING_7__GRBM_6_FREQ_THROTTLING_VOTE_EN__SHIFT 0x14
3523 #define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN_MASK 0x200000
3524 #define CG_FREQ_TRAN_VOTING_7__GRBM_7_FREQ_THROTTLING_VOTE_EN__SHIFT 0x15
3525 #define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN_MASK 0x400000
3526 #define CG_FREQ_TRAN_VOTING_7__GRBM_8_FREQ_THROTTLING_VOTE_EN__SHIFT 0x16
3527 #define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN_MASK 0x800000
3528 #define CG_FREQ_TRAN_VOTING_7__GRBM_9_FREQ_THROTTLING_VOTE_EN__SHIFT 0x17
3529 #define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN_MASK 0x1000000
3530 #define CG_FREQ_TRAN_VOTING_7__GRBM_10_FREQ_THROTTLING_VOTE_EN__SHIFT 0x18
3531 #define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN_MASK 0x2000000
3532 #define CG_FREQ_TRAN_VOTING_7__GRBM_11_FREQ_THROTTLING_VOTE_EN__SHIFT 0x19
3533 #define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN_MASK 0x4000000
3534 #define CG_FREQ_TRAN_VOTING_7__GRBM_12_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1a
3535 #define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN_MASK 0x8000000
3536 #define CG_FREQ_TRAN_VOTING_7__GRBM_13_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1b
3537 #define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN_MASK 0x10000000
3538 #define CG_FREQ_TRAN_VOTING_7__GRBM_14_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1c
3539 #define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN_MASK 0x20000000
3540 #define CG_FREQ_TRAN_VOTING_7__GRBM_15_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1d
3541 #define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN_MASK 0x40000000
3542 #define CG_FREQ_TRAN_VOTING_7__RLC_FREQ_THROTTLING_VOTE_EN__SHIFT 0x1e
3543 #define PLL_TEST_CNTL__TST_SRC_SEL_MASK 0xf
3544 #define PLL_TEST_CNTL__TST_SRC_SEL__SHIFT 0x0
3545 #define PLL_TEST_CNTL__TST_REF_SEL_MASK 0xf0
3546 #define PLL_TEST_CNTL__TST_REF_SEL__SHIFT 0x4
3547 #define PLL_TEST_CNTL__REF_TEST_COUNT_MASK 0x7f00
3548 #define PLL_TEST_CNTL__REF_TEST_COUNT__SHIFT 0x8
3549 #define PLL_TEST_CNTL__TST_RESET_MASK 0x8000
3550 #define PLL_TEST_CNTL__TST_RESET__SHIFT 0xf
3551 #define PLL_TEST_CNTL__TEST_COUNT_MASK 0xfffe0000
3552 #define PLL_TEST_CNTL__TEST_COUNT__SHIFT 0x11
3553 #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_MASK 0xffff
3554 #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD__SHIFT 0x0
3555 #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT_MASK 0xf0000
3556 #define CG_STATIC_SCREEN_PARAMETER__STATIC_SCREEN_THRESHOLD_UNIT__SHIFT 0x10
3557 #define CG_DISPLAY_GAP_CNTL__DISP_GAP_MASK 0x3
3558 #define CG_DISPLAY_GAP_CNTL__DISP_GAP__SHIFT 0x0
3559 #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT_MASK 0x3fff0
3560 #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_COUNT__SHIFT 0x4
3561 #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT_MASK 0x700000
3562 #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_UNIT__SHIFT 0x14
3563 #define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG_MASK 0x3000000
3564 #define CG_DISPLAY_GAP_CNTL__DISP_GAP_MCHG__SHIFT 0x18
3565 #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE_MASK 0x10000000
3566 #define CG_DISPLAY_GAP_CNTL__VBI_TIMER_DISABLE__SHIFT 0x1c
3567 #define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION_MASK 0xffffffff
3568 #define CG_DISPLAY_GAP_CNTL2__VBI_PREDICTION__SHIFT 0x0
3569 #define CG_ACPI_CNTL__SCLK_ACPI_DIV_MASK 0x7f
3570 #define CG_ACPI_CNTL__SCLK_ACPI_DIV__SHIFT 0x0
3571 #define CG_ACPI_CNTL__SCLK_CHANGE_SKIP_MASK 0x80
3572 #define CG_ACPI_CNTL__SCLK_CHANGE_SKIP__SHIFT 0x7
3573 #define SCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
3574 #define SCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
3575 #define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
3576 #define SCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
3577 #define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
3578 #define SCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
3579 #define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK_MASK 0x10000
3580 #define SCLK_DEEP_SLEEP_CNTL__SCLK_RUNNING_MASK__SHIFT 0x10
3581 #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK_MASK 0x20000
3582 #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_MASK__SHIFT 0x11
3583 #define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK_MASK 0x40000
3584 #define SCLK_DEEP_SLEEP_CNTL__ALLOW_NBPSTATE_MASK__SHIFT 0x12
3585 #define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK_MASK 0x80000
3586 #define SCLK_DEEP_SLEEP_CNTL__BIF_BUSY_MASK__SHIFT 0x13
3587 #define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK_MASK 0x100000
3588 #define SCLK_DEEP_SLEEP_CNTL__UVD_BUSY_MASK__SHIFT 0x14
3589 #define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK_MASK 0x200000
3590 #define SCLK_DEEP_SLEEP_CNTL__MC0SRBM_BUSY_MASK__SHIFT 0x15
3591 #define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK_MASK 0x400000
3592 #define SCLK_DEEP_SLEEP_CNTL__MC1SRBM_BUSY_MASK__SHIFT 0x16
3593 #define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK_MASK 0x800000
3594 #define SCLK_DEEP_SLEEP_CNTL__MC_ALLOW_MASK__SHIFT 0x17
3595 #define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK_MASK 0x1000000
3596 #define SCLK_DEEP_SLEEP_CNTL__SMU_BUSY_MASK__SHIFT 0x18
3597 #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK_MASK 0x2000000
3598 #define SCLK_DEEP_SLEEP_CNTL__SELF_REFRESH_NLC_MASK__SHIFT 0x19
3599 #define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE_MASK 0x4000000
3600 #define SCLK_DEEP_SLEEP_CNTL__FAST_EXIT_REQ_NBPSTATE__SHIFT 0x1a
3601 #define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE_MASK 0x8000000
3602 #define SCLK_DEEP_SLEEP_CNTL__DEEP_SLEEP_ENTRY_MODE__SHIFT 0x1b
3603 #define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK_MASK 0x10000000
3604 #define SCLK_DEEP_SLEEP_CNTL__MBUS2_ACTIVE_MASK__SHIFT 0x1c
3605 #define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK_MASK 0x20000000
3606 #define SCLK_DEEP_SLEEP_CNTL__VCE_BUSY_MASK__SHIFT 0x1d
3607 #define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK_MASK 0x40000000
3608 #define SCLK_DEEP_SLEEP_CNTL__AZ_BUSY_MASK__SHIFT 0x1e
3609 #define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
3610 #define SCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
3611 #define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK_MASK 0x1
3612 #define SCLK_DEEP_SLEEP_CNTL2__RLC_BUSY_MASK__SHIFT 0x0
3613 #define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK_MASK 0x2
3614 #define SCLK_DEEP_SLEEP_CNTL2__HDP_BUSY_MASK__SHIFT 0x1
3615 #define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK_MASK 0x4
3616 #define SCLK_DEEP_SLEEP_CNTL2__ROM_BUSY_MASK__SHIFT 0x2
3617 #define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK_MASK 0x8
3618 #define SCLK_DEEP_SLEEP_CNTL2__IH_SEM_BUSY_MASK__SHIFT 0x3
3619 #define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK_MASK 0x10
3620 #define SCLK_DEEP_SLEEP_CNTL2__PDMA_BUSY_MASK__SHIFT 0x4
3621 #define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK_MASK 0x40
3622 #define SCLK_DEEP_SLEEP_CNTL2__IDCT_BUSY_MASK__SHIFT 0x6
3623 #define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK_MASK 0x80
3624 #define SCLK_DEEP_SLEEP_CNTL2__SDMA_BUSY_MASK__SHIFT 0x7
3625 #define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK_MASK 0x100
3626 #define SCLK_DEEP_SLEEP_CNTL2__DC_AZ_BUSY_MASK__SHIFT 0x8
3627 #define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK_MASK 0x200
3628 #define SCLK_DEEP_SLEEP_CNTL2__ACP_SMU_ALLOW_DSLEEP_STUTTER_MASK__SHIFT 0x9
3629 #define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK_MASK 0x400
3630 #define SCLK_DEEP_SLEEP_CNTL2__UVD_CG_MC_STAT_BUSY_MASK__SHIFT 0xa
3631 #define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK_MASK 0x800
3632 #define SCLK_DEEP_SLEEP_CNTL2__VCE_CG_MC_STAT_BUSY_MASK__SHIFT 0xb
3633 #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK_MASK 0x1000
3634 #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_MC_STAT_BUSY_MASK__SHIFT 0xc
3635 #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK_MASK 0x2000
3636 #define SCLK_DEEP_SLEEP_CNTL2__SAM_CG_STATUS_BUSY_MASK__SHIFT 0xd
3637 #define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x4000
3638 #define SCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0xe
3639 #define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID_MASK 0xe00000
3640 #define SCLK_DEEP_SLEEP_CNTL2__SHALLOW_DIV_ID__SHIFT 0x15
3641 #define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION_MASK 0xff000000
3642 #define SCLK_DEEP_SLEEP_CNTL2__INOUT_CUSHION__SHIFT 0x18
3643 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK_MASK 0x1
3644 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_0_SMU_BUSY_MASK__SHIFT 0x0
3645 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK_MASK 0x2
3646 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_1_SMU_BUSY_MASK__SHIFT 0x1
3647 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK_MASK 0x4
3648 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_2_SMU_BUSY_MASK__SHIFT 0x2
3649 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK_MASK 0x8
3650 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_3_SMU_BUSY_MASK__SHIFT 0x3
3651 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK_MASK 0x10
3652 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_4_SMU_BUSY_MASK__SHIFT 0x4
3653 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK_MASK 0x20
3654 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_5_SMU_BUSY_MASK__SHIFT 0x5
3655 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK_MASK 0x40
3656 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_6_SMU_BUSY_MASK__SHIFT 0x6
3657 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK_MASK 0x80
3658 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_7_SMU_BUSY_MASK__SHIFT 0x7
3659 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK_MASK 0x100
3660 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_8_SMU_BUSY_MASK__SHIFT 0x8
3661 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK_MASK 0x200
3662 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_9_SMU_BUSY_MASK__SHIFT 0x9
3663 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK_MASK 0x400
3664 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_10_SMU_BUSY_MASK__SHIFT 0xa
3665 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK_MASK 0x800
3666 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_11_SMU_BUSY_MASK__SHIFT 0xb
3667 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK_MASK 0x1000
3668 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_12_SMU_BUSY_MASK__SHIFT 0xc
3669 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK_MASK 0x2000
3670 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_13_SMU_BUSY_MASK__SHIFT 0xd
3671 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK_MASK 0x4000
3672 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_14_SMU_BUSY_MASK__SHIFT 0xe
3673 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK_MASK 0x8000
3674 #define SCLK_DEEP_SLEEP_CNTL3__GRBM_15_SMU_BUSY_MASK__SHIFT 0xf
3675 #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID_MASK 0x7
3676 #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_DS_DIV_ID__SHIFT 0x0
3677 #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID_MASK 0x38
3678 #define SCLK_DEEP_SLEEP_MISC_CNTL__DPM_SS_DIV_ID__SHIFT 0x3
3679 #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE_MASK 0x10000
3680 #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_ENABLE__SHIFT 0x10
3681 #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID_MASK 0xe0000
3682 #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_DS_DIV_ID__SHIFT 0x11
3683 #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID_MASK 0x700000
3684 #define SCLK_DEEP_SLEEP_MISC_CNTL__OCP_SS_DIV_ID__SHIFT 0x14
3685 #define LCLK_DEEP_SLEEP_CNTL__DIV_ID_MASK 0x7
3686 #define LCLK_DEEP_SLEEP_CNTL__DIV_ID__SHIFT 0x0
3687 #define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS_MASK 0x8
3688 #define LCLK_DEEP_SLEEP_CNTL__RAMP_DIS__SHIFT 0x3
3689 #define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS_MASK 0xfff0
3690 #define LCLK_DEEP_SLEEP_CNTL__HYSTERESIS__SHIFT 0x4
3691 #define LCLK_DEEP_SLEEP_CNTL__RESERVED_MASK 0x7fff0000
3692 #define LCLK_DEEP_SLEEP_CNTL__RESERVED__SHIFT 0x10
3693 #define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS_MASK 0x80000000
3694 #define LCLK_DEEP_SLEEP_CNTL__ENABLE_DS__SHIFT 0x1f
3695 #define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK_MASK 0x1
3696 #define LCLK_DEEP_SLEEP_CNTL2__RFE_BUSY_MASK__SHIFT 0x0
3697 #define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK_MASK 0x2
3698 #define LCLK_DEEP_SLEEP_CNTL2__BIF_CG_LCLK_BUSY_MASK__SHIFT 0x1
3699 #define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK_MASK 0x4
3700 #define LCLK_DEEP_SLEEP_CNTL2__L1IMU_SMU_IDLE_MASK__SHIFT 0x2
3701 #define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3_MASK 0x8
3702 #define LCLK_DEEP_SLEEP_CNTL2__RESERVED_BIT3__SHIFT 0x3
3703 #define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK_MASK 0x10
3704 #define LCLK_DEEP_SLEEP_CNTL2__SCLK_RUNNING_MASK__SHIFT 0x4
3705 #define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK_MASK 0x20
3706 #define LCLK_DEEP_SLEEP_CNTL2__SMU_BUSY_MASK__SHIFT 0x5
3707 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK_MASK 0x40
3708 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE1_MASK__SHIFT 0x6
3709 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK_MASK 0x80
3710 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE2_MASK__SHIFT 0x7
3711 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK_MASK 0x100
3712 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE3_MASK__SHIFT 0x8
3713 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK_MASK 0x200
3714 #define LCLK_DEEP_SLEEP_CNTL2__PCIE_LCLK_IDLE4_MASK__SHIFT 0x9
3715 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK_MASK 0x400
3716 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPP_IDLE_MASK__SHIFT 0xa
3717 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK_MASK 0x800
3718 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUGPPSB_IDLE_MASK__SHIFT 0xb
3719 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK_MASK 0x1000
3720 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUBIF_IDLE_MASK__SHIFT 0xc
3721 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK_MASK 0x2000
3722 #define LCLK_DEEP_SLEEP_CNTL2__L1IMUINTGEN_IDLE_MASK__SHIFT 0xd
3723 #define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK_MASK 0x4000
3724 #define LCLK_DEEP_SLEEP_CNTL2__L2IMU_IDLE_MASK__SHIFT 0xe
3725 #define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK_MASK 0x8000
3726 #define LCLK_DEEP_SLEEP_CNTL2__ORB_IDLE_MASK__SHIFT 0xf
3727 #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK_MASK 0x10000
3728 #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_MASK__SHIFT 0x10
3729 #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK_MASK 0x20000
3730 #define LCLK_DEEP_SLEEP_CNTL2__ON_INB_WAKE_ACK_MASK__SHIFT 0x11
3731 #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK_MASK 0x40000
3732 #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_MASK__SHIFT 0x12
3733 #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK_MASK 0x80000
3734 #define LCLK_DEEP_SLEEP_CNTL2__ON_OUTB_WAKE_ACK_MASK__SHIFT 0x13
3735 #define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK_MASK 0x100000
3736 #define LCLK_DEEP_SLEEP_CNTL2__DMAACTIVE_MASK__SHIFT 0x14
3737 #define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK_MASK 0x200000
3738 #define LCLK_DEEP_SLEEP_CNTL2__RLC_SMU_GFXCLK_OFF_MASK__SHIFT 0x15
3739 #define LCLK_DEEP_SLEEP_CNTL2__RESERVED_MASK 0xffc00000
3740 #define LCLK_DEEP_SLEEP_CNTL2__RESERVED__SHIFT 0x16
3741 #define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS_MASK 0x1
3742 #define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_STATUS__SHIFT 0x0
3743 #define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL_MASK 0x1fe
3744 #define SMU_VOLTAGE_STATUS__SMU_VOLTAGE_CURRENT_LEVEL__SHIFT 0x1
3745 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX_MASK 0xf
3746 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDCI_INDEX__SHIFT 0x0
3747 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX_MASK 0xf0
3748 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDCI_INDEX__SHIFT 0x4
3749 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX_MASK 0xf00
3750 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_MVDD_INDEX__SHIFT 0x8
3751 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX_MASK 0xf000
3752 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_MVDD_INDEX__SHIFT 0xc
3753 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX_MASK 0xf0000
3754 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_VDDC_INDEX__SHIFT 0x10
3755 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX_MASK 0xf00000
3756 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_VDDC_INDEX__SHIFT 0x14
3757 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX_MASK 0xf000000
3758 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__CURR_PCIE_INDEX__SHIFT 0x18
3759 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX_MASK 0xf0000000
3760 #define TARGET_AND_CURRENT_PROFILE_INDEX_1__TARG_PCIE_INDEX__SHIFT 0x1c
3761 #define CG_ULV_PARAMETER__ULV_THRESHOLD_MASK 0xffff
3762 #define CG_ULV_PARAMETER__ULV_THRESHOLD__SHIFT 0x0
3763 #define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT_MASK 0xf0000
3764 #define CG_ULV_PARAMETER__ULV_THRESHOLD_UNIT__SHIFT 0x10
3765 #define SCLK_MIN_DIV__FRACV_MASK 0xfff
3766 #define SCLK_MIN_DIV__FRACV__SHIFT 0x0
3767 #define SCLK_MIN_DIV__INTV_MASK 0x7f000
3768 #define SCLK_MIN_DIV__INTV__SHIFT 0xc
3769 #define LCAC_SX0_CNTL__SX0_ENABLE_MASK 0x1
3770 #define LCAC_SX0_CNTL__SX0_ENABLE__SHIFT 0x0
3771 #define LCAC_SX0_CNTL__SX0_THRESHOLD_MASK 0x1fffe
3772 #define LCAC_SX0_CNTL__SX0_THRESHOLD__SHIFT 0x1
3773 #define LCAC_SX0_CNTL__SX0_BLOCK_ID_MASK 0x3e0000
3774 #define LCAC_SX0_CNTL__SX0_BLOCK_ID__SHIFT 0x11
3775 #define LCAC_SX0_CNTL__SX0_SIGNAL_ID_MASK 0x3fc00000
3776 #define LCAC_SX0_CNTL__SX0_SIGNAL_ID__SHIFT 0x16
3777 #define LCAC_SX0_OVR_SEL__SX0_OVR_SEL_MASK 0xffffffff
3778 #define LCAC_SX0_OVR_SEL__SX0_OVR_SEL__SHIFT 0x0
3779 #define LCAC_SX0_OVR_VAL__SX0_OVR_VAL_MASK 0xffffffff
3780 #define LCAC_SX0_OVR_VAL__SX0_OVR_VAL__SHIFT 0x0
3781 #define LCAC_MC0_CNTL__MC0_ENABLE_MASK 0x1
3782 #define LCAC_MC0_CNTL__MC0_ENABLE__SHIFT 0x0
3783 #define LCAC_MC0_CNTL__MC0_THRESHOLD_MASK 0x1fffe
3784 #define LCAC_MC0_CNTL__MC0_THRESHOLD__SHIFT 0x1
3785 #define LCAC_MC0_CNTL__MC0_BLOCK_ID_MASK 0x3e0000
3786 #define LCAC_MC0_CNTL__MC0_BLOCK_ID__SHIFT 0x11
3787 #define LCAC_MC0_CNTL__MC0_SIGNAL_ID_MASK 0x3fc00000
3788 #define LCAC_MC0_CNTL__MC0_SIGNAL_ID__SHIFT 0x16
3789 #define LCAC_MC0_OVR_SEL__MC0_OVR_SEL_MASK 0xffffffff
3790 #define LCAC_MC0_OVR_SEL__MC0_OVR_SEL__SHIFT 0x0
3791 #define LCAC_MC0_OVR_VAL__MC0_OVR_VAL_MASK 0xffffffff
3792 #define LCAC_MC0_OVR_VAL__MC0_OVR_VAL__SHIFT 0x0
3793 #define LCAC_MC1_CNTL__MC1_ENABLE_MASK 0x1
3794 #define LCAC_MC1_CNTL__MC1_ENABLE__SHIFT 0x0
3795 #define LCAC_MC1_CNTL__MC1_THRESHOLD_MASK 0x1fffe
3796 #define LCAC_MC1_CNTL__MC1_THRESHOLD__SHIFT 0x1
3797 #define LCAC_MC1_CNTL__MC1_BLOCK_ID_MASK 0x3e0000
3798 #define LCAC_MC1_CNTL__MC1_BLOCK_ID__SHIFT 0x11
3799 #define LCAC_MC1_CNTL__MC1_SIGNAL_ID_MASK 0x3fc00000
3800 #define LCAC_MC1_CNTL__MC1_SIGNAL_ID__SHIFT 0x16
3801 #define LCAC_MC1_OVR_SEL__MC1_OVR_SEL_MASK 0xffffffff
3802 #define LCAC_MC1_OVR_SEL__MC1_OVR_SEL__SHIFT 0x0
3803 #define LCAC_MC1_OVR_VAL__MC1_OVR_VAL_MASK 0xffffffff
3804 #define LCAC_MC1_OVR_VAL__MC1_OVR_VAL__SHIFT 0x0
3805 #define LCAC_MC2_CNTL__MC2_ENABLE_MASK 0x1
3806 #define LCAC_MC2_CNTL__MC2_ENABLE__SHIFT 0x0
3807 #define LCAC_MC2_CNTL__MC2_THRESHOLD_MASK 0x1fffe
3808 #define LCAC_MC2_CNTL__MC2_THRESHOLD__SHIFT 0x1
3809 #define LCAC_MC2_CNTL__MC2_BLOCK_ID_MASK 0x3e0000
3810 #define LCAC_MC2_CNTL__MC2_BLOCK_ID__SHIFT 0x11
3811 #define LCAC_MC2_CNTL__MC2_SIGNAL_ID_MASK 0x3fc00000
3812 #define LCAC_MC2_CNTL__MC2_SIGNAL_ID__SHIFT 0x16
3813 #define LCAC_MC2_OVR_SEL__MC2_OVR_SEL_MASK 0xffffffff
3814 #define LCAC_MC2_OVR_SEL__MC2_OVR_SEL__SHIFT 0x0
3815 #define LCAC_MC2_OVR_VAL__MC2_OVR_VAL_MASK 0xffffffff
3816 #define LCAC_MC2_OVR_VAL__MC2_OVR_VAL__SHIFT 0x0
3817 #define LCAC_MC3_CNTL__MC3_ENABLE_MASK 0x1
3818 #define LCAC_MC3_CNTL__MC3_ENABLE__SHIFT 0x0
3819 #define LCAC_MC3_CNTL__MC3_THRESHOLD_MASK 0x1fffe
3820 #define LCAC_MC3_CNTL__MC3_THRESHOLD__SHIFT 0x1
3821 #define LCAC_MC3_CNTL__MC3_BLOCK_ID_MASK 0x3e0000
3822 #define LCAC_MC3_CNTL__MC3_BLOCK_ID__SHIFT 0x11
3823 #define LCAC_MC3_CNTL__MC3_SIGNAL_ID_MASK 0x3fc00000
3824 #define LCAC_MC3_CNTL__MC3_SIGNAL_ID__SHIFT 0x16
3825 #define LCAC_MC3_OVR_SEL__MC3_OVR_SEL_MASK 0xffffffff
3826 #define LCAC_MC3_OVR_SEL__MC3_OVR_SEL__SHIFT 0x0
3827 #define LCAC_MC3_OVR_VAL__MC3_OVR_VAL_MASK 0xffffffff
3828 #define LCAC_MC3_OVR_VAL__MC3_OVR_VAL__SHIFT 0x0
3829 #define LCAC_CPL_CNTL__CPL_ENABLE_MASK 0x1
3830 #define LCAC_CPL_CNTL__CPL_ENABLE__SHIFT 0x0
3831 #define LCAC_CPL_CNTL__CPL_THRESHOLD_MASK 0x1fffe
3832 #define LCAC_CPL_CNTL__CPL_THRESHOLD__SHIFT 0x1
3833 #define LCAC_CPL_CNTL__CPL_BLOCK_ID_MASK 0x3e0000
3834 #define LCAC_CPL_CNTL__CPL_BLOCK_ID__SHIFT 0x11
3835 #define LCAC_CPL_CNTL__CPL_SIGNAL_ID_MASK 0x3fc00000
3836 #define LCAC_CPL_CNTL__CPL_SIGNAL_ID__SHIFT 0x16
3837 #define LCAC_CPL_OVR_SEL__CPL_OVR_SEL_MASK 0xffffffff
3838 #define LCAC_CPL_OVR_SEL__CPL_OVR_SEL__SHIFT 0x0
3839 #define LCAC_CPL_OVR_VAL__CPL_OVR_VAL_MASK 0xffffffff
3840 #define LCAC_CPL_OVR_VAL__CPL_OVR_VAL__SHIFT 0x0
3841 
3842 #endif /* SMU_7_0_0_SH_MASK_H */
3843