1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Power domain driver for Broadcom BCM2835
4 *
5 * Copyright (C) 2018 Broadcom
6 */
7
8 #include <dt-bindings/soc/bcm2835-pm.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/mfd/bcm2835-pm.h>
14 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_domain.h>
17 #include <linux/reset-controller.h>
18 #include <linux/types.h>
19
20 #define PM_GNRIC 0x00
21 #define PM_AUDIO 0x04
22 #define PM_STATUS 0x18
23 #define PM_RSTC 0x1c
24 #define PM_RSTS 0x20
25 #define PM_WDOG 0x24
26 #define PM_PADS0 0x28
27 #define PM_PADS2 0x2c
28 #define PM_PADS3 0x30
29 #define PM_PADS4 0x34
30 #define PM_PADS5 0x38
31 #define PM_PADS6 0x3c
32 #define PM_CAM0 0x44
33 #define PM_CAM0_LDOHPEN BIT(2)
34 #define PM_CAM0_LDOLPEN BIT(1)
35 #define PM_CAM0_CTRLEN BIT(0)
36
37 #define PM_CAM1 0x48
38 #define PM_CAM1_LDOHPEN BIT(2)
39 #define PM_CAM1_LDOLPEN BIT(1)
40 #define PM_CAM1_CTRLEN BIT(0)
41
42 #define PM_CCP2TX 0x4c
43 #define PM_CCP2TX_LDOEN BIT(1)
44 #define PM_CCP2TX_CTRLEN BIT(0)
45
46 #define PM_DSI0 0x50
47 #define PM_DSI0_LDOHPEN BIT(2)
48 #define PM_DSI0_LDOLPEN BIT(1)
49 #define PM_DSI0_CTRLEN BIT(0)
50
51 #define PM_DSI1 0x54
52 #define PM_DSI1_LDOHPEN BIT(2)
53 #define PM_DSI1_LDOLPEN BIT(1)
54 #define PM_DSI1_CTRLEN BIT(0)
55
56 #define PM_HDMI 0x58
57 #define PM_HDMI_RSTDR BIT(19)
58 #define PM_HDMI_LDOPD BIT(1)
59 #define PM_HDMI_CTRLEN BIT(0)
60
61 #define PM_USB 0x5c
62 /* The power gates must be enabled with this bit before enabling the LDO in the
63 * USB block.
64 */
65 #define PM_USB_CTRLEN BIT(0)
66
67 #define PM_PXLDO 0x60
68 #define PM_PXBG 0x64
69 #define PM_DFT 0x68
70 #define PM_SMPS 0x6c
71 #define PM_XOSC 0x70
72 #define PM_SPAREW 0x74
73 #define PM_SPARER 0x78
74 #define PM_AVS_RSTDR 0x7c
75 #define PM_AVS_STAT 0x80
76 #define PM_AVS_EVENT 0x84
77 #define PM_AVS_INTEN 0x88
78 #define PM_DUMMY 0xfc
79
80 #define PM_IMAGE 0x108
81 #define PM_GRAFX 0x10c
82 #define PM_PROC 0x110
83 #define PM_GRAFX_2712 0x304
84 #define PM_ENAB BIT(12)
85 #define PM_ISPRSTN BIT(8)
86 #define PM_H264RSTN BIT(7)
87 #define PM_PERIRSTN BIT(6)
88 #define PM_V3DRSTN BIT(6)
89 #define PM_ISFUNC BIT(5)
90 #define PM_MRDONE BIT(4)
91 #define PM_MEMREP BIT(3)
92 #define PM_ISPOW BIT(2)
93 #define PM_POWOK BIT(1)
94 #define PM_POWUP BIT(0)
95 #define PM_INRUSH_SHIFT 13
96 #define PM_INRUSH_3_5_MA 0
97 #define PM_INRUSH_5_MA 1
98 #define PM_INRUSH_10_MA 2
99 #define PM_INRUSH_20_MA 3
100 #define PM_INRUSH_MASK (3 << PM_INRUSH_SHIFT)
101
102 #define PM_PASSWORD 0x5a000000
103
104 #define PM_WDOG_TIME_SET 0x000fffff
105 #define PM_RSTC_WRCFG_CLR 0xffffffcf
106 #define PM_RSTS_HADWRH_SET 0x00000040
107 #define PM_RSTC_WRCFG_SET 0x00000030
108 #define PM_RSTC_WRCFG_FULL_RESET 0x00000020
109 #define PM_RSTC_RESET 0x00000102
110
111 #define PM_READ(reg) readl(power->base + (reg))
112 #define PM_WRITE(reg, val) writel(PM_PASSWORD | (val), power->base + (reg))
113
114 #define ASB_BRDG_VERSION 0x00
115 #define ASB_CPR_CTRL 0x04
116
117 #define ASB_V3D_S_CTRL 0x08
118 #define ASB_V3D_M_CTRL 0x0c
119 #define ASB_ISP_S_CTRL 0x10
120 #define ASB_ISP_M_CTRL 0x14
121 #define ASB_H264_S_CTRL 0x18
122 #define ASB_H264_M_CTRL 0x1c
123
124 #define ASB_REQ_STOP BIT(0)
125 #define ASB_ACK BIT(1)
126 #define ASB_EMPTY BIT(2)
127 #define ASB_FULL BIT(3)
128
129 #define ASB_AXI_BRDG_ID 0x20
130
131 #define BCM2835_BRDG_ID 0x62726467
132
133 struct bcm2835_power_domain {
134 struct generic_pm_domain base;
135 struct bcm2835_power *power;
136 u32 domain;
137 struct clk *clk;
138 };
139
140 struct bcm2835_power {
141 struct device *dev;
142 /* PM registers. */
143 void __iomem *base;
144 /* AXI Async bridge registers. */
145 void __iomem *asb;
146 /* RPiVid bridge registers. */
147 void __iomem *rpivid_asb;
148
149 struct genpd_onecell_data pd_xlate;
150 struct bcm2835_power_domain domains[BCM2835_POWER_DOMAIN_COUNT];
151 struct reset_controller_dev reset;
152 };
153
bcm2835_asb_control(struct bcm2835_power * power,u32 reg,bool enable)154 static int bcm2835_asb_control(struct bcm2835_power *power, u32 reg, bool enable)
155 {
156 void __iomem *base = power->asb;
157 u32 val;
158
159 switch (reg) {
160 case 0:
161 return 0;
162 case ASB_V3D_S_CTRL:
163 case ASB_V3D_M_CTRL:
164 if (power->rpivid_asb)
165 base = power->rpivid_asb;
166 break;
167 }
168
169 /* Enable the module's async AXI bridges. */
170 if (enable) {
171 val = readl(base + reg) & ~ASB_REQ_STOP;
172 } else {
173 val = readl(base + reg) | ASB_REQ_STOP;
174 }
175 writel(PM_PASSWORD | val, base + reg);
176
177 if (readl_poll_timeout_atomic(base + reg, val,
178 !!(val & ASB_ACK) != enable, 0, 5))
179 return -ETIMEDOUT;
180
181 return 0;
182 }
183
bcm2835_asb_enable(struct bcm2835_power * power,u32 reg)184 static int bcm2835_asb_enable(struct bcm2835_power *power, u32 reg)
185 {
186 return bcm2835_asb_control(power, reg, true);
187 }
188
bcm2835_asb_disable(struct bcm2835_power * power,u32 reg)189 static int bcm2835_asb_disable(struct bcm2835_power *power, u32 reg)
190 {
191 return bcm2835_asb_control(power, reg, false);
192 }
193
bcm2835_power_power_off(struct bcm2835_power_domain * pd,u32 pm_reg)194 static int bcm2835_power_power_off(struct bcm2835_power_domain *pd, u32 pm_reg)
195 {
196 struct bcm2835_power *power = pd->power;
197
198 /* We don't run this on BCM2711 */
199 if (power->rpivid_asb)
200 return 0;
201
202 /* Enable functional isolation */
203 PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISFUNC);
204
205 /* Enable electrical isolation */
206 PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
207
208 /* Open the power switches. */
209 PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_POWUP);
210
211 return 0;
212 }
213
bcm2835_power_power_on(struct bcm2835_power_domain * pd,u32 pm_reg)214 static int bcm2835_power_power_on(struct bcm2835_power_domain *pd, u32 pm_reg)
215 {
216 struct bcm2835_power *power = pd->power;
217 struct device *dev = power->dev;
218 int ret;
219 int inrush;
220 bool powok;
221 u32 val;
222
223 /* We don't run this on BCM2711 */
224 if (power->rpivid_asb)
225 return 0;
226
227 /* If it was already powered on by the fw, leave it that way. */
228 if (PM_READ(pm_reg) & PM_POWUP)
229 return 0;
230
231 /* Enable power. Allowing too much current at once may result
232 * in POWOK never getting set, so start low and ramp it up as
233 * necessary to succeed.
234 */
235 powok = false;
236 for (inrush = PM_INRUSH_3_5_MA; inrush <= PM_INRUSH_20_MA; inrush++) {
237 PM_WRITE(pm_reg,
238 (PM_READ(pm_reg) & ~PM_INRUSH_MASK) |
239 (inrush << PM_INRUSH_SHIFT) |
240 PM_POWUP);
241
242 powok = !readl_poll_timeout_atomic(power->base + pm_reg,
243 val, val & PM_POWOK, 0, 3);
244 }
245 if (!powok) {
246 dev_err(dev, "Timeout waiting for %s power OK\n",
247 pd->base.name);
248 ret = -ETIMEDOUT;
249 goto err_disable_powup;
250 }
251
252 /* Disable electrical isolation */
253 PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISPOW);
254
255 /* Repair memory */
256 PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_MEMREP);
257 if (readl_poll_timeout_atomic(power->base + pm_reg, val,
258 val & PM_MRDONE, 0, 1)) {
259 dev_err(dev, "Timeout waiting for %s memory repair\n",
260 pd->base.name);
261 ret = -ETIMEDOUT;
262 goto err_disable_ispow;
263 }
264
265 /* Disable functional isolation */
266 PM_WRITE(pm_reg, PM_READ(pm_reg) | PM_ISFUNC);
267
268 return 0;
269
270 err_disable_ispow:
271 PM_WRITE(pm_reg, PM_READ(pm_reg) & ~PM_ISPOW);
272 err_disable_powup:
273 PM_WRITE(pm_reg, PM_READ(pm_reg) & ~(PM_POWUP | PM_INRUSH_MASK));
274 return ret;
275 }
276
bcm2835_asb_power_on(struct bcm2835_power_domain * pd,u32 pm_reg,u32 asb_m_reg,u32 asb_s_reg,u32 reset_flags)277 static int bcm2835_asb_power_on(struct bcm2835_power_domain *pd,
278 u32 pm_reg,
279 u32 asb_m_reg,
280 u32 asb_s_reg,
281 u32 reset_flags)
282 {
283 struct bcm2835_power *power = pd->power;
284 int ret;
285
286 ret = clk_prepare_enable(pd->clk);
287 if (ret) {
288 dev_err(power->dev, "Failed to enable clock for %s\n",
289 pd->base.name);
290 return ret;
291 }
292
293 /* Wait 32 clocks for reset to propagate, 1 us will be enough */
294 udelay(1);
295
296 clk_disable_unprepare(pd->clk);
297
298 /* Deassert the resets. */
299 PM_WRITE(pm_reg, PM_READ(pm_reg) | reset_flags);
300
301 ret = clk_prepare_enable(pd->clk);
302 if (ret) {
303 dev_err(power->dev, "Failed to enable clock for %s\n",
304 pd->base.name);
305 goto err_enable_resets;
306 }
307
308 ret = bcm2835_asb_enable(power, asb_m_reg);
309 if (ret) {
310 dev_err(power->dev, "Failed to enable ASB master for %s\n",
311 pd->base.name);
312 goto err_disable_clk;
313 }
314 ret = bcm2835_asb_enable(power, asb_s_reg);
315 if (ret) {
316 dev_err(power->dev, "Failed to enable ASB slave for %s\n",
317 pd->base.name);
318 goto err_disable_asb_master;
319 }
320
321 return 0;
322
323 err_disable_asb_master:
324 bcm2835_asb_disable(power, asb_m_reg);
325 err_disable_clk:
326 clk_disable_unprepare(pd->clk);
327 err_enable_resets:
328 PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
329 return ret;
330 }
331
bcm2835_asb_power_off(struct bcm2835_power_domain * pd,u32 pm_reg,u32 asb_m_reg,u32 asb_s_reg,u32 reset_flags)332 static int bcm2835_asb_power_off(struct bcm2835_power_domain *pd,
333 u32 pm_reg,
334 u32 asb_m_reg,
335 u32 asb_s_reg,
336 u32 reset_flags)
337 {
338 struct bcm2835_power *power = pd->power;
339 int ret;
340
341 ret = bcm2835_asb_disable(power, asb_s_reg);
342 if (ret) {
343 dev_warn(power->dev, "Failed to disable ASB slave for %s\n",
344 pd->base.name);
345 return ret;
346 }
347 ret = bcm2835_asb_disable(power, asb_m_reg);
348 if (ret) {
349 dev_warn(power->dev, "Failed to disable ASB master for %s\n",
350 pd->base.name);
351 bcm2835_asb_enable(power, asb_s_reg);
352 return ret;
353 }
354
355 clk_disable_unprepare(pd->clk);
356
357 /* Assert the resets. */
358 PM_WRITE(pm_reg, PM_READ(pm_reg) & ~reset_flags);
359
360 return 0;
361 }
362
bcm2835_power_pd_power_on(struct generic_pm_domain * domain)363 static int bcm2835_power_pd_power_on(struct generic_pm_domain *domain)
364 {
365 struct bcm2835_power_domain *pd =
366 container_of(domain, struct bcm2835_power_domain, base);
367 struct bcm2835_power *power = pd->power;
368
369 switch (pd->domain) {
370 case BCM2835_POWER_DOMAIN_GRAFX:
371 return bcm2835_power_power_on(pd, PM_GRAFX);
372
373 case BCM2835_POWER_DOMAIN_GRAFX_V3D:
374 if (!power->asb)
375 return bcm2835_asb_power_on(pd, PM_GRAFX_2712,
376 0, 0, PM_V3DRSTN);
377 return bcm2835_asb_power_on(pd, PM_GRAFX,
378 ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
379 PM_V3DRSTN);
380
381 case BCM2835_POWER_DOMAIN_IMAGE:
382 return bcm2835_power_power_on(pd, PM_IMAGE);
383
384 case BCM2835_POWER_DOMAIN_IMAGE_PERI:
385 return bcm2835_asb_power_on(pd, PM_IMAGE,
386 0, 0,
387 PM_PERIRSTN);
388
389 case BCM2835_POWER_DOMAIN_IMAGE_ISP:
390 return bcm2835_asb_power_on(pd, PM_IMAGE,
391 ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
392 PM_ISPRSTN);
393
394 case BCM2835_POWER_DOMAIN_IMAGE_H264:
395 return bcm2835_asb_power_on(pd, PM_IMAGE,
396 ASB_H264_M_CTRL, ASB_H264_S_CTRL,
397 PM_H264RSTN);
398
399 case BCM2835_POWER_DOMAIN_USB:
400 PM_WRITE(PM_USB, PM_USB_CTRLEN);
401 return 0;
402
403 case BCM2835_POWER_DOMAIN_DSI0:
404 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
405 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN | PM_DSI0_LDOHPEN);
406 return 0;
407
408 case BCM2835_POWER_DOMAIN_DSI1:
409 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
410 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN | PM_DSI1_LDOHPEN);
411 return 0;
412
413 case BCM2835_POWER_DOMAIN_CCP2TX:
414 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
415 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN | PM_CCP2TX_LDOEN);
416 return 0;
417
418 case BCM2835_POWER_DOMAIN_HDMI:
419 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_RSTDR);
420 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_CTRLEN);
421 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_LDOPD);
422 usleep_range(100, 200);
423 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_RSTDR);
424 return 0;
425
426 default:
427 dev_err(power->dev, "Invalid domain %d\n", pd->domain);
428 return -EINVAL;
429 }
430 }
431
bcm2835_power_pd_power_off(struct generic_pm_domain * domain)432 static int bcm2835_power_pd_power_off(struct generic_pm_domain *domain)
433 {
434 struct bcm2835_power_domain *pd =
435 container_of(domain, struct bcm2835_power_domain, base);
436 struct bcm2835_power *power = pd->power;
437
438 switch (pd->domain) {
439 case BCM2835_POWER_DOMAIN_GRAFX:
440 return bcm2835_power_power_off(pd, PM_GRAFX);
441
442 case BCM2835_POWER_DOMAIN_GRAFX_V3D:
443 if (!power->asb)
444 return bcm2835_asb_power_off(pd, PM_GRAFX_2712,
445 0, 0, PM_V3DRSTN);
446 return bcm2835_asb_power_off(pd, PM_GRAFX,
447 ASB_V3D_M_CTRL, ASB_V3D_S_CTRL,
448 PM_V3DRSTN);
449
450 case BCM2835_POWER_DOMAIN_IMAGE:
451 return bcm2835_power_power_off(pd, PM_IMAGE);
452
453 case BCM2835_POWER_DOMAIN_IMAGE_PERI:
454 return bcm2835_asb_power_off(pd, PM_IMAGE,
455 0, 0,
456 PM_PERIRSTN);
457
458 case BCM2835_POWER_DOMAIN_IMAGE_ISP:
459 return bcm2835_asb_power_off(pd, PM_IMAGE,
460 ASB_ISP_M_CTRL, ASB_ISP_S_CTRL,
461 PM_ISPRSTN);
462
463 case BCM2835_POWER_DOMAIN_IMAGE_H264:
464 return bcm2835_asb_power_off(pd, PM_IMAGE,
465 ASB_H264_M_CTRL, ASB_H264_S_CTRL,
466 PM_H264RSTN);
467
468 case BCM2835_POWER_DOMAIN_USB:
469 PM_WRITE(PM_USB, 0);
470 return 0;
471
472 case BCM2835_POWER_DOMAIN_DSI0:
473 PM_WRITE(PM_DSI0, PM_DSI0_CTRLEN);
474 PM_WRITE(PM_DSI0, 0);
475 return 0;
476
477 case BCM2835_POWER_DOMAIN_DSI1:
478 PM_WRITE(PM_DSI1, PM_DSI1_CTRLEN);
479 PM_WRITE(PM_DSI1, 0);
480 return 0;
481
482 case BCM2835_POWER_DOMAIN_CCP2TX:
483 PM_WRITE(PM_CCP2TX, PM_CCP2TX_CTRLEN);
484 PM_WRITE(PM_CCP2TX, 0);
485 return 0;
486
487 case BCM2835_POWER_DOMAIN_HDMI:
488 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) | PM_HDMI_LDOPD);
489 PM_WRITE(PM_HDMI, PM_READ(PM_HDMI) & ~PM_HDMI_CTRLEN);
490 return 0;
491
492 default:
493 dev_err(power->dev, "Invalid domain %d\n", pd->domain);
494 return -EINVAL;
495 }
496 }
497
498 static int
bcm2835_init_power_domain(struct bcm2835_power * power,int pd_xlate_index,const char * name)499 bcm2835_init_power_domain(struct bcm2835_power *power,
500 int pd_xlate_index, const char *name)
501 {
502 struct device *dev = power->dev;
503 struct bcm2835_power_domain *dom = &power->domains[pd_xlate_index];
504
505 dom->clk = devm_clk_get_optional(dev->parent, name);
506 if (IS_ERR(dom->clk))
507 return dev_err_probe(dev, PTR_ERR(dom->clk), "Failed to get clock %s\n",
508 name);
509
510 dom->base.name = name;
511 dom->base.flags = GENPD_FLAG_ACTIVE_WAKEUP;
512 dom->base.power_on = bcm2835_power_pd_power_on;
513 dom->base.power_off = bcm2835_power_pd_power_off;
514
515 dom->domain = pd_xlate_index;
516 dom->power = power;
517
518 /* XXX: on/off at boot? */
519 pm_genpd_init(&dom->base, NULL, true);
520
521 power->pd_xlate.domains[pd_xlate_index] = &dom->base;
522
523 return 0;
524 }
525
526 /** bcm2835_reset_reset - Resets a block that has a reset line in the
527 * PM block.
528 *
529 * The consumer of the reset controller must have the power domain up
530 * -- there's no reset ability with the power domain down. To reset
531 * the sub-block, we just disable its access to memory through the
532 * ASB, reset, and re-enable.
533 */
bcm2835_reset_reset(struct reset_controller_dev * rcdev,unsigned long id)534 static int bcm2835_reset_reset(struct reset_controller_dev *rcdev,
535 unsigned long id)
536 {
537 struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
538 reset);
539 struct bcm2835_power_domain *pd;
540 int ret;
541
542 switch (id) {
543 case BCM2835_RESET_V3D:
544 pd = &power->domains[BCM2835_POWER_DOMAIN_GRAFX_V3D];
545 break;
546 case BCM2835_RESET_H264:
547 pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_H264];
548 break;
549 case BCM2835_RESET_ISP:
550 pd = &power->domains[BCM2835_POWER_DOMAIN_IMAGE_ISP];
551 break;
552 default:
553 dev_err(power->dev, "Bad reset id %ld\n", id);
554 return -EINVAL;
555 }
556
557 ret = bcm2835_power_pd_power_off(&pd->base);
558 if (ret)
559 return ret;
560
561 return bcm2835_power_pd_power_on(&pd->base);
562 }
563
bcm2835_reset_status(struct reset_controller_dev * rcdev,unsigned long id)564 static int bcm2835_reset_status(struct reset_controller_dev *rcdev,
565 unsigned long id)
566 {
567 struct bcm2835_power *power = container_of(rcdev, struct bcm2835_power,
568 reset);
569
570 switch (id) {
571 case BCM2835_RESET_V3D:
572 return !(PM_READ(PM_GRAFX) & PM_V3DRSTN);
573 case BCM2835_RESET_H264:
574 return !(PM_READ(PM_IMAGE) & PM_H264RSTN);
575 case BCM2835_RESET_ISP:
576 return !(PM_READ(PM_IMAGE) & PM_ISPRSTN);
577 default:
578 return -EINVAL;
579 }
580 }
581
582 static const struct reset_control_ops bcm2835_reset_ops = {
583 .reset = bcm2835_reset_reset,
584 .status = bcm2835_reset_status,
585 };
586
587 static const char *const power_domain_names[] = {
588 [BCM2835_POWER_DOMAIN_GRAFX] = "grafx",
589 [BCM2835_POWER_DOMAIN_GRAFX_V3D] = "v3d",
590
591 [BCM2835_POWER_DOMAIN_IMAGE] = "image",
592 [BCM2835_POWER_DOMAIN_IMAGE_PERI] = "peri_image",
593 [BCM2835_POWER_DOMAIN_IMAGE_H264] = "h264",
594 [BCM2835_POWER_DOMAIN_IMAGE_ISP] = "isp",
595
596 [BCM2835_POWER_DOMAIN_USB] = "usb",
597 [BCM2835_POWER_DOMAIN_DSI0] = "dsi0",
598 [BCM2835_POWER_DOMAIN_DSI1] = "dsi1",
599 [BCM2835_POWER_DOMAIN_CAM0] = "cam0",
600 [BCM2835_POWER_DOMAIN_CAM1] = "cam1",
601 [BCM2835_POWER_DOMAIN_CCP2TX] = "ccp2tx",
602 [BCM2835_POWER_DOMAIN_HDMI] = "hdmi",
603 };
604
bcm2835_power_probe(struct platform_device * pdev)605 static int bcm2835_power_probe(struct platform_device *pdev)
606 {
607 struct bcm2835_pm *pm = dev_get_drvdata(pdev->dev.parent);
608 struct device *dev = &pdev->dev;
609 struct bcm2835_power *power;
610 static const struct {
611 int parent, child;
612 } domain_deps[] = {
613 { BCM2835_POWER_DOMAIN_GRAFX, BCM2835_POWER_DOMAIN_GRAFX_V3D },
614 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_PERI },
615 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_H264 },
616 { BCM2835_POWER_DOMAIN_IMAGE, BCM2835_POWER_DOMAIN_IMAGE_ISP },
617 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_USB },
618 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM0 },
619 { BCM2835_POWER_DOMAIN_IMAGE_PERI, BCM2835_POWER_DOMAIN_CAM1 },
620 };
621 int ret = 0, i;
622 u32 id;
623
624 power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL);
625 if (!power)
626 return -ENOMEM;
627 platform_set_drvdata(pdev, power);
628
629 power->dev = dev;
630 power->base = pm->base;
631 power->asb = pm->asb;
632 power->rpivid_asb = pm->rpivid_asb;
633
634 if (power->asb) {
635 id = readl(power->asb + ASB_AXI_BRDG_ID);
636 if (id != BCM2835_BRDG_ID /* "BRDG" */) {
637 dev_err(dev, "ASB register ID returned 0x%08x\n", id);
638 return -ENODEV;
639 }
640 }
641
642 if (power->rpivid_asb) {
643 id = readl(power->rpivid_asb + ASB_AXI_BRDG_ID);
644 if (id != BCM2835_BRDG_ID /* "BRDG" */) {
645 dev_err(dev, "RPiVid ASB register ID returned 0x%08x\n",
646 id);
647 return -ENODEV;
648 }
649 }
650
651 power->pd_xlate.domains = devm_kcalloc(dev,
652 ARRAY_SIZE(power_domain_names),
653 sizeof(*power->pd_xlate.domains),
654 GFP_KERNEL);
655 if (!power->pd_xlate.domains)
656 return -ENOMEM;
657
658 power->pd_xlate.num_domains = ARRAY_SIZE(power_domain_names);
659
660 for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
661 ret = bcm2835_init_power_domain(power, i, power_domain_names[i]);
662 if (ret)
663 goto fail;
664 }
665
666 for (i = 0; i < ARRAY_SIZE(domain_deps); i++) {
667 pm_genpd_add_subdomain(&power->domains[domain_deps[i].parent].base,
668 &power->domains[domain_deps[i].child].base);
669 }
670
671 power->reset.owner = THIS_MODULE;
672 power->reset.nr_resets = BCM2835_RESET_COUNT;
673 power->reset.ops = &bcm2835_reset_ops;
674 power->reset.of_node = dev->parent->of_node;
675
676 ret = devm_reset_controller_register(dev, &power->reset);
677 if (ret)
678 goto fail;
679
680 of_genpd_add_provider_onecell(dev->parent->of_node, &power->pd_xlate);
681
682 dev_info(dev, "Broadcom BCM2835 power domains driver");
683 return 0;
684
685 fail:
686 for (i = 0; i < ARRAY_SIZE(power_domain_names); i++) {
687 struct generic_pm_domain *dom = &power->domains[i].base;
688
689 if (dom->name)
690 pm_genpd_remove(dom);
691 }
692 return ret;
693 }
694
695 static struct platform_driver bcm2835_power_driver = {
696 .probe = bcm2835_power_probe,
697 .driver = {
698 .name = "bcm2835-power",
699 },
700 };
701 module_platform_driver(bcm2835_power_driver);
702
703 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
704 MODULE_DESCRIPTION("Driver for Broadcom BCM2835 PM power domains and reset");
705