1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * pmbus.h - Common defines and structures for PMBus devices 4 * 5 * Copyright (c) 2010, 2011 Ericsson AB. 6 * Copyright (c) 2012 Guenter Roeck 7 */ 8 9 #ifndef PMBUS_H 10 #define PMBUS_H 11 12 #include <linux/bitops.h> 13 #include <linux/cleanup.h> 14 #include <linux/regulator/driver.h> 15 16 /* 17 * Registers 18 */ 19 enum pmbus_regs { 20 PMBUS_PAGE = 0x00, 21 PMBUS_OPERATION = 0x01, 22 PMBUS_ON_OFF_CONFIG = 0x02, 23 PMBUS_CLEAR_FAULTS = 0x03, 24 PMBUS_PHASE = 0x04, 25 26 PMBUS_WRITE_PROTECT = 0x10, 27 28 PMBUS_CAPABILITY = 0x19, 29 PMBUS_QUERY = 0x1A, 30 PMBUS_SMBALERT_MASK = 0x1B, 31 PMBUS_VOUT_MODE = 0x20, 32 PMBUS_VOUT_COMMAND = 0x21, 33 PMBUS_VOUT_TRIM = 0x22, 34 PMBUS_VOUT_CAL_OFFSET = 0x23, 35 PMBUS_VOUT_MAX = 0x24, 36 PMBUS_VOUT_MARGIN_HIGH = 0x25, 37 PMBUS_VOUT_MARGIN_LOW = 0x26, 38 PMBUS_VOUT_TRANSITION_RATE = 0x27, 39 PMBUS_VOUT_DROOP = 0x28, 40 PMBUS_VOUT_SCALE_LOOP = 0x29, 41 PMBUS_VOUT_SCALE_MONITOR = 0x2A, 42 43 PMBUS_COEFFICIENTS = 0x30, 44 PMBUS_POUT_MAX = 0x31, 45 46 PMBUS_FAN_CONFIG_12 = 0x3A, 47 PMBUS_FAN_COMMAND_1 = 0x3B, 48 PMBUS_FAN_COMMAND_2 = 0x3C, 49 PMBUS_FAN_CONFIG_34 = 0x3D, 50 PMBUS_FAN_COMMAND_3 = 0x3E, 51 PMBUS_FAN_COMMAND_4 = 0x3F, 52 53 PMBUS_VOUT_OV_FAULT_LIMIT = 0x40, 54 PMBUS_VOUT_OV_FAULT_RESPONSE = 0x41, 55 PMBUS_VOUT_OV_WARN_LIMIT = 0x42, 56 PMBUS_VOUT_UV_WARN_LIMIT = 0x43, 57 PMBUS_VOUT_UV_FAULT_LIMIT = 0x44, 58 PMBUS_VOUT_UV_FAULT_RESPONSE = 0x45, 59 PMBUS_IOUT_OC_FAULT_LIMIT = 0x46, 60 PMBUS_IOUT_OC_FAULT_RESPONSE = 0x47, 61 PMBUS_IOUT_OC_LV_FAULT_LIMIT = 0x48, 62 PMBUS_IOUT_OC_LV_FAULT_RESPONSE = 0x49, 63 PMBUS_IOUT_OC_WARN_LIMIT = 0x4A, 64 PMBUS_IOUT_UC_FAULT_LIMIT = 0x4B, 65 PMBUS_IOUT_UC_FAULT_RESPONSE = 0x4C, 66 67 PMBUS_OT_FAULT_LIMIT = 0x4F, 68 PMBUS_OT_FAULT_RESPONSE = 0x50, 69 PMBUS_OT_WARN_LIMIT = 0x51, 70 PMBUS_UT_WARN_LIMIT = 0x52, 71 PMBUS_UT_FAULT_LIMIT = 0x53, 72 PMBUS_UT_FAULT_RESPONSE = 0x54, 73 PMBUS_VIN_OV_FAULT_LIMIT = 0x55, 74 PMBUS_VIN_OV_FAULT_RESPONSE = 0x56, 75 PMBUS_VIN_OV_WARN_LIMIT = 0x57, 76 PMBUS_VIN_UV_WARN_LIMIT = 0x58, 77 PMBUS_VIN_UV_FAULT_LIMIT = 0x59, 78 79 PMBUS_IIN_OC_FAULT_LIMIT = 0x5B, 80 PMBUS_IIN_OC_WARN_LIMIT = 0x5D, 81 82 PMBUS_POUT_OP_FAULT_LIMIT = 0x68, 83 PMBUS_POUT_OP_WARN_LIMIT = 0x6A, 84 PMBUS_PIN_OP_WARN_LIMIT = 0x6B, 85 86 PMBUS_STATUS_BYTE = 0x78, 87 PMBUS_STATUS_WORD = 0x79, 88 PMBUS_STATUS_VOUT = 0x7A, 89 PMBUS_STATUS_IOUT = 0x7B, 90 PMBUS_STATUS_INPUT = 0x7C, 91 PMBUS_STATUS_TEMPERATURE = 0x7D, 92 PMBUS_STATUS_CML = 0x7E, 93 PMBUS_STATUS_OTHER = 0x7F, 94 PMBUS_STATUS_MFR_SPECIFIC = 0x80, 95 PMBUS_STATUS_FAN_12 = 0x81, 96 PMBUS_STATUS_FAN_34 = 0x82, 97 98 PMBUS_READ_VIN = 0x88, 99 PMBUS_READ_IIN = 0x89, 100 PMBUS_READ_VCAP = 0x8A, 101 PMBUS_READ_VOUT = 0x8B, 102 PMBUS_READ_IOUT = 0x8C, 103 PMBUS_READ_TEMPERATURE_1 = 0x8D, 104 PMBUS_READ_TEMPERATURE_2 = 0x8E, 105 PMBUS_READ_TEMPERATURE_3 = 0x8F, 106 PMBUS_READ_FAN_SPEED_1 = 0x90, 107 PMBUS_READ_FAN_SPEED_2 = 0x91, 108 PMBUS_READ_FAN_SPEED_3 = 0x92, 109 PMBUS_READ_FAN_SPEED_4 = 0x93, 110 PMBUS_READ_DUTY_CYCLE = 0x94, 111 PMBUS_READ_FREQUENCY = 0x95, 112 PMBUS_READ_POUT = 0x96, 113 PMBUS_READ_PIN = 0x97, 114 115 PMBUS_REVISION = 0x98, 116 PMBUS_MFR_ID = 0x99, 117 PMBUS_MFR_MODEL = 0x9A, 118 PMBUS_MFR_REVISION = 0x9B, 119 PMBUS_MFR_LOCATION = 0x9C, 120 PMBUS_MFR_DATE = 0x9D, 121 PMBUS_MFR_SERIAL = 0x9E, 122 123 PMBUS_MFR_VIN_MIN = 0xA0, 124 PMBUS_MFR_VIN_MAX = 0xA1, 125 PMBUS_MFR_IIN_MAX = 0xA2, 126 PMBUS_MFR_PIN_MAX = 0xA3, 127 PMBUS_MFR_VOUT_MIN = 0xA4, 128 PMBUS_MFR_VOUT_MAX = 0xA5, 129 PMBUS_MFR_IOUT_MAX = 0xA6, 130 PMBUS_MFR_POUT_MAX = 0xA7, 131 132 PMBUS_IC_DEVICE_ID = 0xAD, 133 PMBUS_IC_DEVICE_REV = 0xAE, 134 135 PMBUS_MFR_MAX_TEMP_1 = 0xC0, 136 PMBUS_MFR_MAX_TEMP_2 = 0xC1, 137 PMBUS_MFR_MAX_TEMP_3 = 0xC2, 138 139 /* 140 * Virtual registers. 141 * Useful to support attributes which are not supported by standard PMBus 142 * registers but exist as manufacturer specific registers on individual chips. 143 * Must be mapped to real registers in device specific code. 144 * 145 * Semantics: 146 * Virtual registers are all word size. 147 * READ registers are read-only; writes are either ignored or return an error. 148 * RESET registers are read/write. Reading reset registers returns zero 149 * (used for detection), writing any value causes the associated history to be 150 * reset. 151 * Virtual registers have to be handled in device specific driver code. Chip 152 * driver code returns non-negative register values if a virtual register is 153 * supported, or a negative error code if not. The chip driver may return 154 * -ENODATA or any other error code in this case, though an error code other 155 * than -ENODATA is handled more efficiently and thus preferred. Either case, 156 * the calling PMBus core code will abort if the chip driver returns an error 157 * code when reading or writing virtual registers. 158 */ 159 PMBUS_VIRT_BASE = 0x100, 160 PMBUS_VIRT_READ_TEMP_AVG, 161 PMBUS_VIRT_READ_TEMP_MIN, 162 PMBUS_VIRT_READ_TEMP_MAX, 163 PMBUS_VIRT_RESET_TEMP_HISTORY, 164 PMBUS_VIRT_READ_VIN_AVG, 165 PMBUS_VIRT_READ_VIN_MIN, 166 PMBUS_VIRT_READ_VIN_MAX, 167 PMBUS_VIRT_RESET_VIN_HISTORY, 168 PMBUS_VIRT_READ_IIN_AVG, 169 PMBUS_VIRT_READ_IIN_MIN, 170 PMBUS_VIRT_READ_IIN_MAX, 171 PMBUS_VIRT_RESET_IIN_HISTORY, 172 PMBUS_VIRT_READ_PIN_AVG, 173 PMBUS_VIRT_READ_PIN_MIN, 174 PMBUS_VIRT_READ_PIN_MAX, 175 PMBUS_VIRT_RESET_PIN_HISTORY, 176 PMBUS_VIRT_READ_POUT_AVG, 177 PMBUS_VIRT_READ_POUT_MIN, 178 PMBUS_VIRT_READ_POUT_MAX, 179 PMBUS_VIRT_RESET_POUT_HISTORY, 180 PMBUS_VIRT_READ_VOUT_AVG, 181 PMBUS_VIRT_READ_VOUT_MIN, 182 PMBUS_VIRT_READ_VOUT_MAX, 183 PMBUS_VIRT_RESET_VOUT_HISTORY, 184 PMBUS_VIRT_READ_IOUT_AVG, 185 PMBUS_VIRT_READ_IOUT_MIN, 186 PMBUS_VIRT_READ_IOUT_MAX, 187 PMBUS_VIRT_RESET_IOUT_HISTORY, 188 PMBUS_VIRT_READ_TEMP2_AVG, 189 PMBUS_VIRT_READ_TEMP2_MIN, 190 PMBUS_VIRT_READ_TEMP2_MAX, 191 PMBUS_VIRT_RESET_TEMP2_HISTORY, 192 193 PMBUS_VIRT_READ_VMON, 194 PMBUS_VIRT_VMON_UV_WARN_LIMIT, 195 PMBUS_VIRT_VMON_OV_WARN_LIMIT, 196 PMBUS_VIRT_VMON_UV_FAULT_LIMIT, 197 PMBUS_VIRT_VMON_OV_FAULT_LIMIT, 198 PMBUS_VIRT_STATUS_VMON, 199 200 /* 201 * RPM and PWM Fan control 202 * 203 * Drivers wanting to expose PWM control must define the behaviour of 204 * PMBUS_VIRT_PWM_[1-4] and PMBUS_VIRT_PWM_ENABLE_[1-4] in the 205 * {read,write}_word_data callback. 206 * 207 * pmbus core provides a default implementation for 208 * PMBUS_VIRT_FAN_TARGET_[1-4]. 209 * 210 * TARGET, PWM and PWM_ENABLE members must be defined sequentially; 211 * pmbus core uses the difference between the provided register and 212 * it's _1 counterpart to calculate the FAN/PWM ID. 213 */ 214 PMBUS_VIRT_FAN_TARGET_1, 215 PMBUS_VIRT_FAN_TARGET_2, 216 PMBUS_VIRT_FAN_TARGET_3, 217 PMBUS_VIRT_FAN_TARGET_4, 218 PMBUS_VIRT_PWM_1, 219 PMBUS_VIRT_PWM_2, 220 PMBUS_VIRT_PWM_3, 221 PMBUS_VIRT_PWM_4, 222 PMBUS_VIRT_PWM_ENABLE_1, 223 PMBUS_VIRT_PWM_ENABLE_2, 224 PMBUS_VIRT_PWM_ENABLE_3, 225 PMBUS_VIRT_PWM_ENABLE_4, 226 227 /* Samples for average 228 * 229 * Drivers wanting to expose functionality for changing the number of 230 * samples used for average values should implement support in 231 * {read,write}_word_data callback for either PMBUS_VIRT_SAMPLES if it 232 * applies to all types of measurements, or any number of specific 233 * PMBUS_VIRT_*_SAMPLES registers to allow for individual control. 234 */ 235 PMBUS_VIRT_SAMPLES, 236 PMBUS_VIRT_IN_SAMPLES, 237 PMBUS_VIRT_CURR_SAMPLES, 238 PMBUS_VIRT_POWER_SAMPLES, 239 PMBUS_VIRT_TEMP_SAMPLES, 240 }; 241 242 /* 243 * OPERATION 244 */ 245 #define PB_OPERATION_CONTROL_V_SRC GENMASK(5, 4) 246 #define PB_OPERATION_CONTROL_ON BIT(7) 247 248 /* 249 * ON_OFF_CONFIG 250 */ 251 #define PB_ON_OFF_CONFIG_POWERUP_CONTROL BIT(4) 252 #define PB_ON_OFF_CONFIG_OPERATION_REQ BIT(3) 253 #define PB_ON_OFF_CONFIG_EN_PIN_REQ BIT(2) 254 #define PB_ON_OFF_CONFIG_POLARITY_HIGH BIT(1) 255 #define PB_ON_OFF_CONFIG_TURN_OFF_FAST BIT(0) 256 257 /* 258 * WRITE_PROTECT 259 */ 260 #define PB_WP_ALL BIT(7) /* all but WRITE_PROTECT */ 261 #define PB_WP_OP BIT(6) /* all but WP, OPERATION, PAGE */ 262 #define PB_WP_VOUT BIT(5) /* all but WP, OPERATION, PAGE, VOUT, ON_OFF */ 263 264 #define PB_WP_ANY (PB_WP_ALL | PB_WP_OP | PB_WP_VOUT) 265 266 /* 267 * CAPABILITY 268 */ 269 #define PB_CAPABILITY_SMBALERT BIT(4) 270 #define PB_CAPABILITY_ERROR_CHECK BIT(7) 271 272 /* 273 * VOUT_MODE 274 */ 275 #define PB_VOUT_MODE_MODE_MASK 0xe0 276 #define PB_VOUT_MODE_PARAM_MASK 0x1f 277 278 #define PB_VOUT_MODE_LINEAR 0x00 279 #define PB_VOUT_MODE_VID 0x20 280 #define PB_VOUT_MODE_DIRECT 0x40 281 282 /* 283 * Fan configuration 284 */ 285 #define PB_FAN_2_PULSE_MASK (BIT(0) | BIT(1)) 286 #define PB_FAN_2_RPM BIT(2) 287 #define PB_FAN_2_INSTALLED BIT(3) 288 #define PB_FAN_1_PULSE_MASK (BIT(4) | BIT(5)) 289 #define PB_FAN_1_RPM BIT(6) 290 #define PB_FAN_1_INSTALLED BIT(7) 291 292 enum pmbus_fan_mode { percent = 0, rpm }; 293 294 /* 295 * STATUS_BYTE, STATUS_WORD (lower) 296 */ 297 #define PB_STATUS_NONE_ABOVE BIT(0) 298 #define PB_STATUS_CML BIT(1) 299 #define PB_STATUS_TEMPERATURE BIT(2) 300 #define PB_STATUS_VIN_UV BIT(3) 301 #define PB_STATUS_IOUT_OC BIT(4) 302 #define PB_STATUS_VOUT_OV BIT(5) 303 #define PB_STATUS_OFF BIT(6) 304 #define PB_STATUS_BUSY BIT(7) 305 306 /* 307 * STATUS_WORD (upper) 308 */ 309 #define PB_STATUS_UNKNOWN BIT(8) 310 #define PB_STATUS_OTHER BIT(9) 311 #define PB_STATUS_FANS BIT(10) 312 #define PB_STATUS_POWER_GOOD_N BIT(11) 313 #define PB_STATUS_WORD_MFR BIT(12) 314 #define PB_STATUS_INPUT BIT(13) 315 #define PB_STATUS_IOUT_POUT BIT(14) 316 #define PB_STATUS_VOUT BIT(15) 317 318 /* 319 * STATUS_IOUT 320 */ 321 #define PB_POUT_OP_WARNING BIT(0) 322 #define PB_POUT_OP_FAULT BIT(1) 323 #define PB_POWER_LIMITING BIT(2) 324 #define PB_CURRENT_SHARE_FAULT BIT(3) 325 #define PB_IOUT_UC_FAULT BIT(4) 326 #define PB_IOUT_OC_WARNING BIT(5) 327 #define PB_IOUT_OC_LV_FAULT BIT(6) 328 #define PB_IOUT_OC_FAULT BIT(7) 329 330 /* 331 * STATUS_VOUT, STATUS_INPUT 332 */ 333 #define PB_VOLTAGE_VIN_OFF BIT(3) 334 #define PB_VOLTAGE_UV_FAULT BIT(4) 335 #define PB_VOLTAGE_UV_WARNING BIT(5) 336 #define PB_VOLTAGE_OV_WARNING BIT(6) 337 #define PB_VOLTAGE_OV_FAULT BIT(7) 338 339 /* 340 * STATUS_INPUT 341 */ 342 #define PB_PIN_OP_WARNING BIT(0) 343 #define PB_IIN_OC_WARNING BIT(1) 344 #define PB_IIN_OC_FAULT BIT(2) 345 346 /* 347 * STATUS_TEMPERATURE 348 */ 349 #define PB_TEMP_UT_FAULT BIT(4) 350 #define PB_TEMP_UT_WARNING BIT(5) 351 #define PB_TEMP_OT_WARNING BIT(6) 352 #define PB_TEMP_OT_FAULT BIT(7) 353 354 /* 355 * STATUS_FAN 356 */ 357 #define PB_FAN_AIRFLOW_WARNING BIT(0) 358 #define PB_FAN_AIRFLOW_FAULT BIT(1) 359 #define PB_FAN_FAN2_SPEED_OVERRIDE BIT(2) 360 #define PB_FAN_FAN1_SPEED_OVERRIDE BIT(3) 361 #define PB_FAN_FAN2_WARNING BIT(4) 362 #define PB_FAN_FAN1_WARNING BIT(5) 363 #define PB_FAN_FAN2_FAULT BIT(6) 364 #define PB_FAN_FAN1_FAULT BIT(7) 365 366 /* 367 * CML_FAULT_STATUS 368 */ 369 #define PB_CML_FAULT_OTHER_MEM_LOGIC BIT(0) 370 #define PB_CML_FAULT_OTHER_COMM BIT(1) 371 #define PB_CML_FAULT_PROCESSOR BIT(3) 372 #define PB_CML_FAULT_MEMORY BIT(4) 373 #define PB_CML_FAULT_PACKET_ERROR BIT(5) 374 #define PB_CML_FAULT_INVALID_DATA BIT(6) 375 #define PB_CML_FAULT_INVALID_COMMAND BIT(7) 376 377 enum pmbus_sensor_classes { 378 PSC_VOLTAGE_IN = 0, 379 PSC_VOLTAGE_OUT, 380 PSC_CURRENT_IN, 381 PSC_CURRENT_OUT, 382 PSC_POWER, 383 PSC_TEMPERATURE, 384 PSC_FAN, 385 PSC_PWM, 386 PSC_NUM_CLASSES /* Number of power sensor classes */ 387 }; 388 389 #define PMBUS_PAGES 32 /* Per PMBus specification */ 390 #define PMBUS_PHASES 16 /* Maximum number of phases per page */ 391 392 /* Functionality bit mask */ 393 #define PMBUS_HAVE_VIN BIT(0) 394 #define PMBUS_HAVE_VCAP BIT(1) 395 #define PMBUS_HAVE_VOUT BIT(2) 396 #define PMBUS_HAVE_IIN BIT(3) 397 #define PMBUS_HAVE_IOUT BIT(4) 398 #define PMBUS_HAVE_PIN BIT(5) 399 #define PMBUS_HAVE_POUT BIT(6) 400 #define PMBUS_HAVE_FAN12 BIT(7) 401 #define PMBUS_HAVE_FAN34 BIT(8) 402 #define PMBUS_HAVE_TEMP BIT(9) 403 #define PMBUS_HAVE_TEMP2 BIT(10) 404 #define PMBUS_HAVE_TEMP3 BIT(11) 405 #define PMBUS_HAVE_STATUS_VOUT BIT(12) 406 #define PMBUS_HAVE_STATUS_IOUT BIT(13) 407 #define PMBUS_HAVE_STATUS_INPUT BIT(14) 408 #define PMBUS_HAVE_STATUS_TEMP BIT(15) 409 #define PMBUS_HAVE_STATUS_FAN12 BIT(16) 410 #define PMBUS_HAVE_STATUS_FAN34 BIT(17) 411 #define PMBUS_HAVE_VMON BIT(18) 412 #define PMBUS_HAVE_STATUS_VMON BIT(19) 413 #define PMBUS_HAVE_PWM12 BIT(20) 414 #define PMBUS_HAVE_PWM34 BIT(21) 415 #define PMBUS_HAVE_SAMPLES BIT(22) 416 417 #define PMBUS_PHASE_VIRTUAL BIT(30) /* Phases on this page are virtual */ 418 #define PMBUS_PAGE_VIRTUAL BIT(31) /* Page is virtual */ 419 420 enum pmbus_data_format { linear = 0, ieee754, direct, vid }; 421 enum vrm_version { vr11 = 0, vr12, vr13, imvp9, amd625mv, nvidia195mv }; 422 423 /* PMBus revision identifiers */ 424 #define PMBUS_REV_10 0x00 /* PMBus revision 1.0 */ 425 #define PMBUS_REV_11 0x11 /* PMBus revision 1.1 */ 426 #define PMBUS_REV_12 0x22 /* PMBus revision 1.2 */ 427 #define PMBUS_REV_13 0x33 /* PMBus revision 1.3 */ 428 #define PMBUS_REV_131 0x44 /* PMBus revision 1.3.1 */ 429 #define PMBUS_REV_14 0x55 /* PMBus revision 1.4 */ 430 431 /* Operation type flags for pmbus_update_ts */ 432 #define PMBUS_OP_WRITE BIT(0) 433 #define PMBUS_OP_PAGE_CHANGE BIT(1) 434 435 struct pmbus_driver_info { 436 int pages; /* Total number of pages */ 437 u8 phases[PMBUS_PAGES]; /* Number of phases per page */ 438 enum pmbus_data_format format[PSC_NUM_CLASSES]; 439 enum vrm_version vrm_version[PMBUS_PAGES]; /* vrm version per page */ 440 /* 441 * Support one set of coefficients for each sensor type 442 * Used for chips providing data in direct mode. 443 */ 444 int m[PSC_NUM_CLASSES]; /* mantissa for direct data format */ 445 int b[PSC_NUM_CLASSES]; /* offset */ 446 int R[PSC_NUM_CLASSES]; /* exponent */ 447 448 u32 func[PMBUS_PAGES]; /* Functionality, per page */ 449 u32 pfunc[PMBUS_PHASES];/* Functionality, per phase */ 450 /* 451 * The following functions map manufacturing specific register values 452 * to PMBus standard register values. Specify only if mapping is 453 * necessary. 454 * Functions return the register value (read) or zero (write) if 455 * successful. A return value of -ENODATA indicates that there is no 456 * manufacturer specific register, but that a standard PMBus register 457 * may exist. Any other negative return value indicates that the 458 * register does not exist, and that no attempt should be made to read 459 * the standard register. 460 */ 461 int (*read_byte_data)(struct i2c_client *client, int page, int reg); 462 int (*read_word_data)(struct i2c_client *client, int page, int phase, 463 int reg); 464 int (*write_byte_data)(struct i2c_client *client, int page, int reg, 465 u8 byte); 466 int (*write_word_data)(struct i2c_client *client, int page, int reg, 467 u16 word); 468 int (*write_byte)(struct i2c_client *client, int page, u8 value); 469 /* 470 * The identify function determines supported PMBus functionality. 471 * This function is only necessary if a chip driver supports multiple 472 * chips, and the chip functionality is not pre-determined. 473 */ 474 int (*identify)(struct i2c_client *client, 475 struct pmbus_driver_info *info); 476 477 /* Regulator functionality, if supported by this chip driver. */ 478 int num_regulators; 479 const struct regulator_desc *reg_desc; 480 481 /* custom attributes */ 482 const struct attribute_group **groups; 483 484 /* 485 * Some chips need a little delay between SMBus communication. When 486 * set, the generic PMBus helper functions will wait if necessary 487 * to meet this requirement. The access delay is honored after 488 * every SMBus operation. The write delay is only honored after 489 * SMBus write operations. 490 */ 491 int access_delay; /* in microseconds */ 492 int write_delay; /* in microseconds */ 493 int page_change_delay; /* in microseconds */ 494 495 /* 496 * Some chips do not support the PMBUS_REVISION command. 497 * Drivers for such chips can report the supported PMBus revision here. 498 * 499 * Drivers must set have_pmbus_revision to true and provide the 500 * supported PMBus version in pmbus_revision. 501 */ 502 bool have_pmbus_revision; /* true if pmbus_revision is valid */ 503 u8 pmbus_revision; /* PMBus revision */ 504 }; 505 506 /* Regulator ops */ 507 508 extern const struct regulator_ops pmbus_regulator_ops; 509 int pmbus_regulator_init_cb(struct regulator_dev *rdev, 510 struct regulator_config *config); 511 512 /* Macros for filling in array of struct regulator_desc */ 513 #define PMBUS_REGULATOR_STEP(_name, _id, _voltages, _step, _min_uV) \ 514 [_id] = { \ 515 .name = (_name # _id), \ 516 .id = (_id), \ 517 .of_match = of_match_ptr(_name # _id), \ 518 .regulators_node = of_match_ptr("regulators"), \ 519 .ops = &pmbus_regulator_ops, \ 520 .type = REGULATOR_VOLTAGE, \ 521 .owner = THIS_MODULE, \ 522 .n_voltages = _voltages, \ 523 .uV_step = _step, \ 524 .min_uV = _min_uV, \ 525 .init_cb = pmbus_regulator_init_cb, \ 526 } 527 528 #define PMBUS_REGULATOR(_name, _id) PMBUS_REGULATOR_STEP(_name, _id, 0, 0, 0) 529 530 #define __PMBUS_REGULATOR_STEP_ONE(_name, _node, _voltages, _step, _min_uV) \ 531 { \ 532 .name = (_name), \ 533 .of_match = of_match_ptr(_name), \ 534 .regulators_node = of_match_ptr(_node), \ 535 .ops = &pmbus_regulator_ops, \ 536 .type = REGULATOR_VOLTAGE, \ 537 .owner = THIS_MODULE, \ 538 .n_voltages = _voltages, \ 539 .uV_step = _step, \ 540 .min_uV = _min_uV, \ 541 .init_cb = pmbus_regulator_init_cb, \ 542 } 543 544 /* 545 * _NODE macros are defined for historic reasons and MUST NOT be used in new 546 * drivers. 547 */ 548 #define PMBUS_REGULATOR_STEP_ONE_NODE(_name, _voltages, _step, _min_uV) \ 549 __PMBUS_REGULATOR_STEP_ONE(_name, "regulators", _voltages, _step, _min_uV) 550 551 #define PMBUS_REGULATOR_ONE_NODE(_name) PMBUS_REGULATOR_STEP_ONE_NODE(_name, 0, 0, 0) 552 553 #define PMBUS_REGULATOR_STEP_ONE(_name, _voltages, _step, _min_uV) \ 554 __PMBUS_REGULATOR_STEP_ONE(_name, NULL, _voltages, _step, _min_uV) 555 556 #define PMBUS_REGULATOR_ONE(_name) PMBUS_REGULATOR_STEP_ONE(_name, 0, 0, 0) 557 558 /* Function declarations */ 559 560 void pmbus_clear_cache(struct i2c_client *client); 561 void pmbus_set_update(struct i2c_client *client, u8 reg, bool update); 562 void pmbus_wait(struct i2c_client *client); 563 void pmbus_update_ts(struct i2c_client *client, int op); 564 int pmbus_set_page(struct i2c_client *client, int page, int phase); 565 int pmbus_read_smbus_i2c_block_data(struct i2c_client *client, u8 reg, char *data_buf); 566 int pmbus_read_word_data(struct i2c_client *client, int page, int phase, 567 u8 reg); 568 int pmbus_write_word_data(struct i2c_client *client, int page, u8 reg, 569 u16 word); 570 int pmbus_read_byte_data(struct i2c_client *client, int page, u8 reg); 571 int pmbus_write_byte(struct i2c_client *client, int page, u8 value); 572 int pmbus_write_byte_data(struct i2c_client *client, int page, u8 reg, 573 u8 value); 574 int pmbus_update_byte_data(struct i2c_client *client, int page, u8 reg, 575 u8 mask, u8 value); 576 void pmbus_clear_faults(struct i2c_client *client); 577 void pmbus_check_and_notify_faults(struct i2c_client *client); 578 bool pmbus_check_byte_register(struct i2c_client *client, int page, int reg); 579 bool pmbus_check_word_register(struct i2c_client *client, int page, int reg); 580 int pmbus_do_probe(struct i2c_client *client, struct pmbus_driver_info *info); 581 const struct pmbus_driver_info *pmbus_get_driver_info(struct i2c_client 582 *client); 583 int pmbus_get_fan_rate_device(struct i2c_client *client, int page, int id, 584 enum pmbus_fan_mode mode); 585 int pmbus_get_fan_rate_cached(struct i2c_client *client, int page, int id, 586 enum pmbus_fan_mode mode); 587 int pmbus_lock_interruptible(struct i2c_client *client); 588 void pmbus_lock(struct i2c_client *client); 589 void pmbus_unlock(struct i2c_client *client); 590 591 DEFINE_GUARD(pmbus_lock, struct i2c_client *, pmbus_lock(_T), pmbus_unlock(_T)) 592 593 int pmbus_update_fan(struct i2c_client *client, int page, int id, 594 u8 config, u8 mask, u16 command); 595 struct dentry *pmbus_get_debugfs_dir(struct i2c_client *client); 596 597 #endif /* PMBUS_H */ 598