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Searched refs:PLL_VPLL (Results 1 – 25 of 25) sorted by relevance

/linux/arch/arm64/boot/dts/rockchip/
H A Drk3566-powkiddy-rk2023.dts17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-powkiddy-rgb30.dts17 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3566-powkiddy-rgb10max3.dts21 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3568-wolfvision-pf5-display.dtsi42 assigned-clocks = <&cru PLL_VPLL>;
H A Drk3566-anbernic-rg353x.dtsi82 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
H A Drk3568-evb1-v10.dts729 assigned-clocks = <&cru DCLK_VOP0>, <&cru PLL_VPLL>, <&cru DCLK_VOP1>;
730 assigned-clock-parents = <&pmucru PLL_HPLL>, <&xin24m>, <&cru PLL_VPLL>;
H A Drk3566-pinetab2.dtsi265 <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
924 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-radxa-zero-3.dtsi517 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-box-demo.dts469 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-lubancat-1.dts576 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-photonicat.dts570 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-nanopi-r5s.dtsi592 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-odroid-m1s.dts650 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-easepi-r1.dts610 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-orangepi-3b.dtsi670 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-quartz64-b.dts732 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-anbernic-rgxx3.dtsi706 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3568-odroid-m1.dts730 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-powkiddy-rk2023.dtsi841 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
H A Drk3566-quartz64-a.dts831 assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
/linux/include/dt-bindings/clock/
H A Drockchip,rk3576-cru.h18 #define PLL_VPLL 2 macro
H A Drk3399-cru.h17 #define PLL_VPLL 7 macro
H A Drk3568-cru.h74 #define PLL_VPLL 5 macro
/linux/drivers/clk/rockchip/
H A Dclk-rk3399.c231 [vpll] = PLL(pll_rk3399, PLL_VPLL, "vpll", mux_pll_p, 0, RK3399_PLL_CON(48),
H A Dclk-rk3576.c372 [vpll] = PLL(pll_rk3588, PLL_VPLL, "vpll", mux_pll_p,