| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3566-powkiddy-rk2023.dts | 16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
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| H A D | rk3566-powkiddy-rgb30.dts | 16 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
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| H A D | rk3566-powkiddy-rgb10max3.dts | 20 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
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| H A D | rk3566-anbernic-rg353x.dtsi | 81 assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
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| H A D | rk3399-pinephone-pro.dts | 815 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
827 assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
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| /linux/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 13 #define PLL_GPLL 3 macro
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| H A D | rk3128-cru.h | 14 #define PLL_GPLL 4 macro
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| H A D | rk3228-cru.h | 14 #define PLL_GPLL 4 macro
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| H A D | rockchip,rk3506-cru.h | 11 #define PLL_GPLL 0 macro
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| H A D | rv1108-cru.h | 13 #define PLL_GPLL 2 macro
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| H A D | rk3328-cru.h | 14 #define PLL_GPLL 4 macro
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| H A D | px30-cru.h | 180 #define PLL_GPLL 1 macro
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| H A D | rk3288-cru.h | 14 #define PLL_GPLL 4 macro
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| H A D | rk3368-cru.h | 14 #define PLL_GPLL 5 macro
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| H A D | rockchip,rv1126b-cru.h | 11 #define PLL_GPLL 0 macro
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| H A D | rockchip,rk3528-cru.h | 14 #define PLL_GPLL 2 macro
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| H A D | rockchip,rv1126-cru.h | 13 #define PLL_GPLL 1 macro
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| H A D | rockchip,rk3576-cru.h | 21 #define PLL_GPLL 5 macro
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| H A D | rk3399-cru.h | 15 #define PLL_GPLL 5 macro
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| H A D | rockchip,rk3588-cru.h | 21 #define PLL_GPLL 6 macro
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| H A D | rk3568-cru.h | 73 #define PLL_GPLL 4 macro
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 142 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
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| H A D | clk-rk3128.c | 165 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(12),
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| H A D | clk-rk3228.c | 175 [gpll] = PLL(pll_rk3036, PLL_GPLL, "gpll", mux_pll_p, 0, RK2928_PLL_CON(9),
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| H A D | clk-rv1108.c | 158 [gpll] = PLL(pll_rk3399, PLL_GPLL, "gpll", mux_pll_p, 0, RV1108_PLL_CON(16),
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