1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2008, Creative Technology Ltd. All Rights Reserved.
4 *
5 * @File cthw20k2.c
6 *
7 * @Brief
8 * This file contains the implementation of hardware access method for 20k2.
9 *
10 * @Author Liu Chun
11 * @Date May 14 2008
12 */
13
14 #include <linux/types.h>
15 #include <linux/slab.h>
16 #include <linux/pci.h>
17 #include <linux/io.h>
18 #include <linux/string.h>
19 #include <linux/kernel.h>
20 #include <linux/interrupt.h>
21 #include <linux/delay.h>
22 #include "cthw20k2.h"
23 #include "ct20k2reg.h"
24
25 struct hw20k2 {
26 struct hw hw;
27 /* for i2c */
28 unsigned char dev_id;
29 unsigned char addr_size;
30 unsigned char data_size;
31
32 int mic_source;
33 };
34
35 static u32 hw_read_20kx(struct hw *hw, u32 reg);
36 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
37
38 /*
39 * Type definition block.
40 * The layout of control structures can be directly applied on 20k2 chip.
41 */
42
43 /*
44 * SRC control block definitions.
45 */
46
47 /* SRC resource control block */
48 #define SRCCTL_STATE 0x00000007
49 #define SRCCTL_BM 0x00000008
50 #define SRCCTL_RSR 0x00000030
51 #define SRCCTL_SF 0x000001C0
52 #define SRCCTL_WR 0x00000200
53 #define SRCCTL_PM 0x00000400
54 #define SRCCTL_ROM 0x00001800
55 #define SRCCTL_VO 0x00002000
56 #define SRCCTL_ST 0x00004000
57 #define SRCCTL_IE 0x00008000
58 #define SRCCTL_ILSZ 0x000F0000
59 #define SRCCTL_BP 0x00100000
60
61 #define SRCCCR_CISZ 0x000007FF
62 #define SRCCCR_CWA 0x001FF800
63 #define SRCCCR_D 0x00200000
64 #define SRCCCR_RS 0x01C00000
65 #define SRCCCR_NAL 0x3E000000
66 #define SRCCCR_RA 0xC0000000
67
68 #define SRCCA_CA 0x0FFFFFFF
69 #define SRCCA_RS 0xE0000000
70
71 #define SRCSA_SA 0x0FFFFFFF
72
73 #define SRCLA_LA 0x0FFFFFFF
74
75 /* Mixer Parameter Ring ram Low and Hight register.
76 * Fixed-point value in 8.24 format for parameter channel */
77 #define MPRLH_PITCH 0xFFFFFFFF
78
79 /* SRC resource register dirty flags */
80 union src_dirty {
81 struct {
82 u16 ctl:1;
83 u16 ccr:1;
84 u16 sa:1;
85 u16 la:1;
86 u16 ca:1;
87 u16 mpr:1;
88 u16 czbfs:1; /* Clear Z-Buffers */
89 u16 rsv:9;
90 } bf;
91 u16 data;
92 };
93
94 struct src_rsc_ctrl_blk {
95 unsigned int ctl;
96 unsigned int ccr;
97 unsigned int ca;
98 unsigned int sa;
99 unsigned int la;
100 unsigned int mpr;
101 union src_dirty dirty;
102 };
103
104 /* SRC manager control block */
105 union src_mgr_dirty {
106 struct {
107 u16 enb0:1;
108 u16 enb1:1;
109 u16 enb2:1;
110 u16 enb3:1;
111 u16 enb4:1;
112 u16 enb5:1;
113 u16 enb6:1;
114 u16 enb7:1;
115 u16 enbsa:1;
116 u16 rsv:7;
117 } bf;
118 u16 data;
119 };
120
121 struct src_mgr_ctrl_blk {
122 unsigned int enbsa;
123 unsigned int enb[8];
124 union src_mgr_dirty dirty;
125 };
126
127 /* SRCIMP manager control block */
128 #define SRCAIM_ARC 0x00000FFF
129 #define SRCAIM_NXT 0x00FF0000
130 #define SRCAIM_SRC 0xFF000000
131
132 struct srcimap {
133 unsigned int srcaim;
134 unsigned int idx;
135 };
136
137 /* SRCIMP manager register dirty flags */
138 union srcimp_mgr_dirty {
139 struct {
140 u16 srcimap:1;
141 u16 rsv:15;
142 } bf;
143 u16 data;
144 };
145
146 struct srcimp_mgr_ctrl_blk {
147 struct srcimap srcimap;
148 union srcimp_mgr_dirty dirty;
149 };
150
151 /*
152 * Function implementation block.
153 */
154
src_get_rsc_ctrl_blk(void ** rblk)155 static int src_get_rsc_ctrl_blk(void **rblk)
156 {
157 struct src_rsc_ctrl_blk *blk;
158
159 *rblk = NULL;
160 blk = kzalloc_obj(*blk);
161 if (!blk)
162 return -ENOMEM;
163
164 *rblk = blk;
165
166 return 0;
167 }
168
src_put_rsc_ctrl_blk(void * blk)169 static int src_put_rsc_ctrl_blk(void *blk)
170 {
171 kfree(blk);
172
173 return 0;
174 }
175
src_set_state(void * blk,unsigned int state)176 static int src_set_state(void *blk, unsigned int state)
177 {
178 struct src_rsc_ctrl_blk *ctl = blk;
179
180 set_field(&ctl->ctl, SRCCTL_STATE, state);
181 ctl->dirty.bf.ctl = 1;
182 return 0;
183 }
184
src_set_bm(void * blk,unsigned int bm)185 static int src_set_bm(void *blk, unsigned int bm)
186 {
187 struct src_rsc_ctrl_blk *ctl = blk;
188
189 set_field(&ctl->ctl, SRCCTL_BM, bm);
190 ctl->dirty.bf.ctl = 1;
191 return 0;
192 }
193
src_set_rsr(void * blk,unsigned int rsr)194 static int src_set_rsr(void *blk, unsigned int rsr)
195 {
196 struct src_rsc_ctrl_blk *ctl = blk;
197
198 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
199 ctl->dirty.bf.ctl = 1;
200 return 0;
201 }
202
src_set_sf(void * blk,unsigned int sf)203 static int src_set_sf(void *blk, unsigned int sf)
204 {
205 struct src_rsc_ctrl_blk *ctl = blk;
206
207 set_field(&ctl->ctl, SRCCTL_SF, sf);
208 ctl->dirty.bf.ctl = 1;
209 return 0;
210 }
211
src_set_wr(void * blk,unsigned int wr)212 static int src_set_wr(void *blk, unsigned int wr)
213 {
214 struct src_rsc_ctrl_blk *ctl = blk;
215
216 set_field(&ctl->ctl, SRCCTL_WR, wr);
217 ctl->dirty.bf.ctl = 1;
218 return 0;
219 }
220
src_set_pm(void * blk,unsigned int pm)221 static int src_set_pm(void *blk, unsigned int pm)
222 {
223 struct src_rsc_ctrl_blk *ctl = blk;
224
225 set_field(&ctl->ctl, SRCCTL_PM, pm);
226 ctl->dirty.bf.ctl = 1;
227 return 0;
228 }
229
src_set_rom(void * blk,unsigned int rom)230 static int src_set_rom(void *blk, unsigned int rom)
231 {
232 struct src_rsc_ctrl_blk *ctl = blk;
233
234 set_field(&ctl->ctl, SRCCTL_ROM, rom);
235 ctl->dirty.bf.ctl = 1;
236 return 0;
237 }
238
src_set_vo(void * blk,unsigned int vo)239 static int src_set_vo(void *blk, unsigned int vo)
240 {
241 struct src_rsc_ctrl_blk *ctl = blk;
242
243 set_field(&ctl->ctl, SRCCTL_VO, vo);
244 ctl->dirty.bf.ctl = 1;
245 return 0;
246 }
247
src_set_st(void * blk,unsigned int st)248 static int src_set_st(void *blk, unsigned int st)
249 {
250 struct src_rsc_ctrl_blk *ctl = blk;
251
252 set_field(&ctl->ctl, SRCCTL_ST, st);
253 ctl->dirty.bf.ctl = 1;
254 return 0;
255 }
256
src_set_ie(void * blk,unsigned int ie)257 static int src_set_ie(void *blk, unsigned int ie)
258 {
259 struct src_rsc_ctrl_blk *ctl = blk;
260
261 set_field(&ctl->ctl, SRCCTL_IE, ie);
262 ctl->dirty.bf.ctl = 1;
263 return 0;
264 }
265
src_set_ilsz(void * blk,unsigned int ilsz)266 static int src_set_ilsz(void *blk, unsigned int ilsz)
267 {
268 struct src_rsc_ctrl_blk *ctl = blk;
269
270 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
271 ctl->dirty.bf.ctl = 1;
272 return 0;
273 }
274
src_set_bp(void * blk,unsigned int bp)275 static int src_set_bp(void *blk, unsigned int bp)
276 {
277 struct src_rsc_ctrl_blk *ctl = blk;
278
279 set_field(&ctl->ctl, SRCCTL_BP, bp);
280 ctl->dirty.bf.ctl = 1;
281 return 0;
282 }
283
src_set_cisz(void * blk,unsigned int cisz)284 static int src_set_cisz(void *blk, unsigned int cisz)
285 {
286 struct src_rsc_ctrl_blk *ctl = blk;
287
288 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
289 ctl->dirty.bf.ccr = 1;
290 return 0;
291 }
292
src_set_ca(void * blk,unsigned int ca)293 static int src_set_ca(void *blk, unsigned int ca)
294 {
295 struct src_rsc_ctrl_blk *ctl = blk;
296
297 set_field(&ctl->ca, SRCCA_CA, ca);
298 ctl->dirty.bf.ca = 1;
299 return 0;
300 }
301
src_set_sa(void * blk,unsigned int sa)302 static int src_set_sa(void *blk, unsigned int sa)
303 {
304 struct src_rsc_ctrl_blk *ctl = blk;
305
306 set_field(&ctl->sa, SRCSA_SA, sa);
307 ctl->dirty.bf.sa = 1;
308 return 0;
309 }
310
src_set_la(void * blk,unsigned int la)311 static int src_set_la(void *blk, unsigned int la)
312 {
313 struct src_rsc_ctrl_blk *ctl = blk;
314
315 set_field(&ctl->la, SRCLA_LA, la);
316 ctl->dirty.bf.la = 1;
317 return 0;
318 }
319
src_set_pitch(void * blk,unsigned int pitch)320 static int src_set_pitch(void *blk, unsigned int pitch)
321 {
322 struct src_rsc_ctrl_blk *ctl = blk;
323
324 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
325 ctl->dirty.bf.mpr = 1;
326 return 0;
327 }
328
src_set_clear_zbufs(void * blk,unsigned int clear)329 static int src_set_clear_zbufs(void *blk, unsigned int clear)
330 {
331 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
332 return 0;
333 }
334
src_set_dirty(void * blk,unsigned int flags)335 static int src_set_dirty(void *blk, unsigned int flags)
336 {
337 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
338 return 0;
339 }
340
src_set_dirty_all(void * blk)341 static int src_set_dirty_all(void *blk)
342 {
343 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
344 return 0;
345 }
346
347 #define AR_SLOT_SIZE 4096
348 #define AR_SLOT_BLOCK_SIZE 16
349 #define AR_PTS_PITCH 6
350 #define AR_PARAM_SRC_OFFSET 0x60
351
src_param_pitch_mixer(unsigned int src_idx)352 static unsigned int src_param_pitch_mixer(unsigned int src_idx)
353 {
354 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
355 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
356
357 }
358
src_commit_write(struct hw * hw,unsigned int idx,void * blk)359 static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
360 {
361 struct src_rsc_ctrl_blk *ctl = blk;
362 int i;
363
364 if (ctl->dirty.bf.czbfs) {
365 /* Clear Z-Buffer registers */
366 for (i = 0; i < 8; i++)
367 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
368
369 for (i = 0; i < 4; i++)
370 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
371
372 for (i = 0; i < 8; i++)
373 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
374
375 ctl->dirty.bf.czbfs = 0;
376 }
377 if (ctl->dirty.bf.mpr) {
378 /* Take the parameter mixer resource in the same group as that
379 * the idx src is in for simplicity. Unlike src, all conjugate
380 * parameter mixer resources must be programmed for
381 * corresponding conjugate src resources. */
382 unsigned int pm_idx = src_param_pitch_mixer(idx);
383 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
384 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
385 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
386 ctl->dirty.bf.mpr = 0;
387 }
388 if (ctl->dirty.bf.sa) {
389 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
390 ctl->dirty.bf.sa = 0;
391 }
392 if (ctl->dirty.bf.la) {
393 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
394 ctl->dirty.bf.la = 0;
395 }
396 if (ctl->dirty.bf.ca) {
397 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
398 ctl->dirty.bf.ca = 0;
399 }
400
401 /* Write srccf register */
402 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
403
404 if (ctl->dirty.bf.ccr) {
405 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
406 ctl->dirty.bf.ccr = 0;
407 }
408 if (ctl->dirty.bf.ctl) {
409 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
410 ctl->dirty.bf.ctl = 0;
411 }
412
413 return 0;
414 }
415
src_get_ca(struct hw * hw,unsigned int idx,void * blk)416 static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
417 {
418 struct src_rsc_ctrl_blk *ctl = blk;
419
420 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
421 ctl->dirty.bf.ca = 0;
422
423 return get_field(ctl->ca, SRCCA_CA);
424 }
425
src_get_dirty(void * blk)426 static unsigned int src_get_dirty(void *blk)
427 {
428 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
429 }
430
src_dirty_conj_mask(void)431 static unsigned int src_dirty_conj_mask(void)
432 {
433 return 0x20;
434 }
435
src_mgr_enbs_src(void * blk,unsigned int idx)436 static int src_mgr_enbs_src(void *blk, unsigned int idx)
437 {
438 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
439 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
440 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
441 return 0;
442 }
443
src_mgr_enb_src(void * blk,unsigned int idx)444 static int src_mgr_enb_src(void *blk, unsigned int idx)
445 {
446 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
447 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
448 return 0;
449 }
450
src_mgr_dsb_src(void * blk,unsigned int idx)451 static int src_mgr_dsb_src(void *blk, unsigned int idx)
452 {
453 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
454 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
455 return 0;
456 }
457
src_mgr_commit_write(struct hw * hw,void * blk)458 static int src_mgr_commit_write(struct hw *hw, void *blk)
459 {
460 struct src_mgr_ctrl_blk *ctl = blk;
461 int i;
462 unsigned int ret;
463
464 if (ctl->dirty.bf.enbsa) {
465 do {
466 ret = hw_read_20kx(hw, SRC_ENBSTAT);
467 } while (ret & 0x1);
468 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
469 ctl->dirty.bf.enbsa = 0;
470 }
471 for (i = 0; i < 8; i++) {
472 if ((ctl->dirty.data & (0x1 << i))) {
473 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
474 ctl->dirty.data &= ~(0x1 << i);
475 }
476 }
477
478 return 0;
479 }
480
src_mgr_get_ctrl_blk(void ** rblk)481 static int src_mgr_get_ctrl_blk(void **rblk)
482 {
483 struct src_mgr_ctrl_blk *blk;
484
485 *rblk = NULL;
486 blk = kzalloc_obj(*blk);
487 if (!blk)
488 return -ENOMEM;
489
490 *rblk = blk;
491
492 return 0;
493 }
494
src_mgr_put_ctrl_blk(void * blk)495 static int src_mgr_put_ctrl_blk(void *blk)
496 {
497 kfree(blk);
498
499 return 0;
500 }
501
srcimp_mgr_get_ctrl_blk(void ** rblk)502 static int srcimp_mgr_get_ctrl_blk(void **rblk)
503 {
504 struct srcimp_mgr_ctrl_blk *blk;
505
506 *rblk = NULL;
507 blk = kzalloc_obj(*blk);
508 if (!blk)
509 return -ENOMEM;
510
511 *rblk = blk;
512
513 return 0;
514 }
515
srcimp_mgr_put_ctrl_blk(void * blk)516 static int srcimp_mgr_put_ctrl_blk(void *blk)
517 {
518 kfree(blk);
519
520 return 0;
521 }
522
srcimp_mgr_set_imaparc(void * blk,unsigned int slot)523 static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
524 {
525 struct srcimp_mgr_ctrl_blk *ctl = blk;
526
527 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
528 ctl->dirty.bf.srcimap = 1;
529 return 0;
530 }
531
srcimp_mgr_set_imapuser(void * blk,unsigned int user)532 static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
533 {
534 struct srcimp_mgr_ctrl_blk *ctl = blk;
535
536 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
537 ctl->dirty.bf.srcimap = 1;
538 return 0;
539 }
540
srcimp_mgr_set_imapnxt(void * blk,unsigned int next)541 static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
542 {
543 struct srcimp_mgr_ctrl_blk *ctl = blk;
544
545 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
546 ctl->dirty.bf.srcimap = 1;
547 return 0;
548 }
549
srcimp_mgr_set_imapaddr(void * blk,unsigned int addr)550 static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
551 {
552 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
553 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
554 return 0;
555 }
556
srcimp_mgr_commit_write(struct hw * hw,void * blk)557 static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
558 {
559 struct srcimp_mgr_ctrl_blk *ctl = blk;
560
561 if (ctl->dirty.bf.srcimap) {
562 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
563 ctl->srcimap.srcaim);
564 ctl->dirty.bf.srcimap = 0;
565 }
566
567 return 0;
568 }
569
570 /*
571 * AMIXER control block definitions.
572 */
573
574 #define AMOPLO_M 0x00000003
575 #define AMOPLO_IV 0x00000004
576 #define AMOPLO_X 0x0003FFF0
577 #define AMOPLO_Y 0xFFFC0000
578
579 #define AMOPHI_SADR 0x000000FF
580 #define AMOPHI_SE 0x80000000
581
582 /* AMIXER resource register dirty flags */
583 union amixer_dirty {
584 struct {
585 u16 amoplo:1;
586 u16 amophi:1;
587 u16 rsv:14;
588 } bf;
589 u16 data;
590 };
591
592 /* AMIXER resource control block */
593 struct amixer_rsc_ctrl_blk {
594 unsigned int amoplo;
595 unsigned int amophi;
596 union amixer_dirty dirty;
597 };
598
amixer_set_mode(void * blk,unsigned int mode)599 static int amixer_set_mode(void *blk, unsigned int mode)
600 {
601 struct amixer_rsc_ctrl_blk *ctl = blk;
602
603 set_field(&ctl->amoplo, AMOPLO_M, mode);
604 ctl->dirty.bf.amoplo = 1;
605 return 0;
606 }
607
amixer_set_iv(void * blk,unsigned int iv)608 static int amixer_set_iv(void *blk, unsigned int iv)
609 {
610 struct amixer_rsc_ctrl_blk *ctl = blk;
611
612 set_field(&ctl->amoplo, AMOPLO_IV, iv);
613 ctl->dirty.bf.amoplo = 1;
614 return 0;
615 }
616
amixer_set_x(void * blk,unsigned int x)617 static int amixer_set_x(void *blk, unsigned int x)
618 {
619 struct amixer_rsc_ctrl_blk *ctl = blk;
620
621 set_field(&ctl->amoplo, AMOPLO_X, x);
622 ctl->dirty.bf.amoplo = 1;
623 return 0;
624 }
625
amixer_set_y(void * blk,unsigned int y)626 static int amixer_set_y(void *blk, unsigned int y)
627 {
628 struct amixer_rsc_ctrl_blk *ctl = blk;
629
630 set_field(&ctl->amoplo, AMOPLO_Y, y);
631 ctl->dirty.bf.amoplo = 1;
632 return 0;
633 }
634
amixer_set_sadr(void * blk,unsigned int sadr)635 static int amixer_set_sadr(void *blk, unsigned int sadr)
636 {
637 struct amixer_rsc_ctrl_blk *ctl = blk;
638
639 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
640 ctl->dirty.bf.amophi = 1;
641 return 0;
642 }
643
amixer_set_se(void * blk,unsigned int se)644 static int amixer_set_se(void *blk, unsigned int se)
645 {
646 struct amixer_rsc_ctrl_blk *ctl = blk;
647
648 set_field(&ctl->amophi, AMOPHI_SE, se);
649 ctl->dirty.bf.amophi = 1;
650 return 0;
651 }
652
amixer_set_dirty(void * blk,unsigned int flags)653 static int amixer_set_dirty(void *blk, unsigned int flags)
654 {
655 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
656 return 0;
657 }
658
amixer_set_dirty_all(void * blk)659 static int amixer_set_dirty_all(void *blk)
660 {
661 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
662 return 0;
663 }
664
amixer_commit_write(struct hw * hw,unsigned int idx,void * blk)665 static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
666 {
667 struct amixer_rsc_ctrl_blk *ctl = blk;
668
669 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
670 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
671 ctl->dirty.bf.amoplo = 0;
672 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
673 ctl->dirty.bf.amophi = 0;
674 }
675
676 return 0;
677 }
678
amixer_get_y(void * blk)679 static int amixer_get_y(void *blk)
680 {
681 struct amixer_rsc_ctrl_blk *ctl = blk;
682
683 return get_field(ctl->amoplo, AMOPLO_Y);
684 }
685
amixer_get_dirty(void * blk)686 static unsigned int amixer_get_dirty(void *blk)
687 {
688 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
689 }
690
amixer_rsc_get_ctrl_blk(void ** rblk)691 static int amixer_rsc_get_ctrl_blk(void **rblk)
692 {
693 struct amixer_rsc_ctrl_blk *blk;
694
695 *rblk = NULL;
696 blk = kzalloc_obj(*blk);
697 if (!blk)
698 return -ENOMEM;
699
700 *rblk = blk;
701
702 return 0;
703 }
704
amixer_rsc_put_ctrl_blk(void * blk)705 static int amixer_rsc_put_ctrl_blk(void *blk)
706 {
707 kfree(blk);
708
709 return 0;
710 }
711
amixer_mgr_get_ctrl_blk(void ** rblk)712 static int amixer_mgr_get_ctrl_blk(void **rblk)
713 {
714 *rblk = NULL;
715
716 return 0;
717 }
718
amixer_mgr_put_ctrl_blk(void * blk)719 static int amixer_mgr_put_ctrl_blk(void *blk)
720 {
721 return 0;
722 }
723
724 /*
725 * DAIO control block definitions.
726 */
727
728 /* Receiver Sample Rate Tracker Control register */
729 #define SRTCTL_SRCO 0x000000FF
730 #define SRTCTL_SRCM 0x0000FF00
731 #define SRTCTL_RSR 0x00030000
732 #define SRTCTL_DRAT 0x00300000
733 #define SRTCTL_EC 0x01000000
734 #define SRTCTL_ET 0x10000000
735
736 /* DAIO Receiver register dirty flags */
737 union dai_dirty {
738 struct {
739 u16 srt:1;
740 u16 rsv:15;
741 } bf;
742 u16 data;
743 };
744
745 /* DAIO Receiver control block */
746 struct dai_ctrl_blk {
747 unsigned int srt;
748 union dai_dirty dirty;
749 };
750
751 /* Audio Input Mapper RAM */
752 #define AIM_ARC 0x00000FFF
753 #define AIM_NXT 0x007F0000
754
755 struct daoimap {
756 unsigned int aim;
757 unsigned int idx;
758 };
759
760 /* Audio Transmitter Control and Status register */
761 #define ATXCTL_EN 0x00000001
762 #define ATXCTL_MODE 0x00000010
763 #define ATXCTL_CD 0x00000020
764 #define ATXCTL_RAW 0x00000100
765 #define ATXCTL_MT 0x00000200
766 #define ATXCTL_NUC 0x00003000
767 #define ATXCTL_BEN 0x00010000
768 #define ATXCTL_BMUX 0x00700000
769 #define ATXCTL_B24 0x01000000
770 #define ATXCTL_CPF 0x02000000
771 #define ATXCTL_RIV 0x10000000
772 #define ATXCTL_LIV 0x20000000
773 #define ATXCTL_RSAT 0x40000000
774 #define ATXCTL_LSAT 0x80000000
775
776 /* XDIF Transmitter register dirty flags */
777 union dao_dirty {
778 struct {
779 u16 atxcsl:1;
780 u16 rsv:15;
781 } bf;
782 u16 data;
783 };
784
785 /* XDIF Transmitter control block */
786 struct dao_ctrl_blk {
787 /* XDIF Transmitter Channel Status Low Register */
788 unsigned int atxcsl;
789 union dao_dirty dirty;
790 };
791
792 /* Audio Receiver Control register */
793 #define ARXCTL_EN 0x00000001
794
795 /* DAIO manager register dirty flags */
796 union daio_mgr_dirty {
797 struct {
798 u32 atxctl:8;
799 u32 arxctl:8;
800 u32 daoimap:1;
801 u32 rsv:15;
802 } bf;
803 u32 data;
804 };
805
806 /* DAIO manager control block */
807 struct daio_mgr_ctrl_blk {
808 struct daoimap daoimap;
809 unsigned int txctl[8];
810 unsigned int rxctl[8];
811 union daio_mgr_dirty dirty;
812 };
813
dai_srt_set_srco(void * blk,unsigned int src)814 static int dai_srt_set_srco(void *blk, unsigned int src)
815 {
816 struct dai_ctrl_blk *ctl = blk;
817
818 set_field(&ctl->srt, SRTCTL_SRCO, src);
819 ctl->dirty.bf.srt = 1;
820 return 0;
821 }
822
dai_srt_set_srcm(void * blk,unsigned int src)823 static int dai_srt_set_srcm(void *blk, unsigned int src)
824 {
825 struct dai_ctrl_blk *ctl = blk;
826
827 set_field(&ctl->srt, SRTCTL_SRCM, src);
828 ctl->dirty.bf.srt = 1;
829 return 0;
830 }
831
dai_srt_set_rsr(void * blk,unsigned int rsr)832 static int dai_srt_set_rsr(void *blk, unsigned int rsr)
833 {
834 struct dai_ctrl_blk *ctl = blk;
835
836 set_field(&ctl->srt, SRTCTL_RSR, rsr);
837 ctl->dirty.bf.srt = 1;
838 return 0;
839 }
840
dai_srt_set_drat(void * blk,unsigned int drat)841 static int dai_srt_set_drat(void *blk, unsigned int drat)
842 {
843 struct dai_ctrl_blk *ctl = blk;
844
845 set_field(&ctl->srt, SRTCTL_DRAT, drat);
846 ctl->dirty.bf.srt = 1;
847 return 0;
848 }
849
dai_srt_set_ec(void * blk,unsigned int ec)850 static int dai_srt_set_ec(void *blk, unsigned int ec)
851 {
852 struct dai_ctrl_blk *ctl = blk;
853
854 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
855 ctl->dirty.bf.srt = 1;
856 return 0;
857 }
858
dai_srt_set_et(void * blk,unsigned int et)859 static int dai_srt_set_et(void *blk, unsigned int et)
860 {
861 struct dai_ctrl_blk *ctl = blk;
862
863 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
864 ctl->dirty.bf.srt = 1;
865 return 0;
866 }
867
dai_commit_write(struct hw * hw,unsigned int idx,void * blk)868 static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
869 {
870 struct dai_ctrl_blk *ctl = blk;
871
872 if (ctl->dirty.bf.srt) {
873 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
874 ctl->dirty.bf.srt = 0;
875 }
876
877 return 0;
878 }
879
dai_get_ctrl_blk(void ** rblk)880 static int dai_get_ctrl_blk(void **rblk)
881 {
882 struct dai_ctrl_blk *blk;
883
884 *rblk = NULL;
885 blk = kzalloc_obj(*blk);
886 if (!blk)
887 return -ENOMEM;
888
889 *rblk = blk;
890
891 return 0;
892 }
893
dai_put_ctrl_blk(void * blk)894 static int dai_put_ctrl_blk(void *blk)
895 {
896 kfree(blk);
897
898 return 0;
899 }
900
dao_set_spos(void * blk,unsigned int spos)901 static int dao_set_spos(void *blk, unsigned int spos)
902 {
903 ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
904 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
905 return 0;
906 }
907
dao_commit_write(struct hw * hw,unsigned int idx,void * blk)908 static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
909 {
910 struct dao_ctrl_blk *ctl = blk;
911
912 if (ctl->dirty.bf.atxcsl) {
913 if ((idx < 4) && ((hw->model != CTOK0010) || (idx < 3))) {
914 /* S/PDIF SPOSx */
915 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
916 ctl->atxcsl);
917 }
918 ctl->dirty.bf.atxcsl = 0;
919 }
920
921 return 0;
922 }
923
dao_get_spos(void * blk,unsigned int * spos)924 static int dao_get_spos(void *blk, unsigned int *spos)
925 {
926 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
927 return 0;
928 }
929
dao_get_ctrl_blk(void ** rblk)930 static int dao_get_ctrl_blk(void **rblk)
931 {
932 struct dao_ctrl_blk *blk;
933
934 *rblk = NULL;
935 blk = kzalloc_obj(*blk);
936 if (!blk)
937 return -ENOMEM;
938
939 *rblk = blk;
940
941 return 0;
942 }
943
dao_put_ctrl_blk(void * blk)944 static int dao_put_ctrl_blk(void *blk)
945 {
946 kfree(blk);
947
948 return 0;
949 }
950
daio_mgr_enb_dai(void * blk,unsigned int idx)951 static int daio_mgr_enb_dai(void *blk, unsigned int idx)
952 {
953 struct daio_mgr_ctrl_blk *ctl = blk;
954
955 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
956 ctl->dirty.bf.arxctl |= (0x1 << idx);
957 return 0;
958 }
959
daio_mgr_dsb_dai(void * blk,unsigned int idx)960 static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
961 {
962 struct daio_mgr_ctrl_blk *ctl = blk;
963
964 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
965
966 ctl->dirty.bf.arxctl |= (0x1 << idx);
967 return 0;
968 }
969
daio_mgr_enb_dao(void * blk,unsigned int idx)970 static int daio_mgr_enb_dao(void *blk, unsigned int idx)
971 {
972 struct daio_mgr_ctrl_blk *ctl = blk;
973
974 set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
975 ctl->dirty.bf.atxctl |= (0x1 << idx);
976 return 0;
977 }
978
daio_mgr_dsb_dao(void * blk,unsigned int idx)979 static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
980 {
981 struct daio_mgr_ctrl_blk *ctl = blk;
982
983 set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
984 ctl->dirty.bf.atxctl |= (0x1 << idx);
985 return 0;
986 }
987
daio_mgr_dao_init(struct hw * hw,void * blk,unsigned int idx,unsigned int conf)988 static int daio_mgr_dao_init(struct hw *hw, void *blk, unsigned int idx, unsigned int conf)
989 {
990 struct daio_mgr_ctrl_blk *ctl = blk;
991
992 /* Port 3 is dedicated to RCA on SE-300PCIE */
993 if ((idx < 4) && ((hw->model != CTOK0010) || (idx < 3))) {
994 /* S/PDIF output */
995 switch ((conf & 0xf)) {
996 case 1:
997 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
998 break;
999 case 2:
1000 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
1001 break;
1002 case 4:
1003 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1004 break;
1005 case 8:
1006 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1007 break;
1008 default:
1009 break;
1010 }
1011 /* CDIF */
1012 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1013 /* Non-audio */
1014 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1015 /* Non-audio */
1016 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1017 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1018 ((conf >> 3) & 0x1) ? 0 : 0);
1019 ctl->dirty.bf.atxctl |= (0x1 << idx);
1020 } else {
1021 /* I2S output */
1022 /*idx %= 4; */
1023 }
1024 return 0;
1025 }
1026
daio_mgr_set_imaparc(void * blk,unsigned int slot)1027 static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1028 {
1029 struct daio_mgr_ctrl_blk *ctl = blk;
1030
1031 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1032 ctl->dirty.bf.daoimap = 1;
1033 return 0;
1034 }
1035
daio_mgr_set_imapnxt(void * blk,unsigned int next)1036 static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1037 {
1038 struct daio_mgr_ctrl_blk *ctl = blk;
1039
1040 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1041 ctl->dirty.bf.daoimap = 1;
1042 return 0;
1043 }
1044
daio_mgr_set_imapaddr(void * blk,unsigned int addr)1045 static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1046 {
1047 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1048 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1049 return 0;
1050 }
1051
daio_mgr_commit_write(struct hw * hw,void * blk)1052 static int daio_mgr_commit_write(struct hw *hw, void *blk)
1053 {
1054 struct daio_mgr_ctrl_blk *ctl = blk;
1055 unsigned int data;
1056 int i;
1057
1058 for (i = 0; i < 8; i++) {
1059 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1060 data = ctl->txctl[i];
1061 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1062 ctl->dirty.bf.atxctl &= ~(0x1 << i);
1063 mdelay(1);
1064 }
1065 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1066 data = ctl->rxctl[i];
1067 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1068 ctl->dirty.bf.arxctl &= ~(0x1 << i);
1069 mdelay(1);
1070 }
1071 }
1072 if (ctl->dirty.bf.daoimap) {
1073 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1074 ctl->daoimap.aim);
1075 ctl->dirty.bf.daoimap = 0;
1076 }
1077
1078 return 0;
1079 }
1080
daio_mgr_get_ctrl_blk(struct hw * hw,void ** rblk)1081 static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1082 {
1083 struct daio_mgr_ctrl_blk *blk;
1084 int i;
1085
1086 *rblk = NULL;
1087 blk = kzalloc_obj(*blk);
1088 if (!blk)
1089 return -ENOMEM;
1090
1091 for (i = 0; i < 8; i++) {
1092 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1093 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1094 }
1095
1096 *rblk = blk;
1097
1098 return 0;
1099 }
1100
daio_mgr_put_ctrl_blk(void * blk)1101 static int daio_mgr_put_ctrl_blk(void *blk)
1102 {
1103 kfree(blk);
1104
1105 return 0;
1106 }
1107
1108 /* Timer interrupt */
set_timer_irq(struct hw * hw,int enable)1109 static int set_timer_irq(struct hw *hw, int enable)
1110 {
1111 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1112 return 0;
1113 }
1114
set_timer_tick(struct hw * hw,unsigned int ticks)1115 static int set_timer_tick(struct hw *hw, unsigned int ticks)
1116 {
1117 if (ticks)
1118 ticks |= TIMR_IE | TIMR_IP;
1119 hw_write_20kx(hw, TIMR, ticks);
1120 return 0;
1121 }
1122
get_wc(struct hw * hw)1123 static unsigned int get_wc(struct hw *hw)
1124 {
1125 return hw_read_20kx(hw, WC);
1126 }
1127
1128 /* Card hardware initialization block */
1129 struct dac_conf {
1130 unsigned int msr; /* master sample rate in rsrs */
1131 };
1132
1133 struct adc_conf {
1134 unsigned int msr; /* master sample rate in rsrs */
1135 unsigned char input; /* the input source of ADC */
1136 unsigned char mic20db; /* boost mic by 20db if input is microphone */
1137 };
1138
1139 struct daio_conf {
1140 unsigned int msr; /* master sample rate in rsrs */
1141 };
1142
1143 struct trn_conf {
1144 unsigned long vm_pgt_phys;
1145 };
1146
hw_daio_init(struct hw * hw,const struct daio_conf * info)1147 static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1148 {
1149 u32 data;
1150 int i;
1151
1152 /* Program I2S with proper sample rate and enable the correct I2S
1153 * channel. ED(0/8/16/24): Enable all I2S/I2X master clock output */
1154 if (1 == info->msr) {
1155 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1156 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1157 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1158 } else if (2 == info->msr) {
1159 if (hw->model != CTSB1270) {
1160 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1161 } else {
1162 /* PCM4220 on Titanium HD is different. */
1163 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111);
1164 }
1165 /* Specify all playing 96khz
1166 * EA [0] - Enabled
1167 * RTA [4:5] - 96kHz
1168 * EB [8] - Enabled
1169 * RTB [12:13] - 96kHz
1170 * EC [16] - Enabled
1171 * RTC [20:21] - 96kHz
1172 * ED [24] - Enabled
1173 * RTD [28:29] - 96kHz */
1174 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1175 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1176 } else if ((4 == info->msr) && (hw->model == CTSB1270)) {
1177 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111);
1178 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121);
1179 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1180 } else if ((4 == info->msr) && (hw->model == CTOK0010)) {
1181 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21212121);
1182 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121);
1183 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1184 } else {
1185 dev_alert(hw->card->dev,
1186 "ERROR!!! Invalid sampling rate!!!\n");
1187 return -EINVAL;
1188 }
1189
1190 for (i = 0; i < 8; i++) {
1191 /* Port 3 is configured as I2S on SE-300PCIE */
1192 if ((i < 4) && ((hw->model != CTOK0010) || (i < 3))) {
1193 /* This comment looks wrong since loop is over 4 */
1194 /* channels and emu20k2 supports 4 spdif IOs. */
1195 /* 1st 3 channels are SPDIFs (SB0960) */
1196 if (i == 3)
1197 data = 0x1001001;
1198 else
1199 data = 0x1000001;
1200
1201 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1202 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1203
1204 /* Initialize the SPDIF Out Channel status registers.
1205 * The value specified here is based on the typical
1206 * values provided in the specification, namely: Clock
1207 * Accuracy of 1000ppm, Sample Rate of 48KHz,
1208 * unspecified source number, Generation status = 1,
1209 * Category code = 0x12 (Digital Signal Mixer),
1210 * Mode = 0, Emph = 0, Copy Permitted, AN = 0
1211 * (indicating that we're transmitting digital audio,
1212 * and the Professional Use bit is 0. */
1213
1214 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1215 0x02109204); /* Default to 48kHz */
1216
1217 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1218 } else {
1219 /* Again, loop is over 4 channels not 5. */
1220 /* Next 5 channels are I2S (SB0960) */
1221 data = 0x11;
1222 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
1223 if (2 == info->msr) {
1224 /* Four channels per sample period */
1225 data |= 0x1000;
1226 } else if (4 == info->msr) {
1227 /* FIXME: check this against the chip spec */
1228 data |= 0x2000;
1229 }
1230 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
1231 }
1232 }
1233
1234 return 0;
1235 }
1236
1237 /* TRANSPORT operations */
hw_trn_init(struct hw * hw,const struct trn_conf * info)1238 static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1239 {
1240 u32 vmctl, data;
1241 u32 ptp_phys_low, ptp_phys_high;
1242 int i;
1243
1244 /* Set up device page table */
1245 if ((~0UL) == info->vm_pgt_phys) {
1246 dev_alert(hw->card->dev,
1247 "Wrong device page table page address!!!\n");
1248 return -1;
1249 }
1250
1251 vmctl = 0x80000C0F; /* 32-bit, 4k-size page */
1252 ptp_phys_low = (u32)info->vm_pgt_phys;
1253 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1254 if (sizeof(void *) == 8) /* 64bit address */
1255 vmctl |= (3 << 8);
1256 /* Write page table physical address to all PTPAL registers */
1257 for (i = 0; i < 64; i++) {
1258 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1259 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1260 }
1261 /* Enable virtual memory transfer */
1262 hw_write_20kx(hw, VMEM_CTL, vmctl);
1263 /* Enable transport bus master and queueing of request */
1264 hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1265 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1266 /* Enable transport ring */
1267 data = hw_read_20kx(hw, TRANSPORT_ENB);
1268 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1269
1270 return 0;
1271 }
1272
1273 /* Card initialization */
1274 #define GCTL_AIE 0x00000001
1275 #define GCTL_UAA 0x00000002
1276 #define GCTL_DPC 0x00000004
1277 #define GCTL_DBP 0x00000008
1278 #define GCTL_ABP 0x00000010
1279 #define GCTL_TBP 0x00000020
1280 #define GCTL_SBP 0x00000040
1281 #define GCTL_FBP 0x00000080
1282 #define GCTL_ME 0x00000100
1283 #define GCTL_AID 0x00001000
1284
1285 #define PLLCTL_SRC 0x00000007
1286 #define PLLCTL_SPE 0x00000008
1287 #define PLLCTL_RD 0x000000F0
1288 #define PLLCTL_FD 0x0001FF00
1289 #define PLLCTL_OD 0x00060000
1290 #define PLLCTL_B 0x00080000
1291 #define PLLCTL_AS 0x00100000
1292 #define PLLCTL_LF 0x03E00000
1293 #define PLLCTL_SPS 0x1C000000
1294 #define PLLCTL_AD 0x60000000
1295
1296 #define PLLSTAT_CCS 0x00000007
1297 #define PLLSTAT_SPL 0x00000008
1298 #define PLLSTAT_CRD 0x000000F0
1299 #define PLLSTAT_CFD 0x0001FF00
1300 #define PLLSTAT_SL 0x00020000
1301 #define PLLSTAT_FAS 0x00040000
1302 #define PLLSTAT_B 0x00080000
1303 #define PLLSTAT_PD 0x00100000
1304 #define PLLSTAT_OCA 0x00200000
1305 #define PLLSTAT_NCA 0x00400000
1306
hw_pll_init(struct hw * hw,unsigned int rsr)1307 static int hw_pll_init(struct hw *hw, unsigned int rsr)
1308 {
1309 unsigned int pllenb;
1310 unsigned int pllctl;
1311 unsigned int pllstat;
1312 int i;
1313
1314 pllenb = 0xB;
1315 hw_write_20kx(hw, PLL_ENB, pllenb);
1316 pllctl = 0x20C00000;
1317 set_field(&pllctl, PLLCTL_B, 0);
1318 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
1319 set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
1320 hw_write_20kx(hw, PLL_CTL, pllctl);
1321 msleep(40);
1322
1323 pllctl = hw_read_20kx(hw, PLL_CTL);
1324 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
1325 hw_write_20kx(hw, PLL_CTL, pllctl);
1326 msleep(40);
1327
1328 for (i = 0; i < 1000; i++) {
1329 pllstat = hw_read_20kx(hw, PLL_STAT);
1330 if (get_field(pllstat, PLLSTAT_PD))
1331 continue;
1332
1333 if (get_field(pllstat, PLLSTAT_B) !=
1334 get_field(pllctl, PLLCTL_B))
1335 continue;
1336
1337 if (get_field(pllstat, PLLSTAT_CCS) !=
1338 get_field(pllctl, PLLCTL_SRC))
1339 continue;
1340
1341 if (get_field(pllstat, PLLSTAT_CRD) !=
1342 get_field(pllctl, PLLCTL_RD))
1343 continue;
1344
1345 if (get_field(pllstat, PLLSTAT_CFD) !=
1346 get_field(pllctl, PLLCTL_FD))
1347 continue;
1348
1349 break;
1350 }
1351 if (i >= 1000) {
1352 dev_alert(hw->card->dev,
1353 "PLL initialization failed!!!\n");
1354 return -EBUSY;
1355 }
1356
1357 return 0;
1358 }
1359
hw_auto_init(struct hw * hw)1360 static int hw_auto_init(struct hw *hw)
1361 {
1362 unsigned int gctl;
1363 int i;
1364
1365 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1366 set_field(&gctl, GCTL_AIE, 0);
1367 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1368 set_field(&gctl, GCTL_AIE, 1);
1369 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1370 mdelay(10);
1371 for (i = 0; i < 400000; i++) {
1372 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1373 if (get_field(gctl, GCTL_AID))
1374 break;
1375 }
1376 if (!get_field(gctl, GCTL_AID)) {
1377 dev_alert(hw->card->dev, "Card Auto-init failed!!!\n");
1378 return -EBUSY;
1379 }
1380
1381 return 0;
1382 }
1383
1384 /* DAC operations */
1385
1386 #define CS4382_MC1 0x1
1387 #define CS4382_MC2 0x2
1388 #define CS4382_MC3 0x3
1389 #define CS4382_FC 0x4
1390 #define CS4382_IC 0x5
1391 #define CS4382_XC1 0x6
1392 #define CS4382_VCA1 0x7
1393 #define CS4382_VCB1 0x8
1394 #define CS4382_XC2 0x9
1395 #define CS4382_VCA2 0xA
1396 #define CS4382_VCB2 0xB
1397 #define CS4382_XC3 0xC
1398 #define CS4382_VCA3 0xD
1399 #define CS4382_VCB3 0xE
1400 #define CS4382_XC4 0xF
1401 #define CS4382_VCA4 0x10
1402 #define CS4382_VCB4 0x11
1403 #define CS4382_CREV 0x12
1404
1405 /* I2C status */
1406 #define STATE_LOCKED 0x00
1407 #define STATE_UNLOCKED 0xAA
1408 #define DATA_READY 0x800000 /* Used with I2C_IF_STATUS */
1409 #define DATA_ABORT 0x10000 /* Used with I2C_IF_STATUS */
1410
1411 #define I2C_STATUS_DCM 0x00000001
1412 #define I2C_STATUS_BC 0x00000006
1413 #define I2C_STATUS_APD 0x00000008
1414 #define I2C_STATUS_AB 0x00010000
1415 #define I2C_STATUS_DR 0x00800000
1416
1417 #define I2C_ADDRESS_PTAD 0x0000FFFF
1418 #define I2C_ADDRESS_SLAD 0x007F0000
1419
1420 struct regs_cs4382 {
1421 u32 mode_control_1;
1422 u32 mode_control_2;
1423 u32 mode_control_3;
1424
1425 u32 filter_control;
1426 u32 invert_control;
1427
1428 u32 mix_control_P1;
1429 u32 vol_control_A1;
1430 u32 vol_control_B1;
1431
1432 u32 mix_control_P2;
1433 u32 vol_control_A2;
1434 u32 vol_control_B2;
1435
1436 u32 mix_control_P3;
1437 u32 vol_control_A3;
1438 u32 vol_control_B3;
1439
1440 u32 mix_control_P4;
1441 u32 vol_control_A4;
1442 u32 vol_control_B4;
1443 };
1444
hw20k2_i2c_unlock_full_access(struct hw * hw)1445 static int hw20k2_i2c_unlock_full_access(struct hw *hw)
1446 {
1447 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1448
1449 /* Send keys for forced BIOS mode */
1450 hw_write_20kx(hw, I2C_IF_WLOCK,
1451 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1452 hw_write_20kx(hw, I2C_IF_WLOCK,
1453 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1454 /* Check whether the chip is unlocked */
1455 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1456 return 0;
1457
1458 return -1;
1459 }
1460
hw20k2_i2c_lock_chip(struct hw * hw)1461 static int hw20k2_i2c_lock_chip(struct hw *hw)
1462 {
1463 /* Write twice */
1464 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1465 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1466 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1467 return 0;
1468
1469 return -1;
1470 }
1471
hw20k2_i2c_init(struct hw * hw,u8 dev_id,u8 addr_size,u8 data_size)1472 static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
1473 {
1474 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1475 int err;
1476 unsigned int i2c_status;
1477 unsigned int i2c_addr;
1478
1479 err = hw20k2_i2c_unlock_full_access(hw);
1480 if (err < 0)
1481 return err;
1482
1483 hw20k2->addr_size = addr_size;
1484 hw20k2->data_size = data_size;
1485 hw20k2->dev_id = dev_id;
1486
1487 i2c_addr = 0;
1488 set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
1489
1490 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1491
1492 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1493
1494 set_field(&i2c_status, I2C_STATUS_DCM, 1); /* Direct control mode */
1495
1496 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1497
1498 return 0;
1499 }
1500
hw20k2_i2c_uninit(struct hw * hw)1501 static int hw20k2_i2c_uninit(struct hw *hw)
1502 {
1503 unsigned int i2c_status;
1504 unsigned int i2c_addr;
1505
1506 i2c_addr = 0;
1507 set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57); /* I2C id */
1508
1509 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1510
1511 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1512
1513 set_field(&i2c_status, I2C_STATUS_DCM, 0); /* I2C mode */
1514
1515 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1516
1517 return hw20k2_i2c_lock_chip(hw);
1518 }
1519
hw20k2_i2c_wait_data_ready(struct hw * hw)1520 static int hw20k2_i2c_wait_data_ready(struct hw *hw)
1521 {
1522 int i = 0x400000;
1523 unsigned int ret;
1524
1525 do {
1526 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1527 } while ((!(ret & DATA_READY)) && --i);
1528
1529 return i;
1530 }
1531
hw20k2_i2c_read(struct hw * hw,u16 addr,u32 * datap)1532 static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
1533 {
1534 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1535 unsigned int i2c_status;
1536
1537 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1538 set_field(&i2c_status, I2C_STATUS_BC,
1539 (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
1540 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1541 if (!hw20k2_i2c_wait_data_ready(hw))
1542 return -1;
1543
1544 hw_write_20kx(hw, I2C_IF_WDATA, addr);
1545 if (!hw20k2_i2c_wait_data_ready(hw))
1546 return -1;
1547
1548 /* Force a read operation */
1549 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1550 if (!hw20k2_i2c_wait_data_ready(hw))
1551 return -1;
1552
1553 *datap = hw_read_20kx(hw, I2C_IF_RDATA);
1554
1555 return 0;
1556 }
1557
hw20k2_i2c_write(struct hw * hw,u16 addr,u32 data)1558 static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
1559 {
1560 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1561 unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
1562 unsigned int i2c_status;
1563
1564 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1565
1566 set_field(&i2c_status, I2C_STATUS_BC,
1567 (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
1568 0 : (hw20k2->addr_size + hw20k2->data_size));
1569
1570 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1571 hw20k2_i2c_wait_data_ready(hw);
1572 /* Dummy write to trigger the write operation */
1573 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1574 hw20k2_i2c_wait_data_ready(hw);
1575
1576 /* This is the real data */
1577 hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
1578 hw20k2_i2c_wait_data_ready(hw);
1579
1580 return 0;
1581 }
1582
hw_dac_stop(struct hw * hw)1583 static void hw_dac_stop(struct hw *hw)
1584 {
1585 u32 data;
1586 data = hw_read_20kx(hw, GPIO_DATA);
1587 data &= 0xFFFFFFFD;
1588 hw_write_20kx(hw, GPIO_DATA, data);
1589 usleep_range(10000, 11000);
1590 }
1591
hw_dac_start(struct hw * hw)1592 static void hw_dac_start(struct hw *hw)
1593 {
1594 u32 data;
1595 data = hw_read_20kx(hw, GPIO_DATA);
1596 data |= 0x2;
1597 hw_write_20kx(hw, GPIO_DATA, data);
1598 msleep(50);
1599 }
1600
hw_dac_reset(struct hw * hw)1601 static void hw_dac_reset(struct hw *hw)
1602 {
1603 hw_dac_stop(hw);
1604 hw_dac_start(hw);
1605 }
1606
hw_dac_init(struct hw * hw,const struct dac_conf * info)1607 static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1608 {
1609 int err;
1610 u32 data;
1611 int i;
1612 struct regs_cs4382 cs_read = {0};
1613 struct regs_cs4382 cs_def = {
1614 .mode_control_1 = 0x00000001, /* Mode Control 1 */
1615 .mode_control_2 = 0x00000000, /* Mode Control 2 */
1616 .mode_control_3 = 0x00000084, /* Mode Control 3 */
1617 .filter_control = 0x00000000, /* Filter Control */
1618 .invert_control = 0x00000000, /* Invert Control */
1619 .mix_control_P1 = 0x00000024, /* Mixing Control Pair 1 */
1620 .vol_control_A1 = 0x00000000, /* Vol Control A1 */
1621 .vol_control_B1 = 0x00000000, /* Vol Control B1 */
1622 .mix_control_P2 = 0x00000024, /* Mixing Control Pair 2 */
1623 .vol_control_A2 = 0x00000000, /* Vol Control A2 */
1624 .vol_control_B2 = 0x00000000, /* Vol Control B2 */
1625 .mix_control_P3 = 0x00000024, /* Mixing Control Pair 3 */
1626 .vol_control_A3 = 0x00000000, /* Vol Control A3 */
1627 .vol_control_B3 = 0x00000000, /* Vol Control B3 */
1628 .mix_control_P4 = 0x00000024, /* Mixing Control Pair 4 */
1629 .vol_control_A4 = 0x00000000, /* Vol Control A4 */
1630 .vol_control_B4 = 0x00000000 /* Vol Control B4 */
1631 };
1632
1633 if (hw->model == CTSB1270) {
1634 hw_dac_stop(hw);
1635 data = hw_read_20kx(hw, GPIO_DATA);
1636 data &= ~0x0600;
1637 if (1 == info->msr)
1638 data |= 0x0000; /* Single Speed Mode 0-50kHz */
1639 else if (2 == info->msr)
1640 data |= 0x0200; /* Double Speed Mode 50-100kHz */
1641 else
1642 data |= 0x0600; /* Quad Speed Mode 100-200kHz */
1643 hw_write_20kx(hw, GPIO_DATA, data);
1644 hw_dac_start(hw);
1645 return 0;
1646 } else if (hw->model == CTOK0010) {
1647 hw_dac_stop(hw);
1648 data = hw_read_20kx(hw, GPIO_DATA);
1649 data |= 0x1000;
1650 hw_write_20kx(hw, GPIO_DATA, data);
1651 hw_dac_start(hw);
1652 return 0;
1653 }
1654
1655 /* Set DAC reset bit as output */
1656 data = hw_read_20kx(hw, GPIO_CTRL);
1657 data |= 0x02;
1658 hw_write_20kx(hw, GPIO_CTRL, data);
1659
1660 err = hw20k2_i2c_init(hw, 0x18, 1, 1);
1661 if (err < 0)
1662 goto End;
1663
1664 for (i = 0; i < 2; i++) {
1665 /* Reset DAC twice just in-case the chip
1666 * didn't initialized properly */
1667 hw_dac_reset(hw);
1668 hw_dac_reset(hw);
1669
1670 if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
1671 continue;
1672
1673 if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
1674 continue;
1675
1676 if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
1677 continue;
1678
1679 if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
1680 continue;
1681
1682 if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
1683 continue;
1684
1685 if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
1686 continue;
1687
1688 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
1689 continue;
1690
1691 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
1692 continue;
1693
1694 if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
1695 continue;
1696
1697 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
1698 continue;
1699
1700 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
1701 continue;
1702
1703 if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
1704 continue;
1705
1706 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
1707 continue;
1708
1709 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
1710 continue;
1711
1712 if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
1713 continue;
1714
1715 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
1716 continue;
1717
1718 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
1719 continue;
1720
1721 if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
1722 continue;
1723 else
1724 break;
1725 }
1726
1727 if (i >= 2)
1728 goto End;
1729
1730 /* Note: Every I2C write must have some delay.
1731 * This is not a requirement but the delay works here... */
1732 hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
1733 hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
1734 if (1 == info->msr) {
1735 hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
1736 hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
1737 hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
1738 hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
1739 } else if (2 == info->msr) {
1740 hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
1741 hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
1742 hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
1743 hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
1744 } else {
1745 hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
1746 hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
1747 hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
1748 hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
1749 }
1750
1751 return 0;
1752 End:
1753
1754 hw20k2_i2c_uninit(hw);
1755 return -1;
1756 }
1757
1758 /* ADC operations */
1759 #define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1760 #define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1761
1762 #define WM8775_IC 0x0B
1763 #define WM8775_MMC 0x0C
1764 #define WM8775_AADCL 0x0E
1765 #define WM8775_AADCR 0x0F
1766 #define WM8775_ADCMC 0x15
1767 #define WM8775_RESET 0x17
1768
hw_is_adc_input_selected(struct hw * hw,enum ADCSRC type)1769 static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1770 {
1771 u32 data;
1772 if ((hw->model == CTSB1270) || (hw->model == CTOK0010)) {
1773 /* Titanium HD has two ADC chips, one for line in and one */
1774 /* for MIC. Also, SE-300PCIE has a single ADC chip that */
1775 /* simultaneously supports 4-channel input. We don't need */
1776 /* to switch the ADC input. */
1777 return 1;
1778 }
1779 data = hw_read_20kx(hw, GPIO_DATA);
1780 switch (type) {
1781 case ADC_MICIN:
1782 data = (data & (0x1 << 14)) ? 1 : 0;
1783 break;
1784 case ADC_LINEIN:
1785 data = (data & (0x1 << 14)) ? 0 : 1;
1786 break;
1787 default:
1788 data = 0;
1789 }
1790 return data;
1791 }
1792
1793 #define MIC_BOOST_0DB 0xCF
1794 #define MIC_BOOST_STEPS_PER_DB 2
1795
hw_wm8775_input_select(struct hw * hw,u8 input,s8 gain_in_db)1796 static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db)
1797 {
1798 u32 adcmc, gain;
1799
1800 if (input > 3)
1801 input = 3;
1802
1803 adcmc = ((u32)1 << input) | 0x100; /* Link L+R gain... */
1804
1805 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc),
1806 MAKE_WM8775_DATA(adcmc));
1807
1808 if (gain_in_db < -103)
1809 gain_in_db = -103;
1810 if (gain_in_db > 24)
1811 gain_in_db = 24;
1812
1813 gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB;
1814
1815 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain),
1816 MAKE_WM8775_DATA(gain));
1817 /* ...so there should be no need for the following. */
1818 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain),
1819 MAKE_WM8775_DATA(gain));
1820 }
1821
hw_adc_input_select(struct hw * hw,enum ADCSRC type)1822 static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1823 {
1824 u32 data;
1825 data = hw_read_20kx(hw, GPIO_DATA);
1826 switch (type) {
1827 case ADC_MICIN:
1828 data |= (0x1 << 14);
1829 hw_write_20kx(hw, GPIO_DATA, data);
1830 hw_wm8775_input_select(hw, 0, 20); /* Mic, 20dB */
1831 break;
1832 case ADC_LINEIN:
1833 data &= ~(0x1 << 14);
1834 hw_write_20kx(hw, GPIO_DATA, data);
1835 hw_wm8775_input_select(hw, 1, 0); /* Line-in, 0dB */
1836 break;
1837 default:
1838 break;
1839 }
1840
1841 return 0;
1842 }
1843
hw_adc_stop(struct hw * hw)1844 static void hw_adc_stop(struct hw *hw)
1845 {
1846 u32 data;
1847 /* Reset the ADC (reset is active low). */
1848 data = hw_read_20kx(hw, GPIO_DATA);
1849 data &= ~(0x1 << 15);
1850 hw_write_20kx(hw, GPIO_DATA, data);
1851 usleep_range(10000, 11000);
1852 }
1853
hw_adc_start(struct hw * hw)1854 static void hw_adc_start(struct hw *hw)
1855 {
1856 u32 data;
1857 /* Return the ADC to normal operation. */
1858 data = hw_read_20kx(hw, GPIO_DATA);
1859 data |= (0x1 << 15);
1860 hw_write_20kx(hw, GPIO_DATA, data);
1861 msleep(50);
1862 }
1863
hw_adc_reset(struct hw * hw)1864 static void hw_adc_reset(struct hw *hw)
1865 {
1866 hw_adc_stop(hw);
1867 hw_adc_start(hw);
1868 }
1869
hw_adc_init(struct hw * hw,const struct adc_conf * info)1870 static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1871 {
1872 int err;
1873 u32 data, ctl;
1874
1875 /* Set ADC reset bit as output */
1876 data = hw_read_20kx(hw, GPIO_CTRL);
1877 data |= (0x1 << 15);
1878 hw_write_20kx(hw, GPIO_CTRL, data);
1879
1880 if (hw->model == CTOK0010) {
1881 /* Manual ADC setup for SE-300PCIE is not needed. */
1882 hw_adc_reset(hw);
1883 return 0;
1884 }
1885
1886 /* Initialize I2C */
1887 err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
1888 if (err < 0) {
1889 dev_alert(hw->card->dev, "Failure to acquire I2C!!!\n");
1890 goto error;
1891 }
1892
1893 hw_adc_stop(hw);
1894
1895 if (hw->model == CTSB1270) {
1896 /* Set up the PCM4220 ADC on Titanium HD */
1897 data &= ~0x0C;
1898 if (1 == info->msr)
1899 data |= 0x00; /* Single Speed Mode 32-50kHz */
1900 else if (2 == info->msr)
1901 data |= 0x08; /* Double Speed Mode 50-108kHz */
1902 else
1903 data |= 0x04; /* Quad Speed Mode 108kHz-216kHz */
1904 hw_write_20kx(hw, GPIO_DATA, data);
1905 }
1906
1907 hw_adc_start(hw);
1908
1909 /* I2C write to register offset 0x0B to set ADC LRCLK polarity */
1910 /* invert bit, interface format to I2S, word length to 24-bit, */
1911 /* enable ADC high pass filter. Fixes bug 5323? */
1912 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26),
1913 MAKE_WM8775_DATA(0x26));
1914
1915 /* Set the master mode (256fs) */
1916 if (1 == info->msr) {
1917 /* slave mode, 128x oversampling 256fs */
1918 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1919 MAKE_WM8775_DATA(0x02));
1920 } else if ((2 == info->msr) || (4 == info->msr)) {
1921 /* slave mode, 64x oversampling, 256fs */
1922 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1923 MAKE_WM8775_DATA(0x0A));
1924 } else {
1925 dev_alert(hw->card->dev,
1926 "Invalid master sampling rate (msr %d)!!!\n",
1927 info->msr);
1928 err = -EINVAL;
1929 goto error;
1930 }
1931
1932 if (hw->model != CTSB1270) {
1933 /* Configure GPIO bit 14 change to line-in/mic-in */
1934 ctl = hw_read_20kx(hw, GPIO_CTRL);
1935 ctl |= 0x1 << 14;
1936 hw_write_20kx(hw, GPIO_CTRL, ctl);
1937 hw_adc_input_select(hw, ADC_LINEIN);
1938 } else {
1939 hw_wm8775_input_select(hw, 0, 0);
1940 }
1941
1942 return 0;
1943 error:
1944 hw20k2_i2c_uninit(hw);
1945 return err;
1946 }
1947
hw_capabilities(struct hw * hw)1948 static struct capabilities hw_capabilities(struct hw *hw)
1949 {
1950 struct capabilities cap;
1951
1952 cap.digit_io_switch = 0;
1953 cap.dedicated_mic = (hw->model == CTSB1270) || (hw->model == CTOK0010);
1954 cap.dedicated_rca = hw->model == CTOK0010;
1955 cap.output_switch = hw->model == CTSB1270;
1956 cap.mic_source_switch = hw->model == CTSB1270;
1957
1958 return cap;
1959 }
1960
hw_output_switch_get(struct hw * hw)1961 static int hw_output_switch_get(struct hw *hw)
1962 {
1963 u32 data = hw_read_20kx(hw, GPIO_EXT_DATA);
1964
1965 switch (data & 0x30) {
1966 case 0x00:
1967 return 0;
1968 case 0x10:
1969 return 1;
1970 case 0x20:
1971 return 2;
1972 default:
1973 return 3;
1974 }
1975 }
1976
hw_output_switch_put(struct hw * hw,int position)1977 static int hw_output_switch_put(struct hw *hw, int position)
1978 {
1979 u32 data;
1980
1981 if (position == hw_output_switch_get(hw))
1982 return 0;
1983
1984 /* Mute line and headphones (intended for anti-pop). */
1985 data = hw_read_20kx(hw, GPIO_DATA);
1986 data |= (0x03 << 11);
1987 hw_write_20kx(hw, GPIO_DATA, data);
1988
1989 data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30;
1990 switch (position) {
1991 case 0:
1992 break;
1993 case 1:
1994 data |= 0x10;
1995 break;
1996 default:
1997 data |= 0x20;
1998 }
1999 hw_write_20kx(hw, GPIO_EXT_DATA, data);
2000
2001 /* Unmute line and headphones. */
2002 data = hw_read_20kx(hw, GPIO_DATA);
2003 data &= ~(0x03 << 11);
2004 hw_write_20kx(hw, GPIO_DATA, data);
2005
2006 return 1;
2007 }
2008
hw_mic_source_switch_get(struct hw * hw)2009 static int hw_mic_source_switch_get(struct hw *hw)
2010 {
2011 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
2012
2013 return hw20k2->mic_source;
2014 }
2015
hw_mic_source_switch_put(struct hw * hw,int position)2016 static int hw_mic_source_switch_put(struct hw *hw, int position)
2017 {
2018 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
2019
2020 if (position == hw20k2->mic_source)
2021 return 0;
2022
2023 switch (position) {
2024 case 0:
2025 hw_wm8775_input_select(hw, 0, 0); /* Mic, 0dB */
2026 break;
2027 case 1:
2028 hw_wm8775_input_select(hw, 1, 0); /* FP Mic, 0dB */
2029 break;
2030 case 2:
2031 hw_wm8775_input_select(hw, 3, 0); /* Aux Ext, 0dB */
2032 break;
2033 default:
2034 return 0;
2035 }
2036
2037 hw20k2->mic_source = position;
2038
2039 return 1;
2040 }
2041
ct_20k2_interrupt(int irq,void * dev_id)2042 static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id)
2043 {
2044 struct hw *hw = dev_id;
2045 unsigned int status;
2046
2047 status = hw_read_20kx(hw, GIP);
2048 if (!status)
2049 return IRQ_NONE;
2050
2051 if (hw->irq_callback)
2052 hw->irq_callback(hw->irq_callback_data, status);
2053
2054 hw_write_20kx(hw, GIP, status);
2055 return IRQ_HANDLED;
2056 }
2057
hw_card_start(struct hw * hw)2058 static int hw_card_start(struct hw *hw)
2059 {
2060 int err = 0;
2061 struct pci_dev *pci = hw->pci;
2062 unsigned int gctl;
2063 const unsigned int dma_bits = BITS_PER_LONG;
2064
2065 err = pci_enable_device(pci);
2066 if (err < 0)
2067 return err;
2068
2069 /* Set DMA transfer mask */
2070 if (dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(dma_bits)))
2071 dma_set_mask_and_coherent(&pci->dev, DMA_BIT_MASK(32));
2072
2073 if (!hw->io_base) {
2074 err = pci_request_regions(pci, "XFi");
2075 if (err < 0)
2076 goto error1;
2077
2078 hw->io_base = pci_resource_start(hw->pci, 2);
2079 hw->mem_base = ioremap(hw->io_base,
2080 pci_resource_len(hw->pci, 2));
2081 if (!hw->mem_base) {
2082 err = -ENOENT;
2083 goto error2;
2084 }
2085 }
2086
2087 /* Switch to 20k2 mode from UAA mode. */
2088 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2089 set_field(&gctl, GCTL_UAA, 0);
2090 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2091
2092 if (hw->irq < 0) {
2093 err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED,
2094 KBUILD_MODNAME, hw);
2095 if (err < 0) {
2096 dev_err(hw->card->dev,
2097 "XFi: Cannot get irq %d\n", pci->irq);
2098 goto error2;
2099 }
2100 hw->irq = pci->irq;
2101 hw->card->sync_irq = hw->irq;
2102 }
2103
2104 pci_set_master(pci);
2105
2106 return 0;
2107
2108 /*error3:
2109 iounmap((void *)hw->mem_base);
2110 hw->mem_base = (unsigned long)NULL;*/
2111 error2:
2112 pci_release_regions(pci);
2113 hw->io_base = 0;
2114 error1:
2115 pci_disable_device(pci);
2116 return err;
2117 }
2118
hw_card_stop(struct hw * hw)2119 static int hw_card_stop(struct hw *hw)
2120 {
2121 unsigned int data;
2122
2123 /* disable transport bus master and queueing of request */
2124 hw_write_20kx(hw, TRANSPORT_CTL, 0x00);
2125
2126 /* disable pll */
2127 data = hw_read_20kx(hw, PLL_ENB);
2128 hw_write_20kx(hw, PLL_ENB, (data & (~0x07)));
2129
2130 /* TODO: Disable interrupt and so on... */
2131 return 0;
2132 }
2133
hw_card_shutdown(struct hw * hw)2134 static int hw_card_shutdown(struct hw *hw)
2135 {
2136 if (hw->irq >= 0)
2137 free_irq(hw->irq, hw);
2138
2139 hw->irq = -1;
2140 iounmap(hw->mem_base);
2141 hw->mem_base = NULL;
2142
2143 if (hw->io_base)
2144 pci_release_regions(hw->pci);
2145
2146 hw->io_base = 0;
2147
2148 pci_disable_device(hw->pci);
2149
2150 return 0;
2151 }
2152
hw_card_init(struct hw * hw,struct card_conf * info)2153 static int hw_card_init(struct hw *hw, struct card_conf *info)
2154 {
2155 int err;
2156 unsigned int gctl;
2157 u32 data = 0;
2158 struct dac_conf dac_info = {0};
2159 struct adc_conf adc_info = {0};
2160 struct daio_conf daio_info = {0};
2161 struct trn_conf trn_info = {0};
2162
2163 /* Get PCI io port/memory base address and
2164 * do 20kx core switch if needed. */
2165 err = hw_card_start(hw);
2166 if (err)
2167 return err;
2168
2169 /* PLL init */
2170 err = hw_pll_init(hw, info->rsr);
2171 if (err < 0)
2172 return err;
2173
2174 /* kick off auto-init */
2175 err = hw_auto_init(hw);
2176 if (err < 0)
2177 return err;
2178
2179 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2180 set_field(&gctl, GCTL_DBP, 1);
2181 set_field(&gctl, GCTL_TBP, 1);
2182 set_field(&gctl, GCTL_FBP, 1);
2183 set_field(&gctl, GCTL_DPC, 0);
2184 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2185
2186 /* Reset all global pending interrupts */
2187 hw_write_20kx(hw, GIE, 0);
2188 /* Reset all SRC pending interrupts */
2189 hw_write_20kx(hw, SRC_IP, 0);
2190
2191 if (hw->model == CTSB1270) {
2192 hw_write_20kx(hw, GPIO_CTRL, 0x9E5F);
2193 } else if (hw->model == CTOK0010) {
2194 hw_write_20kx(hw, GPIO_CTRL, 0x9902);
2195 } else {
2196 /* TODO: detect the card ID and configure GPIO accordingly. */
2197 /* Configures GPIO (0xD802 0x98028) */
2198 /*hw_write_20kx(hw, GPIO_CTRL, 0x7F07);*/
2199 /* Configures GPIO (SB0880) */
2200 /*hw_write_20kx(hw, GPIO_CTRL, 0xFF07);*/
2201 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
2202 }
2203 /* Enable audio ring */
2204 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
2205
2206 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2207 err = hw_trn_init(hw, &trn_info);
2208 if (err < 0)
2209 return err;
2210
2211 daio_info.msr = info->msr;
2212 err = hw_daio_init(hw, &daio_info);
2213 if (err < 0)
2214 return err;
2215
2216 dac_info.msr = info->msr;
2217 err = hw_dac_init(hw, &dac_info);
2218 if (err < 0)
2219 return err;
2220
2221 adc_info.msr = info->msr;
2222 adc_info.input = ADC_LINEIN;
2223 adc_info.mic20db = 0;
2224 err = hw_adc_init(hw, &adc_info);
2225 if (err < 0)
2226 return err;
2227
2228 data = hw_read_20kx(hw, SRC_MCTL);
2229 data |= 0x1; /* Enables input from the audio ring */
2230 hw_write_20kx(hw, SRC_MCTL, data);
2231
2232 return 0;
2233 }
2234
2235 #ifdef CONFIG_PM_SLEEP
hw_suspend(struct hw * hw)2236 static int hw_suspend(struct hw *hw)
2237 {
2238 hw_card_stop(hw);
2239 return 0;
2240 }
2241
hw_resume(struct hw * hw,struct card_conf * info)2242 static int hw_resume(struct hw *hw, struct card_conf *info)
2243 {
2244 /* Re-initialize card hardware. */
2245 return hw_card_init(hw, info);
2246 }
2247 #endif
2248
hw_read_20kx(struct hw * hw,u32 reg)2249 static u32 hw_read_20kx(struct hw *hw, u32 reg)
2250 {
2251 return readl(hw->mem_base + reg);
2252 }
2253
hw_write_20kx(struct hw * hw,u32 reg,u32 data)2254 static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2255 {
2256 writel(data, hw->mem_base + reg);
2257 }
2258
2259 static const struct hw ct20k2_preset = {
2260 .irq = -1,
2261
2262 .card_init = hw_card_init,
2263 .card_stop = hw_card_stop,
2264 .pll_init = hw_pll_init,
2265 .is_adc_source_selected = hw_is_adc_input_selected,
2266 .select_adc_source = hw_adc_input_select,
2267 .capabilities = hw_capabilities,
2268 .output_switch_get = hw_output_switch_get,
2269 .output_switch_put = hw_output_switch_put,
2270 .mic_source_switch_get = hw_mic_source_switch_get,
2271 .mic_source_switch_put = hw_mic_source_switch_put,
2272 #ifdef CONFIG_PM_SLEEP
2273 .suspend = hw_suspend,
2274 .resume = hw_resume,
2275 #endif
2276
2277 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2278 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2279 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2280 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2281 .src_set_state = src_set_state,
2282 .src_set_bm = src_set_bm,
2283 .src_set_rsr = src_set_rsr,
2284 .src_set_sf = src_set_sf,
2285 .src_set_wr = src_set_wr,
2286 .src_set_pm = src_set_pm,
2287 .src_set_rom = src_set_rom,
2288 .src_set_vo = src_set_vo,
2289 .src_set_st = src_set_st,
2290 .src_set_ie = src_set_ie,
2291 .src_set_ilsz = src_set_ilsz,
2292 .src_set_bp = src_set_bp,
2293 .src_set_cisz = src_set_cisz,
2294 .src_set_ca = src_set_ca,
2295 .src_set_sa = src_set_sa,
2296 .src_set_la = src_set_la,
2297 .src_set_pitch = src_set_pitch,
2298 .src_set_dirty = src_set_dirty,
2299 .src_set_clear_zbufs = src_set_clear_zbufs,
2300 .src_set_dirty_all = src_set_dirty_all,
2301 .src_commit_write = src_commit_write,
2302 .src_get_ca = src_get_ca,
2303 .src_get_dirty = src_get_dirty,
2304 .src_dirty_conj_mask = src_dirty_conj_mask,
2305 .src_mgr_enbs_src = src_mgr_enbs_src,
2306 .src_mgr_enb_src = src_mgr_enb_src,
2307 .src_mgr_dsb_src = src_mgr_dsb_src,
2308 .src_mgr_commit_write = src_mgr_commit_write,
2309
2310 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2311 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2312 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2313 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2314 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2315 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2316 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2317
2318 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2319 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2320 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2321 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2322 .amixer_set_mode = amixer_set_mode,
2323 .amixer_set_iv = amixer_set_iv,
2324 .amixer_set_x = amixer_set_x,
2325 .amixer_set_y = amixer_set_y,
2326 .amixer_set_sadr = amixer_set_sadr,
2327 .amixer_set_se = amixer_set_se,
2328 .amixer_set_dirty = amixer_set_dirty,
2329 .amixer_set_dirty_all = amixer_set_dirty_all,
2330 .amixer_commit_write = amixer_commit_write,
2331 .amixer_get_y = amixer_get_y,
2332 .amixer_get_dirty = amixer_get_dirty,
2333
2334 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2335 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2336 .dai_srt_set_srco = dai_srt_set_srco,
2337 .dai_srt_set_srcm = dai_srt_set_srcm,
2338 .dai_srt_set_rsr = dai_srt_set_rsr,
2339 .dai_srt_set_drat = dai_srt_set_drat,
2340 .dai_srt_set_ec = dai_srt_set_ec,
2341 .dai_srt_set_et = dai_srt_set_et,
2342 .dai_commit_write = dai_commit_write,
2343
2344 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2345 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2346 .dao_set_spos = dao_set_spos,
2347 .dao_commit_write = dao_commit_write,
2348 .dao_get_spos = dao_get_spos,
2349
2350 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2351 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2352 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2353 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2354 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2355 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2356 .daio_mgr_dao_init = daio_mgr_dao_init,
2357 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2358 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2359 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2360 .daio_mgr_commit_write = daio_mgr_commit_write,
2361
2362 .set_timer_irq = set_timer_irq,
2363 .set_timer_tick = set_timer_tick,
2364 .get_wc = get_wc,
2365 };
2366
create_20k2_hw_obj(struct hw ** rhw)2367 int create_20k2_hw_obj(struct hw **rhw)
2368 {
2369 struct hw20k2 *hw20k2;
2370
2371 *rhw = NULL;
2372 hw20k2 = kzalloc_obj(*hw20k2);
2373 if (!hw20k2)
2374 return -ENOMEM;
2375
2376 hw20k2->hw = ct20k2_preset;
2377 *rhw = &hw20k2->hw;
2378
2379 return 0;
2380 }
2381
destroy_20k2_hw_obj(struct hw * hw)2382 int destroy_20k2_hw_obj(struct hw *hw)
2383 {
2384 if (hw->io_base)
2385 hw_card_shutdown(hw);
2386
2387 kfree(hw);
2388 return 0;
2389 }
2390