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Searched refs:PHY_REG (Results 1 – 10 of 10) sorted by relevance

/linux/drivers/net/ethernet/intel/e1000e/
H A Dich8lan.h110 #define PHY_REG(page, reg) (((page) << PHY_PAGE_SHIFT) | \ macro
112 #define IGP3_KMRN_DIAG PHY_REG(770, 19) /* KMRN Diagnostic */
113 #define IGP3_VR_CTRL PHY_REG(776, 18) /* Voltage Regulator Control */
120 #define BM_PORT_GEN_CFG PHY_REG(BM_PORT_CTRL_PAGE, 17)
121 #define BM_RCTL PHY_REG(BM_WUC_PAGE, 0)
122 #define BM_WUC PHY_REG(BM_WUC_PAGE, 1)
123 #define BM_WUFC PHY_REG(BM_WUC_PAGE, 2)
124 #define BM_WUS PHY_REG(BM_WUC_PAGE, 3)
139 #define HV_LED_CONFIG PHY_REG(768, 30) /* LED Configuration */
140 #define HV_MUX_DATA_CTRL PHY_REG(776, 16)
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H A Dethtool.c1351 e1e_rphy(hw, PHY_REG(2, 21), &phy_reg); in e1000_integrated_phy_loopback()
1354 e1e_wphy(hw, PHY_REG(2, 21), phy_reg); in e1000_integrated_phy_loopback()
1359 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1360 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x000C); in e1000_integrated_phy_loopback()
1362 e1e_rphy(hw, PHY_REG(776, 16), &phy_reg); in e1000_integrated_phy_loopback()
1363 e1e_wphy(hw, PHY_REG(776, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1365 e1e_rphy(hw, PHY_REG(769, 16), &phy_reg); in e1000_integrated_phy_loopback()
1366 e1e_wphy(hw, PHY_REG(769, 16), phy_reg | 0x0040); in e1000_integrated_phy_loopback()
1368 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_integrated_phy_loopback()
1369 e1e_wphy(hw, PHY_REG(769, 20), phy_reg | 0x0400); in e1000_integrated_phy_loopback()
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H A Dich8lan.c1561 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1574 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
1586 PHY_REG(776, 20), in e1000_check_for_copper_link_ich8lan()
2349 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x0100); in e1000_k1_gig_workaround_hv()
2355 ret_val = e1e_wphy_locked(hw, PHY_REG(770, 19), 0x4100); in e1000_k1_gig_workaround_hv()
2534 ret_val = e1e_wphy(hw, PHY_REG(769, 25), 0x4431); in e1000_hv_phy_workarounds_ich8lan()
2648 e1e_rphy(hw, PHY_REG(769, 20), &phy_reg); in e1000_lv_jumbo_workaround_ich8lan()
2649 ret_val = e1e_wphy(hw, PHY_REG(769, 20), phy_reg | BIT(14)); in e1000_lv_jumbo_workaround_ich8lan()
2712 e1e_rphy(hw, PHY_REG(769, 23), &data); in e1000_lv_jumbo_workaround_ich8lan()
2715 ret_val = e1e_wphy(hw, PHY_REG(769, 23), data); in e1000_lv_jumbo_workaround_ich8lan()
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H A Dregs.h243 #define I82579_DFT_CTRL PHY_REG(769, 20)
H A Dnetdev.c3074 e1e_rphy(hw, PHY_REG(770, 26), &phy_data); in e1000_setup_rctl()
3077 e1e_wphy(hw, PHY_REG(770, 26), phy_data); in e1000_setup_rctl()
/linux/drivers/phy/freescale/
H A Dphy-fsl-samsung-hdmi.c17 #define PHY_REG(reg) (reg * 4) macro
285 { PHY_REG(0), 0x00 },
287 { PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
288 { PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
292 { PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },
293 { PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },
294 { PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },
296 { PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
297 { PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },
298 { PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 },
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/linux/drivers/phy/rockchip/
H A Dphy-rockchip-dphy-rx0.c109 #define PHY_REG(_offset, _width, _shift) \ macro
113 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0),
114 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10),
115 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11),
116 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0),
117 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4),
118 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8),
119 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12),
120 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0),
121 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4),
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/linux/drivers/net/dsa/
H A Dlan9303_mdio.c18 #define PHY_REG(x) (((x) >> 1) & 0x1f) macro
27 mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val); in lan9303_mdio_real_write()
45 return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg)); in lan9303_mdio_real_read()
/linux/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h2912 #define PHY_REG(page, reg) \ macro
2916 PHY_REG(769, 17) /* Port General Configuration */
2918 PHY_REG(769, 25) /* Rate Adapter Control Register */
2921 PHY_REG(770, 16) /* KMRN FIFO's control/status register */
2923 PHY_REG(770, 17) /* KMRN Power Management Control Register */
2925 PHY_REG(770, 18) /* KMRN Inband Control Register */
2927 PHY_REG(770, 19) /* KMRN Diagnostic register */
2930 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */
2933 PHY_REG(776, 18) /* Voltage regulator control register */
2938 PHY_REG(776, 19) /* IGP3 Capability Register */
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/linux/drivers/net/wireless/realtek/rtlwifi/rtl8192se/
H A Dreg.h230 #define PHY_REG 0x02F3 macro