1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * RISC-V processor specific defines
4 *
5 * Copyright (C) 2021 Western Digital Corporation or its affiliates.
6 */
7 #ifndef SELFTEST_KVM_PROCESSOR_H
8 #define SELFTEST_KVM_PROCESSOR_H
9
10 #include <linux/stringify.h>
11 #include <asm/csr.h>
12 #include "kvm_util.h"
13
__kvm_reg_id(uint64_t type,uint64_t subtype,uint64_t idx,uint64_t size)14 static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
15 uint64_t idx, uint64_t size)
16 {
17 return KVM_REG_RISCV | type | subtype | idx | size;
18 }
19
20 #if __riscv_xlen == 64
21 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U64
22 #else
23 #define KVM_REG_SIZE_ULONG KVM_REG_SIZE_U32
24 #endif
25
26 #define RISCV_CONFIG_REG(name) __kvm_reg_id(KVM_REG_RISCV_CONFIG, 0, \
27 KVM_REG_RISCV_CONFIG_REG(name), \
28 KVM_REG_SIZE_ULONG)
29
30 #define RISCV_CORE_REG(name) __kvm_reg_id(KVM_REG_RISCV_CORE, 0, \
31 KVM_REG_RISCV_CORE_REG(name), \
32 KVM_REG_SIZE_ULONG)
33
34 #define RISCV_GENERAL_CSR_REG(name) __kvm_reg_id(KVM_REG_RISCV_CSR, \
35 KVM_REG_RISCV_CSR_GENERAL, \
36 KVM_REG_RISCV_CSR_REG(name), \
37 KVM_REG_SIZE_ULONG)
38
39 #define RISCV_TIMER_REG(name) __kvm_reg_id(KVM_REG_RISCV_TIMER, 0, \
40 KVM_REG_RISCV_TIMER_REG(name), \
41 KVM_REG_SIZE_U64)
42
43 #define RISCV_ISA_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_ISA_EXT, \
44 KVM_REG_RISCV_ISA_SINGLE, \
45 idx, KVM_REG_SIZE_ULONG)
46
47 #define RISCV_SBI_EXT_REG(idx) __kvm_reg_id(KVM_REG_RISCV_SBI_EXT, \
48 KVM_REG_RISCV_SBI_SINGLE, \
49 idx, KVM_REG_SIZE_ULONG)
50
51 bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext);
52
__vcpu_has_isa_ext(struct kvm_vcpu * vcpu,uint64_t isa_ext)53 static inline bool __vcpu_has_isa_ext(struct kvm_vcpu *vcpu, uint64_t isa_ext)
54 {
55 return __vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(isa_ext));
56 }
57
__vcpu_has_sbi_ext(struct kvm_vcpu * vcpu,uint64_t sbi_ext)58 static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, uint64_t sbi_ext)
59 {
60 return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext));
61 }
62
63 struct ex_regs {
64 unsigned long ra;
65 unsigned long sp;
66 unsigned long gp;
67 unsigned long tp;
68 unsigned long t0;
69 unsigned long t1;
70 unsigned long t2;
71 unsigned long s0;
72 unsigned long s1;
73 unsigned long a0;
74 unsigned long a1;
75 unsigned long a2;
76 unsigned long a3;
77 unsigned long a4;
78 unsigned long a5;
79 unsigned long a6;
80 unsigned long a7;
81 unsigned long s2;
82 unsigned long s3;
83 unsigned long s4;
84 unsigned long s5;
85 unsigned long s6;
86 unsigned long s7;
87 unsigned long s8;
88 unsigned long s9;
89 unsigned long s10;
90 unsigned long s11;
91 unsigned long t3;
92 unsigned long t4;
93 unsigned long t5;
94 unsigned long t6;
95 unsigned long epc;
96 unsigned long status;
97 unsigned long cause;
98 };
99
100 #define NR_VECTORS 2
101 #define NR_EXCEPTIONS 32
102 #define EC_MASK (NR_EXCEPTIONS - 1)
103
104 typedef void(*exception_handler_fn)(struct ex_regs *);
105
106 void vm_init_vector_tables(struct kvm_vm *vm);
107 void vcpu_init_vector_tables(struct kvm_vcpu *vcpu);
108
109 void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler);
110
111 void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handler);
112
113 /* L3 index Bit[47:39] */
114 #define PGTBL_L3_INDEX_MASK 0x0000FF8000000000ULL
115 #define PGTBL_L3_INDEX_SHIFT 39
116 #define PGTBL_L3_BLOCK_SHIFT 39
117 #define PGTBL_L3_BLOCK_SIZE 0x0000008000000000ULL
118 #define PGTBL_L3_MAP_MASK (~(PGTBL_L3_BLOCK_SIZE - 1))
119 /* L2 index Bit[38:30] */
120 #define PGTBL_L2_INDEX_MASK 0x0000007FC0000000ULL
121 #define PGTBL_L2_INDEX_SHIFT 30
122 #define PGTBL_L2_BLOCK_SHIFT 30
123 #define PGTBL_L2_BLOCK_SIZE 0x0000000040000000ULL
124 #define PGTBL_L2_MAP_MASK (~(PGTBL_L2_BLOCK_SIZE - 1))
125 /* L1 index Bit[29:21] */
126 #define PGTBL_L1_INDEX_MASK 0x000000003FE00000ULL
127 #define PGTBL_L1_INDEX_SHIFT 21
128 #define PGTBL_L1_BLOCK_SHIFT 21
129 #define PGTBL_L1_BLOCK_SIZE 0x0000000000200000ULL
130 #define PGTBL_L1_MAP_MASK (~(PGTBL_L1_BLOCK_SIZE - 1))
131 /* L0 index Bit[20:12] */
132 #define PGTBL_L0_INDEX_MASK 0x00000000001FF000ULL
133 #define PGTBL_L0_INDEX_SHIFT 12
134 #define PGTBL_L0_BLOCK_SHIFT 12
135 #define PGTBL_L0_BLOCK_SIZE 0x0000000000001000ULL
136 #define PGTBL_L0_MAP_MASK (~(PGTBL_L0_BLOCK_SIZE - 1))
137
138 #define PGTBL_PTE_ADDR_MASK 0x003FFFFFFFFFFC00ULL
139 #define PGTBL_PTE_ADDR_SHIFT 10
140 #define PGTBL_PTE_RSW_MASK 0x0000000000000300ULL
141 #define PGTBL_PTE_RSW_SHIFT 8
142 #define PGTBL_PTE_DIRTY_MASK 0x0000000000000080ULL
143 #define PGTBL_PTE_DIRTY_SHIFT 7
144 #define PGTBL_PTE_ACCESSED_MASK 0x0000000000000040ULL
145 #define PGTBL_PTE_ACCESSED_SHIFT 6
146 #define PGTBL_PTE_GLOBAL_MASK 0x0000000000000020ULL
147 #define PGTBL_PTE_GLOBAL_SHIFT 5
148 #define PGTBL_PTE_USER_MASK 0x0000000000000010ULL
149 #define PGTBL_PTE_USER_SHIFT 4
150 #define PGTBL_PTE_EXECUTE_MASK 0x0000000000000008ULL
151 #define PGTBL_PTE_EXECUTE_SHIFT 3
152 #define PGTBL_PTE_WRITE_MASK 0x0000000000000004ULL
153 #define PGTBL_PTE_WRITE_SHIFT 2
154 #define PGTBL_PTE_READ_MASK 0x0000000000000002ULL
155 #define PGTBL_PTE_READ_SHIFT 1
156 #define PGTBL_PTE_PERM_MASK (PGTBL_PTE_ACCESSED_MASK | \
157 PGTBL_PTE_DIRTY_MASK | \
158 PGTBL_PTE_EXECUTE_MASK | \
159 PGTBL_PTE_WRITE_MASK | \
160 PGTBL_PTE_READ_MASK)
161 #define PGTBL_PTE_VALID_MASK 0x0000000000000001ULL
162 #define PGTBL_PTE_VALID_SHIFT 0
163
164 #define PGTBL_PAGE_SIZE PGTBL_L0_BLOCK_SIZE
165 #define PGTBL_PAGE_SIZE_SHIFT PGTBL_L0_BLOCK_SHIFT
166
local_irq_enable(void)167 static inline void local_irq_enable(void)
168 {
169 csr_set(CSR_SSTATUS, SR_SIE);
170 }
171
local_irq_disable(void)172 static inline void local_irq_disable(void)
173 {
174 csr_clear(CSR_SSTATUS, SR_SIE);
175 }
176
177 #endif /* SELFTEST_KVM_PROCESSOR_H */
178