1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #ifndef __RTW89_PHY_H__
6 #define __RTW89_PHY_H__
7
8 #include "core.h"
9
10 #define RTW89_BBMCU_ADDR_OFFSET 0x30000
11 #define RTW89_RF_ADDR_ADSEL_MASK BIT(16)
12
13 #define get_phy_headline(addr) FIELD_GET(GENMASK(31, 28), addr)
14 #define PHY_HEADLINE_VALID 0xf
15 #define get_phy_target(addr) FIELD_GET(GENMASK(27, 0), addr)
16 #define get_phy_compare(rfe, cv) (FIELD_PREP(GENMASK(23, 16), rfe) | \
17 FIELD_PREP(GENMASK(7, 0), cv))
18
19 #define get_phy_cond(addr) FIELD_GET(GENMASK(31, 28), addr)
20 #define get_phy_cond_rfe(addr) FIELD_GET(GENMASK(23, 16), addr)
21 #define get_phy_cond_pkg(addr) FIELD_GET(GENMASK(15, 8), addr)
22 #define get_phy_cond_cv(addr) FIELD_GET(GENMASK(7, 0), addr)
23 #define phy_div(a, b) ({typeof(b) _b = (b); (_b) ? ((a) / (_b)) : 0; })
24 #define PHY_COND_BRANCH_IF 0x8
25 #define PHY_COND_BRANCH_ELIF 0x9
26 #define PHY_COND_BRANCH_ELSE 0xa
27 #define PHY_COND_BRANCH_END 0xb
28 #define PHY_COND_CHECK 0x4
29 #define PHY_COND_DONT_CARE 0xff
30
31 #define RA_MASK_CCK_RATES GENMASK_ULL(3, 0)
32 #define RA_MASK_OFDM_RATES GENMASK_ULL(11, 4)
33 #define RA_MASK_SUBCCK_RATES 0x5ULL
34 #define RA_MASK_SUBOFDM_RATES 0x10ULL
35 #define RA_MASK_HT_1SS_RATES GENMASK_ULL(19, 12)
36 #define RA_MASK_HT_2SS_RATES GENMASK_ULL(31, 24)
37 #define RA_MASK_HT_3SS_RATES GENMASK_ULL(43, 36)
38 #define RA_MASK_HT_4SS_RATES GENMASK_ULL(55, 48)
39 #define RA_MASK_HT_RATES GENMASK_ULL(55, 12)
40 #define RA_MASK_VHT_1SS_RATES GENMASK_ULL(21, 12)
41 #define RA_MASK_VHT_2SS_RATES GENMASK_ULL(33, 24)
42 #define RA_MASK_VHT_3SS_RATES GENMASK_ULL(45, 36)
43 #define RA_MASK_VHT_4SS_RATES GENMASK_ULL(57, 48)
44 #define RA_MASK_VHT_RATES GENMASK_ULL(57, 12)
45 #define RA_MASK_HE_1SS_RATES GENMASK_ULL(23, 12)
46 #define RA_MASK_HE_2SS_RATES GENMASK_ULL(35, 24)
47 #define RA_MASK_HE_3SS_RATES GENMASK_ULL(47, 36)
48 #define RA_MASK_HE_4SS_RATES GENMASK_ULL(59, 48)
49 #define RA_MASK_HE_RATES GENMASK_ULL(59, 12)
50 #define RA_MASK_EHT_1SS_RATES GENMASK_ULL(27, 12)
51 #define RA_MASK_EHT_2SS_RATES GENMASK_ULL(43, 28)
52 #define RA_MASK_EHT_3SS_RATES GENMASK_ULL(59, 44)
53 #define RA_MASK_EHT_4SS_RATES GENMASK_ULL(62, 60)
54 #define RA_MASK_EHT_1SS_MCS0_11 GENMASK_ULL(23, 12)
55 #define RA_MASK_EHT_2SS_MCS0_11 GENMASK_ULL(39, 28)
56 #define RA_MASK_EHT_3SS_MCS0_11 GENMASK_ULL(55, 44)
57 #define RA_MASK_EHT_4SS_MCS0_11 GENMASK_ULL(62, 60)
58 #define RA_MASK_EHT_RATES GENMASK_ULL(62, 12)
59
60 #define TX_STATUS_TYPE GENMASK(3, 0)
61 #define TX_STATUS_SUBTYPE GENMASK(7, 4)
62 #define TX_STATUS_TXCMD GENMASK(29, 24)
63 #define TX_STATUS_TXCMD_V1 GENMASK(13, 8)
64 #define TX_STATUS_TXCMD_V2 GENMASK(15, 8)
65 #define TX_STATUS_TXSC GENMASK(7, 4)
66 #define TX_STATUS_TXSC_V1 GENMASK(27, 24)
67 #define TX_STATUS_BW GENMASK(17, 16)
68 #define TX_STATUS_BW_V1 GENMASK(6, 4)
69 #define TX_STATUS_TMAC_TXPWR GENMASK(26, 18)
70 #define TX_STATUS_TMAC_TXPWR_V1 GENMASK(16, 8)
71 #define TX_STATUS_TX_PATH_EN GENMASK(15, 12)
72 #define TX_STATUS_TX_PATH_EN_V1 GENMASK(7, 4)
73 #define TX_STATUS_PATH_MAP GENMASK(23, 16)
74 #define TX_STATUS_PATH_MAP_V1 GENMASK(15, 8)
75 #define TX_STATUS_MAX_MCS GENMASK(7, 4)
76 #define TX_STATUS_MAX_MCS_V1 GENMASK(3, 0)
77 #define TX_STATUS_STBC BIT(0)
78
79 #define CFO_TRK_ENABLE_TH (2 << 2)
80 #define CFO_TRK_STOP_TH_4 (30 << 2)
81 #define CFO_TRK_STOP_TH_3 (20 << 2)
82 #define CFO_TRK_STOP_TH_2 (10 << 2)
83 #define CFO_TRK_STOP_TH_1 (03 << 2)
84 #define CFO_TRK_STOP_TH (2 << 2)
85 #define CFO_SW_COMP_FINE_TUNE (2 << 2)
86 #define CFO_PERIOD_CNT 15
87 #define CFO_BOUND 64
88 #define CFO_TP_UPPER 100
89 #define CFO_TP_LOWER 50
90 #define CFO_COMP_PERIOD 250
91 #define CFO_COMP_WEIGHT 8
92 #define MAX_CFO_TOLERANCE 30
93 #define CFO_TF_CNT_TH 300
94
95 #define UL_TB_TF_CNT_L2H_TH 100
96 #define UL_TB_TF_CNT_H2L_TH 70
97
98 #define ANTDIV_TRAINNING_CNT 2
99 #define ANTDIV_TRAINNING_INTVL 30
100 #define ANTDIV_DELAY 110
101 #define ANTDIV_TP_DIFF_TH_HIGH 100
102 #define ANTDIV_TP_DIFF_TH_LOW 5
103 #define ANTDIV_EVM_DIFF_TH 8
104 #define ANTDIV_RSSI_DIFF_TH 3
105
106 #define CCX_MAX_PERIOD 2097
107 #define CCX_MAX_PERIOD_UNIT 32
108 #define MS_TO_4US_RATIO 250
109 #define ENV_MNTR_FAIL_DWORD 0xffffffff
110 #define ENV_MNTR_IFSCLM_HIS_MAX 127
111 #define PERMIL 1000
112 #define PERCENT 100
113 #define IFS_CLM_TH0_UPPER 64
114 #define IFS_CLM_TH_MUL 4
115 #define IFS_CLM_TH_START_IDX 0
116
117 #define TIA0_GAIN_A 12
118 #define TIA0_GAIN_G 16
119 #define LNA0_GAIN (-24)
120 #define U4_MAX_BIT 3
121 #define U8_MAX_BIT 7
122 #define DIG_GAIN_SHIFT 2
123 #define DIG_GAIN 8
124
125 #define LNA_IDX_MAX 6
126 #define LNA_IDX_MIN 0
127 #define TIA_IDX_MAX 1
128 #define TIA_IDX_MIN 0
129 #define RXB_IDX_MAX 31
130 #define RXB_IDX_MIN 0
131
132 #define IGI_RSSI_MAX 110
133 #define PD_TH_MAX_RSSI 70
134 #define PD_TH_MIN_RSSI 8
135 #define CCKPD_TH_MIN_RSSI (-18)
136 #define PD_TH_BW160_CMP_VAL 9
137 #define PD_TH_BW80_CMP_VAL 6
138 #define PD_TH_BW40_CMP_VAL 3
139 #define PD_TH_BW20_CMP_VAL 0
140 #define PD_TH_CMP_VAL 3
141 #define PD_TH_SB_FLTR_CMP_VAL 7
142
143 #define PHYSTS_MGNT BIT(RTW89_RX_TYPE_MGNT)
144 #define PHYSTS_CTRL BIT(RTW89_RX_TYPE_CTRL)
145 #define PHYSTS_DATA BIT(RTW89_RX_TYPE_DATA)
146 #define PHYSTS_RSVD BIT(RTW89_RX_TYPE_RSVD)
147 #define PPDU_FILTER_BITMAP (PHYSTS_MGNT | PHYSTS_DATA)
148
149 #define EDCCA_MAX 249
150 #define EDCCA_TH_L2H_LB 66
151 #define EDCCA_TH_REF 3
152 #define EDCCA_HL_DIFF_NORMAL 8
153 #define RSSI_UNIT_CONVER 110
154 #define EDCCA_UNIT_CONVER 128
155 #define EDCCA_PWROFST_DEFAULT 18
156
157 #define VAR_LEN 0xff
158 #define VAR_LEN_UNIT 8
159
160 enum rtw89_phy_c2h_ra_func {
161 RTW89_PHY_C2H_FUNC_STS_RPT,
162 RTW89_PHY_C2H_FUNC_MU_GPTBL_RPT,
163 RTW89_PHY_C2H_FUNC_TXSTS,
164 RTW89_PHY_C2H_FUNC_TX_HISTORY = 0x4,
165 RTW89_PHY_C2H_FUNC_ACCELERATE_EN = 0x7,
166
167 RTW89_PHY_C2H_FUNC_RA_NUM,
168 };
169
170 enum rtw89_phy_c2h_rfk_log_func {
171 RTW89_PHY_C2H_RFK_LOG_FUNC_IQK = 0,
172 RTW89_PHY_C2H_RFK_LOG_FUNC_DPK = 1,
173 RTW89_PHY_C2H_RFK_LOG_FUNC_DACK = 2,
174 RTW89_PHY_C2H_RFK_LOG_FUNC_RXDCK = 3,
175 RTW89_PHY_C2H_RFK_LOG_FUNC_TSSI = 4,
176 RTW89_PHY_C2H_RFK_LOG_FUNC_TXGAPK = 5,
177 RTW89_PHY_C2H_RFK_LOG_FUNC_TAS_PWR = 9,
178 RTW89_PHY_C2H_RFK_LOG_FUNC_TXIQK = 0xc,
179 RTW89_PHY_C2H_RFK_LOG_FUNC_CIM3K = 0xe,
180
181 RTW89_PHY_C2H_RFK_LOG_FUNC_NUM,
182 };
183
184 enum rtw89_phy_c2h_rfk_report_func {
185 RTW89_PHY_C2H_RFK_REPORT_FUNC_STATE = 0,
186 RTW89_PHY_C2H_RFK_REPORT_FUNC_TAS_PWR = 6,
187 };
188
189 enum rtw89_phy_c2h_dm_func {
190 RTW89_PHY_C2H_DM_FUNC_FW_TEST,
191 RTW89_PHY_C2H_DM_FUNC_FW_TRIG_TX_RPT,
192 RTW89_PHY_C2H_DM_FUNC_SIGB,
193 RTW89_PHY_C2H_DM_FUNC_LOWRT_RTY,
194 RTW89_PHY_C2H_DM_FUNC_MCC_DIG,
195 RTW89_PHY_C2H_DM_FUNC_LPS = 0x9,
196 RTW89_PHY_C2H_DM_FUNC_ENV_MNTR = 0xa,
197 RTW89_PHY_C2H_DM_FUNC_FW_SCAN = 0xc,
198 RTW89_PHY_C2H_DM_FUNC_NUM,
199 };
200
201 enum rtw89_phy_c2h_class {
202 RTW89_PHY_C2H_CLASS_RUA,
203 RTW89_PHY_C2H_CLASS_RA,
204 RTW89_PHY_C2H_CLASS_DM,
205 RTW89_PHY_C2H_RFK_LOG = 0x8,
206 RTW89_PHY_C2H_RFK_REPORT = 0x9,
207 RTW89_PHY_C2H_CLASS_BTC_MIN = 0x10,
208 RTW89_PHY_C2H_CLASS_BTC_MAX = 0x17,
209 RTW89_PHY_C2H_CLASS_MAX,
210 };
211
212 enum rtw89_env_monitor_result_level {
213 RTW89_PHY_ENV_MON_CCX_FAIL = 0,
214 RTW89_PHY_ENV_MON_NHM = BIT(0),
215 RTW89_PHY_ENV_MON_CLM = BIT(1),
216 RTW89_PHY_ENV_MON_FAHM = BIT(2),
217 RTW89_PHY_ENV_MON_IFS_CLM = BIT(3),
218 RTW89_PHY_ENV_MON_EDCCA_CLM = BIT(4),
219 };
220
221 #define RTW89_NHM_WEIGHT_OFFSET 2
222 #define RTW89_NHM_WA_TH (109 << 1)
223 #define RTW89_NOISE_DEFAULT -96
224 #define RTW89_NHM_MNTR_TIME 40
225 #define RTW89_NHM_TH_FACTOR 1
226
227 #define CCX_US_BASE_RATIO 4
228 enum rtw89_ccx_unit {
229 RTW89_CCX_4_US = 0,
230 RTW89_CCX_8_US = 1,
231 RTW89_CCX_16_US = 2,
232 RTW89_CCX_32_US = 3
233 };
234
235 enum rtw89_phy_status_ie_type {
236 RTW89_PHYSTS_IE00_CMN_CCK = 0,
237 RTW89_PHYSTS_IE01_CMN_OFDM = 1,
238 RTW89_PHYSTS_IE02_CMN_EXT_AX = 2,
239 RTW89_PHYSTS_IE03_CMN_EXT_SEG_1 = 3,
240 RTW89_PHYSTS_IE04_CMN_EXT_PATH_A = 4,
241 RTW89_PHYSTS_IE05_CMN_EXT_PATH_B = 5,
242 RTW89_PHYSTS_IE06_CMN_EXT_PATH_C = 6,
243 RTW89_PHYSTS_IE07_CMN_EXT_PATH_D = 7,
244 RTW89_PHYSTS_IE08_FTR_CH = 8,
245 RTW89_PHYSTS_IE09_FTR_0 = 9,
246 RTW89_PHYSTS_IE10_FTR_PLCP_EXT = 10,
247 RTW89_PHYSTS_IE11_FTR_PLCP_HISTOGRAM = 11,
248 RTW89_PHYSTS_IE12_MU_EIGEN_INFO = 12,
249 RTW89_PHYSTS_IE13_DL_MU_DEF = 13,
250 RTW89_PHYSTS_IE14_TB_UL_CQI = 14,
251 RTW89_PHYSTS_IE15_TB_UL_DEF = 15,
252 RTW89_PHYSTS_IE16_RSVD16 = 16,
253 RTW89_PHYSTS_IE17_TB_UL_CTRL = 17,
254 RTW89_PHYSTS_IE18_DBG_OFDM_FD_CMN = 18,
255 RTW89_PHYSTS_IE19_DBG_OFDM_TD_CMN = 19,
256 RTW89_PHYSTS_IE20_DBG_OFDM_FD_USER_SEG_0 = 20,
257 RTW89_PHYSTS_IE21_DBG_OFDM_FD_USER_SEG_1 = 21,
258 RTW89_PHYSTS_IE22_DBG_OFDM_FD_USER_AGC = 22,
259 RTW89_PHYSTS_IE23_RSVD23 = 23,
260 RTW89_PHYSTS_IE24_OFDM_TD_PATH_A = 24,
261 RTW89_PHYSTS_IE25_OFDM_TD_PATH_B = 25,
262 RTW89_PHYSTS_IE26_OFDM_TD_PATH_C = 26,
263 RTW89_PHYSTS_IE27_OFDM_TD_PATH_D = 27,
264 RTW89_PHYSTS_IE28_DBG_CCK_PATH_A = 28,
265 RTW89_PHYSTS_IE29_DBG_CCK_PATH_B = 29,
266 RTW89_PHYSTS_IE30_DBG_CCK_PATH_C = 30,
267 RTW89_PHYSTS_IE31_DBG_CCK_PATH_D = 31,
268
269 /* keep last */
270 RTW89_PHYSTS_IE_NUM,
271 RTW89_PHYSTS_IE_MAX = RTW89_PHYSTS_IE_NUM - 1
272 };
273
274 enum rtw89_phy_status_bitmap {
275 RTW89_TD_SEARCH_FAIL = 0,
276 RTW89_BRK_BY_TX_PKT = 1,
277 RTW89_CCA_SPOOF = 2,
278 RTW89_OFDM_BRK = 3,
279 RTW89_CCK_BRK = 4,
280 RTW89_DL_MU_SPOOFING = 5,
281 RTW89_HE_MU = 6,
282 RTW89_VHT_MU = 7,
283 RTW89_UL_TB_SPOOFING = 8,
284 RTW89_RSVD_9 = 9,
285 RTW89_TRIG_BASE_PPDU = 10,
286 RTW89_CCK_PKT = 11,
287 RTW89_LEGACY_OFDM_PKT = 12,
288 RTW89_HT_PKT = 13,
289 RTW89_VHT_PKT = 14,
290 RTW89_HE_PKT = 15,
291 RTW89_EHT_PKT = 16,
292
293 RTW89_PHYSTS_BITMAP_NUM
294 };
295
296 enum rtw89_dig_gain_type {
297 RTW89_DIG_GAIN_LNA_G = 0,
298 RTW89_DIG_GAIN_TIA_G = 1,
299 RTW89_DIG_GAIN_LNA_A = 2,
300 RTW89_DIG_GAIN_TIA_A = 3,
301 RTW89_DIG_GAIN_MAX = 4
302 };
303
304 enum rtw89_dig_gain_lna_idx {
305 RTW89_DIG_GAIN_LNA_IDX1 = 1,
306 RTW89_DIG_GAIN_LNA_IDX2 = 2,
307 RTW89_DIG_GAIN_LNA_IDX3 = 3,
308 RTW89_DIG_GAIN_LNA_IDX4 = 4,
309 RTW89_DIG_GAIN_LNA_IDX5 = 5,
310 RTW89_DIG_GAIN_LNA_IDX6 = 6
311 };
312
313 enum rtw89_dig_gain_tia_idx {
314 RTW89_DIG_GAIN_TIA_IDX0 = 0,
315 RTW89_DIG_GAIN_TIA_IDX1 = 1
316 };
317
318 enum rtw89_tssi_bandedge_cfg {
319 RTW89_TSSI_BANDEDGE_FLAT,
320 RTW89_TSSI_BANDEDGE_LOW,
321 RTW89_TSSI_BANDEDGE_MID,
322 RTW89_TSSI_BANDEDGE_HIGH,
323
324 RTW89_TSSI_CFG_NUM,
325 };
326
327 enum rtw89_tssi_sbw_idx {
328 RTW89_TSSI_SBW20,
329 RTW89_TSSI_SBW40_0,
330 RTW89_TSSI_SBW40_1,
331 RTW89_TSSI_SBW80_0,
332 RTW89_TSSI_SBW80_1,
333 RTW89_TSSI_SBW80_2,
334 RTW89_TSSI_SBW80_3,
335 RTW89_TSSI_SBW160_0,
336 RTW89_TSSI_SBW160_1,
337 RTW89_TSSI_SBW160_2,
338 RTW89_TSSI_SBW160_3,
339 RTW89_TSSI_SBW160_4,
340 RTW89_TSSI_SBW160_5,
341 RTW89_TSSI_SBW160_6,
342 RTW89_TSSI_SBW160_7,
343
344 RTW89_TSSI_SBW_NUM,
345 };
346
347 struct rtw89_txpwr_byrate_cfg {
348 enum rtw89_band band;
349 enum rtw89_nss nss;
350 enum rtw89_rate_section rs;
351 u8 shf;
352 u8 len;
353 u32 data;
354 };
355
356 struct rtw89_phy_dig_gain_cfg {
357 const struct rtw89_reg_def *table;
358 u8 size;
359 };
360
361 struct rtw89_phy_dig_gain_table {
362 const struct rtw89_phy_dig_gain_cfg *cfg_lna_g;
363 const struct rtw89_phy_dig_gain_cfg *cfg_tia_g;
364 const struct rtw89_phy_dig_gain_cfg *cfg_lna_a;
365 const struct rtw89_phy_dig_gain_cfg *cfg_tia_a;
366 };
367
368 struct rtw89_phy_tssi_dbw_table {
369 u32 data[RTW89_TSSI_CFG_NUM][RTW89_TSSI_SBW_NUM];
370 };
371
372 struct rtw89_phy_reg3_tbl {
373 const struct rtw89_reg3_def *reg3;
374 int size;
375 };
376
377 #define DECLARE_PHY_REG3_TBL(_name) \
378 const struct rtw89_phy_reg3_tbl _name ## _tbl = { \
379 .reg3 = _name, \
380 .size = ARRAY_SIZE(_name), \
381 }
382
383 struct rtw89_nbi_reg_def {
384 struct rtw89_reg_def notch1_idx;
385 struct rtw89_reg_def notch1_frac_idx;
386 struct rtw89_reg_def notch1_en;
387 struct rtw89_reg_def notch2_idx;
388 struct rtw89_reg_def notch2_frac_idx;
389 struct rtw89_reg_def notch2_en;
390 };
391
392 struct rtw89_ccx_regs {
393 u32 setting_addr;
394 u32 edcca_opt_mask;
395 u32 measurement_trig_mask;
396 u32 trig_opt_mask;
397 u32 en_mask;
398 u32 ifs_cnt_addr;
399 u32 ifs_clm_period_mask;
400 u32 ifs_clm_cnt_unit_mask;
401 u32 ifs_clm_cnt_clear_mask;
402 u32 ifs_collect_en_mask;
403 u32 ifs_t1_addr;
404 u32 ifs_t1_th_h_mask;
405 u32 ifs_t1_en_mask;
406 u32 ifs_t1_th_l_mask;
407 u32 ifs_t2_addr;
408 u32 ifs_t2_th_h_mask;
409 u32 ifs_t2_en_mask;
410 u32 ifs_t2_th_l_mask;
411 u32 ifs_t3_addr;
412 u32 ifs_t3_th_h_mask;
413 u32 ifs_t3_en_mask;
414 u32 ifs_t3_th_l_mask;
415 u32 ifs_t4_addr;
416 u32 ifs_t4_th_h_mask;
417 u32 ifs_t4_en_mask;
418 u32 ifs_t4_th_l_mask;
419 u32 ifs_clm_tx_cnt_addr;
420 u32 ifs_clm_edcca_excl_cca_fa_mask;
421 u32 ifs_clm_tx_cnt_msk;
422 u32 ifs_clm_cca_addr;
423 u32 ifs_clm_ofdmcca_excl_fa_mask;
424 u32 ifs_clm_cckcca_excl_fa_mask;
425 u32 ifs_clm_fa_addr;
426 u32 ifs_clm_ofdm_fa_mask;
427 u32 ifs_clm_cck_fa_mask;
428 u32 ifs_his_addr;
429 u32 ifs_his_addr2;
430 u32 ifs_t4_his_mask;
431 u32 ifs_t3_his_mask;
432 u32 ifs_t2_his_mask;
433 u32 ifs_t1_his_mask;
434 u32 ifs_avg_l_addr;
435 u32 ifs_t2_avg_mask;
436 u32 ifs_t1_avg_mask;
437 u32 ifs_avg_h_addr;
438 u32 ifs_t4_avg_mask;
439 u32 ifs_t3_avg_mask;
440 u32 ifs_cca_l_addr;
441 u32 ifs_t2_cca_mask;
442 u32 ifs_t1_cca_mask;
443 u32 ifs_cca_h_addr;
444 u32 ifs_t4_cca_mask;
445 u32 ifs_t3_cca_mask;
446 u32 ifs_total_addr;
447 u32 ifs_cnt_done_mask;
448 u32 ifs_total_mask;
449 u32 nhm;
450 u32 nhm_ready;
451 u32 nhm_config;
452 u32 nhm_period_mask;
453 u32 nhm_unit_mask;
454 u32 nhm_include_cca_mask;
455 u32 nhm_en_mask;
456 u32 nhm_method;
457 u32 nhm_pwr_method_msk;
458 u32 edcca_clm_rdy;
459 u32 edcca_clm_rdy_mask;
460 u32 edcca_clm_cnt;
461 u32 edcca_clm_cnt_mask;
462 };
463
464 struct rtw89_physts_regs {
465 u32 setting_addr;
466 u32 dis_trigger_fail_mask;
467 u32 dis_trigger_brk_mask;
468 struct rtw89_reg_def mac_phy_intf_sel;
469 const struct rtw89_reg_def *txpwr;
470 struct rtw89_regs_def tx_info;
471 struct rtw89_regs_def tx_common_ctrl;
472 };
473
474 struct rtw89_cfo_regs {
475 u32 comp;
476 u32 weighting_mask;
477 u32 comp_seg0;
478 u32 valid_0_mask;
479 };
480
481 struct rtw89_bb_wrap_regs {
482 u32 pwr_macid_lmt;
483 u32 pwr_macid_path;
484 };
485
486 struct rtw89_nctl_regs {
487 u32 cfg;
488 u32 rw;
489 };
490
491 enum rtw89_bandwidth_section_num_ax {
492 RTW89_BW20_SEC_NUM_AX = 8,
493 RTW89_BW40_SEC_NUM_AX = 4,
494 RTW89_BW80_SEC_NUM_AX = 2,
495 };
496
497 enum rtw89_bandwidth_section_num_be {
498 RTW89_BW20_SEC_NUM_BE = 16,
499 RTW89_BW40_SEC_NUM_BE = 8,
500 RTW89_BW80_SEC_NUM_BE = 4,
501 RTW89_BW160_SEC_NUM_BE = 2,
502 };
503
504 #define RTW89_TXPWR_LMT_PAGE_SIZE_AX 40
505
506 struct rtw89_txpwr_limit_ax {
507 s8 cck_20m[RTW89_BF_NUM];
508 s8 cck_40m[RTW89_BF_NUM];
509 s8 ofdm[RTW89_BF_NUM];
510 s8 mcs_20m[RTW89_BW20_SEC_NUM_AX][RTW89_BF_NUM];
511 s8 mcs_40m[RTW89_BW40_SEC_NUM_AX][RTW89_BF_NUM];
512 s8 mcs_80m[RTW89_BW80_SEC_NUM_AX][RTW89_BF_NUM];
513 s8 mcs_160m[RTW89_BF_NUM];
514 s8 mcs_40m_0p5[RTW89_BF_NUM];
515 s8 mcs_40m_2p5[RTW89_BF_NUM];
516 };
517
518 #define RTW89_TXPWR_LMT_PAGE_SIZE_BE 76
519
520 struct rtw89_txpwr_limit_be {
521 s8 cck_20m[RTW89_BF_NUM];
522 s8 cck_40m[RTW89_BF_NUM];
523 s8 ofdm[RTW89_BF_NUM];
524 s8 mcs_20m[RTW89_BW20_SEC_NUM_BE][RTW89_BF_NUM];
525 s8 mcs_40m[RTW89_BW40_SEC_NUM_BE][RTW89_BF_NUM];
526 s8 mcs_80m[RTW89_BW80_SEC_NUM_BE][RTW89_BF_NUM];
527 s8 mcs_160m[RTW89_BW160_SEC_NUM_BE][RTW89_BF_NUM];
528 s8 mcs_320m[RTW89_BF_NUM];
529 s8 mcs_40m_0p5[RTW89_BF_NUM];
530 s8 mcs_40m_2p5[RTW89_BF_NUM];
531 s8 mcs_40m_4p5[RTW89_BF_NUM];
532 s8 mcs_40m_6p5[RTW89_BF_NUM];
533 };
534
535 #define RTW89_RU_SEC_NUM_AX 8
536
537 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX 24
538
539 struct rtw89_txpwr_limit_ru_ax {
540 s8 ru26[RTW89_RU_SEC_NUM_AX];
541 s8 ru52[RTW89_RU_SEC_NUM_AX];
542 s8 ru106[RTW89_RU_SEC_NUM_AX];
543 };
544
545 #define RTW89_RU_SEC_NUM_BE 16
546
547 #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE 80
548
549 struct rtw89_txpwr_limit_ru_be {
550 s8 ru26[RTW89_RU_SEC_NUM_BE];
551 s8 ru52[RTW89_RU_SEC_NUM_BE];
552 s8 ru106[RTW89_RU_SEC_NUM_BE];
553 s8 ru52_26[RTW89_RU_SEC_NUM_BE];
554 s8 ru106_26[RTW89_RU_SEC_NUM_BE];
555 };
556
557 #define RTW89_RU484_242_SEC_NUM_BE 4
558 #define RTW89_RU996_484_SEC_NUM_BE 2
559 #define RTW89_RU996_484_242_SEC_NUM_BE 2
560
561 struct rtw89_txpwr_limit_large_mru_be {
562 s8 ru484_242[RTW89_NSS_NUM][RTW89_RU484_242_SEC_NUM_BE];
563 s8 ru996_484[RTW89_NSS_NUM][RTW89_RU996_484_SEC_NUM_BE];
564 s8 ru996_484_242[RTW89_NSS_NUM][RTW89_RU996_484_242_SEC_NUM_BE];
565 };
566
567 struct rtw89_phy_rfk_log_fmt {
568 const struct rtw89_fw_element_hdr *elm[RTW89_PHY_C2H_RFK_LOG_FUNC_NUM];
569 };
570
571 enum rtw89_mdpd_onoff {
572 MDPD_ON = 0,
573 MDPD_OFF = 1,
574 };
575
576 enum rtw89_oob_dpd_onoff {
577 OOB_DPD_OFF = 0,
578 OOB_DPD_ON = 1,
579 };
580
581 enum rtw89_cim3k_onoff {
582 CIM3K_ON = 1,
583 CIM3K_OFF = 0,
584 };
585
586 enum rtw89_cim3k_en_dis {
587 CIM3K_ENABLE = 1,
588 CIM3K_DISABLE = 0,
589 };
590
591 enum rtw89_rfsi_ctrl_modulation {
592 RFSI_BPSK = 0,
593 RFSI_QPSK = 1,
594 RFSI_16QAM = 2,
595 RFSI_64QAM = 3,
596 RFSI_256QAM = 4,
597 RFSI_1024QAM = 5,
598 RFSI_4096QAM = 6,
599 RFSI_MAX,
600 };
601
602 enum rtw89_cfir_onoff {
603 CFIR_ON = 1,
604 CFIR_OFF = 0,
605 };
606
607 enum rtw89_filter_onoff {
608 FILTER_A_ON = 1,
609 FILTER_A_OFF = 0,
610 };
611
612 #define MAX_TX_RFSI_CTRL_OPT 10
613
614 #define _8nibble(n0, n1, n2, n3, n4, n5, n6, n7) \
615 ((n0) << 0 | (n1) << 4 | (n2) << 8 | (n3) << 12 | \
616 (n4) << 16 | (n5) << 20 | (n6) << 24 | (n7) << 28)
617
618 #define _qam_comp_code(c) ((((c) & (BIT(15) | BIT(14))) >> 11) | \
619 (((c) & BIT(12)) >> 10) | \
620 (((c) & (BIT(9) | BIT(8))) >> 8))
621
622 #define _10qam_comp_code(c0, c1, c2, c3, c4, c5, c6, c7, c8, c9) \
623 _qam_comp_code(c0), _qam_comp_code(c1), _qam_comp_code(c2), _qam_comp_code(c3), \
624 _qam_comp_code(c4), _qam_comp_code(c5), _qam_comp_code(c6), _qam_comp_code(c7), \
625 _qam_comp_code(c8), _qam_comp_code(c9)
626
627 struct rtw89_bb_wrap_common_data {
628 struct {
629 struct rtw89_bb_wrap_data_cim3k {
630 u8 th, ow, non_bandedge, bandedge;
631 } cim3k;
632 u32 rfsi_ct_opt[2];
633 u8 pb_tb;
634 } bands[RFSI_CTRL_BAND_NUM];
635 u8 qam_th[6];
636 };
637
638 struct rtw89_bb_wrap_common_data_gen3 {
639 struct {
640 u8 qam_th[6];
641 } bands[RFSI_CTRL_BAND_NUM];
642 u8 cck_val[2];
643 };
644
645 struct rtw89_bb_wrap_data {
646 const struct rtw89_bb_wrap_common_data *common;
647 const struct rtw89_bb_wrap_common_data_gen3 *common_gen3;
648 struct {
649 u16 qam_comp_th0[MAX_TX_RFSI_CTRL_OPT];
650 u16 qam_comp_th1[MAX_TX_RFSI_CTRL_OPT]; /* encoded */
651 u16 qam_comp_th2[MAX_TX_RFSI_CTRL_OPT]; /* encoded */
652 u16 qam_comp_ow[MAX_TX_RFSI_CTRL_OPT];
653 u8 oob_dpd_by_cbw[8];
654 } bands[RFSI_CTRL_BAND_NUM];
655 u8 mdpd_by_dbw[4];
656 };
657
658 struct rtw89_phy_gen_def {
659 u32 cr_base;
660 u32 physt_bmp_start;
661 u32 physt_bmp_eht;
662 u8 physt_ie_len[32];
663 u8 physt_gen;
664 const struct rtw89_ccx_regs *ccx;
665 const struct rtw89_physts_regs *physts;
666 const struct rtw89_cfo_regs *cfo;
667 const struct rtw89_bb_wrap_regs *bb_wrap;
668 const struct rtw89_nctl_regs *nctl;
669 u32 (*phy0_phy1_offset)(struct rtw89_dev *rtwdev, u32 addr);
670 void (*config_bb_gain)(struct rtw89_dev *rtwdev,
671 const struct rtw89_reg2_def *reg,
672 enum rtw89_rf_path rf_path,
673 void *extra_data);
674 void (*preinit_rf_nctl)(struct rtw89_dev *rtwdev);
675 void (*bb_wrap_init)(struct rtw89_dev *rtwdev);
676 void (*ch_info_init)(struct rtw89_dev *rtwdev);
677
678 void (*set_txpwr_byrate)(struct rtw89_dev *rtwdev,
679 const struct rtw89_chan *chan,
680 enum rtw89_phy_idx phy_idx);
681 void (*set_txpwr_offset)(struct rtw89_dev *rtwdev,
682 const struct rtw89_chan *chan,
683 enum rtw89_phy_idx phy_idx);
684 void (*set_txpwr_limit)(struct rtw89_dev *rtwdev,
685 const struct rtw89_chan *chan,
686 enum rtw89_phy_idx phy_idx);
687 void (*set_txpwr_limit_ru)(struct rtw89_dev *rtwdev,
688 const struct rtw89_chan *chan,
689 enum rtw89_phy_idx phy_idx);
690 };
691
692 extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax;
693 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be;
694 extern const struct rtw89_phy_gen_def rtw89_phy_gen_be_v1;
695
rtw89_raw_phy_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)696 static inline void rtw89_raw_phy_write8(struct rtw89_dev *rtwdev,
697 u32 addr, u8 data)
698 {
699 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
700
701 rtw89_write8(rtwdev, addr + phy->cr_base, data);
702 }
703
rtw89_raw_phy_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)704 static inline void rtw89_raw_phy_write16(struct rtw89_dev *rtwdev,
705 u32 addr, u16 data)
706 {
707 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
708
709 rtw89_write16(rtwdev, addr + phy->cr_base, data);
710 }
711
rtw89_raw_phy_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)712 static inline void rtw89_raw_phy_write32(struct rtw89_dev *rtwdev,
713 u32 addr, u32 data)
714 {
715 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
716
717 rtw89_write32(rtwdev, addr + phy->cr_base, data);
718 }
719
rtw89_phy_write8(struct rtw89_dev * rtwdev,u32 addr,u8 data)720 static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev,
721 u32 addr, u8 data)
722 {
723 rtwdev->io->phy_write8(rtwdev, addr, data);
724 }
725
rtw89_phy_write16(struct rtw89_dev * rtwdev,u32 addr,u16 data)726 static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev,
727 u32 addr, u16 data)
728 {
729 rtwdev->io->phy_write16(rtwdev, addr, data);
730 }
731
rtw89_phy_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data)732 static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev,
733 u32 addr, u32 data)
734 {
735 rtwdev->io->phy_write32(rtwdev, addr, data);
736 }
737
rtw89_phy_write32_set(struct rtw89_dev * rtwdev,u32 addr,u32 bits)738 static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev,
739 u32 addr, u32 bits)
740 {
741 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
742
743 rtw89_write32_set(rtwdev, addr + phy->cr_base, bits);
744 }
745
rtw89_phy_write32_clr(struct rtw89_dev * rtwdev,u32 addr,u32 bits)746 static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev,
747 u32 addr, u32 bits)
748 {
749 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
750
751 rtw89_write32_clr(rtwdev, addr + phy->cr_base, bits);
752 }
753
rtw89_phy_write32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask,u32 data)754 static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev,
755 u32 addr, u32 mask, u32 data)
756 {
757 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
758
759 rtw89_write32_mask(rtwdev, addr + phy->cr_base, mask, data);
760 }
761
rtw89_phy_read8(struct rtw89_dev * rtwdev,u32 addr)762 static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr)
763 {
764 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
765
766 return rtw89_read8(rtwdev, addr + phy->cr_base);
767 }
768
rtw89_phy_read16(struct rtw89_dev * rtwdev,u32 addr)769 static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr)
770 {
771 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
772
773 return rtw89_read16(rtwdev, addr + phy->cr_base);
774 }
775
rtw89_phy_read32(struct rtw89_dev * rtwdev,u32 addr)776 static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr)
777 {
778 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
779
780 return rtw89_read32(rtwdev, addr + phy->cr_base);
781 }
782
rtw89_phy_read32_mask(struct rtw89_dev * rtwdev,u32 addr,u32 mask)783 static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev,
784 u32 addr, u32 mask)
785 {
786 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
787
788 return rtw89_read32_mask(rtwdev, addr + phy->cr_base, mask);
789 }
790
rtw89_bbmcu_write32(struct rtw89_dev * rtwdev,u32 addr,u32 data,enum rtw89_phy_idx phy_idx)791 static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev,
792 u32 addr, u32 data, enum rtw89_phy_idx phy_idx)
793 {
794 if (phy_idx && addr < 0x10000)
795 addr += 0x20000;
796
797 rtw89_write32(rtwdev, addr + RTW89_BBMCU_ADDR_OFFSET, data);
798 }
799
800 static inline
rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)801 enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband)
802 {
803 switch (subband) {
804 default:
805 case RTW89_CH_2G:
806 return RTW89_GAIN_OFFSET_2G_OFDM;
807 case RTW89_CH_5G_BAND_1:
808 return RTW89_GAIN_OFFSET_5G_LOW;
809 case RTW89_CH_5G_BAND_3:
810 return RTW89_GAIN_OFFSET_5G_MID;
811 case RTW89_CH_5G_BAND_4:
812 return RTW89_GAIN_OFFSET_5G_HIGH;
813 case RTW89_CH_6G_BAND_IDX0:
814 return RTW89_GAIN_OFFSET_6G_L0;
815 case RTW89_CH_6G_BAND_IDX1:
816 return RTW89_GAIN_OFFSET_6G_L1;
817 case RTW89_CH_6G_BAND_IDX2:
818 return RTW89_GAIN_OFFSET_6G_M0;
819 case RTW89_CH_6G_BAND_IDX3:
820 return RTW89_GAIN_OFFSET_6G_M1;
821 case RTW89_CH_6G_BAND_IDX4:
822 return RTW89_GAIN_OFFSET_6G_H0;
823 case RTW89_CH_6G_BAND_IDX5:
824 return RTW89_GAIN_OFFSET_6G_H1;
825 case RTW89_CH_6G_BAND_IDX6:
826 return RTW89_GAIN_OFFSET_6G_UH0;
827 case RTW89_CH_6G_BAND_IDX7:
828 return RTW89_GAIN_OFFSET_6G_UH1;
829 }
830 }
831
832 static inline
rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)833 enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband)
834 {
835 switch (subband) {
836 default:
837 case RTW89_CH_2G:
838 return RTW89_BB_GAIN_BAND_2G;
839 case RTW89_CH_5G_BAND_1:
840 return RTW89_BB_GAIN_BAND_5G_L;
841 case RTW89_CH_5G_BAND_3:
842 return RTW89_BB_GAIN_BAND_5G_M;
843 case RTW89_CH_5G_BAND_4:
844 return RTW89_BB_GAIN_BAND_5G_H;
845 case RTW89_CH_6G_BAND_IDX0:
846 case RTW89_CH_6G_BAND_IDX1:
847 return RTW89_BB_GAIN_BAND_6G_L;
848 case RTW89_CH_6G_BAND_IDX2:
849 case RTW89_CH_6G_BAND_IDX3:
850 return RTW89_BB_GAIN_BAND_6G_M;
851 case RTW89_CH_6G_BAND_IDX4:
852 case RTW89_CH_6G_BAND_IDX5:
853 return RTW89_BB_GAIN_BAND_6G_H;
854 case RTW89_CH_6G_BAND_IDX6:
855 case RTW89_CH_6G_BAND_IDX7:
856 return RTW89_BB_GAIN_BAND_6G_UH;
857 }
858 }
859
860 static inline
rtw89_subband_to_gain_band_be(enum rtw89_subband subband)861 enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband)
862 {
863 switch (subband) {
864 default:
865 case RTW89_CH_2G:
866 return RTW89_BB_GAIN_BAND_2G_BE;
867 case RTW89_CH_5G_BAND_1:
868 return RTW89_BB_GAIN_BAND_5G_L_BE;
869 case RTW89_CH_5G_BAND_3:
870 return RTW89_BB_GAIN_BAND_5G_M_BE;
871 case RTW89_CH_5G_BAND_4:
872 return RTW89_BB_GAIN_BAND_5G_H_BE;
873 case RTW89_CH_6G_BAND_IDX0:
874 return RTW89_BB_GAIN_BAND_6G_L0_BE;
875 case RTW89_CH_6G_BAND_IDX1:
876 return RTW89_BB_GAIN_BAND_6G_L1_BE;
877 case RTW89_CH_6G_BAND_IDX2:
878 return RTW89_BB_GAIN_BAND_6G_M0_BE;
879 case RTW89_CH_6G_BAND_IDX3:
880 return RTW89_BB_GAIN_BAND_6G_M1_BE;
881 case RTW89_CH_6G_BAND_IDX4:
882 return RTW89_BB_GAIN_BAND_6G_H0_BE;
883 case RTW89_CH_6G_BAND_IDX5:
884 return RTW89_BB_GAIN_BAND_6G_H1_BE;
885 case RTW89_CH_6G_BAND_IDX6:
886 return RTW89_BB_GAIN_BAND_6G_UH0_BE;
887 case RTW89_CH_6G_BAND_IDX7:
888 return RTW89_BB_GAIN_BAND_6G_UH1_BE;
889 }
890 }
891
892 struct rtw89_rfk_chan_desc {
893 /* desc is valid iff ch is non-zero */
894 u8 ch;
895
896 /* To avoid us from extending old chip code every time, each new
897 * field must be defined along with a bool flag in positivte way.
898 */
899 bool has_band;
900 u8 band;
901 bool has_bw;
902 u8 bw;
903 };
904
905 enum rtw89_rfk_flag {
906 RTW89_RFK_F_WRF = 0,
907 RTW89_RFK_F_WM = 1,
908 RTW89_RFK_F_WS = 2,
909 RTW89_RFK_F_WC = 3,
910 RTW89_RFK_F_DELAY = 4,
911 RTW89_RFK_F_NUM,
912 };
913
914 struct rtw89_rfk_tbl {
915 const struct rtw89_reg5_def *defs;
916 u32 size;
917 };
918
919 #define RTW89_DECLARE_RFK_TBL(_name) \
920 const struct rtw89_rfk_tbl _name ## _tbl = { \
921 .defs = _name, \
922 .size = ARRAY_SIZE(_name), \
923 }
924
925 #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) \
926 {.flag = RTW89_RFK_F_WRF, \
927 .path = _path, \
928 .addr = _addr, \
929 .mask = _mask, \
930 .data = _data,}
931
932 #define RTW89_DECL_RFK_WM(_addr, _mask, _data) \
933 {.flag = RTW89_RFK_F_WM, \
934 .addr = _addr, \
935 .mask = _mask, \
936 .data = _data,}
937
938 #define RTW89_DECL_RFK_WS(_addr, _mask) \
939 {.flag = RTW89_RFK_F_WS, \
940 .addr = _addr, \
941 .mask = _mask,}
942
943 #define RTW89_DECL_RFK_WC(_addr, _mask) \
944 {.flag = RTW89_RFK_F_WC, \
945 .addr = _addr, \
946 .mask = _mask,}
947
948 #define RTW89_DECL_RFK_DELAY(_data) \
949 {.flag = RTW89_RFK_F_DELAY, \
950 .data = _data,}
951
952 void
953 rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl);
954
955 #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) \
956 do { \
957 typeof(dev) __dev = (dev); \
958 if (cond) \
959 rtw89_rfk_parser(__dev, (tbl_t)); \
960 else \
961 rtw89_rfk_parser(__dev, (tbl_f)); \
962 } while (0)
963
964 void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev,
965 const struct rtw89_phy_reg3_tbl *tbl);
966 u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev,
967 const struct rtw89_chan *chan,
968 enum rtw89_bandwidth dbw);
969 u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan,
970 enum rtw89_bandwidth dbw);
971 u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
972 u32 addr, u32 mask);
973 u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
974 u32 addr, u32 mask);
975 u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
976 u32 addr, u32 mask);
977 u32 rtw89_phy_read_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
978 u32 addr, u32 mask);
979 bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
980 u32 addr, u32 mask, u32 data);
981 bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
982 u32 addr, u32 mask, u32 data);
983 bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
984 u32 addr, u32 mask, u32 data);
985 bool rtw89_phy_write_rf_v3(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path,
986 u32 addr, u32 mask, u32 data);
987 void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev);
988 void rtw89_phy_init_bb_afe(struct rtw89_dev *rtwdev);
989 void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio);
990 void rtw89_phy_config_rf_reg(struct rtw89_dev *rtwdev,
991 const struct rtw89_reg2_def *reg,
992 enum rtw89_rf_path rf_path,
993 void *extra_data);
994 void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev,
995 const struct rtw89_reg2_def *reg,
996 enum rtw89_rf_path rf_path,
997 void *extra_data);
998 void rtw89_phy_dm_init(struct rtw89_dev *rtwdev);
999 void rtw89_phy_dm_reinit(struct rtw89_dev *rtwdev);
1000 void rtw89_phy_dm_init_data(struct rtw89_dev *rtwdev);
1001 void rtw89_physts_parsing_init(struct rtw89_dev *rtwdev);
1002 void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1003 u32 data, enum rtw89_phy_idx phy_idx);
1004 void rtw89_phy_write32_idx_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1005 enum rtw89_phy_idx phy_idx);
1006 void rtw89_phy_write32_idx_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits,
1007 enum rtw89_phy_idx phy_idx);
1008 u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1009 enum rtw89_phy_idx phy_idx);
1010 s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev,
1011 struct rtw89_txpwr_byrate *head,
1012 const struct rtw89_rate_desc *desc);
1013 s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw,
1014 const struct rtw89_rate_desc *rate_desc);
1015 void rtw89_phy_ant_gain_init(struct rtw89_dev *rtwdev);
1016 s16 rtw89_phy_ant_gain_pwr_offset(struct rtw89_dev *rtwdev,
1017 const struct rtw89_chan *chan);
1018 int rtw89_print_ant_gain(struct rtw89_dev *rtwdev, char *buf, size_t bufsz,
1019 const struct rtw89_chan *chan);
1020 void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev,
1021 const struct rtw89_txpwr_table *tbl);
1022 s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band,
1023 u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch);
1024 s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band,
1025 u8 ru, u8 ntx, u8 ch);
1026
rtw89_phy_preinit_rf_nctl(struct rtw89_dev * rtwdev)1027 static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev)
1028 {
1029 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
1030
1031 phy->preinit_rf_nctl(rtwdev);
1032 }
1033
rtw89_phy_bb_wrap_init(struct rtw89_dev * rtwdev)1034 static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev)
1035 {
1036 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
1037
1038 if (phy->bb_wrap_init)
1039 phy->bb_wrap_init(rtwdev);
1040 }
1041
1042 void rtw89_phy_bb_wrap_set_rfsi_ct_opt(struct rtw89_dev *rtwdev,
1043 enum rtw89_rfsi_ctrl_band ctrl_band,
1044 enum rtw89_phy_idx phy_idx);
1045 void rtw89_phy_bb_wrap_set_rfsi_bandedge_ch(struct rtw89_dev *rtwdev,
1046 const struct rtw89_chan *chan,
1047 enum rtw89_phy_idx phy_idx);
1048
rtw89_phy_ch_info_init(struct rtw89_dev * rtwdev)1049 static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev)
1050 {
1051 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
1052
1053 if (phy->ch_info_init)
1054 phy->ch_info_init(rtwdev);
1055 }
1056
1057 static inline
rtw89_phy_set_txpwr_byrate(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1058 void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev,
1059 const struct rtw89_chan *chan,
1060 enum rtw89_phy_idx phy_idx)
1061 {
1062 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
1063
1064 phy->set_txpwr_byrate(rtwdev, chan, phy_idx);
1065 }
1066
1067 static inline
rtw89_phy_set_txpwr_offset(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1068 void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev,
1069 const struct rtw89_chan *chan,
1070 enum rtw89_phy_idx phy_idx)
1071 {
1072 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
1073
1074 phy->set_txpwr_offset(rtwdev, chan, phy_idx);
1075 }
1076
1077 static inline
rtw89_phy_set_txpwr_limit(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1078 void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev,
1079 const struct rtw89_chan *chan,
1080 enum rtw89_phy_idx phy_idx)
1081 {
1082 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
1083
1084 phy->set_txpwr_limit(rtwdev, chan, phy_idx);
1085 }
1086
1087 static inline
rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)1088 void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev,
1089 const struct rtw89_chan *chan,
1090 enum rtw89_phy_idx phy_idx)
1091 {
1092 const struct rtw89_phy_gen_def *phy = rtwdev->chip->phy_def;
1093
1094 phy->set_txpwr_limit_ru(rtwdev, chan, phy_idx);
1095 }
1096
rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev * rtwdev,s8 txpwr_rf)1097 static inline s8 rtw89_phy_txpwr_rf_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_rf)
1098 {
1099 const struct rtw89_chip_info *chip = rtwdev->chip;
1100
1101 return txpwr_rf << (chip->txpwr_factor_bb - chip->txpwr_factor_rf);
1102 }
1103
rtw89_phy_txpwr_bb_to_rf(struct rtw89_dev * rtwdev,s8 txpwr_bb)1104 static inline s8 rtw89_phy_txpwr_bb_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_bb)
1105 {
1106 const struct rtw89_chip_info *chip = rtwdev->chip;
1107
1108 return txpwr_bb >> (chip->txpwr_factor_bb - chip->txpwr_factor_rf);
1109 }
1110
rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev * rtwdev,s8 txpwr_rf)1111 static inline s8 rtw89_phy_txpwr_rf_to_mac(struct rtw89_dev *rtwdev, s8 txpwr_rf)
1112 {
1113 const struct rtw89_chip_info *chip = rtwdev->chip;
1114
1115 return txpwr_rf >> (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
1116 }
1117
rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev * rtwdev,s8 dbm)1118 static inline s8 rtw89_phy_txpwr_dbm_to_mac(struct rtw89_dev *rtwdev, s8 dbm)
1119 {
1120 const struct rtw89_chip_info *chip = rtwdev->chip;
1121
1122 return clamp_t(s16, dbm << chip->txpwr_factor_mac, -64, 63);
1123 }
1124
rtw89_phy_txpwr_mac_to_rf(struct rtw89_dev * rtwdev,s8 txpwr_mac)1125 static inline s16 rtw89_phy_txpwr_mac_to_rf(struct rtw89_dev *rtwdev, s8 txpwr_mac)
1126 {
1127 const struct rtw89_chip_info *chip = rtwdev->chip;
1128
1129 return txpwr_mac << (chip->txpwr_factor_rf - chip->txpwr_factor_mac);
1130 }
1131
rtw89_phy_txpwr_mac_to_bb(struct rtw89_dev * rtwdev,s8 txpwr_mac)1132 static inline s16 rtw89_phy_txpwr_mac_to_bb(struct rtw89_dev *rtwdev, s8 txpwr_mac)
1133 {
1134 const struct rtw89_chip_info *chip = rtwdev->chip;
1135
1136 return txpwr_mac << (chip->txpwr_factor_bb - chip->txpwr_factor_mac);
1137 }
1138
1139 void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct rtw89_sta_link *rtwsta_link);
1140 void rtw89_phy_ra_update(struct rtw89_dev *rtwdev);
1141 void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta,
1142 u32 changed);
1143 void rtw89_phy_ra_update_sta_link(struct rtw89_dev *rtwdev,
1144 struct rtw89_sta_link *rtwsta_link,
1145 u32 changed);
1146 void rtw89_phy_ra_recalc_agg_limit(struct rtw89_dev *rtwdev);
1147 void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev,
1148 struct ieee80211_vif *vif,
1149 const struct cfg80211_bitrate_mask *mask);
1150 bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func);
1151 void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1152 u32 len, u8 class, u8 func);
1153
1154 extern const char * const rtw89_rfk_report_names[];
1155
1156 int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev,
1157 enum rtw89_phy_idx phy_idx,
1158 unsigned int ms);
1159 int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev,
1160 enum rtw89_phy_idx phy_idx,
1161 const struct rtw89_chan *chan,
1162 enum rtw89_tssi_mode tssi_mode,
1163 unsigned int ms);
1164 int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev,
1165 enum rtw89_phy_idx phy_idx,
1166 const struct rtw89_chan *chan,
1167 unsigned int ms);
1168 int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev,
1169 enum rtw89_phy_idx phy_idx,
1170 const struct rtw89_chan *chan,
1171 unsigned int ms);
1172 int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev,
1173 enum rtw89_phy_idx phy_idx,
1174 const struct rtw89_chan *chan,
1175 unsigned int ms);
1176 int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev,
1177 enum rtw89_phy_idx phy_idx,
1178 const struct rtw89_chan *chan,
1179 unsigned int ms);
1180 int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev,
1181 enum rtw89_phy_idx phy_idx,
1182 const struct rtw89_chan *chan,
1183 bool is_chl_k, unsigned int ms);
1184 int rtw89_phy_rfk_txiqk_and_wait(struct rtw89_dev *rtwdev,
1185 enum rtw89_phy_idx phy_idx,
1186 const struct rtw89_chan *chan,
1187 unsigned int ms);
1188 int rtw89_phy_rfk_cim3k_and_wait(struct rtw89_dev *rtwdev,
1189 enum rtw89_phy_idx phy_idx,
1190 const struct rtw89_chan *chan,
1191 unsigned int ms);
1192 void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev,
1193 enum rtw89_phy_idx phy,
1194 const struct rtw89_chan *chan,
1195 struct rtw89_h2c_rf_tssi *h2c);
1196 void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev,
1197 enum rtw89_phy_idx phy,
1198 const struct rtw89_chan *chan,
1199 struct rtw89_h2c_rf_tssi *h2c);
1200 void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev);
1201 void rtw89_phy_cfo_track_work(struct wiphy *wiphy, struct wiphy_work *work);
1202 void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val,
1203 struct rtw89_rx_phy_ppdu *phy_ppdu);
1204 void rtw89_phy_stat_track(struct rtw89_dev *rtwdev);
1205 void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev);
1206 void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask,
1207 u32 val);
1208 void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb);
1209 void rtw89_phy_dig(struct rtw89_dev *rtwdev);
1210 void rtw89_phy_dig_suspend(struct rtw89_dev *rtwdev);
1211 void rtw89_phy_dig_resume(struct rtw89_dev *rtwdev, bool restore);
1212 void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev);
1213 void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev,
1214 struct rtw89_rx_phy_ppdu *phy_ppdu);
1215 void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev);
1216 void rtw89_phy_antdiv_work(struct wiphy *wiphy, struct wiphy_work *work);
1217 void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev,
1218 struct rtw89_vif_link *rtwvif_link);
1219 void __rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, u8 bss_color, u16 aid,
1220 enum rtw89_phy_idx phy_idx);
1221 void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev,
1222 enum rtw89_mac_idx mac_idx,
1223 enum rtw89_tssi_bandedge_cfg bandedge_cfg);
1224 void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link);
1225 void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev);
1226 u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band);
1227 void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx,
1228 u8 *ch, enum nl80211_band *band);
1229 void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev,
1230 struct rtw89_bb_ctx *bb, bool scan);
1231 void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev);
1232 void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev, struct rtw89_bb_ctx *bb);
1233 enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev,
1234 enum rtw89_phy_idx phy_idx);
1235 enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev,
1236 enum rtw89_phy_idx phy_idx);
1237 u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev,
1238 const struct rtw89_rfk_chan_desc *desc, u8 desc_nr,
1239 const struct rtw89_chan *target_chan);
1240 void rtw89_phy_nhm_setting_init(struct rtw89_dev *rtwdev);
1241 void rtw89_phy_nhm_get_result(struct rtw89_dev *rtwdev, enum rtw89_band hw_band,
1242 u16 ch_hw_value);
1243 void rtw89_phy_nhm_trigger(struct rtw89_dev *rtwdev);
1244
1245 #endif
1246