1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/bitfield.h>
7 #include <linux/err.h>
8 #include <linux/init.h>
9 #include <linux/interrupt.h>
10 #include <linux/irq.h>
11 #include <linux/irqchip.h>
12 #include <linux/irqdomain.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/of_irq.h>
19 #include <linux/soc/qcom/irq.h>
20 #include <linux/spinlock.h>
21 #include <linux/slab.h>
22 #include <linux/types.h>
23 #include <linux/firmware/qcom/qcom_scm.h>
24
25 #define PDC_MAX_IRQS 256
26 #define IRQ_ENABLE_BANK_MAX BITS_TO_BYTES(PDC_MAX_IRQS)
27 #define IRQ_ENABLE_BANK_INDEX_MASK GENMASK(31, 5)
28 #define IRQ_ENABLE_BANK_BIT_MASK GENMASK(4, 0)
29
30 /* Secure DRV register to configure the PDC mode via qcom_scm_io_writel() */
31 #define PDC_GPIO_INT_CTL_ENABLE 0xb2045e8
32 #define PDC_PASS_THROUGH_MODE 0x0
33 #define PDC_SECONDARY_MODE 0x1
34
35 #define PDC_DRV_SIZE 0x10000
36 #define PDC_VERSION_REG 0x1000
37 #define PDC_VERSION_MAJOR GENMASK(23, 16)
38 #define PDC_VERSION_MINOR GENMASK(15, 8)
39 #define PDC_VERSION_STEP GENMASK(7, 0)
40 #define PDC_VERSION(maj, min, step) (FIELD_PREP(PDC_VERSION_MAJOR, (maj)) | \
41 FIELD_PREP(PDC_VERSION_MINOR, (min)) | \
42 FIELD_PREP(PDC_VERSION_STEP, (step)))
43
44 /* Notable PDC versions */
45 #define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0)
46 #define PDC_VERSION_3_0 PDC_VERSION(3, 0, 0)
47 #define PDC_VERSION_2_7 PDC_VERSION(2, 7, 0)
48
49 /*
50 * PDC Hardware registers layout per version:
51 *
52 * IRQ_ENABLE_BANK[b], b = 0....BITS_TO_BYTES(PDC_MAX_IRQS)
53 * IRQ_CFG[n], n = 0....PDC_MAX_IRQS
54 *
55 * +---------------------------------------------------------------+
56 * | v2.7 | v3.0 | v3.2 |
57 * |---------------------------------------------------------------|
58 * | BASE | BASE | BASE |
59 * |---------------------------------------------------------------|
60 * | |
61 * | IRQ_ENABLE_BANK | IRQ_ENABLE_BANK | NA |
62 * |---------------------------------------------------------------|
63 * | IRQ_CFG | IRQ_CFG | IRQ_CFG |
64 * | | | |
65 * | | | [31:6] Unused |
66 * | | [31:5] Unused | [5] GPIO_STATUS |
67 * | | [4] GPIO_STATUS| [4] GPIO_MASK |
68 * | [31:3] Unused | [3] GPIO_MASK | [3] IRQ_ENABLE |
69 * | [0:2] Type | [0:2] Type | [0:2] Type |
70 * |---------------------------------------------------------------|
71 * | IRQ_PARAM | IRQ_PARAM | IRQ_PARAM |
72 * | | |
73 * | [15:8] NUM_GPIO | [15:8] NUM_GPIO | [15:8] NUM_GPIO |
74 * | [7:0] NUM_SPI | [7:0] NUM_SPI | [7:0] NUM_SPI |
75 * +---------------------------------------------------------------+
76 */
77
78 /**
79 * struct pdc_regs: PDC registers location
80 *
81 * @irq_en_reg: IRQ_ENABLE_BANK register location
82 * @irq_cfg_reg: IRQ_CFG register location
83 * @irq_param_reg: IRQ_PARAM register location
84 */
85 struct pdc_regs {
86 u32 irq_en_reg;
87 u32 irq_cfg_reg;
88 u32 irq_param_reg;
89 };
90
91 /**
92 * struct pdc_irq_cfg: bit fields for PDC IRQ_CFG register
93 *
94 * @gpio_irq_sts: bit number for GPIO_STATUS field
95 * @gpio_irq_mask: bit number for GPIO_MASK field
96 * @irq_enable: bit number for IRQ_ENABLE field
97 * @irq_type: GENMASK for IRQ_TYPE field
98 */
99 struct pdc_irq_cfg {
100 u32 gpio_irq_sts;
101 u32 gpio_irq_mask;
102 u32 irq_enable;
103 u32 irq_type;
104 };
105
106 /**
107 * struct pdc_desc: PDC driver state
108 *
109 * @base: PDC base register for DRV2 / HLOS
110 * @prev_base: PDC DRV1 base, applicable only for x1e RTL bug.
111 * @version: PDC version
112 * @num_spis: Total number of direct SPI interrupts
113 * @region: PDC interrupt continuous range
114 * @region_cnt: Total PDC ranges
115 * @mode: PDC_PASS_THROUGH_MODE or PDC_SECONDARY_MODE
116 * @x1e_quirk: x1e H/W Bug handling
117 * @lock: lock for IRQ_ENABLE_BANK protection
118 * @regs: PDC regs (IRQ_ENABLE_BANK and IRQ_CFG)
119 * @cfg_fields: Fields of IRQ_CFG reg
120 * @enable_intr: pointer to enable function based on PDC version
121 * @unmask_gpio: pointer to GPIO irq unmask function
122 * @clear_gpio: pointer to GPIO irq clear function
123 */
124 struct pdc_desc {
125 void __iomem *base;
126 void __iomem *prev_base;
127 u32 version;
128 u32 num_spis;
129
130 struct pdc_pin_region *region;
131 int region_cnt;
132
133 bool x1e_quirk;
134
135 u8 mode;
136 raw_spinlock_t lock;
137
138 const struct pdc_regs *regs;
139 const struct pdc_irq_cfg *cfg_fields;
140
141 void (*enable_intr)(int pin_out, bool on);
142 void (*unmask_gpio)(int pin_out, bool on);
143 void (*clear_gpio)(int pin_out);
144 };
145
146 static const struct pdc_regs pdc_v3_2 = {
147 .irq_cfg_reg = 0x110,
148 .irq_param_reg = 0x100c,
149 };
150
151 static const struct pdc_irq_cfg pdc_cfg_v3_2 = {
152 .gpio_irq_sts = 5,
153 .gpio_irq_mask = 4,
154 .irq_enable = 3,
155 .irq_type = GENMASK(2, 0),
156 };
157
158 static const struct pdc_regs pdc_v3_0 = {
159 .irq_en_reg = 0x10,
160 .irq_cfg_reg = 0x110,
161 .irq_param_reg = 0x100c,
162 };
163
164 static const struct pdc_irq_cfg pdc_cfg_v3_0 = {
165 .gpio_irq_sts = 4,
166 .gpio_irq_mask = 3,
167 .irq_type = GENMASK(2, 0),
168 };
169
170 static const struct pdc_regs pdc_v2_7 = {
171 .irq_en_reg = 0x10,
172 .irq_cfg_reg = 0x110,
173 .irq_param_reg = 0x100c,
174 };
175
176 static const struct pdc_irq_cfg pdc_cfg_v2_7 = {
177 .irq_type = GENMASK(2, 0),
178 };
179
180 struct pdc_pin_region {
181 u32 pin_base;
182 u32 parent_base;
183 u32 cnt;
184 };
185
186 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base)
187
188 static struct pdc_desc *pdc;
189
pdc_base_reg_write(void __iomem * base,int reg,u32 i,u32 val)190 static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val)
191 {
192 writel_relaxed(val, base + reg + i * sizeof(u32));
193 }
194
pdc_reg_write(int reg,u32 i,u32 val)195 static void pdc_reg_write(int reg, u32 i, u32 val)
196 {
197 pdc_base_reg_write(pdc->base, reg, i, val);
198 }
199
pdc_reg_read(int reg,u32 i)200 static u32 pdc_reg_read(int reg, u32 i)
201 {
202 return readl_relaxed(pdc->base + reg + i * sizeof(u32));
203 }
204
pdc_pin_is_gpio(int pin_out)205 static inline bool pdc_pin_is_gpio(int pin_out)
206 {
207 /*
208 * PDC allocates direct SPIs at the beginning and
209 * all GPIOs as SPIs are allocated after direct SPIs.
210 */
211 return pin_out >= pdc->num_spis;
212 }
213
pdc_x1e_irq_enable_write(u32 bank,u32 enable)214 static void pdc_x1e_irq_enable_write(u32 bank, u32 enable)
215 {
216 void __iomem *base;
217
218 /* Remap the write access to work around a hardware bug on X1E */
219 switch (bank) {
220 case 0 ... 1:
221 /* Use previous DRV (client) region and shift to bank 3-4 */
222 base = pdc->prev_base;
223 bank += 3;
224 break;
225 case 2 ... 4:
226 /* Use our own region and shift to bank 0-2 */
227 base = pdc->base;
228 bank -= 2;
229 break;
230 case 5:
231 /* No fixup required for bank 5 */
232 base = pdc->base;
233 break;
234 default:
235 WARN_ON(1);
236 return;
237 }
238
239 pdc_base_reg_write(base, pdc->regs->irq_en_reg, bank, enable);
240 }
241
pdc_enable_intr_bank(int pin_out,bool on)242 static void pdc_enable_intr_bank(int pin_out, bool on)
243 {
244 unsigned long enable;
245 u32 index, mask;
246
247 index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out);
248 mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out);
249
250 guard(raw_spinlock_irqsave)(&pdc->lock);
251
252 enable = pdc_reg_read(pdc->regs->irq_en_reg, index);
253 __assign_bit(mask, &enable, on);
254
255 if (pdc->x1e_quirk)
256 pdc_x1e_irq_enable_write(index, enable);
257 else
258 pdc_reg_write(pdc->regs->irq_en_reg, index, enable);
259 }
260
pdc_clear_gpio_cfg(int pin_out)261 static void pdc_clear_gpio_cfg(int pin_out)
262 {
263 unsigned long gpio_sts;
264
265 gpio_sts = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out);
266 __clear_bit(pdc->cfg_fields->gpio_irq_sts, &gpio_sts);
267 pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_sts);
268 }
269
pdc_unmask_gpio_cfg(int pin_out,bool unmask)270 static void pdc_unmask_gpio_cfg(int pin_out, bool unmask)
271 {
272 unsigned long gpio_mask;
273
274 gpio_mask = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out);
275 __assign_bit(pdc->cfg_fields->gpio_irq_mask, &gpio_mask, !unmask);
276 pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, gpio_mask);
277 }
278
pdc_enable_intr_cfg(int pin_out,bool on)279 static void pdc_enable_intr_cfg(int pin_out, bool on)
280 {
281 unsigned long enable = pdc_reg_read(pdc->regs->irq_cfg_reg, pin_out);
282
283 __assign_bit(pdc->cfg_fields->irq_enable, &enable, on);
284 pdc_reg_write(pdc->regs->irq_cfg_reg, pin_out, enable);
285 }
286
qcom_pdc_gic_secondary_disable(struct irq_data * d)287 static void qcom_pdc_gic_secondary_disable(struct irq_data *d)
288 {
289 pdc->enable_intr(d->hwirq, false);
290 pdc->unmask_gpio(d->hwirq, false);
291 irq_chip_disable_parent(d);
292 }
293
qcom_pdc_gic_disable(struct irq_data * d)294 static void qcom_pdc_gic_disable(struct irq_data *d)
295 {
296 pdc->enable_intr(d->hwirq, false);
297 irq_chip_disable_parent(d);
298 }
299
qcom_pdc_gic_enable(struct irq_data * d)300 static void qcom_pdc_gic_enable(struct irq_data *d)
301 {
302 pdc->enable_intr(d->hwirq, true);
303 irq_chip_enable_parent(d);
304 }
305
qcom_pdc_gic_secondary_enable(struct irq_data * d)306 static void qcom_pdc_gic_secondary_enable(struct irq_data *d)
307 {
308 pdc->enable_intr(d->hwirq, true);
309 pdc->unmask_gpio(d->hwirq, true);
310 irq_chip_enable_parent(d);
311 }
312
qcom_pdc_secondary_ack(struct irq_data * d)313 static void qcom_pdc_secondary_ack(struct irq_data *d)
314 {
315 if (!irqd_is_level_type(d))
316 pdc->clear_gpio(d->hwirq);
317 }
318
qcom_pdc_gic_secondary_eoi(struct irq_data * d)319 static void qcom_pdc_gic_secondary_eoi(struct irq_data *d)
320 {
321 if (irqd_is_level_type(d))
322 pdc->clear_gpio(d->hwirq);
323
324 irq_chip_eoi_parent(d);
325 }
326
qcom_pdc_secondary_mask(struct irq_data * d)327 static void qcom_pdc_secondary_mask(struct irq_data *d)
328 {
329 pdc->enable_intr(d->hwirq, false);
330 pdc->unmask_gpio(d->hwirq, false);
331 irq_chip_mask_parent(d);
332 }
333
qcom_pdc_secondary_unmask(struct irq_data * d)334 static void qcom_pdc_secondary_unmask(struct irq_data *d)
335 {
336 pdc->enable_intr(d->hwirq, true);
337 pdc->unmask_gpio(d->hwirq, true);
338 irq_chip_unmask_parent(d);
339 }
340
341 /*
342 * GIC does not handle falling edge or active low. To allow falling edge and
343 * active low interrupts to be handled at GIC, PDC has an inverter that inverts
344 * falling edge into a rising edge and active low into an active high.
345 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to
346 * set as per the table below.
347 * Level sensitive active low LOW
348 * Rising edge sensitive NOT USED
349 * Falling edge sensitive LOW
350 * Dual Edge sensitive NOT USED
351 * Level sensitive active High HIGH
352 * Falling Edge sensitive NOT USED
353 * Rising edge sensitive HIGH
354 * Dual Edge sensitive HIGH
355 */
356 enum pdc_irq_config_bits {
357 PDC_LEVEL_LOW = 0b000,
358 PDC_EDGE_FALLING = 0b010,
359 PDC_LEVEL_HIGH = 0b100,
360 PDC_EDGE_RISING = 0b110,
361 PDC_EDGE_DUAL = 0b111,
362 };
363
364 /**
365 * qcom_pdc_gic_set_type: Configure PDC for the interrupt
366 *
367 * @d: the interrupt data
368 * @type: the interrupt type
369 *
370 * If @type is edge triggered, forward that as rising edge as PDC
371 * takes care of converting all edge types to rising edge signal
372 * If @type is level, then forward that as level high as PDC
373 * takes care of converting all level types to level high signal
374 */
qcom_pdc_gic_set_type(struct irq_data * d,unsigned int type)375 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type)
376 {
377 enum pdc_irq_config_bits old_pdc_type;
378 enum pdc_irq_config_bits pdc_type;
379 int ret;
380
381 switch (type) {
382 case IRQ_TYPE_EDGE_RISING:
383 pdc_type = PDC_EDGE_RISING;
384 break;
385 case IRQ_TYPE_EDGE_FALLING:
386 pdc_type = PDC_EDGE_FALLING;
387 type = IRQ_TYPE_EDGE_RISING;
388 break;
389 case IRQ_TYPE_EDGE_BOTH:
390 pdc_type = PDC_EDGE_DUAL;
391 type = IRQ_TYPE_EDGE_RISING;
392 break;
393 case IRQ_TYPE_LEVEL_HIGH:
394 pdc_type = PDC_LEVEL_HIGH;
395 break;
396 case IRQ_TYPE_LEVEL_LOW:
397 pdc_type = PDC_LEVEL_LOW;
398 type = IRQ_TYPE_LEVEL_HIGH;
399 break;
400 default:
401 WARN_ON(1);
402 return -EINVAL;
403 }
404
405 old_pdc_type = pdc_reg_read(pdc->regs->irq_cfg_reg, d->hwirq);
406 pdc_type |= (old_pdc_type & ~pdc->cfg_fields->irq_type);
407 pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type);
408
409 ret = irq_chip_set_type_parent(d, type);
410 if (ret)
411 return ret;
412
413 /*
414 * When we change types the PDC can give a phantom interrupt.
415 * Clear it. Specifically the phantom shows up when reconfiguring
416 * polarity of interrupt without changing the state of the signal
417 * but let's be consistent and clear it always.
418 *
419 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
420 * interrupt will be cleared before the rest of the system sees it.
421 */
422 if (old_pdc_type != pdc_type)
423 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
424
425 return 0;
426 }
427
428 /**
429 * qcom_pdc_gic_secondary_set_type: Configure PDC for the interrupt in secondary mode
430 *
431 * @d: the interrupt data
432 * @type: the interrupt type
433 *
434 * All @type are forwarded as level high type to parent GIC
435 */
qcom_pdc_gic_secondary_set_type(struct irq_data * d,unsigned int type)436 static int qcom_pdc_gic_secondary_set_type(struct irq_data *d, unsigned int type)
437 {
438 enum pdc_irq_config_bits old_pdc_type;
439 enum pdc_irq_config_bits pdc_type;
440 int ret;
441
442 switch (type) {
443 case IRQ_TYPE_EDGE_RISING:
444 pdc_type = PDC_EDGE_RISING;
445 break;
446 case IRQ_TYPE_EDGE_FALLING:
447 pdc_type = PDC_EDGE_FALLING;
448 break;
449 case IRQ_TYPE_EDGE_BOTH:
450 pdc_type = PDC_EDGE_DUAL;
451 break;
452 case IRQ_TYPE_LEVEL_HIGH:
453 pdc_type = PDC_LEVEL_HIGH;
454 break;
455 case IRQ_TYPE_LEVEL_LOW:
456 pdc_type = PDC_LEVEL_LOW;
457 break;
458 default:
459 WARN_ON(1);
460 return -EINVAL;
461 }
462
463 old_pdc_type = pdc_reg_read(pdc->regs->irq_cfg_reg, d->hwirq);
464 pdc_type |= (old_pdc_type & ~pdc->cfg_fields->irq_type);
465 pdc_reg_write(pdc->regs->irq_cfg_reg, d->hwirq, pdc_type);
466
467 /*
468 * PDC forwards GPIOs as level high to GIC in secondary
469 * mode. Update the type and clear any previously latched
470 * phantom interrupt at PDC.
471 */
472 type = IRQ_TYPE_LEVEL_HIGH;
473 pdc->clear_gpio(d->hwirq);
474
475 ret = irq_chip_set_type_parent(d, type);
476 if (ret)
477 return ret;
478
479 /*
480 * When we change types the PDC can give a phantom interrupt.
481 * Clear it. Specifically the phantom shows up when reconfiguring
482 * polarity of interrupt without changing the state of the signal
483 * but let's be consistent and clear it always.
484 *
485 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the
486 * interrupt will be cleared before the rest of the system sees it.
487 */
488 if (old_pdc_type != pdc_type)
489 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
490
491 return 0;
492 }
493
494 static struct irq_chip qcom_pdc_gic_chip = {
495 .name = "PDC",
496 .irq_eoi = irq_chip_eoi_parent,
497 .irq_mask = irq_chip_mask_parent,
498 .irq_unmask = irq_chip_unmask_parent,
499 .irq_disable = qcom_pdc_gic_disable,
500 .irq_enable = qcom_pdc_gic_enable,
501 .irq_get_irqchip_state = irq_chip_get_parent_state,
502 .irq_set_irqchip_state = irq_chip_set_parent_state,
503 .irq_retrigger = irq_chip_retrigger_hierarchy,
504 .irq_set_type = qcom_pdc_gic_set_type,
505 .flags = IRQCHIP_MASK_ON_SUSPEND |
506 IRQCHIP_SET_TYPE_MASKED |
507 IRQCHIP_SKIP_SET_WAKE |
508 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
509 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
510 .irq_set_affinity = irq_chip_set_affinity_parent,
511 };
512
513 static struct irq_chip qcom_pdc_gic_secondary_chip = {
514 .name = "PDC",
515 .irq_ack = qcom_pdc_secondary_ack,
516 .irq_eoi = qcom_pdc_gic_secondary_eoi,
517 .irq_mask = qcom_pdc_secondary_mask,
518 .irq_unmask = qcom_pdc_secondary_unmask,
519 .irq_disable = qcom_pdc_gic_secondary_disable,
520 .irq_enable = qcom_pdc_gic_secondary_enable,
521 .irq_get_irqchip_state = irq_chip_get_parent_state,
522 .irq_set_irqchip_state = irq_chip_set_parent_state,
523 .irq_retrigger = irq_chip_retrigger_hierarchy,
524 .irq_set_type = qcom_pdc_gic_secondary_set_type,
525 .flags = IRQCHIP_MASK_ON_SUSPEND |
526 IRQCHIP_SET_TYPE_MASKED |
527 IRQCHIP_SKIP_SET_WAKE |
528 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
529 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent,
530 .irq_set_affinity = irq_chip_set_affinity_parent,
531 };
532
get_pin_region(int pin)533 static struct pdc_pin_region *get_pin_region(int pin)
534 {
535 for (int i = 0; i < pdc->region_cnt; i++) {
536 if (pin >= pdc->region[i].pin_base &&
537 pin < pdc->region[i].pin_base + pdc->region[i].cnt)
538 return &pdc->region[i];
539 }
540
541 return NULL;
542 }
543
qcom_pdc_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * data)544 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
545 unsigned int nr_irqs, void *data)
546 {
547 struct irq_fwspec *fwspec = data;
548 struct irq_fwspec parent_fwspec;
549 struct pdc_pin_region *region;
550 irq_hw_number_t hwirq;
551 unsigned int type;
552 int ret;
553
554 ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type);
555 if (ret)
556 return ret;
557
558 if (hwirq == GPIO_NO_WAKE_IRQ)
559 return irq_domain_disconnect_hierarchy(domain, virq);
560
561 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
562 &qcom_pdc_gic_chip, NULL);
563 if (ret)
564 return ret;
565
566 /*
567 * PDC secondary chip is only set for the GPIO interrupts as SPIs.
568 * Direct SPI interrupts are still in pass through mode (no latching
569 * at PDC).
570 */
571 if (pdc->mode == PDC_SECONDARY_MODE && pdc_pin_is_gpio(hwirq)) {
572 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
573 &qcom_pdc_gic_secondary_chip,
574 NULL);
575 if (ret)
576 return ret;
577
578 /* Secondary mode converts all interrupts to LEVEL HIGH type */
579 type = IRQ_TYPE_LEVEL_HIGH;
580 } else {
581 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
582 &qcom_pdc_gic_chip,
583 NULL);
584 if (ret)
585 return ret;
586
587 if (type & IRQ_TYPE_EDGE_BOTH)
588 type = IRQ_TYPE_EDGE_RISING;
589
590 if (type & IRQ_TYPE_LEVEL_MASK)
591 type = IRQ_TYPE_LEVEL_HIGH;
592 }
593
594 region = get_pin_region(hwirq);
595 if (!region)
596 return irq_domain_disconnect_hierarchy(domain->parent, virq);
597
598 parent_fwspec.fwnode = domain->parent->fwnode;
599 parent_fwspec.param_count = 3;
600 parent_fwspec.param[0] = 0;
601 parent_fwspec.param[1] = pin_to_hwirq(region, hwirq);
602 parent_fwspec.param[2] = type;
603
604 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);
605 }
606
607 static const struct irq_domain_ops qcom_pdc_ops = {
608 .translate = irq_domain_translate_twocell,
609 .alloc = qcom_pdc_alloc,
610 .free = irq_domain_free_irqs_common,
611 };
612
pdc_setup_pin_mapping(struct device * dev)613 static int pdc_setup_pin_mapping(struct device *dev)
614 {
615 struct device_node *np = dev->of_node;
616 int ret, n;
617
618 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));
619 if (n <= 0 || n % 3)
620 return -EINVAL;
621
622 pdc->region_cnt = n / 3;
623 pdc->region = devm_kcalloc(dev, pdc->region_cnt, sizeof(*pdc->region), GFP_KERNEL);
624 if (!pdc->region) {
625 pdc->region_cnt = 0;
626 return -ENOMEM;
627 }
628
629 for (n = 0; n < pdc->region_cnt; n++) {
630 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 0,
631 &pdc->region[n].pin_base);
632 if (ret)
633 return ret;
634 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 1,
635 &pdc->region[n].parent_base);
636 if (ret)
637 return ret;
638 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", n * 3 + 2,
639 &pdc->region[n].cnt);
640 if (ret)
641 return ret;
642
643 for (int i = 0; i < pdc->region[n].cnt; i++) {
644 if (pdc_pin_is_gpio(i + pdc->region[n].pin_base) &&
645 pdc->mode == PDC_SECONDARY_MODE)
646 pdc->clear_gpio(i + pdc->region[n].pin_base);
647
648 pdc->enable_intr(i + pdc->region[n].pin_base, false);
649 }
650 }
651
652 return 0;
653 }
654
qcom_pdc_probe(struct platform_device * pdev,struct device_node * parent)655 static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *parent)
656 {
657 struct irq_domain *parent_domain, *pdc_domain;
658 struct device_node *node = pdev->dev.of_node;
659 struct device *dev = &pdev->dev;
660 resource_size_t res_size;
661 struct resource res;
662 u32 irq_param;
663 int ret;
664
665 /* compat with old sm8150 DT which had very small region for PDC */
666 if (of_address_to_resource(node, 0, &res))
667 return -EINVAL;
668
669 res_size = max_t(resource_size_t, resource_size(&res), PDC_DRV_SIZE);
670 if (res_size > resource_size(&res))
671 pr_warn("%pOF: invalid reg size, please fix DT\n", node);
672
673 pdc = devm_kzalloc(dev, sizeof(*pdc), GFP_KERNEL);
674 if (!pdc)
675 return -ENOMEM;
676
677 pdc->base = devm_ioremap(dev, res.start, res_size);
678 if (!pdc->base) {
679 pr_err("%pOF: unable to map PDC registers\n", node);
680 return -ENXIO;
681 }
682
683 pdc->version = pdc_reg_read(PDC_VERSION_REG, 0);
684
685 if (pdc->version >= PDC_VERSION_3_2) {
686 pdc->cfg_fields = &pdc_cfg_v3_2;
687 pdc->regs = &pdc_v3_2;
688 pdc->enable_intr = pdc_enable_intr_cfg;
689 } else if (pdc->version >= PDC_VERSION_3_0) {
690 pdc->cfg_fields = &pdc_cfg_v3_0;
691 pdc->regs = &pdc_v3_0;
692 pdc->enable_intr = pdc_enable_intr_bank;
693 } else {
694 pdc->cfg_fields = &pdc_cfg_v2_7;
695 pdc->regs = &pdc_v2_7;
696 pdc->enable_intr = pdc_enable_intr_bank;
697 }
698
699 pdc->mode = PDC_PASS_THROUGH_MODE;
700
701 /*
702 * PDC has multiple DRV regions, each one provides the same set of
703 * registers for a particular client in the system. Due to a hardware
704 * bug on X1E, some writes to the IRQ_ENABLE_BANK register must be
705 * issued inside the previous region. This region belongs to
706 * a different client and is not described in the device tree. Map the
707 * region with the expected offset to preserve support for old DTs.
708 */
709 if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) {
710 pdc->prev_base = devm_ioremap(dev, res.start - PDC_DRV_SIZE,
711 pdc->regs->irq_en_reg + IRQ_ENABLE_BANK_MAX);
712 if (!pdc->prev_base) {
713 pr_err("%pOF: unable to map previous PDC DRV region\n", node);
714 return -ENXIO;
715 }
716
717 pdc->x1e_quirk = true;
718
719 if (!qcom_scm_is_available())
720 return -EPROBE_DEFER;
721
722 ret = qcom_scm_io_writel(PDC_GPIO_INT_CTL_ENABLE, PDC_PASS_THROUGH_MODE);
723 if (ret) {
724 pdc->mode = PDC_SECONDARY_MODE;
725 pdc->unmask_gpio = pdc_unmask_gpio_cfg;
726 pdc->clear_gpio = pdc_clear_gpio_cfg;
727 }
728 }
729
730 irq_param = pdc_reg_read(pdc->regs->irq_param_reg, 0);
731 pdc->num_spis = FIELD_GET(GENMASK(7, 0), irq_param);
732
733 parent_domain = irq_find_host(parent);
734 if (!parent_domain) {
735 pr_err("%pOF: unable to find PDC's parent domain\n", node);
736 return -ENXIO;
737 }
738
739 raw_spin_lock_init(&pdc->lock);
740
741 ret = pdc_setup_pin_mapping(dev);
742 if (ret) {
743 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);
744 return ret;
745 }
746
747 pdc_domain = irq_domain_create_hierarchy(parent_domain, IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP,
748 PDC_MAX_IRQS, of_fwnode_handle(node),
749 &qcom_pdc_ops, NULL);
750 if (!pdc_domain) {
751 pr_err("%pOF: PDC domain add failed\n", node);
752 return -ENOMEM;
753 }
754
755 irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP);
756
757 return 0;
758 }
759
760 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc)
761 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_probe)
762 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc)
763 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller");
764 MODULE_LICENSE("GPL v2");
765