| /linux/include/dt-bindings/clock/ |
| H A D | rockchip,rk3506-cru.h | 210 #define PCLK_UART5 197 macro
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| H A D | px30-cru.h | 156 #define PCLK_UART5 333 macro
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| H A D | rockchip,rv1126b-cru.h | 320 #define PCLK_UART5 307 macro
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| H A D | rockchip,rk3528-cru.h | 173 #define PCLK_UART5 161 macro
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| H A D | rockchip,rv1126-cru.h | 316 #define PCLK_UART5 254 macro
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| H A D | rockchip,rk3576-cru.h | 151 #define PCLK_UART5 133 macro
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| H A D | rockchip,rk3588-cru.h | 178 #define PCLK_UART5 163 macro
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| H A D | rk3568-cru.h | 364 #define PCLK_UART5 300 macro
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3506.c | 646 GATE(PCLK_UART5, "pclk_uart5", "pclk_hsperi_root", 0,
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| H A D | clk-px30.c | 850 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 9, GFLAGS),
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| H A D | clk-rv1126.c | 501 GATE(PCLK_UART5, "pclk_uart5", "pclk_pdbus", 0,
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| H A D | clk-rk3528.c | 916 GATE(PCLK_UART5, "pclk_uart5", "pclk_vpu_root", 0,
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| H A D | clk-rv1126b.c | 928 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,
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| H A D | clk-rk3568.c | 1259 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus", 0,
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| H A D | clk-rk3576.c | 652 GATE(PCLK_UART5, "pclk_uart5", "pclk_bus_root", 0,
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| H A D | clk-rk3588.c | 1208 GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0,
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rv1126.dtsi | 516 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| /linux/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3562.dtsi | 826 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | rk3528.dtsi | 761 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | px30.dtsi | 559 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | rk356x-base.dtsi | 1437 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | rk3576.dtsi | 2413 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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| H A D | rk3588-base.dtsi | 2598 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
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