| /linux/include/dt-bindings/clock/ |
| H A D | samsung,s3c64xx-clock.h | 67 #define PCLK_SPI1 52 macro
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| H A D | exynos7-clk.h | 105 #define PCLK_SPI1 13 macro
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| H A D | rockchip,rk3506-cru.h | 136 #define PCLK_SPI1 123 macro
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| H A D | rockchip,rv1106-cru.h | 84 #define PCLK_SPI1 71 macro
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| H A D | rk3308-cru.h | 187 #define PCLK_SPI1 208 macro
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| H A D | px30-cru.h | 165 #define PCLK_SPI1 342 macro
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| H A D | rk3288-cru.h | 131 #define PCLK_SPI1 339 macro
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| H A D | rk3368-cru.h | 124 #define PCLK_SPI1 339 macro
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| H A D | rockchip,rv1126b-cru.h | 306 #define PCLK_SPI1 293 macro
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| H A D | rockchip,rk3528-cru.h | 169 #define PCLK_SPI1 157 macro
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| H A D | rockchip,rv1126-cru.h | 321 #define PCLK_SPI1 259 macro
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| H A D | rockchip,rk3576-cru.h | 170 #define PCLK_SPI1 152 macro
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| H A D | rk3399-cru.h | 243 #define PCLK_SPI1 348 macro
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| H A D | rockchip,rk3588-cru.h | 162 #define PCLK_SPI1 147 macro
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| H A D | rk3568-cru.h | 403 #define PCLK_SPI1 339 macro
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3xxx.dtsi | 467 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
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| /linux/drivers/clk/rockchip/ |
| H A D | clk-rk3368.c | 801 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3368_CLKGATE_CON(19), 5, GFLAGS),
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| H A D | clk-rk3506.c | 468 GATE(PCLK_SPI1, "pclk_spi1", "pclk_lsperi_root", 0,
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| H A D | clk-rk3288.c | 736 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri", 0, RK3288_CLKGATE_CON(6), 5, GFLAGS),
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| H A D | clk-rk3308.c | 876 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 5, GFLAGS),
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| H A D | clk-px30.c | 859 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_pre", 0, PX30_CLKGATE_CON(15), 2, GFLAGS),
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| H A D | clk-rv1126.c | 534 GATE(PCLK_SPI1, "pclk_spi1", "pclk_pdbus", 0,
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| H A D | clk-rk3528.c | 902 GATE(PCLK_SPI1, "pclk_spi1", "pclk_vpu_root", 0,
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| H A D | clk-rv1126b.c | 900 GATE(PCLK_SPI1, "pclk_spi1", "pclk_bus_root", 0,
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| H A D | clk-rv1106.c | 671 GATE(PCLK_SPI1, "pclk_spi1", "pclk_peri_root", 0,
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