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Searched refs:PCLK_PWM0 (Results 1 – 21 of 21) sorted by relevance

/linux/include/dt-bindings/clock/
H A Drockchip,rk3506-cru.h265 #define PCLK_PWM0 252 macro
H A Drk3308-cru.h185 #define PCLK_PWM0 206 macro
H A Dpx30-cru.h162 #define PCLK_PWM0 339 macro
H A Drk3368-cru.h135 #define PCLK_PWM0 350 macro
H A Drockchip,rv1126b-cru.h307 #define PCLK_PWM0 294 macro
H A Drockchip,rk3528-cru.h122 #define PCLK_PWM0 110 macro
H A Drockchip,rv1126-cru.h48 #define PCLK_PWM0 35 macro
H A Drk3568-cru.h61 #define PCLK_PWM0 48 macro
/linux/arch/arm/boot/dts/rockchip/
H A Drv1126.dtsi276 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
287 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
298 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
309 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3528.dtsi910 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
920 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
930 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
940 clocks = <&cru CLK_PWM0>, <&cru PCLK_PWM0>;
H A Drk3308.dtsi503 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
514 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
525 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
536 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
H A Dpx30.dtsi665 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
676 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
687 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
698 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>;
H A Drk356x-base.dtsi436 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
447 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
458 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
469 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
/linux/drivers/clk/rockchip/
H A Dclk-rk3368.c704 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", CLK_IGNORE_UNUSED, RK3368_CLKGATE_CON(12), 0, GFLAGS),
H A Dclk-rk3506.c722 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pmu_root", 0,
H A Dclk-rk3308.c874 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus", 0, RK3308_CLKGATE_CON(6), 3, GFLAGS),
H A Dclk-px30.c856 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_pre", 0, PX30_CLKGATE_CON(14), 15, GFLAGS),
H A Dclk-rv1126.c318 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,
H A Dclk-rk3528.c477 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
H A Dclk-rv1126b.c902 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_bus_root", 0,
H A Dclk-rk3568.c1517 GATE(PCLK_PWM0, "pclk_pwm0", "pclk_pdpmu", 0,