1 /* SPDX-License-Identifier: GPL-2.0 */ 2 #ifndef DRIVERS_PCI_H 3 #define DRIVERS_PCI_H 4 5 #include <linux/align.h> 6 #include <linux/bitfield.h> 7 #include <linux/pci.h> 8 #include <trace/events/pci.h> 9 10 struct pcie_tlp_log; 11 12 /* Number of possible devfns: 0.0 to 1f.7 inclusive */ 13 #define MAX_NR_DEVFNS 256 14 #define PCI_MAX_NR_DEVS 32 15 16 #define MAX_NR_LANES 16 17 18 #define PCI_FIND_CAP_TTL 48 19 20 #define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */ 21 22 #define PCIE_LINK_RETRAIN_TIMEOUT_MS 1000 23 24 /* 25 * Power stable to PERST# inactive. 26 * 27 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 28 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 29 * "T_PVPERL". 30 */ 31 #define PCIE_T_PVPERL_MS 100 32 33 /* 34 * REFCLK stable before PERST# inactive. 35 * 36 * See the "Power Sequencing and Reset Signal Timings" table of the PCI Express 37 * Card Electromechanical Specification, Revision 5.1, Section 2.9.2, Symbol 38 * "T_PERST-CLK". 39 */ 40 #define PCIE_T_PERST_CLK_US 100 41 42 /* 43 * PCIe r6.0, sec 5.3.3.2.1 <PME Synchronization> 44 * Recommends 1ms to 10ms timeout to check L2 ready. 45 */ 46 #define PCIE_PME_TO_L2_TIMEOUT_US 10000 47 48 /* 49 * PCIe r6.0, sec 6.6.1 <Conventional Reset> 50 * 51 * - "With a Downstream Port that does not support Link speeds greater 52 * than 5.0 GT/s, software must wait a minimum of 100 ms following exit 53 * from a Conventional Reset before sending a Configuration Request to 54 * the device immediately below that Port." 55 * 56 * - "With a Downstream Port that supports Link speeds greater than 57 * 5.0 GT/s, software must wait a minimum of 100 ms after Link training 58 * completes before sending a Configuration Request to the device 59 * immediately below that Port." 60 */ 61 #define PCIE_RESET_CONFIG_WAIT_MS 100 62 63 /* Parameters for the waiting for link up routine */ 64 #define PCIE_LINK_WAIT_MAX_RETRIES 10 65 #define PCIE_LINK_WAIT_SLEEP_MS 90 66 67 /* Format of TLP; PCIe r7.0, sec 2.2.1 */ 68 #define PCIE_TLP_FMT_3DW_NO_DATA 0x00 /* 3DW header, no data */ 69 #define PCIE_TLP_FMT_4DW_NO_DATA 0x01 /* 4DW header, no data */ 70 #define PCIE_TLP_FMT_3DW_DATA 0x02 /* 3DW header, with data */ 71 #define PCIE_TLP_FMT_4DW_DATA 0x03 /* 4DW header, with data */ 72 73 /* Type of TLP; PCIe r7.0, sec 2.2.1 */ 74 #define PCIE_TLP_TYPE_CFG0_RD 0x04 /* Config Type 0 Read Request */ 75 #define PCIE_TLP_TYPE_CFG0_WR 0x04 /* Config Type 0 Write Request */ 76 #define PCIE_TLP_TYPE_CFG1_RD 0x05 /* Config Type 1 Read Request */ 77 #define PCIE_TLP_TYPE_CFG1_WR 0x05 /* Config Type 1 Write Request */ 78 79 /* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */ 80 #define PCIE_MSG_TYPE_R_RC 0 81 #define PCIE_MSG_TYPE_R_ADDR 1 82 #define PCIE_MSG_TYPE_R_ID 2 83 #define PCIE_MSG_TYPE_R_BC 3 84 #define PCIE_MSG_TYPE_R_LOCAL 4 85 #define PCIE_MSG_TYPE_R_GATHER 5 86 87 /* Power Management Messages; PCIe r6.0, sec 2.2.8.2 */ 88 #define PCIE_MSG_CODE_PME_TURN_OFF 0x19 89 90 /* INTx Mechanism Messages; PCIe r6.0, sec 2.2.8.1 */ 91 #define PCIE_MSG_CODE_ASSERT_INTA 0x20 92 #define PCIE_MSG_CODE_ASSERT_INTB 0x21 93 #define PCIE_MSG_CODE_ASSERT_INTC 0x22 94 #define PCIE_MSG_CODE_ASSERT_INTD 0x23 95 #define PCIE_MSG_CODE_DEASSERT_INTA 0x24 96 #define PCIE_MSG_CODE_DEASSERT_INTB 0x25 97 #define PCIE_MSG_CODE_DEASSERT_INTC 0x26 98 #define PCIE_MSG_CODE_DEASSERT_INTD 0x27 99 100 /* Cpl. status of Complete; PCIe r7.0, sec 2.2.9.1 */ 101 #define PCIE_CPL_STS_SUCCESS 0x00 /* Successful Completion */ 102 103 #define PCI_BUS_BRIDGE_IO_WINDOW 0 104 #define PCI_BUS_BRIDGE_MEM_WINDOW 1 105 #define PCI_BUS_BRIDGE_PREF_MEM_WINDOW 2 106 107 #define PCI_EXP_AER_FLAGS (PCI_EXP_DEVCTL_CERE | PCI_EXP_DEVCTL_NFERE | \ 108 PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE) 109 110 extern const unsigned char pcie_link_speed[]; 111 extern bool pci_early_dump; 112 113 extern struct mutex pci_rescan_remove_lock; 114 115 bool pcie_cap_has_lnkctl(const struct pci_dev *dev); 116 bool pcie_cap_has_lnkctl2(const struct pci_dev *dev); 117 bool pcie_cap_has_rtctl(const struct pci_dev *dev); 118 119 /* Standard Capability finder */ 120 /** 121 * PCI_FIND_NEXT_CAP - Find a PCI standard capability 122 * @read_cfg: Function pointer for reading PCI config space 123 * @start: Starting position to begin search 124 * @cap: Capability ID to find 125 * @prev_ptr: Pointer to store position of preceding capability (optional) 126 * @args: Arguments to pass to read_cfg function 127 * 128 * Search the capability list in PCI config space to find @cap. If 129 * found, update *prev_ptr with the position of the preceding capability 130 * (if prev_ptr != NULL) 131 * Implements TTL (time-to-live) protection against infinite loops. 132 * 133 * Return: Position of the capability if found, 0 otherwise. 134 */ 135 #define PCI_FIND_NEXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 136 ({ \ 137 int __ttl = PCI_FIND_CAP_TTL; \ 138 u8 __id, __found_pos = 0; \ 139 u8 __prev_pos = (start); \ 140 u8 __pos = (start); \ 141 u16 __ent; \ 142 \ 143 read_cfg##_byte(args, __pos, &__pos); \ 144 \ 145 while (__ttl--) { \ 146 if (__pos < PCI_STD_HEADER_SIZEOF) \ 147 break; \ 148 \ 149 __pos = ALIGN_DOWN(__pos, 4); \ 150 read_cfg##_word(args, __pos, &__ent); \ 151 \ 152 __id = FIELD_GET(PCI_CAP_ID_MASK, __ent); \ 153 if (__id == 0xff) \ 154 break; \ 155 \ 156 if (__id == (cap)) { \ 157 __found_pos = __pos; \ 158 if (prev_ptr != NULL) \ 159 *(u8 *)prev_ptr = __prev_pos; \ 160 break; \ 161 } \ 162 \ 163 __prev_pos = __pos; \ 164 __pos = FIELD_GET(PCI_CAP_LIST_NEXT_MASK, __ent); \ 165 } \ 166 __found_pos; \ 167 }) 168 169 /* Extended Capability finder */ 170 /** 171 * PCI_FIND_NEXT_EXT_CAP - Find a PCI extended capability 172 * @read_cfg: Function pointer for reading PCI config space 173 * @start: Starting position to begin search (0 for initial search) 174 * @cap: Extended capability ID to find 175 * @prev_ptr: Pointer to store position of preceding capability (optional) 176 * @args: Arguments to pass to read_cfg function 177 * 178 * Search the extended capability list in PCI config space to find @cap. 179 * If found, update *prev_ptr with the position of the preceding capability 180 * (if prev_ptr != NULL) 181 * Implements TTL protection against infinite loops using a calculated 182 * maximum search count. 183 * 184 * Return: Position of the capability if found, 0 otherwise. 185 */ 186 #define PCI_FIND_NEXT_EXT_CAP(read_cfg, start, cap, prev_ptr, args...) \ 187 ({ \ 188 u16 __pos = (start) ?: PCI_CFG_SPACE_SIZE; \ 189 u16 __found_pos = 0; \ 190 u16 __prev_pos; \ 191 int __ttl, __ret; \ 192 u32 __header; \ 193 \ 194 __prev_pos = __pos; \ 195 __ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; \ 196 while (__ttl-- > 0 && __pos >= PCI_CFG_SPACE_SIZE) { \ 197 __ret = read_cfg##_dword(args, __pos, &__header); \ 198 if (__ret != PCIBIOS_SUCCESSFUL) \ 199 break; \ 200 \ 201 if (__header == 0) \ 202 break; \ 203 \ 204 if (PCI_EXT_CAP_ID(__header) == (cap) && __pos != start) {\ 205 __found_pos = __pos; \ 206 if (prev_ptr != NULL) \ 207 *(u16 *)prev_ptr = __prev_pos; \ 208 break; \ 209 } \ 210 \ 211 __prev_pos = __pos; \ 212 __pos = PCI_EXT_CAP_NEXT(__header); \ 213 } \ 214 __found_pos; \ 215 }) 216 217 /* Functions internal to the PCI core code */ 218 219 #ifdef CONFIG_DMI 220 extern const struct attribute_group pci_dev_smbios_attr_group; 221 #endif 222 223 enum pci_mmap_api { 224 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */ 225 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */ 226 }; 227 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai, 228 enum pci_mmap_api mmap_api); 229 230 bool pci_reset_supported(struct pci_dev *dev); 231 void pci_init_reset_methods(struct pci_dev *dev); 232 int pci_bridge_secondary_bus_reset(struct pci_dev *dev); 233 int pci_bus_error_reset(struct pci_dev *dev); 234 int __pci_reset_bus(struct pci_bus *bus); 235 236 struct pci_cap_saved_data { 237 u16 cap_nr; 238 bool cap_extended; 239 unsigned int size; 240 u32 data[]; 241 }; 242 243 struct pci_cap_saved_state { 244 struct hlist_node next; 245 struct pci_cap_saved_data cap; 246 }; 247 248 void pci_allocate_cap_save_buffers(struct pci_dev *dev); 249 void pci_free_cap_save_buffers(struct pci_dev *dev); 250 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size); 251 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, 252 u16 cap, unsigned int size); 253 struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap); 254 struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, 255 u16 cap); 256 257 #define PCI_PM_D2_DELAY 200 /* usec; see PCIe r4.0, sec 5.9.1 */ 258 #define PCI_PM_D3HOT_WAIT 10 /* msec */ 259 #define PCI_PM_D3COLD_WAIT 100 /* msec */ 260 261 void pci_update_current_state(struct pci_dev *dev, pci_power_t state); 262 void pci_refresh_power_state(struct pci_dev *dev); 263 int pci_power_up(struct pci_dev *dev); 264 void pci_disable_enabled_device(struct pci_dev *dev); 265 int pci_finish_runtime_suspend(struct pci_dev *dev); 266 void pcie_clear_device_status(struct pci_dev *dev); 267 void pcie_clear_root_pme_status(struct pci_dev *dev); 268 bool pci_check_pme_status(struct pci_dev *dev); 269 void pci_pme_wakeup_bus(struct pci_bus *bus); 270 void pci_pme_restore(struct pci_dev *dev); 271 bool pci_dev_need_resume(struct pci_dev *dev); 272 void pci_dev_adjust_pme(struct pci_dev *dev); 273 void pci_dev_complete_resume(struct pci_dev *pci_dev); 274 void pci_config_pm_runtime_get(struct pci_dev *dev); 275 void pci_config_pm_runtime_put(struct pci_dev *dev); 276 void pci_pm_power_up_and_verify_state(struct pci_dev *pci_dev); 277 void pci_pm_init(struct pci_dev *dev); 278 void pci_ea_init(struct pci_dev *dev); 279 bool pci_ea_fixed_busnrs(struct pci_dev *dev, u8 *sec, u8 *sub); 280 void pci_msi_init(struct pci_dev *dev); 281 void pci_msix_init(struct pci_dev *dev); 282 bool pci_bridge_d3_possible(struct pci_dev *dev); 283 void pci_bridge_d3_update(struct pci_dev *dev); 284 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type); 285 286 static inline bool pci_bus_rrs_vendor_id(u32 l) 287 { 288 return (l & 0xffff) == PCI_VENDOR_ID_PCI_SIG; 289 } 290 291 static inline void pci_wakeup_event(struct pci_dev *dev) 292 { 293 /* Wait 100 ms before the system can be put into a sleep state. */ 294 pm_wakeup_event(&dev->dev, 100); 295 } 296 297 /** 298 * pci_bar_index_is_valid - Check whether a BAR index is within valid range 299 * @bar: BAR index 300 * 301 * Protects against overflowing &struct pci_dev.resource array. 302 * 303 * Return: true for valid index, false otherwise. 304 */ 305 static inline bool pci_bar_index_is_valid(int bar) 306 { 307 if (bar >= 0 && bar < PCI_NUM_RESOURCES) 308 return true; 309 310 return false; 311 } 312 313 static inline bool pci_has_subordinate(struct pci_dev *pci_dev) 314 { 315 return !!(pci_dev->subordinate); 316 } 317 318 static inline bool pci_power_manageable(struct pci_dev *pci_dev) 319 { 320 /* 321 * Currently we allow normal PCI devices and PCI bridges transition 322 * into D3 if their bridge_d3 is set. 323 */ 324 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3; 325 } 326 327 static inline bool pcie_downstream_port(const struct pci_dev *dev) 328 { 329 int type = pci_pcie_type(dev); 330 331 return type == PCI_EXP_TYPE_ROOT_PORT || 332 type == PCI_EXP_TYPE_DOWNSTREAM || 333 type == PCI_EXP_TYPE_PCIE_BRIDGE; 334 } 335 336 void pci_vpd_init(struct pci_dev *dev); 337 extern const struct attribute_group pci_dev_vpd_attr_group; 338 339 /* PCI Virtual Channel */ 340 int pci_save_vc_state(struct pci_dev *dev); 341 void pci_restore_vc_state(struct pci_dev *dev); 342 void pci_allocate_vc_save_buffers(struct pci_dev *dev); 343 344 /* PCI /proc functions */ 345 #ifdef CONFIG_PROC_FS 346 int pci_proc_attach_device(struct pci_dev *dev); 347 int pci_proc_detach_device(struct pci_dev *dev); 348 int pci_proc_detach_bus(struct pci_bus *bus); 349 #else 350 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; } 351 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; } 352 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; } 353 #endif 354 355 /* Functions for PCI Hotplug drivers to use */ 356 int pci_hp_add_bridge(struct pci_dev *dev); 357 bool pci_hp_spurious_link_change(struct pci_dev *pdev); 358 359 #if defined(CONFIG_SYSFS) && defined(HAVE_PCI_LEGACY) 360 void pci_create_legacy_files(struct pci_bus *bus); 361 void pci_remove_legacy_files(struct pci_bus *bus); 362 #else 363 static inline void pci_create_legacy_files(struct pci_bus *bus) { } 364 static inline void pci_remove_legacy_files(struct pci_bus *bus) { } 365 #endif 366 367 /* Lock for read/write access to pci device and bus lists */ 368 extern struct rw_semaphore pci_bus_sem; 369 extern struct mutex pci_slot_mutex; 370 371 extern raw_spinlock_t pci_lock; 372 373 extern unsigned int pci_pm_d3hot_delay; 374 375 #ifdef CONFIG_PCI_MSI 376 void pci_no_msi(void); 377 #else 378 static inline void pci_no_msi(void) { } 379 #endif 380 381 void pci_realloc_get_opt(char *); 382 383 static inline int pci_no_d1d2(struct pci_dev *dev) 384 { 385 unsigned int parent_dstates = 0; 386 387 if (dev->bus->self) 388 parent_dstates = dev->bus->self->no_d1d2; 389 return (dev->no_d1d2 || parent_dstates); 390 391 } 392 393 #ifdef CONFIG_SYSFS 394 int pci_create_sysfs_dev_files(struct pci_dev *pdev); 395 void pci_remove_sysfs_dev_files(struct pci_dev *pdev); 396 extern const struct attribute_group *pci_dev_groups[]; 397 extern const struct attribute_group *pci_dev_attr_groups[]; 398 extern const struct attribute_group *pcibus_groups[]; 399 extern const struct attribute_group *pci_bus_groups[]; 400 extern const struct attribute_group pci_doe_sysfs_group; 401 #else 402 static inline int pci_create_sysfs_dev_files(struct pci_dev *pdev) { return 0; } 403 static inline void pci_remove_sysfs_dev_files(struct pci_dev *pdev) { } 404 #define pci_dev_groups NULL 405 #define pci_dev_attr_groups NULL 406 #define pcibus_groups NULL 407 #define pci_bus_groups NULL 408 #endif 409 410 extern unsigned long pci_hotplug_io_size; 411 extern unsigned long pci_hotplug_mmio_size; 412 extern unsigned long pci_hotplug_mmio_pref_size; 413 extern unsigned long pci_hotplug_bus_size; 414 415 static inline bool pci_is_cardbus_bridge(struct pci_dev *dev) 416 { 417 return dev->hdr_type == PCI_HEADER_TYPE_CARDBUS; 418 } 419 #ifdef CONFIG_CARDBUS 420 unsigned long pci_cardbus_resource_alignment(struct resource *res); 421 int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 422 struct list_head *realloc_head); 423 int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, struct pci_dev *dev, 424 u32 buses, int max, 425 unsigned int available_buses, int pass); 426 int pci_setup_cardbus(char *str); 427 428 #else 429 static inline unsigned long pci_cardbus_resource_alignment(struct resource *res) 430 { 431 return 0; 432 } 433 static inline int pci_bus_size_cardbus_bridge(struct pci_bus *bus, 434 struct list_head *realloc_head) 435 { 436 return -EOPNOTSUPP; 437 } 438 static inline int pci_cardbus_scan_bridge_extend(struct pci_bus *bus, 439 struct pci_dev *dev, 440 u32 buses, int max, 441 unsigned int available_buses, 442 int pass) 443 { 444 return max; 445 } 446 static inline int pci_setup_cardbus(char *str) { return -ENOENT; } 447 #endif /* CONFIG_CARDBUS */ 448 449 /** 450 * pci_match_one_device - Tell if a PCI device structure has a matching 451 * PCI device id structure 452 * @id: single PCI device id structure to match 453 * @dev: the PCI device structure to match against 454 * 455 * Returns the matching pci_device_id structure or %NULL if there is no match. 456 */ 457 static inline const struct pci_device_id * 458 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev) 459 { 460 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) && 461 (id->device == PCI_ANY_ID || id->device == dev->device) && 462 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) && 463 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) && 464 !((id->class ^ dev->class) & id->class_mask)) 465 return id; 466 return NULL; 467 } 468 469 /* PCI slot sysfs helper code */ 470 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj) 471 472 extern struct kset *pci_slots_kset; 473 474 struct pci_slot_attribute { 475 struct attribute attr; 476 ssize_t (*show)(struct pci_slot *, char *); 477 ssize_t (*store)(struct pci_slot *, const char *, size_t); 478 }; 479 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr) 480 481 enum pci_bar_type { 482 pci_bar_unknown, /* Standard PCI BAR probe */ 483 pci_bar_io, /* An I/O port BAR */ 484 pci_bar_mem32, /* A 32-bit memory BAR */ 485 pci_bar_mem64, /* A 64-bit memory BAR */ 486 }; 487 488 struct device *pci_get_host_bridge_device(struct pci_dev *dev); 489 void pci_put_host_bridge_device(struct device *dev); 490 491 void pci_resize_resource_set_size(struct pci_dev *dev, int resno, int size); 492 int pci_do_resource_release_and_resize(struct pci_dev *dev, int resno, int size, 493 int exclude_bars); 494 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge); 495 int __must_check pci_reassign_resource(struct pci_dev *dev, int i, resource_size_t add_size, resource_size_t align); 496 497 int pci_configure_extended_tags(struct pci_dev *dev, void *ign); 498 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 499 int rrs_timeout); 500 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl, 501 int rrs_timeout); 502 503 int pci_setup_device(struct pci_dev *dev); 504 void __pci_size_stdbars(struct pci_dev *dev, int count, 505 unsigned int pos, u32 *sizes); 506 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type, 507 struct resource *res, unsigned int reg, u32 *sizes); 508 void pci_configure_ari(struct pci_dev *dev); 509 510 int pci_dev_res_add_to_list(struct list_head *head, struct pci_dev *dev, 511 struct resource *res, resource_size_t add_size, 512 resource_size_t min_align); 513 void __pci_bus_size_bridges(struct pci_bus *bus, 514 struct list_head *realloc_head); 515 void __pci_bus_assign_resources(const struct pci_bus *bus, 516 struct list_head *realloc_head, 517 struct list_head *fail_head); 518 bool pci_bus_clip_resource(struct pci_dev *dev, int idx); 519 void pci_walk_bus_locked(struct pci_bus *top, 520 int (*cb)(struct pci_dev *, void *), 521 void *userdata); 522 523 const char *pci_resource_name(struct pci_dev *dev, unsigned int i); 524 bool pci_resource_is_optional(const struct pci_dev *dev, int resno); 525 static inline bool pci_resource_is_bridge_win(int resno) 526 { 527 return resno >= PCI_BRIDGE_RESOURCES && 528 resno <= PCI_BRIDGE_RESOURCE_END; 529 } 530 531 /** 532 * pci_resource_num - Reverse lookup resource number from device resources 533 * @dev: PCI device 534 * @res: Resource to lookup index for (MUST be a @dev's resource) 535 * 536 * Perform reverse lookup to determine the resource number for @res within 537 * @dev resource array. NOTE: The caller is responsible for ensuring @res is 538 * among @dev's resources! 539 * 540 * Returns: resource number. 541 */ 542 static inline int pci_resource_num(const struct pci_dev *dev, 543 const struct resource *res) 544 { 545 int resno = res - &dev->resource[0]; 546 547 /* Passing a resource that is not among dev's resources? */ 548 WARN_ON_ONCE(resno >= PCI_NUM_RESOURCES); 549 550 return resno; 551 } 552 553 void pbus_validate_busn(struct pci_bus *bus); 554 struct resource *pbus_select_window(struct pci_bus *bus, 555 const struct resource *res); 556 void pci_reassigndev_resource_alignment(struct pci_dev *dev); 557 void pci_disable_bridge_window(struct pci_dev *dev); 558 struct pci_bus *pci_bus_get(struct pci_bus *bus); 559 void pci_bus_put(struct pci_bus *bus); 560 561 #define PCIE_LNKCAP_SLS2SPEED(lnkcap) \ 562 ({ \ 563 u32 lnkcap_sls = (lnkcap) & PCI_EXP_LNKCAP_SLS; \ 564 \ 565 (lnkcap_sls == PCI_EXP_LNKCAP_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 566 lnkcap_sls == PCI_EXP_LNKCAP_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 567 lnkcap_sls == PCI_EXP_LNKCAP_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 568 lnkcap_sls == PCI_EXP_LNKCAP_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 569 lnkcap_sls == PCI_EXP_LNKCAP_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 570 lnkcap_sls == PCI_EXP_LNKCAP_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 571 PCI_SPEED_UNKNOWN); \ 572 }) 573 574 /* PCIe link information from Link Capabilities 2 */ 575 #define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \ 576 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_64_0GB ? PCIE_SPEED_64_0GT : \ 577 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \ 578 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \ 579 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \ 580 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \ 581 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \ 582 PCI_SPEED_UNKNOWN) 583 584 #define PCIE_LNKCTL2_TLS2SPEED(lnkctl2) \ 585 ({ \ 586 u16 lnkctl2_tls = (lnkctl2) & PCI_EXP_LNKCTL2_TLS; \ 587 \ 588 (lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_64_0GT ? PCIE_SPEED_64_0GT : \ 589 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_32_0GT ? PCIE_SPEED_32_0GT : \ 590 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_16_0GT ? PCIE_SPEED_16_0GT : \ 591 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_8_0GT ? PCIE_SPEED_8_0GT : \ 592 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_5_0GT ? PCIE_SPEED_5_0GT : \ 593 lnkctl2_tls == PCI_EXP_LNKCTL2_TLS_2_5GT ? PCIE_SPEED_2_5GT : \ 594 PCI_SPEED_UNKNOWN); \ 595 }) 596 597 /* PCIe speed to Mb/s reduced by encoding overhead */ 598 #define PCIE_SPEED2MBS_ENC(speed) \ 599 ((speed) == PCIE_SPEED_64_0GT ? 64000*1/1 : \ 600 (speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \ 601 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \ 602 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \ 603 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \ 604 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \ 605 0) 606 607 static inline int pcie_dev_speed_mbps(enum pci_bus_speed speed) 608 { 609 switch (speed) { 610 case PCIE_SPEED_2_5GT: 611 return 2500; 612 case PCIE_SPEED_5_0GT: 613 return 5000; 614 case PCIE_SPEED_8_0GT: 615 return 8000; 616 case PCIE_SPEED_16_0GT: 617 return 16000; 618 case PCIE_SPEED_32_0GT: 619 return 32000; 620 case PCIE_SPEED_64_0GT: 621 return 64000; 622 default: 623 break; 624 } 625 626 return -EINVAL; 627 } 628 629 u8 pcie_get_supported_speeds(struct pci_dev *dev); 630 const char *pci_speed_string(enum pci_bus_speed speed); 631 void __pcie_print_link_status(struct pci_dev *dev, bool verbose); 632 void pcie_report_downtraining(struct pci_dev *dev); 633 634 enum pcie_link_change_reason { 635 PCIE_LINK_RETRAIN, 636 PCIE_ADD_BUS, 637 PCIE_BWCTRL_ENABLE, 638 PCIE_BWCTRL_IRQ, 639 PCIE_HOTPLUG, 640 }; 641 642 static inline void __pcie_update_link_speed(struct pci_bus *bus, 643 enum pcie_link_change_reason reason, 644 u16 linksta, u16 linksta2) 645 { 646 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS]; 647 bus->flit_mode = (linksta2 & PCI_EXP_LNKSTA2_FLIT) ? 1 : 0; 648 649 trace_pcie_link_event(bus, 650 reason, 651 FIELD_GET(PCI_EXP_LNKSTA_NLW, linksta), 652 linksta & PCI_EXP_LNKSTA_LINK_STATUS_MASK); 653 } 654 655 void pcie_update_link_speed(struct pci_bus *bus, enum pcie_link_change_reason reason); 656 657 /* Single Root I/O Virtualization */ 658 struct pci_sriov { 659 int pos; /* Capability position */ 660 int nres; /* Number of resources */ 661 u32 cap; /* SR-IOV Capabilities */ 662 u16 ctrl; /* SR-IOV Control */ 663 u16 total_VFs; /* Total VFs associated with the PF */ 664 u16 initial_VFs; /* Initial VFs associated with the PF */ 665 u16 num_VFs; /* Number of VFs available */ 666 u16 offset; /* First VF Routing ID offset */ 667 u16 stride; /* Following VF stride */ 668 u16 vf_device; /* VF device ID */ 669 u32 pgsz; /* Page size for BAR alignment */ 670 u8 link; /* Function Dependency Link */ 671 u8 max_VF_buses; /* Max buses consumed by VFs */ 672 u16 driver_max_VFs; /* Max num VFs driver supports */ 673 struct pci_dev *dev; /* Lowest numbered PF */ 674 struct pci_dev *self; /* This PF */ 675 u32 class; /* VF device */ 676 u8 hdr_type; /* VF header type */ 677 u16 subsystem_vendor; /* VF subsystem vendor */ 678 u16 subsystem_device; /* VF subsystem device */ 679 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */ 680 u16 vf_rebar_cap; /* VF Resizable BAR capability offset */ 681 bool drivers_autoprobe; /* Auto probing of VFs by driver */ 682 }; 683 684 #ifdef CONFIG_PCI_DOE 685 void pci_doe_init(struct pci_dev *pdev); 686 void pci_doe_destroy(struct pci_dev *pdev); 687 void pci_doe_disconnected(struct pci_dev *pdev); 688 #else 689 static inline void pci_doe_init(struct pci_dev *pdev) { } 690 static inline void pci_doe_destroy(struct pci_dev *pdev) { } 691 static inline void pci_doe_disconnected(struct pci_dev *pdev) { } 692 #endif 693 694 #ifdef CONFIG_PCI_NPEM 695 void pci_npem_create(struct pci_dev *dev); 696 void pci_npem_remove(struct pci_dev *dev); 697 #else 698 static inline void pci_npem_create(struct pci_dev *dev) { } 699 static inline void pci_npem_remove(struct pci_dev *dev) { } 700 #endif 701 702 #if defined(CONFIG_PCI_DOE) && defined(CONFIG_SYSFS) 703 void pci_doe_sysfs_init(struct pci_dev *pci_dev); 704 void pci_doe_sysfs_teardown(struct pci_dev *pdev); 705 #else 706 static inline void pci_doe_sysfs_init(struct pci_dev *pdev) { } 707 static inline void pci_doe_sysfs_teardown(struct pci_dev *pdev) { } 708 #endif 709 710 #ifdef CONFIG_PCI_IDE 711 void pci_ide_init(struct pci_dev *dev); 712 void pci_ide_init_host_bridge(struct pci_host_bridge *hb); 713 void pci_ide_destroy(struct pci_dev *dev); 714 extern const struct attribute_group pci_ide_attr_group; 715 #else 716 static inline void pci_ide_init(struct pci_dev *dev) { } 717 static inline void pci_ide_init_host_bridge(struct pci_host_bridge *hb) { } 718 static inline void pci_ide_destroy(struct pci_dev *dev) { } 719 #endif 720 721 #ifdef CONFIG_PCI_TSM 722 void pci_tsm_init(struct pci_dev *pdev); 723 void pci_tsm_destroy(struct pci_dev *pdev); 724 extern const struct attribute_group pci_tsm_attr_group; 725 extern const struct attribute_group pci_tsm_auth_attr_group; 726 #else 727 static inline void pci_tsm_init(struct pci_dev *pdev) { } 728 static inline void pci_tsm_destroy(struct pci_dev *pdev) { } 729 #endif 730 731 /** 732 * pci_dev_set_io_state - Set the new error state if possible. 733 * 734 * @dev: PCI device to set new error_state 735 * @new: the state we want dev to be in 736 * 737 * If the device is experiencing perm_failure, it has to remain in that state. 738 * Any other transition is allowed. 739 * 740 * Returns true if state has been changed to the requested state. 741 */ 742 static inline bool pci_dev_set_io_state(struct pci_dev *dev, 743 pci_channel_state_t new) 744 { 745 pci_channel_state_t old; 746 747 switch (new) { 748 case pci_channel_io_perm_failure: 749 xchg(&dev->error_state, pci_channel_io_perm_failure); 750 return true; 751 case pci_channel_io_frozen: 752 old = cmpxchg(&dev->error_state, pci_channel_io_normal, 753 pci_channel_io_frozen); 754 return old != pci_channel_io_perm_failure; 755 case pci_channel_io_normal: 756 old = cmpxchg(&dev->error_state, pci_channel_io_frozen, 757 pci_channel_io_normal); 758 return old != pci_channel_io_perm_failure; 759 default: 760 return false; 761 } 762 } 763 764 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused) 765 { 766 pci_dev_set_io_state(dev, pci_channel_io_perm_failure); 767 pci_doe_disconnected(dev); 768 769 return 0; 770 } 771 772 /* pci_dev priv_flags */ 773 #define PCI_DEV_ADDED 0 774 #define PCI_DPC_RECOVERED 1 775 #define PCI_DPC_RECOVERING 2 776 #define PCI_DEV_REMOVED 3 777 #define PCI_LINK_CHANGED 4 778 #define PCI_LINK_CHANGING 5 779 #define PCI_LINK_LBMS_SEEN 6 780 #define PCI_DEV_ALLOW_BINDING 7 781 782 static inline void pci_dev_assign_added(struct pci_dev *dev) 783 { 784 smp_mb__before_atomic(); 785 set_bit(PCI_DEV_ADDED, &dev->priv_flags); 786 smp_mb__after_atomic(); 787 } 788 789 static inline bool pci_dev_test_and_clear_added(struct pci_dev *dev) 790 { 791 return test_and_clear_bit(PCI_DEV_ADDED, &dev->priv_flags); 792 } 793 794 static inline bool pci_dev_is_added(const struct pci_dev *dev) 795 { 796 return test_bit(PCI_DEV_ADDED, &dev->priv_flags); 797 } 798 799 static inline bool pci_dev_test_and_set_removed(struct pci_dev *dev) 800 { 801 return test_and_set_bit(PCI_DEV_REMOVED, &dev->priv_flags); 802 } 803 804 static inline void pci_dev_allow_binding(struct pci_dev *dev) 805 { 806 set_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 807 } 808 809 static inline bool pci_dev_binding_disallowed(struct pci_dev *dev) 810 { 811 return !test_bit(PCI_DEV_ALLOW_BINDING, &dev->priv_flags); 812 } 813 814 #ifdef CONFIG_PCIEAER 815 #include <linux/aer.h> 816 817 #define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */ 818 819 /** 820 * struct aer_err_info - AER Error Information 821 * @dev: Devices reporting error 822 * @ratelimit_print: Flag to log or not log the devices' error. 0=NotLog/1=Log 823 * @__pad1: Padding for alignment 824 * @error_dev_num: Number of devices reporting an error 825 * @level: printk level to use in logging 826 * @id: Value from register PCI_ERR_ROOT_ERR_SRC 827 * @severity: AER severity, 0-UNCOR Non-fatal, 1-UNCOR fatal, 2-COR 828 * @root_ratelimit_print: Flag to log or not log the root's error. 0=NotLog/1=Log 829 * @multi_error_valid: If multiple errors are reported 830 * @first_error: First reported error 831 * @__pad2: Padding for alignment 832 * @is_cxl: Bus type error: 0-PCI Bus error, 1-CXL Bus error 833 * @tlp_header_valid: Indicates if TLP field contains error information 834 * @status: COR/UNCOR error status 835 * @mask: COR/UNCOR mask 836 * @tlp: Transaction packet information 837 */ 838 struct aer_err_info { 839 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES]; 840 int ratelimit_print[AER_MAX_MULTI_ERR_DEVICES]; 841 int error_dev_num; 842 const char *level; 843 844 unsigned int id:16; 845 846 unsigned int severity:2; 847 unsigned int root_ratelimit_print:1; 848 unsigned int __pad1:4; 849 unsigned int multi_error_valid:1; 850 851 unsigned int first_error:5; 852 unsigned int __pad2:1; 853 unsigned int is_cxl:1; 854 unsigned int tlp_header_valid:1; 855 856 unsigned int status; 857 unsigned int mask; 858 struct pcie_tlp_log tlp; 859 }; 860 861 int aer_get_device_error_info(struct aer_err_info *info, int i); 862 void aer_print_error(struct aer_err_info *info, int i); 863 864 static inline const char *aer_err_bus(struct aer_err_info *info) 865 { 866 return info->is_cxl ? "CXL" : "PCIe"; 867 } 868 869 int pcie_read_tlp_log(struct pci_dev *dev, int where, int where2, 870 unsigned int tlp_len, bool flit, 871 struct pcie_tlp_log *log); 872 unsigned int aer_tlp_log_len(struct pci_dev *dev, u32 aercc); 873 void pcie_print_tlp_log(const struct pci_dev *dev, 874 const struct pcie_tlp_log *log, const char *level, 875 const char *pfx); 876 #endif /* CONFIG_PCIEAER */ 877 878 #ifdef CONFIG_PCIEPORTBUS 879 /* Cached RCEC Endpoint Association */ 880 struct rcec_ea { 881 u8 nextbusn; 882 u8 lastbusn; 883 u32 bitmap; 884 }; 885 #endif 886 887 #ifdef CONFIG_PCIE_DPC 888 void pci_save_dpc_state(struct pci_dev *dev); 889 void pci_restore_dpc_state(struct pci_dev *dev); 890 void pci_dpc_init(struct pci_dev *pdev); 891 void dpc_process_error(struct pci_dev *pdev); 892 pci_ers_result_t dpc_reset_link(struct pci_dev *pdev); 893 bool pci_dpc_recovered(struct pci_dev *pdev); 894 unsigned int dpc_tlp_log_len(struct pci_dev *dev); 895 #else 896 static inline void pci_save_dpc_state(struct pci_dev *dev) { } 897 static inline void pci_restore_dpc_state(struct pci_dev *dev) { } 898 static inline void pci_dpc_init(struct pci_dev *pdev) { } 899 static inline bool pci_dpc_recovered(struct pci_dev *pdev) { return false; } 900 #endif 901 902 #ifdef CONFIG_PCIEPORTBUS 903 void pci_rcec_init(struct pci_dev *dev); 904 void pci_rcec_exit(struct pci_dev *dev); 905 void pcie_link_rcec(struct pci_dev *rcec); 906 void pcie_walk_rcec(struct pci_dev *rcec, 907 int (*cb)(struct pci_dev *, void *), 908 void *userdata); 909 #else 910 static inline void pci_rcec_init(struct pci_dev *dev) { } 911 static inline void pci_rcec_exit(struct pci_dev *dev) { } 912 static inline void pcie_link_rcec(struct pci_dev *rcec) { } 913 static inline void pcie_walk_rcec(struct pci_dev *rcec, 914 int (*cb)(struct pci_dev *, void *), 915 void *userdata) { } 916 #endif 917 918 #ifdef CONFIG_PCI_ATS 919 /* Address Translation Service */ 920 void pci_ats_init(struct pci_dev *dev); 921 void pci_restore_ats_state(struct pci_dev *dev); 922 #else 923 static inline void pci_ats_init(struct pci_dev *d) { } 924 static inline void pci_restore_ats_state(struct pci_dev *dev) { } 925 #endif /* CONFIG_PCI_ATS */ 926 927 #ifdef CONFIG_PCI_PRI 928 void pci_pri_init(struct pci_dev *dev); 929 void pci_restore_pri_state(struct pci_dev *pdev); 930 #else 931 static inline void pci_pri_init(struct pci_dev *dev) { } 932 static inline void pci_restore_pri_state(struct pci_dev *pdev) { } 933 #endif 934 935 #ifdef CONFIG_PCI_PASID 936 void pci_pasid_init(struct pci_dev *dev); 937 void pci_restore_pasid_state(struct pci_dev *pdev); 938 #else 939 static inline void pci_pasid_init(struct pci_dev *dev) { } 940 static inline void pci_restore_pasid_state(struct pci_dev *pdev) { } 941 #endif 942 943 #ifdef CONFIG_PCI_IOV 944 int pci_iov_init(struct pci_dev *dev); 945 void pci_iov_release(struct pci_dev *dev); 946 void pci_iov_remove(struct pci_dev *dev); 947 void pci_iov_update_resource(struct pci_dev *dev, int resno); 948 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno); 949 void pci_restore_iov_state(struct pci_dev *dev); 950 int pci_iov_bus_range(struct pci_bus *bus); 951 void pci_iov_resource_set_size(struct pci_dev *dev, int resno, int size); 952 bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev); 953 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 954 { 955 if (!dev->is_physfn) 956 return 0; 957 958 return dev->sriov->vf_rebar_cap; 959 } 960 static inline bool pci_resource_is_iov(int resno) 961 { 962 return resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END; 963 } 964 static inline int pci_resource_num_from_vf_bar(int resno) 965 { 966 return resno + PCI_IOV_RESOURCES; 967 } 968 static inline int pci_resource_num_to_vf_bar(int resno) 969 { 970 return resno - PCI_IOV_RESOURCES; 971 } 972 extern const struct attribute_group sriov_pf_dev_attr_group; 973 extern const struct attribute_group sriov_vf_dev_attr_group; 974 #else 975 static inline int pci_iov_init(struct pci_dev *dev) 976 { 977 return -ENODEV; 978 } 979 static inline void pci_iov_release(struct pci_dev *dev) { } 980 static inline void pci_iov_remove(struct pci_dev *dev) { } 981 static inline void pci_iov_update_resource(struct pci_dev *dev, int resno) { } 982 static inline resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, 983 int resno) 984 { 985 return 0; 986 } 987 static inline void pci_restore_iov_state(struct pci_dev *dev) { } 988 static inline int pci_iov_bus_range(struct pci_bus *bus) 989 { 990 return 0; 991 } 992 static inline void pci_iov_resource_set_size(struct pci_dev *dev, int resno, 993 int size) { } 994 static inline bool pci_iov_is_memory_decoding_enabled(struct pci_dev *dev) 995 { 996 return false; 997 } 998 static inline u16 pci_iov_vf_rebar_cap(struct pci_dev *dev) 999 { 1000 return 0; 1001 } 1002 static inline bool pci_resource_is_iov(int resno) 1003 { 1004 return false; 1005 } 1006 static inline int pci_resource_num_from_vf_bar(int resno) 1007 { 1008 WARN_ON_ONCE(1); 1009 return -ENODEV; 1010 } 1011 static inline int pci_resource_num_to_vf_bar(int resno) 1012 { 1013 WARN_ON_ONCE(1); 1014 return -ENODEV; 1015 } 1016 #endif /* CONFIG_PCI_IOV */ 1017 1018 #ifdef CONFIG_PCIE_TPH 1019 void pci_restore_tph_state(struct pci_dev *dev); 1020 void pci_save_tph_state(struct pci_dev *dev); 1021 void pci_no_tph(void); 1022 void pci_tph_init(struct pci_dev *dev); 1023 #else 1024 static inline void pci_restore_tph_state(struct pci_dev *dev) { } 1025 static inline void pci_save_tph_state(struct pci_dev *dev) { } 1026 static inline void pci_no_tph(void) { } 1027 static inline void pci_tph_init(struct pci_dev *dev) { } 1028 #endif 1029 1030 #ifdef CONFIG_PCIE_PTM 1031 void pci_ptm_init(struct pci_dev *dev); 1032 void pci_save_ptm_state(struct pci_dev *dev); 1033 void pci_restore_ptm_state(struct pci_dev *dev); 1034 void pci_suspend_ptm(struct pci_dev *dev); 1035 void pci_resume_ptm(struct pci_dev *dev); 1036 #else 1037 static inline void pci_ptm_init(struct pci_dev *dev) { } 1038 static inline void pci_save_ptm_state(struct pci_dev *dev) { } 1039 static inline void pci_restore_ptm_state(struct pci_dev *dev) { } 1040 static inline void pci_suspend_ptm(struct pci_dev *dev) { } 1041 static inline void pci_resume_ptm(struct pci_dev *dev) { } 1042 #endif 1043 1044 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev, 1045 struct resource *res) 1046 { 1047 int resno = pci_resource_num(dev, res); 1048 1049 if (pci_resource_is_iov(resno)) 1050 return pci_sriov_resource_alignment(dev, resno); 1051 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS) 1052 return pci_cardbus_resource_alignment(res); 1053 return resource_alignment(res); 1054 } 1055 1056 void pci_acs_init(struct pci_dev *dev); 1057 void pci_enable_acs(struct pci_dev *dev); 1058 #ifdef CONFIG_PCI_QUIRKS 1059 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags); 1060 int pci_dev_specific_enable_acs(struct pci_dev *dev); 1061 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev); 1062 void pci_disable_broken_acs_cap(struct pci_dev *pdev); 1063 int pcie_failed_link_retrain(struct pci_dev *dev); 1064 #else 1065 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev, 1066 u16 acs_flags) 1067 { 1068 return -ENOTTY; 1069 } 1070 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev) 1071 { 1072 return -ENOTTY; 1073 } 1074 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 1075 { 1076 return -ENOTTY; 1077 } 1078 static inline void pci_disable_broken_acs_cap(struct pci_dev *dev) { } 1079 static inline int pcie_failed_link_retrain(struct pci_dev *dev) 1080 { 1081 return -ENOTTY; 1082 } 1083 #endif 1084 1085 /* PCI error reporting and recovery */ 1086 pci_ers_result_t pcie_do_recovery(struct pci_dev *dev, 1087 pci_channel_state_t state, 1088 pci_ers_result_t (*reset_subordinates)(struct pci_dev *pdev)); 1089 1090 bool pcie_wait_for_link(struct pci_dev *pdev, bool active); 1091 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt); 1092 1093 /* ASPM-related functionality we need even without CONFIG_PCIEASPM */ 1094 void pci_save_ltr_state(struct pci_dev *dev); 1095 void pci_restore_ltr_state(struct pci_dev *dev); 1096 void pci_configure_aspm_l1ss(struct pci_dev *dev); 1097 void pci_save_aspm_l1ss_state(struct pci_dev *dev); 1098 void pci_restore_aspm_l1ss_state(struct pci_dev *dev); 1099 1100 #ifdef CONFIG_PCIEASPM 1101 void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap); 1102 void pcie_aspm_init_link_state(struct pci_dev *pdev); 1103 void pcie_aspm_exit_link_state(struct pci_dev *pdev); 1104 void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked); 1105 void pcie_aspm_powersave_config_link(struct pci_dev *pdev); 1106 void pci_configure_ltr(struct pci_dev *pdev); 1107 void pci_bridge_reconfigure_ltr(struct pci_dev *pdev); 1108 #else 1109 static inline void pcie_aspm_remove_cap(struct pci_dev *pdev, u32 lnkcap) { } 1110 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { } 1111 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { } 1112 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev, bool locked) { } 1113 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { } 1114 static inline void pci_configure_ltr(struct pci_dev *pdev) { } 1115 static inline void pci_bridge_reconfigure_ltr(struct pci_dev *pdev) { } 1116 #endif 1117 1118 #ifdef CONFIG_PCIE_ECRC 1119 void pcie_set_ecrc_checking(struct pci_dev *dev); 1120 void pcie_ecrc_get_policy(char *str); 1121 #else 1122 static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { } 1123 static inline void pcie_ecrc_get_policy(char *str) { } 1124 #endif 1125 1126 #ifdef CONFIG_PCIEPORTBUS 1127 void pcie_reset_lbms(struct pci_dev *port); 1128 #else 1129 static inline void pcie_reset_lbms(struct pci_dev *port) {} 1130 #endif 1131 1132 struct pci_dev_reset_methods { 1133 u16 vendor; 1134 u16 device; 1135 int (*reset)(struct pci_dev *dev, bool probe); 1136 }; 1137 1138 struct pci_reset_fn_method { 1139 int (*reset_fn)(struct pci_dev *pdev, bool probe); 1140 char *name; 1141 }; 1142 extern const struct pci_reset_fn_method pci_reset_fn_methods[]; 1143 1144 #ifdef CONFIG_PCI_QUIRKS 1145 int pci_dev_specific_reset(struct pci_dev *dev, bool probe); 1146 #else 1147 static inline int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 1148 { 1149 return -ENOTTY; 1150 } 1151 #endif 1152 1153 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64) 1154 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment, 1155 struct resource *res); 1156 #else 1157 static inline int acpi_get_rc_resources(struct device *dev, const char *hid, 1158 u16 segment, struct resource *res) 1159 { 1160 return -ENODEV; 1161 } 1162 #endif 1163 1164 void pci_rebar_init(struct pci_dev *pdev); 1165 void pci_restore_rebar_state(struct pci_dev *pdev); 1166 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar); 1167 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size); 1168 1169 struct device_node; 1170 1171 #define PCI_EQ_RESV 0xff 1172 1173 enum equalization_preset_type { 1174 EQ_PRESET_TYPE_8GTS, 1175 EQ_PRESET_TYPE_16GTS, 1176 EQ_PRESET_TYPE_32GTS, 1177 EQ_PRESET_TYPE_64GTS, 1178 EQ_PRESET_TYPE_MAX 1179 }; 1180 1181 struct pci_eq_presets { 1182 u16 eq_presets_8gts[MAX_NR_LANES]; 1183 u8 eq_presets_Ngts[EQ_PRESET_TYPE_MAX - 1][MAX_NR_LANES]; 1184 }; 1185 1186 #ifdef CONFIG_OF 1187 int of_get_pci_domain_nr(struct device_node *node); 1188 int of_pci_get_max_link_speed(struct device_node *node); 1189 u32 of_pci_get_slot_power_limit(struct device_node *node, 1190 u8 *slot_power_limit_value, 1191 u8 *slot_power_limit_scale); 1192 bool of_pci_preserve_config(struct device_node *node); 1193 int pci_set_of_node(struct pci_dev *dev); 1194 void pci_release_of_node(struct pci_dev *dev); 1195 void pci_set_bus_of_node(struct pci_bus *bus); 1196 void pci_release_bus_of_node(struct pci_bus *bus); 1197 1198 int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge); 1199 bool of_pci_supply_present(struct device_node *np); 1200 int of_pci_get_equalization_presets(struct device *dev, 1201 struct pci_eq_presets *presets, 1202 int num_lanes); 1203 #else 1204 static inline int 1205 of_get_pci_domain_nr(struct device_node *node) 1206 { 1207 return -1; 1208 } 1209 1210 static inline int 1211 of_pci_get_max_link_speed(struct device_node *node) 1212 { 1213 return -EINVAL; 1214 } 1215 1216 static inline u32 1217 of_pci_get_slot_power_limit(struct device_node *node, 1218 u8 *slot_power_limit_value, 1219 u8 *slot_power_limit_scale) 1220 { 1221 if (slot_power_limit_value) 1222 *slot_power_limit_value = 0; 1223 if (slot_power_limit_scale) 1224 *slot_power_limit_scale = 0; 1225 return 0; 1226 } 1227 1228 static inline bool of_pci_preserve_config(struct device_node *node) 1229 { 1230 return false; 1231 } 1232 1233 static inline int pci_set_of_node(struct pci_dev *dev) { return 0; } 1234 static inline void pci_release_of_node(struct pci_dev *dev) { } 1235 static inline void pci_set_bus_of_node(struct pci_bus *bus) { } 1236 static inline void pci_release_bus_of_node(struct pci_bus *bus) { } 1237 1238 static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge) 1239 { 1240 return 0; 1241 } 1242 1243 static inline bool of_pci_supply_present(struct device_node *np) 1244 { 1245 return false; 1246 } 1247 1248 static inline int of_pci_get_equalization_presets(struct device *dev, 1249 struct pci_eq_presets *presets, 1250 int num_lanes) 1251 { 1252 presets->eq_presets_8gts[0] = PCI_EQ_RESV; 1253 for (int i = 0; i < EQ_PRESET_TYPE_MAX - 1; i++) 1254 presets->eq_presets_Ngts[i][0] = PCI_EQ_RESV; 1255 1256 return 0; 1257 } 1258 #endif /* CONFIG_OF */ 1259 1260 struct of_changeset; 1261 1262 #ifdef CONFIG_PCI_DYNAMIC_OF_NODES 1263 void of_pci_make_dev_node(struct pci_dev *pdev); 1264 void of_pci_remove_node(struct pci_dev *pdev); 1265 int of_pci_add_properties(struct pci_dev *pdev, struct of_changeset *ocs, 1266 struct device_node *np); 1267 void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge); 1268 void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge); 1269 int of_pci_add_host_bridge_properties(struct pci_host_bridge *bridge, 1270 struct of_changeset *ocs, 1271 struct device_node *np); 1272 #else 1273 static inline void of_pci_make_dev_node(struct pci_dev *pdev) { } 1274 static inline void of_pci_remove_node(struct pci_dev *pdev) { } 1275 static inline void of_pci_make_host_bridge_node(struct pci_host_bridge *bridge) { } 1276 static inline void of_pci_remove_host_bridge_node(struct pci_host_bridge *bridge) { } 1277 #endif 1278 1279 #ifdef CONFIG_PCIEAER 1280 void pci_no_aer(void); 1281 void pci_aer_init(struct pci_dev *dev); 1282 void pci_aer_exit(struct pci_dev *dev); 1283 extern const struct attribute_group aer_stats_attr_group; 1284 extern const struct attribute_group aer_attr_group; 1285 void pci_aer_clear_fatal_status(struct pci_dev *dev); 1286 int pci_aer_clear_status(struct pci_dev *dev); 1287 int pci_aer_raw_clear_status(struct pci_dev *dev); 1288 void pci_save_aer_state(struct pci_dev *dev); 1289 void pci_restore_aer_state(struct pci_dev *dev); 1290 #else 1291 static inline void pci_no_aer(void) { } 1292 static inline void pci_aer_init(struct pci_dev *d) { } 1293 static inline void pci_aer_exit(struct pci_dev *d) { } 1294 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { } 1295 static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; } 1296 static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; } 1297 static inline void pci_save_aer_state(struct pci_dev *dev) { } 1298 static inline void pci_restore_aer_state(struct pci_dev *dev) { } 1299 #endif 1300 1301 #ifdef CONFIG_ACPI 1302 bool pci_acpi_preserve_config(struct pci_host_bridge *bridge); 1303 int pci_acpi_program_hp_params(struct pci_dev *dev); 1304 extern const struct attribute_group pci_dev_acpi_attr_group; 1305 void pci_set_acpi_fwnode(struct pci_dev *dev); 1306 int pci_dev_acpi_reset(struct pci_dev *dev, bool probe); 1307 bool acpi_pci_power_manageable(struct pci_dev *dev); 1308 bool acpi_pci_bridge_d3(struct pci_dev *dev); 1309 int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state); 1310 pci_power_t acpi_pci_get_power_state(struct pci_dev *dev); 1311 void acpi_pci_refresh_power_state(struct pci_dev *dev); 1312 int acpi_pci_wakeup(struct pci_dev *dev, bool enable); 1313 bool acpi_pci_need_resume(struct pci_dev *dev); 1314 pci_power_t acpi_pci_choose_state(struct pci_dev *pdev); 1315 #else 1316 static inline bool pci_acpi_preserve_config(struct pci_host_bridge *bridge) 1317 { 1318 return false; 1319 } 1320 static inline int pci_dev_acpi_reset(struct pci_dev *dev, bool probe) 1321 { 1322 return -ENOTTY; 1323 } 1324 static inline void pci_set_acpi_fwnode(struct pci_dev *dev) { } 1325 static inline int pci_acpi_program_hp_params(struct pci_dev *dev) 1326 { 1327 return -ENODEV; 1328 } 1329 static inline bool acpi_pci_power_manageable(struct pci_dev *dev) 1330 { 1331 return false; 1332 } 1333 static inline bool acpi_pci_bridge_d3(struct pci_dev *dev) 1334 { 1335 return false; 1336 } 1337 static inline int acpi_pci_set_power_state(struct pci_dev *dev, pci_power_t state) 1338 { 1339 return -ENODEV; 1340 } 1341 static inline pci_power_t acpi_pci_get_power_state(struct pci_dev *dev) 1342 { 1343 return PCI_UNKNOWN; 1344 } 1345 static inline void acpi_pci_refresh_power_state(struct pci_dev *dev) { } 1346 static inline int acpi_pci_wakeup(struct pci_dev *dev, bool enable) 1347 { 1348 return -ENODEV; 1349 } 1350 static inline bool acpi_pci_need_resume(struct pci_dev *dev) 1351 { 1352 return false; 1353 } 1354 static inline pci_power_t acpi_pci_choose_state(struct pci_dev *pdev) 1355 { 1356 return PCI_POWER_ERROR; 1357 } 1358 #endif 1359 1360 #ifdef CONFIG_PCIEASPM 1361 extern const struct attribute_group aspm_ctrl_attr_group; 1362 #endif 1363 1364 #ifdef CONFIG_X86_INTEL_MID 1365 bool pci_use_mid_pm(void); 1366 int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); 1367 pci_power_t mid_pci_get_power_state(struct pci_dev *pdev); 1368 #else 1369 static inline bool pci_use_mid_pm(void) 1370 { 1371 return false; 1372 } 1373 static inline int mid_pci_set_power_state(struct pci_dev *pdev, pci_power_t state) 1374 { 1375 return -ENODEV; 1376 } 1377 static inline pci_power_t mid_pci_get_power_state(struct pci_dev *pdev) 1378 { 1379 return PCI_UNKNOWN; 1380 } 1381 #endif 1382 1383 #ifdef CONFIG_PCI_MSI 1384 int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag); 1385 #else 1386 static inline int pci_msix_write_tph_tag(struct pci_dev *pdev, unsigned int index, u16 tag) 1387 { 1388 return -ENODEV; 1389 } 1390 #endif 1391 1392 /* 1393 * Config Address for PCI Configuration Mechanism #1 1394 * 1395 * See PCI Local Bus Specification, Revision 3.0, 1396 * Section 3.2.2.3.2, Figure 3-2, p. 50. 1397 */ 1398 1399 #define PCI_CONF1_BUS_SHIFT 16 /* Bus number */ 1400 #define PCI_CONF1_DEV_SHIFT 11 /* Device number */ 1401 #define PCI_CONF1_FUNC_SHIFT 8 /* Function number */ 1402 1403 #define PCI_CONF1_BUS_MASK 0xff 1404 #define PCI_CONF1_DEV_MASK 0x1f 1405 #define PCI_CONF1_FUNC_MASK 0x7 1406 #define PCI_CONF1_REG_MASK 0xfc /* Limit aligned offset to a maximum of 256B */ 1407 1408 #define PCI_CONF1_ENABLE BIT(31) 1409 #define PCI_CONF1_BUS(x) (((x) & PCI_CONF1_BUS_MASK) << PCI_CONF1_BUS_SHIFT) 1410 #define PCI_CONF1_DEV(x) (((x) & PCI_CONF1_DEV_MASK) << PCI_CONF1_DEV_SHIFT) 1411 #define PCI_CONF1_FUNC(x) (((x) & PCI_CONF1_FUNC_MASK) << PCI_CONF1_FUNC_SHIFT) 1412 #define PCI_CONF1_REG(x) ((x) & PCI_CONF1_REG_MASK) 1413 1414 #define PCI_CONF1_ADDRESS(bus, dev, func, reg) \ 1415 (PCI_CONF1_ENABLE | \ 1416 PCI_CONF1_BUS(bus) | \ 1417 PCI_CONF1_DEV(dev) | \ 1418 PCI_CONF1_FUNC(func) | \ 1419 PCI_CONF1_REG(reg)) 1420 1421 /* 1422 * Extension of PCI Config Address for accessing extended PCIe registers 1423 * 1424 * No standardized specification, but used on lot of non-ECAM-compliant ARM SoCs 1425 * or on AMD Barcelona and new CPUs. Reserved bits [27:24] of PCI Config Address 1426 * are used for specifying additional 4 high bits of PCI Express register. 1427 */ 1428 1429 #define PCI_CONF1_EXT_REG_SHIFT 16 1430 #define PCI_CONF1_EXT_REG_MASK 0xf00 1431 #define PCI_CONF1_EXT_REG(x) (((x) & PCI_CONF1_EXT_REG_MASK) << PCI_CONF1_EXT_REG_SHIFT) 1432 1433 #define PCI_CONF1_EXT_ADDRESS(bus, dev, func, reg) \ 1434 (PCI_CONF1_ADDRESS(bus, dev, func, reg) | \ 1435 PCI_CONF1_EXT_REG(reg)) 1436 1437 #endif /* DRIVERS_PCI_H */ 1438