xref: /linux/drivers/net/ethernet/airoha/airoha_regs.h (revision 87320be9f0d24fce67631b7eef919f0b79c3e45c)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2024 AIROHA Inc
4  * Author: Lorenzo Bianconi <lorenzo@kernel.org>
5  */
6 
7 #ifndef AIROHA_REGS_H
8 #define AIROHA_REGS_H
9 
10 #include <linux/types.h>
11 
12 /* FE */
13 #define PSE_BASE			0x0100
14 #define CSR_IFC_BASE			0x0200
15 #define CDM1_BASE			0x0400
16 #define GDM1_BASE			0x0500
17 #define PPE1_BASE			0x0c00
18 #define PPE2_BASE			0x1c00
19 
20 #define CDM2_BASE			0x1400
21 #define GDM2_BASE			0x1500
22 
23 #define GDM3_BASE			0x1100
24 #define GDM4_BASE			0x2500
25 
26 #define CDM_BASE(_n)			\
27 	((_n) == 2 ? CDM2_BASE : CDM1_BASE)
28 #define GDM_BASE(_n)			\
29 	((_n) == 4 ? GDM4_BASE :	\
30 	 (_n) == 3 ? GDM3_BASE :	\
31 	 (_n) == 2 ? GDM2_BASE : GDM1_BASE)
32 
33 #define REG_FE_DMA_GLO_CFG		0x0000
34 #define FE_DMA_GLO_L2_SPACE_MASK	GENMASK(7, 4)
35 #define FE_DMA_GLO_PG_SZ_MASK		BIT(3)
36 
37 #define REG_FE_RST_GLO_CFG		0x0004
38 #define FE_RST_GDM4_MBI_ARB_MASK	BIT(3)
39 #define FE_RST_GDM3_MBI_ARB_MASK	BIT(2)
40 #define FE_RST_CORE_MASK		BIT(0)
41 
42 #define REG_FE_FOE_TS			0x0010
43 
44 #define REG_FE_WAN_PORT			0x0024
45 #define WAN1_EN_MASK			BIT(16)
46 #define WAN1_MASK			GENMASK(12, 8)
47 #define WAN0_MASK			GENMASK(4, 0)
48 
49 #define REG_FE_WAN_MAC_H		0x0030
50 #define REG_FE_LAN_MAC_H		0x0040
51 
52 #define REG_FE_MAC_LMIN(_n)		((_n) + 0x04)
53 #define REG_FE_MAC_LMAX(_n)		((_n) + 0x08)
54 
55 #define REG_FE_CDM1_OQ_MAP0		0x0050
56 #define REG_FE_CDM1_OQ_MAP1		0x0054
57 #define REG_FE_CDM1_OQ_MAP2		0x0058
58 #define REG_FE_CDM1_OQ_MAP3		0x005c
59 
60 #define REG_FE_PCE_CFG			0x0070
61 #define PCE_DPI_EN_MASK			BIT(2)
62 #define PCE_KA_EN_MASK			BIT(1)
63 #define PCE_MC_EN_MASK			BIT(0)
64 
65 #define REG_FE_PSE_QUEUE_CFG_WR		0x0080
66 #define PSE_CFG_PORT_ID_MASK		GENMASK(27, 24)
67 #define PSE_CFG_QUEUE_ID_MASK		GENMASK(20, 16)
68 #define PSE_CFG_WR_EN_MASK		BIT(8)
69 #define PSE_CFG_OQRSV_SEL_MASK		BIT(0)
70 
71 #define REG_FE_PSE_QUEUE_CFG_VAL	0x0084
72 #define PSE_CFG_OQ_RSV_MASK		GENMASK(13, 0)
73 
74 #define PSE_FQ_CFG			0x008c
75 #define PSE_FQ_LIMIT_MASK		GENMASK(14, 0)
76 
77 #define REG_FE_PSE_BUF_SET		0x0090
78 #define PSE_SHARE_USED_LTHD_MASK	GENMASK(31, 16)
79 #define PSE_ALLRSV_MASK			GENMASK(14, 0)
80 
81 #define REG_PSE_SHARE_USED_THD		0x0094
82 #define PSE_SHARE_USED_MTHD_MASK	GENMASK(31, 16)
83 #define PSE_SHARE_USED_HTHD_MASK	GENMASK(15, 0)
84 
85 #define REG_GDM_MISC_CFG		0x0148
86 #define GDM2_RDM_ACK_WAIT_PREF_MASK	BIT(9)
87 #define GDM2_CHN_VLD_MODE_MASK		BIT(5)
88 
89 #define REG_FE_CSR_IFC_CFG		CSR_IFC_BASE
90 #define FE_IFC_EN_MASK			BIT(0)
91 
92 #define REG_FE_VIP_PORT_EN		0x01f0
93 #define REG_FE_IFC_PORT_EN		0x01f4
94 
95 #define REG_PSE_IQ_REV1			(PSE_BASE + 0x08)
96 #define PSE_IQ_RES1_P2_MASK		GENMASK(23, 16)
97 
98 #define REG_PSE_IQ_REV2			(PSE_BASE + 0x0c)
99 #define PSE_IQ_RES2_P5_MASK		GENMASK(15, 8)
100 #define PSE_IQ_RES2_P4_MASK		GENMASK(7, 0)
101 
102 #define REG_FE_VIP_EN(_n)		(0x0300 + ((_n) << 3))
103 #define PATN_FCPU_EN_MASK		BIT(7)
104 #define PATN_SWP_EN_MASK		BIT(6)
105 #define PATN_DP_EN_MASK			BIT(5)
106 #define PATN_SP_EN_MASK			BIT(4)
107 #define PATN_TYPE_MASK			GENMASK(3, 1)
108 #define PATN_EN_MASK			BIT(0)
109 
110 #define REG_FE_VIP_PATN(_n)		(0x0304 + ((_n) << 3))
111 #define PATN_DP_MASK			GENMASK(31, 16)
112 #define PATN_SP_MASK			GENMASK(15, 0)
113 
114 #define REG_CDM_VLAN_CTRL(_n)		CDM_BASE(_n)
115 #define CDM_VLAN_MASK			GENMASK(31, 16)
116 
117 #define REG_CDM_FWD_CFG(_n)		(CDM_BASE(_n) + 0x08)
118 #define CDM_OAM_QSEL_MASK		GENMASK(31, 27)
119 #define CDM_VIP_QSEL_MASK		GENMASK(24, 20)
120 
121 #define REG_CDM_CRSN_QSEL(_n, _m)	(CDM_BASE(_n) + 0x10 + ((_m) << 2))
122 #define CDM_CRSN_QSEL_REASON_MASK(_n)	\
123 	GENMASK(4 + (((_n) % 4) << 3),	(((_n) % 4) << 3))
124 
125 #define REG_GDM_FWD_CFG(_n)		GDM_BASE(_n)
126 #define GDM_PAD_EN_MASK			BIT(28)
127 #define GDM_DROP_CRC_ERR_MASK		BIT(23)
128 #define GDM_IP4_CKSUM_MASK		BIT(22)
129 #define GDM_TCP_CKSUM_MASK		BIT(21)
130 #define GDM_UDP_CKSUM_MASK		BIT(20)
131 #define GDM_STRIP_CRC_MASK		BIT(16)
132 #define GDM_UCFQ_MASK			GENMASK(15, 12)
133 #define GDM_BCFQ_MASK			GENMASK(11, 8)
134 #define GDM_MCFQ_MASK			GENMASK(7, 4)
135 #define GDM_OCFQ_MASK			GENMASK(3, 0)
136 
137 #define REG_GDM_INGRESS_CFG(_n)		(GDM_BASE(_n) + 0x10)
138 #define GDM_INGRESS_FC_EN_MASK		BIT(1)
139 #define GDM_STAG_EN_MASK		BIT(0)
140 
141 #define REG_GDM_LEN_CFG(_n)		(GDM_BASE(_n) + 0x14)
142 #define GDM_SHORT_LEN_MASK		GENMASK(13, 0)
143 #define GDM_LONG_LEN_MASK		GENMASK(29, 16)
144 
145 #define REG_GDM_LPBK_CFG(_n)		(GDM_BASE(_n) + 0x1c)
146 #define LPBK_GAP_MASK			GENMASK(31, 24)
147 #define LPBK_LEN_MASK			GENMASK(23, 10)
148 #define LPBK_CHAN_MASK			GENMASK(8, 4)
149 #define LPBK_MODE_MASK			GENMASK(3, 1)
150 #define LBK_GAP_MODE_MASK		BIT(3)
151 #define LBK_LEN_MODE_MASK		BIT(2)
152 #define LBK_CHAN_MODE_MASK		BIT(1)
153 #define LPBK_EN_MASK			BIT(0)
154 
155 #define REG_GDM_CHN_RLS(_n)		(GDM_BASE(_n) + 0x20)
156 #define MBI_RX_AGE_SEL_MASK		GENMASK(26, 25)
157 #define MBI_TX_AGE_SEL_MASK		GENMASK(18, 17)
158 
159 #define REG_GDM_TXCHN_EN(_n)		(GDM_BASE(_n) + 0x24)
160 #define REG_GDM_RXCHN_EN(_n)		(GDM_BASE(_n) + 0x28)
161 
162 #define REG_FE_CPORT_CFG		(GDM1_BASE + 0x40)
163 #define FE_CPORT_PAD			BIT(26)
164 #define FE_CPORT_PORT_XFC_MASK		BIT(25)
165 #define FE_CPORT_QUEUE_XFC_MASK		BIT(24)
166 
167 #define REG_FE_GDM_MIB_CLEAR(_n)	(GDM_BASE(_n) + 0xf0)
168 #define FE_GDM_MIB_RX_CLEAR_MASK	BIT(1)
169 #define FE_GDM_MIB_TX_CLEAR_MASK	BIT(0)
170 
171 #define REG_FE_GDM_MIB_CFG(_n)		(GDM_BASE(_n) + 0xf4)
172 #define FE_STRICT_RFC2819_MODE_MASK	BIT(31)
173 #define FE_GDM_TX_MIB_SPLIT_EN_MASK	BIT(17)
174 #define FE_GDM_RX_MIB_SPLIT_EN_MASK	BIT(16)
175 #define FE_TX_MIB_ID_MASK		GENMASK(15, 8)
176 #define FE_RX_MIB_ID_MASK		GENMASK(7, 0)
177 
178 #define REG_FE_GDM_TX_OK_PKT_CNT_L(_n)		(GDM_BASE(_n) + 0x104)
179 #define REG_FE_GDM_TX_OK_BYTE_CNT_L(_n)		(GDM_BASE(_n) + 0x10c)
180 #define REG_FE_GDM_TX_ETH_PKT_CNT_L(_n)		(GDM_BASE(_n) + 0x110)
181 #define REG_FE_GDM_TX_ETH_BYTE_CNT_L(_n)	(GDM_BASE(_n) + 0x114)
182 #define REG_FE_GDM_TX_ETH_DROP_CNT(_n)		(GDM_BASE(_n) + 0x118)
183 #define REG_FE_GDM_TX_ETH_BC_CNT(_n)		(GDM_BASE(_n) + 0x11c)
184 #define REG_FE_GDM_TX_ETH_MC_CNT(_n)		(GDM_BASE(_n) + 0x120)
185 #define REG_FE_GDM_TX_ETH_RUNT_CNT(_n)		(GDM_BASE(_n) + 0x124)
186 #define REG_FE_GDM_TX_ETH_LONG_CNT(_n)		(GDM_BASE(_n) + 0x128)
187 #define REG_FE_GDM_TX_ETH_E64_CNT_L(_n)		(GDM_BASE(_n) + 0x12c)
188 #define REG_FE_GDM_TX_ETH_L64_CNT_L(_n)		(GDM_BASE(_n) + 0x130)
189 #define REG_FE_GDM_TX_ETH_L127_CNT_L(_n)	(GDM_BASE(_n) + 0x134)
190 #define REG_FE_GDM_TX_ETH_L255_CNT_L(_n)	(GDM_BASE(_n) + 0x138)
191 #define REG_FE_GDM_TX_ETH_L511_CNT_L(_n)	(GDM_BASE(_n) + 0x13c)
192 #define REG_FE_GDM_TX_ETH_L1023_CNT_L(_n)	(GDM_BASE(_n) + 0x140)
193 
194 #define REG_FE_GDM_RX_OK_PKT_CNT_L(_n)		(GDM_BASE(_n) + 0x148)
195 #define REG_FE_GDM_RX_FC_DROP_CNT(_n)		(GDM_BASE(_n) + 0x14c)
196 #define REG_FE_GDM_RX_RC_DROP_CNT(_n)		(GDM_BASE(_n) + 0x150)
197 #define REG_FE_GDM_RX_OVERFLOW_DROP_CNT(_n)	(GDM_BASE(_n) + 0x154)
198 #define REG_FE_GDM_RX_ERROR_DROP_CNT(_n)	(GDM_BASE(_n) + 0x158)
199 #define REG_FE_GDM_RX_OK_BYTE_CNT_L(_n)		(GDM_BASE(_n) + 0x15c)
200 #define REG_FE_GDM_RX_ETH_PKT_CNT_L(_n)		(GDM_BASE(_n) + 0x160)
201 #define REG_FE_GDM_RX_ETH_BYTE_CNT_L(_n)	(GDM_BASE(_n) + 0x164)
202 #define REG_FE_GDM_RX_ETH_DROP_CNT(_n)		(GDM_BASE(_n) + 0x168)
203 #define REG_FE_GDM_RX_ETH_BC_CNT(_n)		(GDM_BASE(_n) + 0x16c)
204 #define REG_FE_GDM_RX_ETH_MC_CNT(_n)		(GDM_BASE(_n) + 0x170)
205 #define REG_FE_GDM_RX_ETH_CRC_ERR_CNT(_n)	(GDM_BASE(_n) + 0x174)
206 #define REG_FE_GDM_RX_ETH_FRAG_CNT(_n)		(GDM_BASE(_n) + 0x178)
207 #define REG_FE_GDM_RX_ETH_JABBER_CNT(_n)	(GDM_BASE(_n) + 0x17c)
208 #define REG_FE_GDM_RX_ETH_RUNT_CNT(_n)		(GDM_BASE(_n) + 0x180)
209 #define REG_FE_GDM_RX_ETH_LONG_CNT(_n)		(GDM_BASE(_n) + 0x184)
210 #define REG_FE_GDM_RX_ETH_E64_CNT_L(_n)		(GDM_BASE(_n) + 0x188)
211 #define REG_FE_GDM_RX_ETH_L64_CNT_L(_n)		(GDM_BASE(_n) + 0x18c)
212 #define REG_FE_GDM_RX_ETH_L127_CNT_L(_n)	(GDM_BASE(_n) + 0x190)
213 #define REG_FE_GDM_RX_ETH_L255_CNT_L(_n)	(GDM_BASE(_n) + 0x194)
214 #define REG_FE_GDM_RX_ETH_L511_CNT_L(_n)	(GDM_BASE(_n) + 0x198)
215 #define REG_FE_GDM_RX_ETH_L1023_CNT_L(_n)	(GDM_BASE(_n) + 0x19c)
216 
217 #define REG_GDM_SRC_PORT_SET(_n)		(GDM_BASE(_n) + 0x23c)
218 #define GDM_SPORT_OFF2_MASK			GENMASK(19, 16)
219 #define GDM_SPORT_OFF1_MASK			GENMASK(15, 12)
220 #define GDM_SPORT_OFF0_MASK			GENMASK(11, 8)
221 
222 #define REG_FE_GDM_TX_OK_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x280)
223 #define REG_FE_GDM_TX_OK_BYTE_CNT_H(_n)		(GDM_BASE(_n) + 0x284)
224 #define REG_FE_GDM_TX_ETH_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x288)
225 #define REG_FE_GDM_TX_ETH_BYTE_CNT_H(_n)	(GDM_BASE(_n) + 0x28c)
226 
227 #define REG_FE_GDM_RX_OK_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x290)
228 #define REG_FE_GDM_RX_OK_BYTE_CNT_H(_n)		(GDM_BASE(_n) + 0x294)
229 #define REG_FE_GDM_RX_ETH_PKT_CNT_H(_n)		(GDM_BASE(_n) + 0x298)
230 #define REG_FE_GDM_RX_ETH_BYTE_CNT_H(_n)	(GDM_BASE(_n) + 0x29c)
231 #define REG_FE_GDM_TX_ETH_E64_CNT_H(_n)		(GDM_BASE(_n) + 0x2b8)
232 #define REG_FE_GDM_TX_ETH_L64_CNT_H(_n)		(GDM_BASE(_n) + 0x2bc)
233 #define REG_FE_GDM_TX_ETH_L127_CNT_H(_n)	(GDM_BASE(_n) + 0x2c0)
234 #define REG_FE_GDM_TX_ETH_L255_CNT_H(_n)	(GDM_BASE(_n) + 0x2c4)
235 #define REG_FE_GDM_TX_ETH_L511_CNT_H(_n)	(GDM_BASE(_n) + 0x2c8)
236 #define REG_FE_GDM_TX_ETH_L1023_CNT_H(_n)	(GDM_BASE(_n) + 0x2cc)
237 #define REG_FE_GDM_RX_ETH_E64_CNT_H(_n)		(GDM_BASE(_n) + 0x2e8)
238 #define REG_FE_GDM_RX_ETH_L64_CNT_H(_n)		(GDM_BASE(_n) + 0x2ec)
239 #define REG_FE_GDM_RX_ETH_L127_CNT_H(_n)	(GDM_BASE(_n) + 0x2f0)
240 #define REG_FE_GDM_RX_ETH_L255_CNT_H(_n)	(GDM_BASE(_n) + 0x2f4)
241 #define REG_FE_GDM_RX_ETH_L511_CNT_H(_n)	(GDM_BASE(_n) + 0x2f8)
242 #define REG_FE_GDM_RX_ETH_L1023_CNT_H(_n)	(GDM_BASE(_n) + 0x2fc)
243 
244 #define REG_PPE_GLO_CFG(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x200)
245 #define PPE_GLO_CFG_BUSY_MASK			BIT(31)
246 #define PPE_GLO_CFG_FLOW_DROP_UPDATE_MASK	BIT(9)
247 #define PPE_GLO_CFG_PSE_HASH_OFS_MASK		BIT(6)
248 #define PPE_GLO_CFG_PPE_BSWAP_MASK		BIT(5)
249 #define PPE_GLO_CFG_TTL_DROP_MASK		BIT(4)
250 #define PPE_GLO_CFG_IP4_CS_DROP_MASK		BIT(3)
251 #define PPE_GLO_CFG_IP4_L4_CS_DROP_MASK		BIT(2)
252 #define PPE_GLO_CFG_EN_MASK			BIT(0)
253 
254 #define REG_PPE_PPE_FLOW_CFG(_n)		(((_n) ? PPE2_BASE : PPE1_BASE) + 0x204)
255 #define PPE_FLOW_CFG_IP6_HASH_GRE_KEY_MASK	BIT(20)
256 #define PPE_FLOW_CFG_IP4_HASH_GRE_KEY_MASK	BIT(19)
257 #define PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL_MASK	BIT(18)
258 #define PPE_FLOW_CFG_IP4_NAT_FRAG_MASK		BIT(17)
259 #define PPE_FLOW_CFG_IP_PROTO_BLACKLIST_MASK	BIT(16)
260 #define PPE_FLOW_CFG_IP4_DSLITE_MASK		BIT(14)
261 #define PPE_FLOW_CFG_IP4_NAPT_MASK		BIT(13)
262 #define PPE_FLOW_CFG_IP4_NAT_MASK		BIT(12)
263 #define PPE_FLOW_CFG_IP6_6RD_MASK		BIT(10)
264 #define PPE_FLOW_CFG_IP6_5T_ROUTE_MASK		BIT(9)
265 #define PPE_FLOW_CFG_IP6_3T_ROUTE_MASK		BIT(8)
266 #define PPE_FLOW_CFG_IP4_UDP_FRAG_MASK		BIT(7)
267 #define PPE_FLOW_CFG_IP4_TCP_FRAG_MASK		BIT(6)
268 
269 #define REG_PPE_IP_PROTO_CHK(_n)		(((_n) ? PPE2_BASE : PPE1_BASE) + 0x208)
270 #define PPE_IP_PROTO_CHK_IPV4_MASK		GENMASK(31, 16)
271 #define PPE_IP_PROTO_CHK_IPV6_MASK		GENMASK(15, 0)
272 
273 #define REG_PPE_TB_CFG(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x21c)
274 #define PPE_SRAM_TB_NUM_ENTRY_MASK		GENMASK(26, 24)
275 #define PPE_TB_CFG_KEEPALIVE_MASK		GENMASK(13, 12)
276 #define PPE_TB_CFG_AGE_TCP_FIN_MASK		BIT(11)
277 #define PPE_TB_CFG_AGE_UDP_MASK			BIT(10)
278 #define PPE_TB_CFG_AGE_TCP_MASK			BIT(9)
279 #define PPE_TB_CFG_AGE_UNBIND_MASK		BIT(8)
280 #define PPE_TB_CFG_AGE_NON_L4_MASK		BIT(7)
281 #define PPE_TB_CFG_AGE_PREBIND_MASK		BIT(6)
282 #define PPE_TB_CFG_SEARCH_MISS_MASK		GENMASK(5, 4)
283 #define PPE_TB_ENTRY_SIZE_MASK			BIT(3)
284 #define PPE_DRAM_TB_NUM_ENTRY_MASK		GENMASK(2, 0)
285 
286 #define REG_PPE_TB_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x220)
287 
288 #define REG_PPE_BIND_RATE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x228)
289 #define PPE_BIND_RATE_L2B_BIND_MASK		GENMASK(31, 16)
290 #define PPE_BIND_RATE_BIND_MASK			GENMASK(15, 0)
291 
292 #define REG_PPE_BIND_LIMIT0(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x22c)
293 #define PPE_BIND_LIMIT0_HALF_MASK		GENMASK(29, 16)
294 #define PPE_BIND_LIMIT0_QUARTER_MASK		GENMASK(13, 0)
295 
296 #define REG_PPE_BIND_LIMIT1(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x230)
297 #define PPE_BIND_LIMIT1_NON_L4_MASK		GENMASK(23, 16)
298 #define PPE_BIND_LIMIT1_FULL_MASK		GENMASK(13, 0)
299 
300 #define REG_PPE_BND_AGE0(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x23c)
301 #define PPE_BIND_AGE0_DELTA_NON_L4		GENMASK(30, 16)
302 #define PPE_BIND_AGE0_DELTA_UDP			GENMASK(14, 0)
303 
304 #define REG_PPE_UNBIND_AGE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x238)
305 #define PPE_UNBIND_AGE_MIN_PACKETS_MASK		GENMASK(31, 16)
306 #define PPE_UNBIND_AGE_DELTA_MASK		GENMASK(7, 0)
307 
308 #define REG_PPE_BND_AGE1(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x240)
309 #define PPE_BIND_AGE1_DELTA_TCP_FIN		GENMASK(30, 16)
310 #define PPE_BIND_AGE1_DELTA_TCP			GENMASK(14, 0)
311 
312 #define REG_PPE_HASH_SEED(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x244)
313 #define PPE_HASH_SEED				0x12345678
314 
315 #define REG_PPE_DFT_CPORT_BASE(_n)		(((_n) ? PPE2_BASE : PPE1_BASE) + 0x248)
316 #define REG_PPE_DFT_CPORT(_m, _n)		(REG_PPE_DFT_CPORT_BASE(_m) + (((_n) / 8) << 2))
317 #define DFT_CPORT_MASK(_n)			GENMASK(3 + (((_n) % 8) << 2), (((_n) % 8) << 2))
318 
319 #define REG_PPE_TB_HASH_CFG(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x250)
320 #define PPE_DRAM_HASH1_MODE_MASK		GENMASK(31, 28)
321 #define PPE_DRAM_HASH1_EN_MASK			BIT(24)
322 #define PPE_DRAM_HASH0_MODE_MASK		GENMASK(23, 20)
323 #define PPE_DRAM_TABLE_EN_MASK			BIT(16)
324 #define PPE_SRAM_HASH1_MODE_MASK		GENMASK(15, 12)
325 #define PPE_SRAM_HASH1_EN_MASK			BIT(8)
326 #define PPE_SRAM_HASH0_MODE_MASK		GENMASK(7, 4)
327 #define PPE_SRAM_TABLE_EN_MASK			BIT(0)
328 
329 #define REG_PPE_MTU_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x304)
330 #define REG_PPE_MTU(_m, _n)			(REG_PPE_MTU_BASE(_m) + (((_n) / 2) << 2))
331 #define FP_EGRESS_MTU_MASK(_n)			GENMASK(13 + (((_n) % 2) << 4), ((_n) % 2) << 4)
332 
333 #define REG_PPE_RAM_CTRL(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x31c)
334 #define PPE_SRAM_CTRL_ACK_MASK			BIT(31)
335 #define PPE_SRAM_CTRL_DUAL_SUCESS_MASK		BIT(30)
336 #define PPE_SRAM_CTRL_ENTRY_MASK		GENMASK(23, 8)
337 #define PPE_SRAM_WR_DUAL_DIRECTION_MASK		BIT(2)
338 #define PPE_SRAM_CTRL_WR_MASK			BIT(1)
339 #define PPE_SRAM_CTRL_REQ_MASK			BIT(0)
340 
341 #define REG_PPE_RAM_BASE(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x320)
342 #define REG_PPE_RAM_ENTRY(_m, _n)		(REG_PPE_RAM_BASE(_m) + ((_n) << 2))
343 
344 #define REG_UPDMEM_CTRL(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x370)
345 #define PPE_UPDMEM_ACK_MASK			BIT(31)
346 #define PPE_UPDMEM_ADDR_MASK			GENMASK(11, 8)
347 #define PPE_UPDMEM_OFFSET_MASK			GENMASK(7, 4)
348 #define PPE_UPDMEM_SEL_MASK			GENMASK(3, 2)
349 #define PPE_UPDMEM_WR_MASK			BIT(1)
350 #define PPE_UPDMEM_REQ_MASK			BIT(0)
351 
352 #define REG_UPDMEM_DATA(_n)			(((_n) ? PPE2_BASE : PPE1_BASE) + 0x374)
353 
354 #define REG_IP_FRAG_FP			0x2010
355 #define IP_ASSEMBLE_PORT_MASK		GENMASK(24, 21)
356 #define IP_ASSEMBLE_NBQ_MASK		GENMASK(20, 16)
357 #define IP_FRAGMENT_PORT_MASK		GENMASK(8, 5)
358 #define IP_FRAGMENT_NBQ_MASK		GENMASK(4, 0)
359 
360 #define REG_MC_VLAN_EN			0x2100
361 #define MC_VLAN_EN_MASK			BIT(0)
362 
363 #define REG_MC_VLAN_CFG			0x2104
364 #define MC_VLAN_CFG_CMD_DONE_MASK	BIT(31)
365 #define MC_VLAN_CFG_TABLE_ID_MASK	GENMASK(21, 16)
366 #define MC_VLAN_CFG_PORT_ID_MASK	GENMASK(11, 8)
367 #define MC_VLAN_CFG_TABLE_SEL_MASK	BIT(4)
368 #define MC_VLAN_CFG_RW_MASK		BIT(0)
369 
370 #define REG_MC_VLAN_DATA		0x2108
371 
372 #define REG_SP_DFT_CPORT(_n)		(0x20e0 + ((_n) << 2))
373 #define SP_CPORT_DFT_MASK		GENMASK(2, 0)
374 #define SP_CPORT_MASK(_n)		GENMASK(3 + ((_n) << 2), ((_n) << 2))
375 
376 #define REG_SRC_PORT_FC_MAP6		0x2298
377 #define FC_ID_OF_SRC_PORT_MASK(_n)	GENMASK(4 + ((_n) << 3), ((_n) << 3))
378 
379 #define REG_WAN_MTU0			0x2300
380 #define WAN_MTU1_MASK			GENMASK(29, 16)
381 #define WAN_MTU0_MASK			GENMASK(13, 0)
382 
383 #define REG_CDM5_RX_OQ1_DROP_CNT	0x29d4
384 
385 /* QDMA */
386 #define REG_QDMA_GLOBAL_CFG			0x0004
387 #define GLOBAL_CFG_RX_2B_OFFSET_MASK		BIT(31)
388 #define GLOBAL_CFG_DMA_PREFERENCE_MASK		GENMASK(30, 29)
389 #define GLOBAL_CFG_CPU_TXR_RR_MASK		BIT(28)
390 #define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK		BIT(27)
391 #define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK	BIT(26)
392 #define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK	BIT(25)
393 #define GLOBAL_CFG_OAM_MODIFY_MASK		BIT(24)
394 #define GLOBAL_CFG_RESET_MASK			BIT(23)
395 #define GLOBAL_CFG_RESET_DONE_MASK		BIT(22)
396 #define GLOBAL_CFG_MULTICAST_EN_MASK		BIT(21)
397 #define GLOBAL_CFG_IRQ1_EN_MASK			BIT(20)
398 #define GLOBAL_CFG_IRQ0_EN_MASK			BIT(19)
399 #define GLOBAL_CFG_LOOPCNT_EN_MASK		BIT(18)
400 #define GLOBAL_CFG_RD_BYPASS_WR_MASK		BIT(17)
401 #define GLOBAL_CFG_QDMA_LOOPBACK_MASK		BIT(16)
402 #define GLOBAL_CFG_LPBK_RXQ_SEL_MASK		GENMASK(13, 8)
403 #define GLOBAL_CFG_CHECK_DONE_MASK		BIT(7)
404 #define GLOBAL_CFG_TX_WB_DONE_MASK		BIT(6)
405 #define GLOBAL_CFG_MAX_ISSUE_NUM_MASK		GENMASK(5, 4)
406 #define GLOBAL_CFG_RX_DMA_BUSY_MASK		BIT(3)
407 #define GLOBAL_CFG_RX_DMA_EN_MASK		BIT(2)
408 #define GLOBAL_CFG_TX_DMA_BUSY_MASK		BIT(1)
409 #define GLOBAL_CFG_TX_DMA_EN_MASK		BIT(0)
410 
411 #define REG_FWD_DSCP_BASE			0x0010
412 #define REG_FWD_BUF_BASE			0x0014
413 
414 #define REG_HW_FWD_DSCP_CFG			0x0018
415 #define HW_FWD_DSCP_PAYLOAD_SIZE_MASK		GENMASK(29, 28)
416 #define HW_FWD_DSCP_SCATTER_LEN_MASK		GENMASK(17, 16)
417 #define HW_FWD_DSCP_MIN_SCATTER_LEN_MASK	GENMASK(15, 0)
418 
419 #define REG_INT_STATUS(_n)		\
420 	(((_n) == 4) ? 0x0730 :		\
421 	 ((_n) == 3) ? 0x0724 :		\
422 	 ((_n) == 2) ? 0x0720 :		\
423 	 ((_n) == 1) ? 0x0024 : 0x0020)
424 
425 #define REG_INT_ENABLE(_b, _n)		\
426 	(((_n) == 4) ? 0x0750 + ((_b) << 5) :	\
427 	 ((_n) == 3) ? 0x0744 + ((_b) << 5) :	\
428 	 ((_n) == 2) ? 0x0740 + ((_b) << 5) :	\
429 	 ((_n) == 1) ? 0x002c + ((_b) << 3) :	\
430 		       0x0028 + ((_b) << 3))
431 
432 /* QDMA_CSR_INT_ENABLE1 */
433 #define RX15_COHERENT_INT_MASK		BIT(31)
434 #define RX14_COHERENT_INT_MASK		BIT(30)
435 #define RX13_COHERENT_INT_MASK		BIT(29)
436 #define RX12_COHERENT_INT_MASK		BIT(28)
437 #define RX11_COHERENT_INT_MASK		BIT(27)
438 #define RX10_COHERENT_INT_MASK		BIT(26)
439 #define RX9_COHERENT_INT_MASK		BIT(25)
440 #define RX8_COHERENT_INT_MASK		BIT(24)
441 #define RX7_COHERENT_INT_MASK		BIT(23)
442 #define RX6_COHERENT_INT_MASK		BIT(22)
443 #define RX5_COHERENT_INT_MASK		BIT(21)
444 #define RX4_COHERENT_INT_MASK		BIT(20)
445 #define RX3_COHERENT_INT_MASK		BIT(19)
446 #define RX2_COHERENT_INT_MASK		BIT(18)
447 #define RX1_COHERENT_INT_MASK		BIT(17)
448 #define RX0_COHERENT_INT_MASK		BIT(16)
449 #define TX7_COHERENT_INT_MASK		BIT(15)
450 #define TX6_COHERENT_INT_MASK		BIT(14)
451 #define TX5_COHERENT_INT_MASK		BIT(13)
452 #define TX4_COHERENT_INT_MASK		BIT(12)
453 #define TX3_COHERENT_INT_MASK		BIT(11)
454 #define TX2_COHERENT_INT_MASK		BIT(10)
455 #define TX1_COHERENT_INT_MASK		BIT(9)
456 #define TX0_COHERENT_INT_MASK		BIT(8)
457 #define CNT_OVER_FLOW_INT_MASK		BIT(7)
458 #define IRQ1_FULL_INT_MASK		BIT(5)
459 #define IRQ1_INT_MASK			BIT(4)
460 #define HWFWD_DSCP_LOW_INT_MASK		BIT(3)
461 #define HWFWD_DSCP_EMPTY_INT_MASK	BIT(2)
462 #define IRQ0_FULL_INT_MASK		BIT(1)
463 #define IRQ0_INT_MASK			BIT(0)
464 
465 #define RX_COHERENT_LOW_INT_MASK				\
466 	(RX15_COHERENT_INT_MASK | RX14_COHERENT_INT_MASK |	\
467 	 RX13_COHERENT_INT_MASK | RX12_COHERENT_INT_MASK |	\
468 	 RX11_COHERENT_INT_MASK | RX10_COHERENT_INT_MASK |	\
469 	 RX9_COHERENT_INT_MASK | RX8_COHERENT_INT_MASK |	\
470 	 RX7_COHERENT_INT_MASK | RX6_COHERENT_INT_MASK |	\
471 	 RX5_COHERENT_INT_MASK | RX4_COHERENT_INT_MASK |	\
472 	 RX3_COHERENT_INT_MASK | RX2_COHERENT_INT_MASK |	\
473 	 RX1_COHERENT_INT_MASK | RX0_COHERENT_INT_MASK)
474 
475 #define RX_COHERENT_LOW_OFFSET	__ffs(RX_COHERENT_LOW_INT_MASK)
476 #define INT_RX0_MASK(_n)					\
477 	(((_n) << RX_COHERENT_LOW_OFFSET) & RX_COHERENT_LOW_INT_MASK)
478 
479 #define TX_COHERENT_LOW_INT_MASK				\
480 	(TX7_COHERENT_INT_MASK | TX6_COHERENT_INT_MASK |	\
481 	 TX5_COHERENT_INT_MASK | TX4_COHERENT_INT_MASK |	\
482 	 TX3_COHERENT_INT_MASK | TX2_COHERENT_INT_MASK |	\
483 	 TX1_COHERENT_INT_MASK | TX0_COHERENT_INT_MASK)
484 
485 #define TX_DONE_INT_MASK(_n)					\
486 	((_n) ? IRQ1_INT_MASK | IRQ1_FULL_INT_MASK		\
487 	      : IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
488 
489 #define INT_TX_MASK						\
490 	(IRQ1_INT_MASK | IRQ1_FULL_INT_MASK |			\
491 	 IRQ0_INT_MASK | IRQ0_FULL_INT_MASK)
492 
493 /* QDMA_CSR_INT_ENABLE2 */
494 #define RX15_NO_CPU_DSCP_INT_MASK	BIT(31)
495 #define RX14_NO_CPU_DSCP_INT_MASK	BIT(30)
496 #define RX13_NO_CPU_DSCP_INT_MASK	BIT(29)
497 #define RX12_NO_CPU_DSCP_INT_MASK	BIT(28)
498 #define RX11_NO_CPU_DSCP_INT_MASK	BIT(27)
499 #define RX10_NO_CPU_DSCP_INT_MASK	BIT(26)
500 #define RX9_NO_CPU_DSCP_INT_MASK	BIT(25)
501 #define RX8_NO_CPU_DSCP_INT_MASK	BIT(24)
502 #define RX7_NO_CPU_DSCP_INT_MASK	BIT(23)
503 #define RX6_NO_CPU_DSCP_INT_MASK	BIT(22)
504 #define RX5_NO_CPU_DSCP_INT_MASK	BIT(21)
505 #define RX4_NO_CPU_DSCP_INT_MASK	BIT(20)
506 #define RX3_NO_CPU_DSCP_INT_MASK	BIT(19)
507 #define RX2_NO_CPU_DSCP_INT_MASK	BIT(18)
508 #define RX1_NO_CPU_DSCP_INT_MASK	BIT(17)
509 #define RX0_NO_CPU_DSCP_INT_MASK	BIT(16)
510 #define RX15_DONE_INT_MASK		BIT(15)
511 #define RX14_DONE_INT_MASK		BIT(14)
512 #define RX13_DONE_INT_MASK		BIT(13)
513 #define RX12_DONE_INT_MASK		BIT(12)
514 #define RX11_DONE_INT_MASK		BIT(11)
515 #define RX10_DONE_INT_MASK		BIT(10)
516 #define RX9_DONE_INT_MASK		BIT(9)
517 #define RX8_DONE_INT_MASK		BIT(8)
518 #define RX7_DONE_INT_MASK		BIT(7)
519 #define RX6_DONE_INT_MASK		BIT(6)
520 #define RX5_DONE_INT_MASK		BIT(5)
521 #define RX4_DONE_INT_MASK		BIT(4)
522 #define RX3_DONE_INT_MASK		BIT(3)
523 #define RX2_DONE_INT_MASK		BIT(2)
524 #define RX1_DONE_INT_MASK		BIT(1)
525 #define RX0_DONE_INT_MASK		BIT(0)
526 
527 #define RX_NO_CPU_DSCP_LOW_INT_MASK					\
528 	(RX15_NO_CPU_DSCP_INT_MASK | RX14_NO_CPU_DSCP_INT_MASK |	\
529 	 RX13_NO_CPU_DSCP_INT_MASK | RX12_NO_CPU_DSCP_INT_MASK |	\
530 	 RX11_NO_CPU_DSCP_INT_MASK | RX10_NO_CPU_DSCP_INT_MASK |	\
531 	 RX9_NO_CPU_DSCP_INT_MASK | RX8_NO_CPU_DSCP_INT_MASK |		\
532 	 RX7_NO_CPU_DSCP_INT_MASK | RX6_NO_CPU_DSCP_INT_MASK |		\
533 	 RX5_NO_CPU_DSCP_INT_MASK | RX4_NO_CPU_DSCP_INT_MASK |		\
534 	 RX3_NO_CPU_DSCP_INT_MASK | RX2_NO_CPU_DSCP_INT_MASK |		\
535 	 RX1_NO_CPU_DSCP_INT_MASK | RX0_NO_CPU_DSCP_INT_MASK)
536 
537 #define RX_DONE_LOW_INT_MASK				\
538 	(RX15_DONE_INT_MASK | RX14_DONE_INT_MASK |	\
539 	 RX13_DONE_INT_MASK | RX12_DONE_INT_MASK |	\
540 	 RX11_DONE_INT_MASK | RX10_DONE_INT_MASK |	\
541 	 RX9_DONE_INT_MASK | RX8_DONE_INT_MASK |	\
542 	 RX7_DONE_INT_MASK | RX6_DONE_INT_MASK |	\
543 	 RX5_DONE_INT_MASK | RX4_DONE_INT_MASK |	\
544 	 RX3_DONE_INT_MASK | RX2_DONE_INT_MASK |	\
545 	 RX1_DONE_INT_MASK | RX0_DONE_INT_MASK)
546 
547 #define RX_NO_CPU_DSCP_LOW_OFFSET	__ffs(RX_NO_CPU_DSCP_LOW_INT_MASK)
548 #define INT_RX1_MASK(_n)							\
549 	((((_n) << RX_NO_CPU_DSCP_LOW_OFFSET) & RX_NO_CPU_DSCP_LOW_INT_MASK) |	\
550 	 (RX_DONE_LOW_INT_MASK & (_n)))
551 
552 /* QDMA_CSR_INT_ENABLE3 */
553 #define RX31_NO_CPU_DSCP_INT_MASK	BIT(31)
554 #define RX30_NO_CPU_DSCP_INT_MASK	BIT(30)
555 #define RX29_NO_CPU_DSCP_INT_MASK	BIT(29)
556 #define RX28_NO_CPU_DSCP_INT_MASK	BIT(28)
557 #define RX27_NO_CPU_DSCP_INT_MASK	BIT(27)
558 #define RX26_NO_CPU_DSCP_INT_MASK	BIT(26)
559 #define RX25_NO_CPU_DSCP_INT_MASK	BIT(25)
560 #define RX24_NO_CPU_DSCP_INT_MASK	BIT(24)
561 #define RX23_NO_CPU_DSCP_INT_MASK	BIT(23)
562 #define RX22_NO_CPU_DSCP_INT_MASK	BIT(22)
563 #define RX21_NO_CPU_DSCP_INT_MASK	BIT(21)
564 #define RX20_NO_CPU_DSCP_INT_MASK	BIT(20)
565 #define RX19_NO_CPU_DSCP_INT_MASK	BIT(19)
566 #define RX18_NO_CPU_DSCP_INT_MASK	BIT(18)
567 #define RX17_NO_CPU_DSCP_INT_MASK	BIT(17)
568 #define RX16_NO_CPU_DSCP_INT_MASK	BIT(16)
569 #define RX31_DONE_INT_MASK		BIT(15)
570 #define RX30_DONE_INT_MASK		BIT(14)
571 #define RX29_DONE_INT_MASK		BIT(13)
572 #define RX28_DONE_INT_MASK		BIT(12)
573 #define RX27_DONE_INT_MASK		BIT(11)
574 #define RX26_DONE_INT_MASK		BIT(10)
575 #define RX25_DONE_INT_MASK		BIT(9)
576 #define RX24_DONE_INT_MASK		BIT(8)
577 #define RX23_DONE_INT_MASK		BIT(7)
578 #define RX22_DONE_INT_MASK		BIT(6)
579 #define RX21_DONE_INT_MASK		BIT(5)
580 #define RX20_DONE_INT_MASK		BIT(4)
581 #define RX19_DONE_INT_MASK		BIT(3)
582 #define RX18_DONE_INT_MASK		BIT(2)
583 #define RX17_DONE_INT_MASK		BIT(1)
584 #define RX16_DONE_INT_MASK		BIT(0)
585 
586 #define RX_NO_CPU_DSCP_HIGH_INT_MASK					\
587 	(RX31_NO_CPU_DSCP_INT_MASK | RX30_NO_CPU_DSCP_INT_MASK |	\
588 	 RX29_NO_CPU_DSCP_INT_MASK | RX28_NO_CPU_DSCP_INT_MASK |	\
589 	 RX27_NO_CPU_DSCP_INT_MASK | RX26_NO_CPU_DSCP_INT_MASK |	\
590 	 RX25_NO_CPU_DSCP_INT_MASK | RX24_NO_CPU_DSCP_INT_MASK |	\
591 	 RX23_NO_CPU_DSCP_INT_MASK | RX22_NO_CPU_DSCP_INT_MASK |	\
592 	 RX21_NO_CPU_DSCP_INT_MASK | RX20_NO_CPU_DSCP_INT_MASK |	\
593 	 RX19_NO_CPU_DSCP_INT_MASK | RX18_NO_CPU_DSCP_INT_MASK |	\
594 	 RX17_NO_CPU_DSCP_INT_MASK | RX16_NO_CPU_DSCP_INT_MASK)
595 
596 #define RX_DONE_HIGH_INT_MASK				\
597 	(RX31_DONE_INT_MASK | RX30_DONE_INT_MASK |	\
598 	 RX29_DONE_INT_MASK | RX28_DONE_INT_MASK |	\
599 	 RX27_DONE_INT_MASK | RX26_DONE_INT_MASK |	\
600 	 RX25_DONE_INT_MASK | RX24_DONE_INT_MASK |	\
601 	 RX23_DONE_INT_MASK | RX22_DONE_INT_MASK |	\
602 	 RX21_DONE_INT_MASK | RX20_DONE_INT_MASK |	\
603 	 RX19_DONE_INT_MASK | RX18_DONE_INT_MASK |	\
604 	 RX17_DONE_INT_MASK | RX16_DONE_INT_MASK)
605 
606 #define RX_DONE_HIGH_OFFSET	fls(RX_DONE_HIGH_INT_MASK)
607 #define RX_DONE_INT_MASK	\
608 	((RX_DONE_HIGH_INT_MASK << RX_DONE_HIGH_OFFSET) | RX_DONE_LOW_INT_MASK)
609 
610 #define INT_RX2_MASK(_n)				\
611 	((RX_NO_CPU_DSCP_HIGH_INT_MASK & (_n)) |	\
612 	 (((_n) >> RX_DONE_HIGH_OFFSET) & RX_DONE_HIGH_INT_MASK))
613 
614 /* QDMA_CSR_INT_ENABLE4 */
615 #define RX31_COHERENT_INT_MASK		BIT(31)
616 #define RX30_COHERENT_INT_MASK		BIT(30)
617 #define RX29_COHERENT_INT_MASK		BIT(29)
618 #define RX28_COHERENT_INT_MASK		BIT(28)
619 #define RX27_COHERENT_INT_MASK		BIT(27)
620 #define RX26_COHERENT_INT_MASK		BIT(26)
621 #define RX25_COHERENT_INT_MASK		BIT(25)
622 #define RX24_COHERENT_INT_MASK		BIT(24)
623 #define RX23_COHERENT_INT_MASK		BIT(23)
624 #define RX22_COHERENT_INT_MASK		BIT(22)
625 #define RX21_COHERENT_INT_MASK		BIT(21)
626 #define RX20_COHERENT_INT_MASK		BIT(20)
627 #define RX19_COHERENT_INT_MASK		BIT(19)
628 #define RX18_COHERENT_INT_MASK		BIT(18)
629 #define RX17_COHERENT_INT_MASK		BIT(17)
630 #define RX16_COHERENT_INT_MASK		BIT(16)
631 
632 #define RX_COHERENT_HIGH_INT_MASK				\
633 	(RX31_COHERENT_INT_MASK | RX30_COHERENT_INT_MASK |	\
634 	 RX29_COHERENT_INT_MASK | RX28_COHERENT_INT_MASK |	\
635 	 RX27_COHERENT_INT_MASK | RX26_COHERENT_INT_MASK |	\
636 	 RX25_COHERENT_INT_MASK | RX24_COHERENT_INT_MASK |	\
637 	 RX23_COHERENT_INT_MASK | RX22_COHERENT_INT_MASK |	\
638 	 RX21_COHERENT_INT_MASK | RX20_COHERENT_INT_MASK |	\
639 	 RX19_COHERENT_INT_MASK | RX18_COHERENT_INT_MASK |	\
640 	 RX17_COHERENT_INT_MASK | RX16_COHERENT_INT_MASK)
641 
642 #define INT_RX3_MASK(_n)	(RX_COHERENT_HIGH_INT_MASK & (_n))
643 
644 /* QDMA_CSR_INT_ENABLE5 */
645 #define TX31_COHERENT_INT_MASK		BIT(31)
646 #define TX30_COHERENT_INT_MASK		BIT(30)
647 #define TX29_COHERENT_INT_MASK		BIT(29)
648 #define TX28_COHERENT_INT_MASK		BIT(28)
649 #define TX27_COHERENT_INT_MASK		BIT(27)
650 #define TX26_COHERENT_INT_MASK		BIT(26)
651 #define TX25_COHERENT_INT_MASK		BIT(25)
652 #define TX24_COHERENT_INT_MASK		BIT(24)
653 #define TX23_COHERENT_INT_MASK		BIT(23)
654 #define TX22_COHERENT_INT_MASK		BIT(22)
655 #define TX21_COHERENT_INT_MASK		BIT(21)
656 #define TX20_COHERENT_INT_MASK		BIT(20)
657 #define TX19_COHERENT_INT_MASK		BIT(19)
658 #define TX18_COHERENT_INT_MASK		BIT(18)
659 #define TX17_COHERENT_INT_MASK		BIT(17)
660 #define TX16_COHERENT_INT_MASK		BIT(16)
661 #define TX15_COHERENT_INT_MASK		BIT(15)
662 #define TX14_COHERENT_INT_MASK		BIT(14)
663 #define TX13_COHERENT_INT_MASK		BIT(13)
664 #define TX12_COHERENT_INT_MASK		BIT(12)
665 #define TX11_COHERENT_INT_MASK		BIT(11)
666 #define TX10_COHERENT_INT_MASK		BIT(10)
667 #define TX9_COHERENT_INT_MASK		BIT(9)
668 #define TX8_COHERENT_INT_MASK		BIT(8)
669 
670 #define TX_COHERENT_HIGH_INT_MASK				\
671 	(TX31_COHERENT_INT_MASK | TX30_COHERENT_INT_MASK |	\
672 	 TX29_COHERENT_INT_MASK | TX28_COHERENT_INT_MASK |	\
673 	 TX27_COHERENT_INT_MASK | TX26_COHERENT_INT_MASK |	\
674 	 TX25_COHERENT_INT_MASK | TX24_COHERENT_INT_MASK |	\
675 	 TX23_COHERENT_INT_MASK | TX22_COHERENT_INT_MASK |	\
676 	 TX21_COHERENT_INT_MASK | TX20_COHERENT_INT_MASK |	\
677 	 TX19_COHERENT_INT_MASK | TX18_COHERENT_INT_MASK |	\
678 	 TX17_COHERENT_INT_MASK | TX16_COHERENT_INT_MASK |	\
679 	 TX15_COHERENT_INT_MASK | TX14_COHERENT_INT_MASK |	\
680 	 TX13_COHERENT_INT_MASK | TX12_COHERENT_INT_MASK |	\
681 	 TX11_COHERENT_INT_MASK | TX10_COHERENT_INT_MASK |	\
682 	 TX9_COHERENT_INT_MASK | TX8_COHERENT_INT_MASK)
683 
684 #define REG_TX_IRQ_BASE(_n)		((_n) ? 0x0048 : 0x0050)
685 
686 #define REG_TX_IRQ_CFG(_n)		((_n) ? 0x004c : 0x0054)
687 #define TX_IRQ_THR_MASK			GENMASK(27, 16)
688 #define TX_IRQ_DEPTH_MASK		GENMASK(11, 0)
689 
690 #define REG_IRQ_CLEAR_LEN(_n)		((_n) ? 0x0064 : 0x0058)
691 #define IRQ_CLEAR_LEN_MASK		GENMASK(7, 0)
692 
693 #define REG_IRQ_STATUS(_n)		((_n) ? 0x0068 : 0x005c)
694 #define IRQ_ENTRY_LEN_MASK		GENMASK(27, 16)
695 #define IRQ_HEAD_IDX_MASK		GENMASK(11, 0)
696 
697 #define REG_TX_RING_BASE(_n)	\
698 	(((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5))
699 
700 #define REG_TX_RING_BLOCKING(_n)	\
701 	(((_n) < 8) ? 0x0104 + ((_n) << 5) : 0x0b04 + (((_n) - 8) << 5))
702 
703 #define TX_RING_IRQ_BLOCKING_MAP_MASK			BIT(6)
704 #define TX_RING_IRQ_BLOCKING_CFG_MASK			BIT(4)
705 #define TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK		BIT(2)
706 #define TX_RING_IRQ_BLOCKING_MAX_TH_TXRING_EN_MASK	BIT(1)
707 #define TX_RING_IRQ_BLOCKING_MIN_TH_TXRING_EN_MASK	BIT(0)
708 
709 #define REG_TX_CPU_IDX(_n)	\
710 	(((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5))
711 
712 #define TX_RING_CPU_IDX_MASK		GENMASK(15, 0)
713 
714 #define REG_TX_DMA_IDX(_n)	\
715 	(((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5))
716 
717 #define TX_RING_DMA_IDX_MASK		GENMASK(15, 0)
718 
719 #define IRQ_RING_IDX_MASK		GENMASK(20, 16)
720 #define IRQ_DESC_IDX_MASK		GENMASK(15, 0)
721 
722 #define REG_RX_RING_BASE(_n)	\
723 	(((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5))
724 
725 #define REG_RX_RING_SIZE(_n)	\
726 	(((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5))
727 
728 #define RX_RING_THR_MASK		GENMASK(31, 16)
729 #define RX_RING_SIZE_MASK		GENMASK(15, 0)
730 
731 #define REG_RX_CPU_IDX(_n)	\
732 	(((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5))
733 
734 #define RX_RING_CPU_IDX_MASK		GENMASK(15, 0)
735 
736 #define REG_RX_DMA_IDX(_n)	\
737 	(((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5))
738 
739 #define REG_RX_DELAY_INT_IDX(_n)	\
740 	(((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
741 
742 #define REG_RX_SCATTER_CFG(_n)	\
743 	(((_n) < 16) ? 0x0214 + ((_n) << 5) : 0x0e14 + (((_n) - 16) << 5))
744 
745 #define RX_DELAY_INT_MASK		GENMASK(15, 0)
746 
747 #define RX_RING_DMA_IDX_MASK		GENMASK(15, 0)
748 
749 #define RX_RING_SG_EN_MASK		BIT(0)
750 
751 #define REG_INGRESS_TRTCM_CFG		0x0070
752 #define INGRESS_TRTCM_EN_MASK		BIT(31)
753 #define INGRESS_TRTCM_MODE_MASK		BIT(30)
754 #define INGRESS_SLOW_TICK_RATIO_MASK	GENMASK(29, 16)
755 #define INGRESS_FAST_TICK_MASK		GENMASK(15, 0)
756 
757 #define REG_QUEUE_CLOSE_CFG(_n)		(0x00a0 + ((_n) & 0xfc))
758 #define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m)	BIT((_m) + (((_n) & 0x3) << 3))
759 
760 #define REG_TXQ_DIS_CFG_BASE(_n)	((_n) ? 0x20a0 : 0x00a0)
761 #define REG_TXQ_DIS_CFG(_n, _m)		(REG_TXQ_DIS_CFG_BASE((_n)) + (_m) << 2)
762 
763 #define REG_CNTR_CFG(_n)		(0x0400 + ((_n) << 3))
764 #define CNTR_EN_MASK			BIT(31)
765 #define CNTR_ALL_CHAN_EN_MASK		BIT(30)
766 #define CNTR_ALL_QUEUE_EN_MASK		BIT(29)
767 #define CNTR_ALL_DSCP_RING_EN_MASK	BIT(28)
768 #define CNTR_SRC_MASK			GENMASK(27, 24)
769 #define CNTR_DSCP_RING_MASK		GENMASK(20, 16)
770 #define CNTR_CHAN_MASK			GENMASK(7, 3)
771 #define CNTR_QUEUE_MASK			GENMASK(2, 0)
772 
773 #define REG_CNTR_VAL(_n)		(0x0404 + ((_n) << 3))
774 
775 #define REG_LMGR_INIT_CFG		0x1000
776 #define LMGR_INIT_START			BIT(31)
777 #define LMGR_SRAM_MODE_MASK		BIT(30)
778 #define HW_FWD_PKTSIZE_OVERHEAD_MASK	GENMASK(27, 20)
779 #define HW_FWD_DESC_NUM_MASK		GENMASK(16, 0)
780 
781 #define REG_FWD_DSCP_LOW_THR		0x1004
782 #define FWD_DSCP_LOW_THR_MASK		GENMASK(17, 0)
783 
784 #define REG_EGRESS_RATE_METER_CFG		0x100c
785 #define EGRESS_RATE_METER_EN_MASK		BIT(31)
786 #define EGRESS_RATE_METER_EQ_RATE_EN_MASK	BIT(17)
787 #define EGRESS_RATE_METER_WINDOW_SZ_MASK	GENMASK(16, 12)
788 #define EGRESS_RATE_METER_TIMESLICE_MASK	GENMASK(10, 0)
789 
790 #define REG_EGRESS_TRTCM_CFG		0x1010
791 #define EGRESS_TRTCM_EN_MASK		BIT(31)
792 #define EGRESS_TRTCM_MODE_MASK		BIT(30)
793 #define EGRESS_SLOW_TICK_RATIO_MASK	GENMASK(29, 16)
794 #define EGRESS_FAST_TICK_MASK		GENMASK(15, 0)
795 
796 #define TRTCM_PARAM_RW_MASK		BIT(31)
797 #define TRTCM_PARAM_RW_DONE_MASK	BIT(30)
798 #define TRTCM_PARAM_TYPE_MASK		GENMASK(29, 28)
799 #define TRTCM_METER_GROUP_MASK		GENMASK(27, 26)
800 #define TRTCM_PARAM_INDEX_MASK		GENMASK(23, 17)
801 #define TRTCM_PARAM_RATE_TYPE_MASK	BIT(16)
802 
803 #define REG_TRTCM_CFG_PARAM(_n)		((_n) + 0x4)
804 #define REG_TRTCM_DATA_LOW(_n)		((_n) + 0x8)
805 #define REG_TRTCM_DATA_HIGH(_n)		((_n) + 0xc)
806 
807 #define RATE_LIMIT_PARAM_RW_MASK	BIT(31)
808 #define RATE_LIMIT_PARAM_RW_DONE_MASK	BIT(30)
809 #define RATE_LIMIT_PARAM_TYPE_MASK	GENMASK(29, 28)
810 #define RATE_LIMIT_METER_GROUP_MASK	GENMASK(27, 26)
811 #define RATE_LIMIT_PARAM_INDEX_MASK	GENMASK(23, 16)
812 
813 #define REG_TXWRR_MODE_CFG		0x1020
814 #define TWRR_WEIGHT_SCALE_MASK		BIT(31)
815 #define TWRR_WEIGHT_BASE_MASK		BIT(3)
816 
817 #define REG_TXWRR_WEIGHT_CFG		0x1024
818 #define TWRR_RW_CMD_MASK		BIT(31)
819 #define TWRR_RW_CMD_DONE		BIT(30)
820 #define TWRR_CHAN_IDX_MASK		GENMASK(23, 19)
821 #define TWRR_QUEUE_IDX_MASK		GENMASK(18, 16)
822 #define TWRR_VALUE_MASK			GENMASK(15, 0)
823 
824 #define REG_PSE_BUF_USAGE_CFG		0x1028
825 #define PSE_BUF_ESTIMATE_EN_MASK	BIT(29)
826 
827 #define REG_CHAN_QOS_MODE(_n)		(0x1040 + ((_n) << 2))
828 #define CHAN_QOS_MODE_MASK(_n)		GENMASK(2 + ((_n) << 2), (_n) << 2)
829 
830 #define REG_GLB_TRTCM_CFG		0x1080
831 #define GLB_TRTCM_EN_MASK		BIT(31)
832 #define GLB_TRTCM_MODE_MASK		BIT(30)
833 #define GLB_SLOW_TICK_RATIO_MASK	GENMASK(29, 16)
834 #define GLB_FAST_TICK_MASK		GENMASK(15, 0)
835 
836 #define REG_TXQ_CNGST_CFG		0x10a0
837 #define TXQ_CNGST_DROP_EN		BIT(31)
838 #define TXQ_CNGST_DEI_DROP_EN		BIT(30)
839 
840 #define REG_SLA_TRTCM_CFG		0x1150
841 #define SLA_TRTCM_EN_MASK		BIT(31)
842 #define SLA_TRTCM_MODE_MASK		BIT(30)
843 #define SLA_SLOW_TICK_RATIO_MASK	GENMASK(29, 16)
844 #define SLA_FAST_TICK_MASK		GENMASK(15, 0)
845 
846 /* CTRL */
847 #define QDMA_DESC_DONE_MASK		BIT(31)
848 #define QDMA_DESC_DROP_MASK		BIT(30) /* tx: drop - rx: overflow */
849 #define QDMA_DESC_MORE_MASK		BIT(29) /* more SG elements */
850 #define QDMA_DESC_DEI_MASK		BIT(25)
851 #define QDMA_DESC_NO_DROP_MASK		BIT(24)
852 #define QDMA_DESC_LEN_MASK		GENMASK(15, 0)
853 /* DATA */
854 #define QDMA_DESC_NEXT_ID_MASK		GENMASK(15, 0)
855 /* TX MSG0 */
856 #define QDMA_ETH_TXMSG_MIC_IDX_MASK	BIT(30)
857 #define QDMA_ETH_TXMSG_SP_TAG_MASK	GENMASK(29, 14)
858 #define QDMA_ETH_TXMSG_ICO_MASK		BIT(13)
859 #define QDMA_ETH_TXMSG_UCO_MASK		BIT(12)
860 #define QDMA_ETH_TXMSG_TCO_MASK		BIT(11)
861 #define QDMA_ETH_TXMSG_TSO_MASK		BIT(10)
862 #define QDMA_ETH_TXMSG_FAST_MASK	BIT(9)
863 #define QDMA_ETH_TXMSG_OAM_MASK		BIT(8)
864 #define QDMA_ETH_TXMSG_CHAN_MASK	GENMASK(7, 3)
865 #define QDMA_ETH_TXMSG_QUEUE_MASK	GENMASK(2, 0)
866 /* TX MSG1 */
867 #define QDMA_ETH_TXMSG_NO_DROP		BIT(31)
868 #define QDMA_ETH_TXMSG_METER_MASK	GENMASK(30, 24)	/* 0x7f no meters */
869 #define QDMA_ETH_TXMSG_FPORT_MASK	GENMASK(23, 20)
870 #define QDMA_ETH_TXMSG_NBOQ_MASK	GENMASK(19, 15)
871 #define QDMA_ETH_TXMSG_HWF_MASK		BIT(14)
872 #define QDMA_ETH_TXMSG_HOP_MASK		BIT(13)
873 #define QDMA_ETH_TXMSG_PTP_MASK		BIT(12)
874 #define QDMA_ETH_TXMSG_ACNT_G1_MASK	GENMASK(10, 6)	/* 0x1f do not count */
875 #define QDMA_ETH_TXMSG_ACNT_G0_MASK	GENMASK(5, 0)	/* 0x3f do not count */
876 
877 /* RX MSG0 */
878 #define QDMA_ETH_RXMSG_SPTAG		GENMASK(21, 14)
879 /* RX MSG1 */
880 #define QDMA_ETH_RXMSG_DEI_MASK		BIT(31)
881 #define QDMA_ETH_RXMSG_IP6_MASK		BIT(30)
882 #define QDMA_ETH_RXMSG_IP4_MASK		BIT(29)
883 #define QDMA_ETH_RXMSG_IP4F_MASK	BIT(28)
884 #define QDMA_ETH_RXMSG_L4_VALID_MASK	BIT(27)
885 #define QDMA_ETH_RXMSG_L4F_MASK		BIT(26)
886 #define QDMA_ETH_RXMSG_SPORT_MASK	GENMASK(25, 21)
887 #define QDMA_ETH_RXMSG_CRSN_MASK	GENMASK(20, 16)
888 #define QDMA_ETH_RXMSG_PPE_ENTRY_MASK	GENMASK(15, 0)
889 
890 struct airoha_qdma_desc {
891 	__le32 rsv;
892 	__le32 ctrl;
893 	__le32 addr;
894 	__le32 data;
895 	__le32 msg0;
896 	__le32 msg1;
897 	__le32 msg2;
898 	__le32 msg3;
899 };
900 
901 /* CTRL0 */
902 #define QDMA_FWD_DESC_CTX_MASK		BIT(31)
903 #define QDMA_FWD_DESC_RING_MASK		GENMASK(30, 28)
904 #define QDMA_FWD_DESC_IDX_MASK		GENMASK(27, 16)
905 #define QDMA_FWD_DESC_LEN_MASK		GENMASK(15, 0)
906 /* CTRL1 */
907 #define QDMA_FWD_DESC_FIRST_IDX_MASK	GENMASK(15, 0)
908 /* CTRL2 */
909 #define QDMA_FWD_DESC_MORE_PKT_NUM_MASK	GENMASK(2, 0)
910 
911 struct airoha_qdma_fwd_desc {
912 	__le32 addr;
913 	__le32 ctrl0;
914 	__le32 ctrl1;
915 	__le32 ctrl2;
916 	__le32 msg0;
917 	__le32 msg1;
918 	__le32 rsv0;
919 	__le32 rsv1;
920 };
921 
922 #endif /* AIROHA_REGS_H */
923