1 /* 2 * Copyright 2012 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Alex Deucher 23 */ 24 #ifndef CIK_H 25 #define CIK_H 26 27 #define MC_SEQ_MISC0__MT__MASK 0xf0000000 28 #define MC_SEQ_MISC0__MT__GDDR1 0x10000000 29 #define MC_SEQ_MISC0__MT__DDR2 0x20000000 30 #define MC_SEQ_MISC0__MT__GDDR3 0x30000000 31 #define MC_SEQ_MISC0__MT__GDDR4 0x40000000 32 #define MC_SEQ_MISC0__MT__GDDR5 0x50000000 33 #define MC_SEQ_MISC0__MT__HBM 0x60000000 34 #define MC_SEQ_MISC0__MT__DDR3 0xB0000000 35 36 #define CP_ME_TABLE_SIZE 96 37 38 /* display controller offsets used for crtc/cur/lut/grph/viewport/etc. */ 39 #define CRTC0_REGISTER_OFFSET (0x1b7c - 0x1b7c) 40 #define CRTC1_REGISTER_OFFSET (0x1e7c - 0x1b7c) 41 #define CRTC2_REGISTER_OFFSET (0x417c - 0x1b7c) 42 #define CRTC3_REGISTER_OFFSET (0x447c - 0x1b7c) 43 #define CRTC4_REGISTER_OFFSET (0x477c - 0x1b7c) 44 #define CRTC5_REGISTER_OFFSET (0x4a7c - 0x1b7c) 45 46 /* hpd instance offsets */ 47 #define HPD0_REGISTER_OFFSET (0x1807 - 0x1807) 48 #define HPD1_REGISTER_OFFSET (0x180a - 0x1807) 49 #define HPD2_REGISTER_OFFSET (0x180d - 0x1807) 50 #define HPD3_REGISTER_OFFSET (0x1810 - 0x1807) 51 #define HPD4_REGISTER_OFFSET (0x1813 - 0x1807) 52 #define HPD5_REGISTER_OFFSET (0x1816 - 0x1807) 53 54 #define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 55 #define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003 56 57 #define PIPEID(x) ((x) << 0) 58 #define MEID(x) ((x) << 2) 59 #define VMID(x) ((x) << 4) 60 #define QUEUEID(x) ((x) << 8) 61 62 #define mmCC_DRM_ID_STRAPS 0x1559 63 #define CC_DRM_ID_STRAPS__ATI_REV_ID_MASK 0xf0000000 64 65 #define mmCHUB_CONTROL 0x619 66 #define BYPASS_VM (1 << 0) 67 68 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 69 70 #define mmGRPH_LUT_10BIT_BYPASS_CONTROL 0x1a02 71 #define LUT_10BIT_BYPASS_EN (1 << 8) 72 73 # define CURSOR_MONO 0 74 # define CURSOR_24_1 1 75 # define CURSOR_24_8_PRE_MULT 2 76 # define CURSOR_24_8_UNPRE_MULT 3 77 # define CURSOR_URGENT_ALWAYS 0 78 # define CURSOR_URGENT_1_8 1 79 # define CURSOR_URGENT_1_4 2 80 # define CURSOR_URGENT_3_8 3 81 # define CURSOR_URGENT_1_2 4 82 83 # define GRPH_DEPTH_8BPP 0 84 # define GRPH_DEPTH_16BPP 1 85 # define GRPH_DEPTH_32BPP 2 86 /* 8 BPP */ 87 # define GRPH_FORMAT_INDEXED 0 88 /* 16 BPP */ 89 # define GRPH_FORMAT_ARGB1555 0 90 # define GRPH_FORMAT_ARGB565 1 91 # define GRPH_FORMAT_ARGB4444 2 92 # define GRPH_FORMAT_AI88 3 93 # define GRPH_FORMAT_MONO16 4 94 # define GRPH_FORMAT_BGRA5551 5 95 /* 32 BPP */ 96 # define GRPH_FORMAT_ARGB8888 0 97 # define GRPH_FORMAT_ARGB2101010 1 98 # define GRPH_FORMAT_32BPP_DIG 2 99 # define GRPH_FORMAT_8B_ARGB2101010 3 100 # define GRPH_FORMAT_BGRA1010102 4 101 # define GRPH_FORMAT_8B_BGRA1010102 5 102 # define GRPH_FORMAT_RGB111110 6 103 # define GRPH_FORMAT_BGR101111 7 104 # define ADDR_SURF_MACRO_TILE_ASPECT_1 0 105 # define ADDR_SURF_MACRO_TILE_ASPECT_2 1 106 # define ADDR_SURF_MACRO_TILE_ASPECT_4 2 107 # define ADDR_SURF_MACRO_TILE_ASPECT_8 3 108 # define GRPH_ARRAY_LINEAR_GENERAL 0 109 # define GRPH_ARRAY_LINEAR_ALIGNED 1 110 # define GRPH_ARRAY_1D_TILED_THIN1 2 111 # define GRPH_ARRAY_2D_TILED_THIN1 4 112 # define DISPLAY_MICRO_TILING 0 113 # define THIN_MICRO_TILING 1 114 # define DEPTH_MICRO_TILING 2 115 # define ROTATED_MICRO_TILING 4 116 # define GRPH_ENDIAN_NONE 0 117 # define GRPH_ENDIAN_8IN16 1 118 # define GRPH_ENDIAN_8IN32 2 119 # define GRPH_ENDIAN_8IN64 3 120 # define GRPH_RED_SEL_R 0 121 # define GRPH_RED_SEL_G 1 122 # define GRPH_RED_SEL_B 2 123 # define GRPH_RED_SEL_A 3 124 # define GRPH_GREEN_SEL_G 0 125 # define GRPH_GREEN_SEL_B 1 126 # define GRPH_GREEN_SEL_A 2 127 # define GRPH_GREEN_SEL_R 3 128 # define GRPH_BLUE_SEL_B 0 129 # define GRPH_BLUE_SEL_A 1 130 # define GRPH_BLUE_SEL_R 2 131 # define GRPH_BLUE_SEL_G 3 132 # define GRPH_ALPHA_SEL_A 0 133 # define GRPH_ALPHA_SEL_R 1 134 # define GRPH_ALPHA_SEL_G 2 135 # define GRPH_ALPHA_SEL_B 3 136 # define INPUT_GAMMA_USE_LUT 0 137 # define INPUT_GAMMA_BYPASS 1 138 # define INPUT_GAMMA_SRGB_24 2 139 # define INPUT_GAMMA_XVYCC_222 3 140 141 # define INPUT_CSC_BYPASS 0 142 # define INPUT_CSC_PROG_COEFF 1 143 # define INPUT_CSC_PROG_SHARED_MATRIXA 2 144 145 # define OUTPUT_CSC_BYPASS 0 146 # define OUTPUT_CSC_TV_RGB 1 147 # define OUTPUT_CSC_YCBCR_601 2 148 # define OUTPUT_CSC_YCBCR_709 3 149 # define OUTPUT_CSC_PROG_COEFF 4 150 # define OUTPUT_CSC_PROG_SHARED_MATRIXB 5 151 152 # define DEGAMMA_BYPASS 0 153 # define DEGAMMA_SRGB_24 1 154 # define DEGAMMA_XVYCC_222 2 155 # define GAMUT_REMAP_BYPASS 0 156 # define GAMUT_REMAP_PROG_COEFF 1 157 # define GAMUT_REMAP_PROG_SHARED_MATRIXA 2 158 # define GAMUT_REMAP_PROG_SHARED_MATRIXB 3 159 160 # define REGAMMA_BYPASS 0 161 # define REGAMMA_SRGB_24 1 162 # define REGAMMA_XVYCC_222 2 163 # define REGAMMA_PROG_A 3 164 # define REGAMMA_PROG_B 4 165 166 # define FMT_CLAMP_6BPC 0 167 # define FMT_CLAMP_8BPC 1 168 # define FMT_CLAMP_10BPC 2 169 170 # define HDMI_24BIT_DEEP_COLOR 0 171 # define HDMI_30BIT_DEEP_COLOR 1 172 # define HDMI_36BIT_DEEP_COLOR 2 173 # define HDMI_ACR_HW 0 174 # define HDMI_ACR_32 1 175 # define HDMI_ACR_44 2 176 # define HDMI_ACR_48 3 177 # define HDMI_ACR_X1 1 178 # define HDMI_ACR_X2 2 179 # define HDMI_ACR_X4 4 180 # define AFMT_AVI_INFO_Y_RGB 0 181 # define AFMT_AVI_INFO_Y_YCBCR422 1 182 # define AFMT_AVI_INFO_Y_YCBCR444 2 183 184 #define NO_AUTO 0 185 #define ES_AUTO 1 186 #define GS_AUTO 2 187 #define ES_AND_GS_AUTO 3 188 189 # define ARRAY_MODE(x) ((x) << 2) 190 # define PIPE_CONFIG(x) ((x) << 6) 191 # define TILE_SPLIT(x) ((x) << 11) 192 # define MICRO_TILE_MODE_NEW(x) ((x) << 22) 193 # define SAMPLE_SPLIT(x) ((x) << 25) 194 # define BANK_WIDTH(x) ((x) << 0) 195 # define BANK_HEIGHT(x) ((x) << 2) 196 # define MACRO_TILE_ASPECT(x) ((x) << 4) 197 # define NUM_BANKS(x) ((x) << 6) 198 199 #define MSG_ENTER_RLC_SAFE_MODE 1 200 #define MSG_EXIT_RLC_SAFE_MODE 0 201 202 /* 203 * PM4 204 */ 205 #define PACKET_TYPE0 0 206 #define PACKET_TYPE1 1 207 #define PACKET_TYPE2 2 208 #define PACKET_TYPE3 3 209 210 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 211 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 212 #define CP_PACKET0_GET_REG(h) ((h) & 0xFFFF) 213 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 214 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 215 ((reg) & 0xFFFF) | \ 216 ((n) & 0x3FFF) << 16) 217 #define CP_PACKET2 0x80000000 218 #define PACKET2_PAD_SHIFT 0 219 #define PACKET2_PAD_MASK (0x3fffffff << 0) 220 221 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 222 223 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 224 (((op) & 0xFF) << 8) | \ 225 ((n) & 0x3FFF) << 16) 226 227 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 228 229 /* Packet 3 types */ 230 #define PACKET3_NOP 0x10 231 #define PACKET3_SET_BASE 0x11 232 #define PACKET3_BASE_INDEX(x) ((x) << 0) 233 #define CE_PARTITION_BASE 3 234 #define PACKET3_CLEAR_STATE 0x12 235 #define PACKET3_INDEX_BUFFER_SIZE 0x13 236 #define PACKET3_DISPATCH_DIRECT 0x15 237 #define PACKET3_DISPATCH_INDIRECT 0x16 238 #define PACKET3_ATOMIC_GDS 0x1D 239 #define PACKET3_ATOMIC_MEM 0x1E 240 #define PACKET3_OCCLUSION_QUERY 0x1F 241 #define PACKET3_SET_PREDICATION 0x20 242 #define PACKET3_REG_RMW 0x21 243 #define PACKET3_COND_EXEC 0x22 244 #define PACKET3_PRED_EXEC 0x23 245 #define PACKET3_DRAW_INDIRECT 0x24 246 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 247 #define PACKET3_INDEX_BASE 0x26 248 #define PACKET3_DRAW_INDEX_2 0x27 249 #define PACKET3_CONTEXT_CONTROL 0x28 250 #define PACKET3_INDEX_TYPE 0x2A 251 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 252 #define PACKET3_DRAW_INDEX_AUTO 0x2D 253 #define PACKET3_NUM_INSTANCES 0x2F 254 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 255 #define PACKET3_INDIRECT_BUFFER_CONST 0x33 256 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 257 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 258 #define PACKET3_DRAW_PREAMBLE 0x36 259 #define PACKET3_WRITE_DATA 0x37 260 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 261 /* 0 - register 262 * 1 - memory (sync - via GRBM) 263 * 2 - gl2 264 * 3 - gds 265 * 4 - reserved 266 * 5 - memory (async - direct) 267 */ 268 #define WR_ONE_ADDR (1 << 16) 269 #define WR_CONFIRM (1 << 20) 270 #define WRITE_DATA_CACHE_POLICY(x) ((x) << 25) 271 /* 0 - LRU 272 * 1 - Stream 273 */ 274 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 275 /* 0 - me 276 * 1 - pfp 277 * 2 - ce 278 */ 279 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 280 #define PACKET3_MEM_SEMAPHORE 0x39 281 # define PACKET3_SEM_USE_MAILBOX (0x1 << 16) 282 # define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */ 283 # define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */ 284 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 285 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 286 #define PACKET3_COPY_DW 0x3B 287 #define PACKET3_WAIT_REG_MEM 0x3C 288 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 289 /* 0 - always 290 * 1 - < 291 * 2 - <= 292 * 3 - == 293 * 4 - != 294 * 5 - >= 295 * 6 - > 296 */ 297 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 298 /* 0 - reg 299 * 1 - mem 300 */ 301 #define WAIT_REG_MEM_OPERATION(x) ((x) << 6) 302 /* 0 - wait_reg_mem 303 * 1 - wr_wait_wr_reg 304 */ 305 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 306 /* 0 - me 307 * 1 - pfp 308 */ 309 #define PACKET3_INDIRECT_BUFFER 0x3F 310 #define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22) 311 #define INDIRECT_BUFFER_VALID (1 << 23) 312 #define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28) 313 /* 0 - LRU 314 * 1 - Stream 315 * 2 - Bypass 316 */ 317 #define PACKET3_COPY_DATA 0x40 318 #define PACKET3_PFP_SYNC_ME 0x42 319 #define PACKET3_SURFACE_SYNC 0x43 320 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 321 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 322 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 323 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 324 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 325 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 326 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 327 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 328 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 329 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 330 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 331 # define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15) 332 # define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */ 333 # define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */ 334 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 335 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 336 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 337 # define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */ 338 # define PACKET3_CB_ACTION_ENA (1 << 25) 339 # define PACKET3_DB_ACTION_ENA (1 << 26) 340 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 341 # define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28) 342 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 343 #define PACKET3_COND_WRITE 0x45 344 #define PACKET3_EVENT_WRITE 0x46 345 #define EVENT_TYPE(x) ((x) << 0) 346 #define EVENT_INDEX(x) ((x) << 8) 347 /* 0 - any non-TS event 348 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_* 349 * 2 - SAMPLE_PIPELINESTAT 350 * 3 - SAMPLE_STREAMOUTSTAT* 351 * 4 - *S_PARTIAL_FLUSH 352 * 5 - EOP events 353 * 6 - EOS events 354 */ 355 #define PACKET3_EVENT_WRITE_EOP 0x47 356 #define EOP_TCL1_VOL_ACTION_EN (1 << 12) 357 #define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */ 358 #define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */ 359 #define EOP_TCL1_ACTION_EN (1 << 16) 360 #define EOP_TC_ACTION_EN (1 << 17) /* L2 */ 361 #define EOP_TCL2_VOLATILE (1 << 24) 362 #define EOP_CACHE_POLICY(x) ((x) << 25) 363 /* 0 - LRU 364 * 1 - Stream 365 * 2 - Bypass 366 */ 367 #define EOP_EXEC (1 << 28) /* For Trailing Fence */ 368 #define DATA_SEL(x) ((x) << 29) 369 /* 0 - discard 370 * 1 - send low 32bit data 371 * 2 - send 64bit data 372 * 3 - send 64bit GPU counter value 373 * 4 - send 64bit sys counter value 374 */ 375 #define INT_SEL(x) ((x) << 24) 376 /* 0 - none 377 * 1 - interrupt only (DATA_SEL = 0) 378 * 2 - interrupt when data write is confirmed 379 */ 380 #define DST_SEL(x) ((x) << 16) 381 /* 0 - MC 382 * 1 - TC/L2 383 */ 384 #define PACKET3_EVENT_WRITE_EOS 0x48 385 #define PACKET3_RELEASE_MEM 0x49 386 #define PACKET3_PREAMBLE_CNTL 0x4A 387 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 388 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 389 #define PACKET3_DMA_DATA 0x50 390 /* 1. header 391 * 2. CONTROL 392 * 3. SRC_ADDR_LO or DATA [31:0] 393 * 4. SRC_ADDR_HI [31:0] 394 * 5. DST_ADDR_LO [31:0] 395 * 6. DST_ADDR_HI [7:0] 396 * 7. COMMAND [30:21] | BYTE_COUNT [20:0] 397 */ 398 /* CONTROL */ 399 # define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0) 400 /* 0 - ME 401 * 1 - PFP 402 */ 403 # define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13) 404 /* 0 - LRU 405 * 1 - Stream 406 * 2 - Bypass 407 */ 408 # define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15) 409 # define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20) 410 /* 0 - DST_ADDR using DAS 411 * 1 - GDS 412 * 3 - DST_ADDR using L2 413 */ 414 # define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25) 415 /* 0 - LRU 416 * 1 - Stream 417 * 2 - Bypass 418 */ 419 # define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27) 420 # define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29) 421 /* 0 - SRC_ADDR using SAS 422 * 1 - GDS 423 * 2 - DATA 424 * 3 - SRC_ADDR using L2 425 */ 426 # define PACKET3_DMA_DATA_CP_SYNC (1 << 31) 427 /* COMMAND */ 428 # define PACKET3_DMA_DATA_DIS_WC (1 << 21) 429 # define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22) 430 /* 0 - none 431 * 1 - 8 in 16 432 * 2 - 8 in 32 433 * 3 - 8 in 64 434 */ 435 # define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24) 436 /* 0 - none 437 * 1 - 8 in 16 438 * 2 - 8 in 32 439 * 3 - 8 in 64 440 */ 441 # define PACKET3_DMA_DATA_CMD_SAS (1 << 26) 442 /* 0 - memory 443 * 1 - register 444 */ 445 # define PACKET3_DMA_DATA_CMD_DAS (1 << 27) 446 /* 0 - memory 447 * 1 - register 448 */ 449 # define PACKET3_DMA_DATA_CMD_SAIC (1 << 28) 450 # define PACKET3_DMA_DATA_CMD_DAIC (1 << 29) 451 # define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30) 452 #define PACKET3_ACQUIRE_MEM 0x58 453 #define PACKET3_REWIND 0x59 454 #define PACKET3_LOAD_UCONFIG_REG 0x5E 455 #define PACKET3_LOAD_SH_REG 0x5F 456 #define PACKET3_LOAD_CONFIG_REG 0x60 457 #define PACKET3_LOAD_CONTEXT_REG 0x61 458 #define PACKET3_SET_CONFIG_REG 0x68 459 #define PACKET3_SET_CONFIG_REG_START 0x00002000 460 #define PACKET3_SET_CONFIG_REG_END 0x00002c00 461 #define PACKET3_SET_CONTEXT_REG 0x69 462 #define PACKET3_SET_CONTEXT_REG_START 0x0000a000 463 #define PACKET3_SET_CONTEXT_REG_END 0x0000a400 464 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 465 #define PACKET3_SET_SH_REG 0x76 466 #define PACKET3_SET_SH_REG_START 0x00002c00 467 #define PACKET3_SET_SH_REG_END 0x00003000 468 #define PACKET3_SET_SH_REG_OFFSET 0x77 469 #define PACKET3_SET_QUEUE_REG 0x78 470 #define PACKET3_SET_UCONFIG_REG 0x79 471 #define PACKET3_SET_UCONFIG_REG_START 0x0000c000 472 #define PACKET3_SET_UCONFIG_REG_END 0x0000c400 473 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 474 #define PACKET3_SCRATCH_RAM_READ 0x7E 475 #define PACKET3_LOAD_CONST_RAM 0x80 476 #define PACKET3_WRITE_CONST_RAM 0x81 477 #define PACKET3_DUMP_CONST_RAM 0x83 478 #define PACKET3_INCREMENT_CE_COUNTER 0x84 479 #define PACKET3_INCREMENT_DE_COUNTER 0x85 480 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 481 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 482 #define PACKET3_SWITCH_BUFFER 0x8B 483 484 /* SDMA - first instance at 0xd000, second at 0xd800 */ 485 #define SDMA0_REGISTER_OFFSET 0x0 /* not a register */ 486 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ 487 #define SDMA_MAX_INSTANCE 2 488 489 #define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \ 490 (((sub_op) & 0xFF) << 8) | \ 491 (((op) & 0xFF) << 0)) 492 /* sDMA opcodes */ 493 #define SDMA_OPCODE_NOP 0 494 # define SDMA_NOP_COUNT(x) (((x) & 0x3FFF) << 16) 495 #define SDMA_OPCODE_COPY 1 496 # define SDMA_COPY_SUB_OPCODE_LINEAR 0 497 # define SDMA_COPY_SUB_OPCODE_TILED 1 498 # define SDMA_COPY_SUB_OPCODE_SOA 3 499 # define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4 500 # define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5 501 # define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6 502 #define SDMA_OPCODE_WRITE 2 503 # define SDMA_WRITE_SUB_OPCODE_LINEAR 0 504 # define SDMA_WRITE_SUB_OPCODE_TILED 1 505 #define SDMA_OPCODE_INDIRECT_BUFFER 4 506 #define SDMA_OPCODE_FENCE 5 507 #define SDMA_OPCODE_TRAP 6 508 #define SDMA_OPCODE_SEMAPHORE 7 509 # define SDMA_SEMAPHORE_EXTRA_O (1 << 13) 510 /* 0 - increment 511 * 1 - write 1 512 */ 513 # define SDMA_SEMAPHORE_EXTRA_S (1 << 14) 514 /* 0 - wait 515 * 1 - signal 516 */ 517 # define SDMA_SEMAPHORE_EXTRA_M (1 << 15) 518 /* mailbox */ 519 #define SDMA_OPCODE_POLL_REG_MEM 8 520 # define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10) 521 /* 0 - wait_reg_mem 522 * 1 - wr_wait_wr_reg 523 */ 524 # define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12) 525 /* 0 - always 526 * 1 - < 527 * 2 - <= 528 * 3 - == 529 * 4 - != 530 * 5 - >= 531 * 6 - > 532 */ 533 # define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15) 534 /* 0 = register 535 * 1 = memory 536 */ 537 #define SDMA_OPCODE_COND_EXEC 9 538 #define SDMA_OPCODE_CONSTANT_FILL 11 539 # define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14) 540 /* 0 = byte fill 541 * 2 = DW fill 542 */ 543 #define SDMA_OPCODE_GENERATE_PTE_PDE 12 544 #define SDMA_OPCODE_TIMESTAMP 13 545 # define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0 546 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1 547 # define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2 548 #define SDMA_OPCODE_SRBM_WRITE 14 549 # define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12) 550 /* byte mask */ 551 552 #define VCE_CMD_NO_OP 0x00000000 553 #define VCE_CMD_END 0x00000001 554 #define VCE_CMD_IB 0x00000002 555 #define VCE_CMD_FENCE 0x00000003 556 #define VCE_CMD_TRAP 0x00000004 557 #define VCE_CMD_IB_AUTO 0x00000005 558 #define VCE_CMD_SEMAPHORE 0x00000006 559 560 /* if PTR32, these are the bases for scratch and lds */ 561 #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 562 #define SHARED_BASE(x) ((x) << 16) /* LDS */ 563 564 #define KFD_CIK_SDMA_QUEUE_OFFSET (mmSDMA0_RLC1_RB_CNTL - mmSDMA0_RLC0_RB_CNTL) 565 566 /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 567 enum { 568 MTYPE_CACHED = 0, 569 MTYPE_NONCACHED = 3 570 }; 571 572 /* mmPA_SC_RASTER_CONFIG mask */ 573 #define RB_MAP_PKR0(x) ((x) << 0) 574 #define RB_MAP_PKR0_MASK (0x3 << 0) 575 #define RB_MAP_PKR1(x) ((x) << 2) 576 #define RB_MAP_PKR1_MASK (0x3 << 2) 577 #define RB_XSEL2(x) ((x) << 4) 578 #define RB_XSEL2_MASK (0x3 << 4) 579 #define RB_XSEL (1 << 6) 580 #define RB_YSEL (1 << 7) 581 #define PKR_MAP(x) ((x) << 8) 582 #define PKR_MAP_MASK (0x3 << 8) 583 #define PKR_XSEL(x) ((x) << 10) 584 #define PKR_XSEL_MASK (0x3 << 10) 585 #define PKR_YSEL(x) ((x) << 12) 586 #define PKR_YSEL_MASK (0x3 << 12) 587 #define SC_MAP(x) ((x) << 16) 588 #define SC_MAP_MASK (0x3 << 16) 589 #define SC_XSEL(x) ((x) << 18) 590 #define SC_XSEL_MASK (0x3 << 18) 591 #define SC_YSEL(x) ((x) << 20) 592 #define SC_YSEL_MASK (0x3 << 20) 593 #define SE_MAP(x) ((x) << 24) 594 #define SE_MAP_MASK (0x3 << 24) 595 #define SE_XSEL(x) ((x) << 26) 596 #define SE_XSEL_MASK (0x3 << 26) 597 #define SE_YSEL(x) ((x) << 28) 598 #define SE_YSEL_MASK (0x3 << 28) 599 600 /* mmPA_SC_RASTER_CONFIG_1 mask */ 601 #define SE_PAIR_MAP(x) ((x) << 0) 602 #define SE_PAIR_MAP_MASK (0x3 << 0) 603 #define SE_PAIR_XSEL(x) ((x) << 2) 604 #define SE_PAIR_XSEL_MASK (0x3 << 2) 605 #define SE_PAIR_YSEL(x) ((x) << 4) 606 #define SE_PAIR_YSEL_MASK (0x3 << 4) 607 608 #endif 609