1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "dce110_transform_v.h"
28 #include "basics/conversion.h"
29
30 /* include DCE11 register header files */
31 #include "dce/dce_11_0_d.h"
32 #include "dce/dce_11_0_sh_mask.h"
33 #include "dce/dce_11_0_enum.h"
34
35 enum {
36 OUTPUT_CSC_MATRIX_SIZE = 12
37 };
38
39 /* constrast:0 - 2.0, default 1.0 */
40 #define UNDERLAY_CONTRAST_DEFAULT 100
41 #define UNDERLAY_CONTRAST_MAX 200
42 #define UNDERLAY_CONTRAST_MIN 0
43 #define UNDERLAY_CONTRAST_STEP 1
44 #define UNDERLAY_CONTRAST_DIVIDER 100
45
46 /* Saturation: 0 - 2.0; default 1.0 */
47 #define UNDERLAY_SATURATION_DEFAULT 100 /*1.00*/
48 #define UNDERLAY_SATURATION_MIN 0
49 #define UNDERLAY_SATURATION_MAX 200 /* 2.00 */
50 #define UNDERLAY_SATURATION_STEP 1 /* 0.01 */
51 /*actual max overlay saturation
52 * value = UNDERLAY_SATURATION_MAX /UNDERLAY_SATURATION_DIVIDER
53 */
54
55 /* Hue */
56 #define UNDERLAY_HUE_DEFAULT 0
57 #define UNDERLAY_HUE_MIN -300
58 #define UNDERLAY_HUE_MAX 300
59 #define UNDERLAY_HUE_STEP 5
60 #define UNDERLAY_HUE_DIVIDER 10 /* HW range: -30 ~ +30 */
61 #define UNDERLAY_SATURATION_DIVIDER 100
62
63 /* Brightness: in DAL usually -.25 ~ .25.
64 * In MMD is -100 to +100 in 16-235 range; which when scaled to full range is
65 * ~-116 to +116. When normalized this is about 0.4566.
66 * With 100 divider this becomes 46, but we may use another for better precision
67 * The ideal one is 100/219 ((100/255)*(255/219)),
68 * i.e. min/max = +-100, divider = 219
69 * default 0.0
70 */
71 #define UNDERLAY_BRIGHTNESS_DEFAULT 0
72 #define UNDERLAY_BRIGHTNESS_MIN -46 /* ~116/255 */
73 #define UNDERLAY_BRIGHTNESS_MAX 46
74 #define UNDERLAY_BRIGHTNESS_STEP 1 /* .01 */
75 #define UNDERLAY_BRIGHTNESS_DIVIDER 100
76
77 static const struct out_csc_color_matrix global_color_matrix[] = {
78 { COLOR_SPACE_SRGB,
79 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
80 { COLOR_SPACE_SRGB_LIMITED,
81 { 0x1B60, 0, 0, 0x200, 0, 0x1B60, 0, 0x200, 0, 0, 0x1B60, 0x200} },
82 { COLOR_SPACE_YCBCR601,
83 { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x82F, 0x1012, 0x31F, 0x200, 0xFB47,
84 0xF6B9, 0xE00, 0x1000} },
85 { COLOR_SPACE_YCBCR709, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x5D2, 0x1394, 0x1FA,
86 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
87 /* TODO: correct values below */
88 { COLOR_SPACE_YCBCR601_LIMITED, { 0xE00, 0xF447, 0xFDB9, 0x1000, 0x991,
89 0x12C9, 0x3A6, 0x200, 0xFB47, 0xF6B9, 0xE00, 0x1000} },
90 { COLOR_SPACE_YCBCR709_LIMITED, { 0xE00, 0xF349, 0xFEB7, 0x1000, 0x6CE, 0x16E3,
91 0x24F, 0x200, 0xFCCB, 0xF535, 0xE00, 0x1000} },
92 { COLOR_SPACE_2020_RGB_FULLRANGE,
93 { 0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
94 { COLOR_SPACE_2020_RGB_LIMITEDRANGE,
95 { 0x1B67, 0, 0, 0x201, 0, 0x1B67, 0, 0x201, 0, 0, 0x1B67, 0x201} },
96 { COLOR_SPACE_2020_YCBCR_LIMITED, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868,
97 0x15B2, 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} },
98 { COLOR_SPACE_2020_YCBCR_FULL, { 0x1000, 0xF149, 0xFEB7, 0x1004, 0x0868, 0x15B2,
99 0x01E6, 0x201, 0xFB88, 0xF478, 0x1000, 0x1004} }
100 };
101
102 enum csc_color_mode {
103 /* 00 - BITS2:0 Bypass */
104 CSC_COLOR_MODE_GRAPHICS_BYPASS,
105 /* 01 - hard coded coefficient TV RGB */
106 CSC_COLOR_MODE_GRAPHICS_PREDEFINED,
107 /* 04 - programmable OUTPUT CSC coefficient */
108 CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC,
109 };
110
111 enum grph_color_adjust_option {
112 GRPH_COLOR_MATRIX_HW_DEFAULT = 1,
113 GRPH_COLOR_MATRIX_SW
114 };
115
program_color_matrix_v(struct dce_transform * xfm_dce,const struct out_csc_color_matrix * tbl_entry,enum grph_color_adjust_option options)116 static void program_color_matrix_v(
117 struct dce_transform *xfm_dce,
118 const struct out_csc_color_matrix *tbl_entry,
119 enum grph_color_adjust_option options)
120 {
121 (void)options;
122 struct dc_context *ctx = xfm_dce->base.ctx;
123 uint32_t cntl_value = dm_read_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL);
124 bool use_set_a = (get_reg_field_value(cntl_value,
125 COL_MAN_OUTPUT_CSC_CONTROL,
126 OUTPUT_CSC_MODE) != 4);
127
128 set_reg_field_value(
129 cntl_value,
130 0,
131 COL_MAN_OUTPUT_CSC_CONTROL,
132 OUTPUT_CSC_MODE);
133
134 if (use_set_a) {
135 {
136 uint32_t value = 0;
137 uint32_t addr = mmOUTPUT_CSC_C11_C12_A;
138 /* fixed S2.13 format */
139 set_reg_field_value(
140 value,
141 tbl_entry->regval[0],
142 OUTPUT_CSC_C11_C12_A,
143 OUTPUT_CSC_C11_A);
144
145 set_reg_field_value(
146 value,
147 tbl_entry->regval[1],
148 OUTPUT_CSC_C11_C12_A,
149 OUTPUT_CSC_C12_A);
150
151 dm_write_reg(ctx, addr, value);
152 }
153 {
154 uint32_t value = 0;
155 uint32_t addr = mmOUTPUT_CSC_C13_C14_A;
156 /* fixed S2.13 format */
157 set_reg_field_value(
158 value,
159 tbl_entry->regval[2],
160 OUTPUT_CSC_C13_C14_A,
161 OUTPUT_CSC_C13_A);
162 /* fixed S0.13 format */
163 set_reg_field_value(
164 value,
165 tbl_entry->regval[3],
166 OUTPUT_CSC_C13_C14_A,
167 OUTPUT_CSC_C14_A);
168
169 dm_write_reg(ctx, addr, value);
170 }
171 {
172 uint32_t value = 0;
173 uint32_t addr = mmOUTPUT_CSC_C21_C22_A;
174 /* fixed S2.13 format */
175 set_reg_field_value(
176 value,
177 tbl_entry->regval[4],
178 OUTPUT_CSC_C21_C22_A,
179 OUTPUT_CSC_C21_A);
180 /* fixed S2.13 format */
181 set_reg_field_value(
182 value,
183 tbl_entry->regval[5],
184 OUTPUT_CSC_C21_C22_A,
185 OUTPUT_CSC_C22_A);
186
187 dm_write_reg(ctx, addr, value);
188 }
189 {
190 uint32_t value = 0;
191 uint32_t addr = mmOUTPUT_CSC_C23_C24_A;
192 /* fixed S2.13 format */
193 set_reg_field_value(
194 value,
195 tbl_entry->regval[6],
196 OUTPUT_CSC_C23_C24_A,
197 OUTPUT_CSC_C23_A);
198 /* fixed S0.13 format */
199 set_reg_field_value(
200 value,
201 tbl_entry->regval[7],
202 OUTPUT_CSC_C23_C24_A,
203 OUTPUT_CSC_C24_A);
204
205 dm_write_reg(ctx, addr, value);
206 }
207 {
208 uint32_t value = 0;
209 uint32_t addr = mmOUTPUT_CSC_C31_C32_A;
210 /* fixed S2.13 format */
211 set_reg_field_value(
212 value,
213 tbl_entry->regval[8],
214 OUTPUT_CSC_C31_C32_A,
215 OUTPUT_CSC_C31_A);
216 /* fixed S0.13 format */
217 set_reg_field_value(
218 value,
219 tbl_entry->regval[9],
220 OUTPUT_CSC_C31_C32_A,
221 OUTPUT_CSC_C32_A);
222
223 dm_write_reg(ctx, addr, value);
224 }
225 {
226 uint32_t value = 0;
227 uint32_t addr = mmOUTPUT_CSC_C33_C34_A;
228 /* fixed S2.13 format */
229 set_reg_field_value(
230 value,
231 tbl_entry->regval[10],
232 OUTPUT_CSC_C33_C34_A,
233 OUTPUT_CSC_C33_A);
234 /* fixed S0.13 format */
235 set_reg_field_value(
236 value,
237 tbl_entry->regval[11],
238 OUTPUT_CSC_C33_C34_A,
239 OUTPUT_CSC_C34_A);
240
241 dm_write_reg(ctx, addr, value);
242 }
243 set_reg_field_value(
244 cntl_value,
245 4,
246 COL_MAN_OUTPUT_CSC_CONTROL,
247 OUTPUT_CSC_MODE);
248 } else {
249 {
250 uint32_t value = 0;
251 uint32_t addr = mmOUTPUT_CSC_C11_C12_B;
252 /* fixed S2.13 format */
253 set_reg_field_value(
254 value,
255 tbl_entry->regval[0],
256 OUTPUT_CSC_C11_C12_B,
257 OUTPUT_CSC_C11_B);
258
259 set_reg_field_value(
260 value,
261 tbl_entry->regval[1],
262 OUTPUT_CSC_C11_C12_B,
263 OUTPUT_CSC_C12_B);
264
265 dm_write_reg(ctx, addr, value);
266 }
267 {
268 uint32_t value = 0;
269 uint32_t addr = mmOUTPUT_CSC_C13_C14_B;
270 /* fixed S2.13 format */
271 set_reg_field_value(
272 value,
273 tbl_entry->regval[2],
274 OUTPUT_CSC_C13_C14_B,
275 OUTPUT_CSC_C13_B);
276 /* fixed S0.13 format */
277 set_reg_field_value(
278 value,
279 tbl_entry->regval[3],
280 OUTPUT_CSC_C13_C14_B,
281 OUTPUT_CSC_C14_B);
282
283 dm_write_reg(ctx, addr, value);
284 }
285 {
286 uint32_t value = 0;
287 uint32_t addr = mmOUTPUT_CSC_C21_C22_B;
288 /* fixed S2.13 format */
289 set_reg_field_value(
290 value,
291 tbl_entry->regval[4],
292 OUTPUT_CSC_C21_C22_B,
293 OUTPUT_CSC_C21_B);
294 /* fixed S2.13 format */
295 set_reg_field_value(
296 value,
297 tbl_entry->regval[5],
298 OUTPUT_CSC_C21_C22_B,
299 OUTPUT_CSC_C22_B);
300
301 dm_write_reg(ctx, addr, value);
302 }
303 {
304 uint32_t value = 0;
305 uint32_t addr = mmOUTPUT_CSC_C23_C24_B;
306 /* fixed S2.13 format */
307 set_reg_field_value(
308 value,
309 tbl_entry->regval[6],
310 OUTPUT_CSC_C23_C24_B,
311 OUTPUT_CSC_C23_B);
312 /* fixed S0.13 format */
313 set_reg_field_value(
314 value,
315 tbl_entry->regval[7],
316 OUTPUT_CSC_C23_C24_B,
317 OUTPUT_CSC_C24_B);
318
319 dm_write_reg(ctx, addr, value);
320 }
321 {
322 uint32_t value = 0;
323 uint32_t addr = mmOUTPUT_CSC_C31_C32_B;
324 /* fixed S2.13 format */
325 set_reg_field_value(
326 value,
327 tbl_entry->regval[8],
328 OUTPUT_CSC_C31_C32_B,
329 OUTPUT_CSC_C31_B);
330 /* fixed S0.13 format */
331 set_reg_field_value(
332 value,
333 tbl_entry->regval[9],
334 OUTPUT_CSC_C31_C32_B,
335 OUTPUT_CSC_C32_B);
336
337 dm_write_reg(ctx, addr, value);
338 }
339 {
340 uint32_t value = 0;
341 uint32_t addr = mmOUTPUT_CSC_C33_C34_B;
342 /* fixed S2.13 format */
343 set_reg_field_value(
344 value,
345 tbl_entry->regval[10],
346 OUTPUT_CSC_C33_C34_B,
347 OUTPUT_CSC_C33_B);
348 /* fixed S0.13 format */
349 set_reg_field_value(
350 value,
351 tbl_entry->regval[11],
352 OUTPUT_CSC_C33_C34_B,
353 OUTPUT_CSC_C34_B);
354
355 dm_write_reg(ctx, addr, value);
356 }
357 set_reg_field_value(
358 cntl_value,
359 5,
360 COL_MAN_OUTPUT_CSC_CONTROL,
361 OUTPUT_CSC_MODE);
362 }
363
364 dm_write_reg(ctx, mmCOL_MAN_OUTPUT_CSC_CONTROL, cntl_value);
365 }
366
configure_graphics_mode_v(struct dce_transform * xfm_dce,enum csc_color_mode config,enum graphics_csc_adjust_type csc_adjust_type,enum dc_color_space color_space)367 static bool configure_graphics_mode_v(
368 struct dce_transform *xfm_dce,
369 enum csc_color_mode config,
370 enum graphics_csc_adjust_type csc_adjust_type,
371 enum dc_color_space color_space)
372 {
373 struct dc_context *ctx = xfm_dce->base.ctx;
374 uint32_t addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
375 uint32_t value = dm_read_reg(ctx, addr);
376
377 set_reg_field_value(
378 value,
379 0,
380 COL_MAN_OUTPUT_CSC_CONTROL,
381 OUTPUT_CSC_MODE);
382
383 if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_SW) {
384 if (config == CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC)
385 return true;
386
387 switch (color_space) {
388 case COLOR_SPACE_SRGB:
389 /* by pass */
390 set_reg_field_value(
391 value,
392 0,
393 COL_MAN_OUTPUT_CSC_CONTROL,
394 OUTPUT_CSC_MODE);
395 break;
396 case COLOR_SPACE_SRGB_LIMITED:
397 /* not supported for underlay on CZ */
398 return false;
399
400 case COLOR_SPACE_YCBCR601_LIMITED:
401 /* YCbCr601 */
402 set_reg_field_value(
403 value,
404 2,
405 COL_MAN_OUTPUT_CSC_CONTROL,
406 OUTPUT_CSC_MODE);
407 break;
408 case COLOR_SPACE_YCBCR709:
409 case COLOR_SPACE_YCBCR709_LIMITED:
410 /* YCbCr709 */
411 set_reg_field_value(
412 value,
413 3,
414 COL_MAN_OUTPUT_CSC_CONTROL,
415 OUTPUT_CSC_MODE);
416 break;
417 default:
418 return false;
419 }
420
421 } else if (csc_adjust_type == GRAPHICS_CSC_ADJUST_TYPE_HW) {
422 switch (color_space) {
423 case COLOR_SPACE_SRGB:
424 /* by pass */
425 set_reg_field_value(
426 value,
427 0,
428 COL_MAN_OUTPUT_CSC_CONTROL,
429 OUTPUT_CSC_MODE);
430 break;
431 case COLOR_SPACE_SRGB_LIMITED:
432 /* not supported for underlay on CZ */
433 return false;
434 case COLOR_SPACE_YCBCR601:
435 case COLOR_SPACE_YCBCR601_LIMITED:
436 /* YCbCr601 */
437 set_reg_field_value(
438 value,
439 2,
440 COL_MAN_OUTPUT_CSC_CONTROL,
441 OUTPUT_CSC_MODE);
442 break;
443 case COLOR_SPACE_YCBCR709:
444 case COLOR_SPACE_YCBCR709_LIMITED:
445 /* YCbCr709 */
446 set_reg_field_value(
447 value,
448 3,
449 COL_MAN_OUTPUT_CSC_CONTROL,
450 OUTPUT_CSC_MODE);
451 break;
452 default:
453 return false;
454 }
455
456 } else
457 /* by pass */
458 set_reg_field_value(
459 value,
460 0,
461 COL_MAN_OUTPUT_CSC_CONTROL,
462 OUTPUT_CSC_MODE);
463
464 addr = mmCOL_MAN_OUTPUT_CSC_CONTROL;
465 dm_write_reg(ctx, addr, value);
466
467 return true;
468 }
469
470 /*TODO: color depth is not correct when this is called*/
set_Denormalization(struct transform * xfm,enum dc_color_depth color_depth)471 static void set_Denormalization(struct transform *xfm,
472 enum dc_color_depth color_depth)
473 {
474 uint32_t value = dm_read_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL);
475
476 switch (color_depth) {
477 case COLOR_DEPTH_888:
478 /* 255/256 for 8 bit output color depth */
479 set_reg_field_value(
480 value,
481 1,
482 DENORM_CLAMP_CONTROL,
483 DENORM_MODE);
484 break;
485 case COLOR_DEPTH_101010:
486 /* 1023/1024 for 10 bit output color depth */
487 set_reg_field_value(
488 value,
489 2,
490 DENORM_CLAMP_CONTROL,
491 DENORM_MODE);
492 break;
493 case COLOR_DEPTH_121212:
494 /* 4095/4096 for 12 bit output color depth */
495 set_reg_field_value(
496 value,
497 3,
498 DENORM_CLAMP_CONTROL,
499 DENORM_MODE);
500 break;
501 default:
502 /* not valid case */
503 break;
504 }
505
506 set_reg_field_value(
507 value,
508 1,
509 DENORM_CLAMP_CONTROL,
510 DENORM_10BIT_OUT);
511
512 dm_write_reg(xfm->ctx, mmDENORM_CLAMP_CONTROL, value);
513 }
514
515 struct input_csc_matrix {
516 enum dc_color_space color_space;
517 uint32_t regval[12];
518 };
519
520 static const struct input_csc_matrix input_csc_matrix[] = {
521 {COLOR_SPACE_SRGB,
522 /*1_1 1_2 1_3 1_4 2_1 2_2 2_3 2_4 3_1 3_2 3_3 3_4 */
523 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
524 {COLOR_SPACE_SRGB_LIMITED,
525 {0x2000, 0, 0, 0, 0, 0x2000, 0, 0, 0, 0, 0x2000, 0} },
526 {COLOR_SPACE_YCBCR601,
527 {0x2cdd, 0x2000, 0x0, 0xe991, 0xe926, 0x2000, 0xf4fd, 0x10ef,
528 0x0, 0x2000, 0x38b4, 0xe3a6} },
529 {COLOR_SPACE_YCBCR601_LIMITED,
530 {0x3353, 0x2568, 0x0, 0xe400, 0xe5dc, 0x2568, 0xf367, 0x1108,
531 0x0, 0x2568, 0x40de, 0xdd3a} },
532 {COLOR_SPACE_YCBCR709,
533 {0x3265, 0x2000, 0, 0xe6ce, 0xf105, 0x2000, 0xfa01, 0xa7d, 0,
534 0x2000, 0x3b61, 0xe24f} },
535 {COLOR_SPACE_YCBCR709_LIMITED,
536 {0x39a6, 0x2568, 0, 0xe0d6, 0xeedd, 0x2568, 0xf925, 0x9a8, 0,
537 0x2568, 0x43ee, 0xdbb2} }
538 };
539
program_input_csc(struct transform * xfm,enum dc_color_space color_space)540 static void program_input_csc(
541 struct transform *xfm, enum dc_color_space color_space)
542 {
543 int arr_size = sizeof(input_csc_matrix)/sizeof(struct input_csc_matrix);
544 struct dc_context *ctx = xfm->ctx;
545 const uint32_t *regval = NULL;
546 bool use_set_a;
547 uint32_t value;
548 int i;
549
550 for (i = 0; i < arr_size; i++)
551 if (input_csc_matrix[i].color_space == color_space) {
552 regval = input_csc_matrix[i].regval;
553 break;
554 }
555 if (regval == NULL) {
556 BREAK_TO_DEBUGGER();
557 return;
558 }
559
560 /*
561 * 1 == set A, the logic is 'if currently we're not using set A,
562 * then use set A, otherwise use set B'
563 */
564 value = dm_read_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL);
565 use_set_a = get_reg_field_value(
566 value, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_MODE) != 1;
567
568 if (use_set_a) {
569 /* fixed S2.13 format */
570 value = 0;
571 set_reg_field_value(
572 value, regval[0], INPUT_CSC_C11_C12_A, INPUT_CSC_C11_A);
573 set_reg_field_value(
574 value, regval[1], INPUT_CSC_C11_C12_A, INPUT_CSC_C12_A);
575 dm_write_reg(ctx, mmINPUT_CSC_C11_C12_A, value);
576
577 value = 0;
578 set_reg_field_value(
579 value, regval[2], INPUT_CSC_C13_C14_A, INPUT_CSC_C13_A);
580 set_reg_field_value(
581 value, regval[3], INPUT_CSC_C13_C14_A, INPUT_CSC_C14_A);
582 dm_write_reg(ctx, mmINPUT_CSC_C13_C14_A, value);
583
584 value = 0;
585 set_reg_field_value(
586 value, regval[4], INPUT_CSC_C21_C22_A, INPUT_CSC_C21_A);
587 set_reg_field_value(
588 value, regval[5], INPUT_CSC_C21_C22_A, INPUT_CSC_C22_A);
589 dm_write_reg(ctx, mmINPUT_CSC_C21_C22_A, value);
590
591 value = 0;
592 set_reg_field_value(
593 value, regval[6], INPUT_CSC_C23_C24_A, INPUT_CSC_C23_A);
594 set_reg_field_value(
595 value, regval[7], INPUT_CSC_C23_C24_A, INPUT_CSC_C24_A);
596 dm_write_reg(ctx, mmINPUT_CSC_C23_C24_A, value);
597
598 value = 0;
599 set_reg_field_value(
600 value, regval[8], INPUT_CSC_C31_C32_A, INPUT_CSC_C31_A);
601 set_reg_field_value(
602 value, regval[9], INPUT_CSC_C31_C32_A, INPUT_CSC_C32_A);
603 dm_write_reg(ctx, mmINPUT_CSC_C31_C32_A, value);
604
605 value = 0;
606 set_reg_field_value(
607 value, regval[10], INPUT_CSC_C33_C34_A, INPUT_CSC_C33_A);
608 set_reg_field_value(
609 value, regval[11], INPUT_CSC_C33_C34_A, INPUT_CSC_C34_A);
610 dm_write_reg(ctx, mmINPUT_CSC_C33_C34_A, value);
611 } else {
612 /* fixed S2.13 format */
613 value = 0;
614 set_reg_field_value(
615 value, regval[0], INPUT_CSC_C11_C12_B, INPUT_CSC_C11_B);
616 set_reg_field_value(
617 value, regval[1], INPUT_CSC_C11_C12_B, INPUT_CSC_C12_B);
618 dm_write_reg(ctx, mmINPUT_CSC_C11_C12_B, value);
619
620 value = 0;
621 set_reg_field_value(
622 value, regval[2], INPUT_CSC_C13_C14_B, INPUT_CSC_C13_B);
623 set_reg_field_value(
624 value, regval[3], INPUT_CSC_C13_C14_B, INPUT_CSC_C14_B);
625 dm_write_reg(ctx, mmINPUT_CSC_C13_C14_B, value);
626
627 value = 0;
628 set_reg_field_value(
629 value, regval[4], INPUT_CSC_C21_C22_B, INPUT_CSC_C21_B);
630 set_reg_field_value(
631 value, regval[5], INPUT_CSC_C21_C22_B, INPUT_CSC_C22_B);
632 dm_write_reg(ctx, mmINPUT_CSC_C21_C22_B, value);
633
634 value = 0;
635 set_reg_field_value(
636 value, regval[6], INPUT_CSC_C23_C24_B, INPUT_CSC_C23_B);
637 set_reg_field_value(
638 value, regval[7], INPUT_CSC_C23_C24_B, INPUT_CSC_C24_B);
639 dm_write_reg(ctx, mmINPUT_CSC_C23_C24_B, value);
640
641 value = 0;
642 set_reg_field_value(
643 value, regval[8], INPUT_CSC_C31_C32_B, INPUT_CSC_C31_B);
644 set_reg_field_value(
645 value, regval[9], INPUT_CSC_C31_C32_B, INPUT_CSC_C32_B);
646 dm_write_reg(ctx, mmINPUT_CSC_C31_C32_B, value);
647
648 value = 0;
649 set_reg_field_value(
650 value, regval[10], INPUT_CSC_C33_C34_B, INPUT_CSC_C33_B);
651 set_reg_field_value(
652 value, regval[11], INPUT_CSC_C33_C34_B, INPUT_CSC_C34_B);
653 dm_write_reg(ctx, mmINPUT_CSC_C33_C34_B, value);
654 }
655
656 /* KK: leave INPUT_CSC_CONVERSION_MODE at default */
657 value = 0;
658 /*
659 * select 8.4 input type instead of default 12.0. From the discussion
660 * with HW team, this format depends on the UNP surface format, so for
661 * 8-bit we should select 8.4 (4 bits truncated). For 10 it should be
662 * 10.2. For Carrizo we only support 8-bit surfaces on underlay pipe
663 * so we can always keep this at 8.4 (input_type=2). If the later asics
664 * start supporting 10+ bits, we will have a problem: surface
665 * programming including UNP_GRPH* is being done in DalISR after this,
666 * so either we pass surface format to here, or move this logic to ISR
667 */
668
669 set_reg_field_value(
670 value, 2, COL_MAN_INPUT_CSC_CONTROL, INPUT_CSC_INPUT_TYPE);
671 set_reg_field_value(
672 value,
673 use_set_a ? 1 : 2,
674 COL_MAN_INPUT_CSC_CONTROL,
675 INPUT_CSC_MODE);
676
677 dm_write_reg(ctx, mmCOL_MAN_INPUT_CSC_CONTROL, value);
678 }
679
dce110_opp_v_set_csc_default(struct transform * xfm,const struct default_adjustment * default_adjust)680 void dce110_opp_v_set_csc_default(
681 struct transform *xfm,
682 const struct default_adjustment *default_adjust)
683 {
684 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
685 enum csc_color_mode config =
686 CSC_COLOR_MODE_GRAPHICS_PREDEFINED;
687
688 if (default_adjust->force_hw_default == false) {
689 const struct out_csc_color_matrix *elm;
690 /* currently parameter not in use */
691 enum grph_color_adjust_option option;
692 uint32_t i;
693 /*
694 * HW default false we program locally defined matrix
695 * HW default true we use predefined hw matrix and we
696 * do not need to program matrix
697 * OEM wants the HW default via runtime parameter.
698 */
699 option = GRPH_COLOR_MATRIX_SW;
700
701 for (i = 0; i < ARRAY_SIZE(global_color_matrix); ++i) {
702 elm = &global_color_matrix[i];
703 if (elm->color_space != default_adjust->out_color_space)
704 continue;
705 /* program the matrix with default values from this
706 * file
707 */
708 program_color_matrix_v(xfm_dce, elm, option);
709 config = CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
710 break;
711 }
712 }
713
714 program_input_csc(xfm, default_adjust->in_color_space);
715
716 /* configure the what we programmed :
717 * 1. Default values from this file
718 * 2. Use hardware default from ROM_A and we do not need to program
719 * matrix
720 */
721
722 configure_graphics_mode_v(xfm_dce, config,
723 default_adjust->csc_adjust_type,
724 default_adjust->out_color_space);
725
726 set_Denormalization(xfm, default_adjust->color_depth);
727 }
728
dce110_opp_v_set_csc_adjustment(struct transform * xfm,const struct out_csc_color_matrix * tbl_entry)729 void dce110_opp_v_set_csc_adjustment(
730 struct transform *xfm,
731 const struct out_csc_color_matrix *tbl_entry)
732 {
733 struct dce_transform *xfm_dce = TO_DCE_TRANSFORM(xfm);
734 enum csc_color_mode config =
735 CSC_COLOR_MODE_GRAPHICS_OUTPUT_CSC;
736
737 program_color_matrix_v(
738 xfm_dce, tbl_entry, GRPH_COLOR_MATRIX_SW);
739
740 /* We did everything ,now program DxOUTPUT_CSC_CONTROL */
741 configure_graphics_mode_v(xfm_dce, config, GRAPHICS_CSC_ADJUST_TYPE_SW,
742 tbl_entry->color_space);
743
744 /*TODO: Check if denormalization is needed*/
745 /*set_Denormalization(opp, adjust->color_depth);*/
746 }
747