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Searched refs:OMAP2_L4_IO_ADDRESS (Results 1 – 25 of 25) sorted by relevance

/linux/arch/arm/mach-omap2/
H A Dio.c424 omap2_set_globals_tap(OMAP242X_CLASS, OMAP2_L4_IO_ADDRESS(0x48014000)); in omap2420_init_early()
443 omap2_set_globals_tap(OMAP243X_CLASS, OMAP2_L4_IO_ADDRESS(0x4900a000)); in omap2430_init_early()
466 omap2_set_globals_tap(OMAP343X_CLASS, OMAP2_L4_IO_ADDRESS(0x4830A000)); in omap3_init_early()
514 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); in ti814x_init_early()
531 OMAP2_L4_IO_ADDRESS(TI81XX_TAP_BASE)); in ti816x_init_early()
593 OMAP2_L4_IO_ADDRESS(OMAP443X_SCM_BASE)); in omap4430_init_early()
594 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE)); in omap4430_init_early()
620 OMAP2_L4_IO_ADDRESS(OMAP54XX_SCM_BASE)); in omap5_init_early()
621 omap2_set_globals_prcm_mpu(OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE)); in omap5_init_early()
645 OMAP2_L4_IO_ADDRESS(DRA7XX_TAP_BASE)); in dra7xx_init_early()
[all …]
H A Dcontrol.h23 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
25 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
27 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
32 OMAP2_L4_IO_ADDRESS(OMAP242X_CTRL_BASE + (reg))
34 OMAP2_L4_IO_ADDRESS(OMAP243X_CTRL_BASE + (reg))
36 OMAP2_L4_IO_ADDRESS(OMAP343X_CTRL_BASE + (reg))
363 #define OMAP343X_SCRATCHPAD_REGADDR(reg) OMAP2_L4_IO_ADDRESS(\
H A Dcm2xxx.h20 OMAP2_L4_IO_ADDRESS(OMAP2420_CM_BASE + (module) + (reg))
22 OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
H A Dprm2xxx.h21 OMAP2_L4_IO_ADDRESS(OMAP2420_PRM_BASE + (module) + (reg))
23 OMAP2_L4_IO_ADDRESS(OMAP2430_PRM_BASE + (module) + (reg))
H A Dscrm44xx.h22 OMAP2_L4_IO_ADDRESS(OMAP4_SCRM_BASE + (reg))
H A Dcm1_54xx.h25 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_AON_BASE + (inst) + (reg))
H A Dcm1_44xx.h29 OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (inst) + (reg))
H A Dprm54xx.h27 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRM_BASE + (inst) + (reg))
H A Dcm1_7xx.h26 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_AON_BASE + (inst) + (reg))
H A Dcm2_44xx.h29 OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (inst) + (reg))
H A Dcm2_54xx.h25 OMAP2_L4_IO_ADDRESS(OMAP54XX_CM_CORE_BASE + (inst) + (reg))
H A Dcm2_7xx.h26 OMAP2_L4_IO_ADDRESS(DRA7XX_CM_CORE_BASE + (inst) + (reg))
H A Dprm7xx.h29 OMAP2_L4_IO_ADDRESS(DRA7XX_PRM_BASE + (inst) + (reg))
H A Dprcm_mpu7xx.h27 OMAP2_L4_IO_ADDRESS(DRA7XX_PRCM_MPU_BASE + (inst) + (reg))
H A Dprcm_mpu54xx.h27 OMAP2_L4_IO_ADDRESS(OMAP54XX_PRCM_MPU_BASE + (inst) + (reg))
H A Dcm3xxx.h20 OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
H A Dprm44xx.h31 OMAP2_L4_IO_ADDRESS(OMAP4430_PRM_BASE + (inst) + (reg))
H A Dprcm_mpu44xx.h30 OMAP2_L4_IO_ADDRESS(OMAP4430_PRCM_MPU_BASE + (inst) + (reg))
H A Dprm3xxx.h21 OMAP2_L4_IO_ADDRESS(OMAP3430_PRM_BASE + (module) + (reg))
H A Diomap.h37 #define OMAP2_L4_IO_ADDRESS(pa) IOMEM((pa) + OMAP2_L4_IO_OFFSET) /* L4 */ macro
H A Domap-smp.c270 cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base()); in omap4_smp_init_cpus()
H A Dcontrol.c224 writel_relaxed(l, OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD + 4)); in omap3_ctrl_write_boot_mode()
333 scratchpad_address = OMAP2_L4_IO_ADDRESS(OMAP343X_SCRATCHPAD); in omap3_save_scratchpad_contents()
H A Dsram242x.S125 .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
222 .word OMAP2_L4_IO_ADDRESS(OMAP2420_32KSYNCT_BASE + 0x010)
H A Dsram243x.S125 .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
222 .word OMAP2_L4_IO_ADDRESS(OMAP2430_32KSYNCT_BASE + 0x010)
H A Dvc.c716 writel_relaxed(val, OMAP2_L4_IO_ADDRESS(OMAP4_CTRL_MODULE_PAD_WKUP + in omap4_vc_i2c_timing_init()