1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright(c) 1999 - 2018 Intel Corporation. */ 3 4 #ifndef _E1000_DEFINES_H_ 5 #define _E1000_DEFINES_H_ 6 7 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 8 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 9 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 10 11 /* Definitions for power management and wakeup registers */ 12 /* Wake Up Control */ 13 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 14 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 15 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 16 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */ 18 19 /* Wake Up Filter Control */ 20 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 21 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 22 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 23 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 24 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 25 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 26 27 /* Wake Up Status */ 28 #define E1000_WUS_LNKC E1000_WUFC_LNKC 29 #define E1000_WUS_MAG E1000_WUFC_MAG 30 #define E1000_WUS_EX E1000_WUFC_EX 31 #define E1000_WUS_MC E1000_WUFC_MC 32 #define E1000_WUS_BC E1000_WUFC_BC 33 34 /* Extended Device Control */ 35 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 36 #define E1000_CTRL_EXT_DPG_EN 0x00000008 /* Dynamic Power Gating Enable */ 37 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 38 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 39 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 40 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 41 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 42 #define E1000_CTRL_EXT_DMA_DYN_CLK_EN 0x00080000 /* DMA Dynamic Clock Gating */ 43 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 44 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 45 #define E1000_CTRL_EXT_EIAME 0x01000000 46 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 47 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */ 48 #define E1000_CTRL_EXT_PBA_CLR 0x80000000 /* PBA Clear */ 49 #define E1000_CTRL_EXT_LSECCK 0x00001000 50 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 51 52 /* Receive Descriptor bit definitions */ 53 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 54 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 55 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 56 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 57 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 58 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 59 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 60 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 61 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 62 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 63 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 64 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 65 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 66 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 67 68 #define E1000_RXDEXT_STATERR_TST 0x00000100 /* Time Stamp taken */ 69 #define E1000_RXDEXT_STATERR_CE 0x01000000 70 #define E1000_RXDEXT_STATERR_SE 0x02000000 71 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 72 #define E1000_RXDEXT_STATERR_CXE 0x10000000 73 #define E1000_RXDEXT_STATERR_RXE 0x80000000 74 75 /* mask to determine if packets should be dropped due to frame errors */ 76 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 77 E1000_RXD_ERR_CE | \ 78 E1000_RXD_ERR_SE | \ 79 E1000_RXD_ERR_SEQ | \ 80 E1000_RXD_ERR_CXE | \ 81 E1000_RXD_ERR_RXE) 82 83 /* Same mask, but for extended and packet split descriptors */ 84 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 85 E1000_RXDEXT_STATERR_CE | \ 86 E1000_RXDEXT_STATERR_SE | \ 87 E1000_RXDEXT_STATERR_SEQ | \ 88 E1000_RXDEXT_STATERR_CXE | \ 89 E1000_RXDEXT_STATERR_RXE) 90 91 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 92 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 93 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 94 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 95 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 96 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 97 98 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 99 100 /* Management Control */ 101 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 102 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 103 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 104 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 105 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 106 /* Enable MAC address filtering */ 107 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 108 /* Enable MNG packets to host memory */ 109 #define E1000_MANC_EN_MNG2HOST 0x00200000 110 111 #define E1000_MANC2H_PORT_623 0x00000020 /* Port 0x26f */ 112 #define E1000_MANC2H_PORT_664 0x00000040 /* Port 0x298 */ 113 #define E1000_MDEF_PORT_623 0x00000800 /* Port 0x26f */ 114 #define E1000_MDEF_PORT_664 0x00000400 /* Port 0x298 */ 115 116 /* Receive Control */ 117 #define E1000_RCTL_EN 0x00000002 /* enable */ 118 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 119 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 120 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 121 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 122 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 123 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 124 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 125 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 126 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* Rx desc min threshold size */ 127 #define E1000_RCTL_RDMTS_HEX 0x00010000 128 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 129 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 130 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 131 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 132 #define E1000_RCTL_SZ_2048 0x00000000 /* Rx buffer size 2048 */ 133 #define E1000_RCTL_SZ_1024 0x00010000 /* Rx buffer size 1024 */ 134 #define E1000_RCTL_SZ_512 0x00020000 /* Rx buffer size 512 */ 135 #define E1000_RCTL_SZ_256 0x00030000 /* Rx buffer size 256 */ 136 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 137 #define E1000_RCTL_SZ_16384 0x00010000 /* Rx buffer size 16384 */ 138 #define E1000_RCTL_SZ_8192 0x00020000 /* Rx buffer size 8192 */ 139 #define E1000_RCTL_SZ_4096 0x00030000 /* Rx buffer size 4096 */ 140 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 141 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 142 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 143 #define E1000_RCTL_DPF 0x00400000 /* Discard Pause Frames */ 144 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 145 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 146 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 147 148 /* Use byte values for the following shift parameters 149 * Usage: 150 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 151 * E1000_PSRCTL_BSIZE0_MASK) | 152 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 153 * E1000_PSRCTL_BSIZE1_MASK) | 154 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 155 * E1000_PSRCTL_BSIZE2_MASK) | 156 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 157 * E1000_PSRCTL_BSIZE3_MASK)) 158 * where value0 = [128..16256], default=256 159 * value1 = [1024..64512], default=4096 160 * value2 = [0..64512], default=4096 161 * value3 = [0..64512], default=0 162 */ 163 164 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 165 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 166 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 167 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 168 169 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 170 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 171 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 172 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 173 174 /* SWFW_SYNC Definitions */ 175 #define E1000_SWFW_EEP_SM 0x1 176 #define E1000_SWFW_PHY0_SM 0x2 177 #define E1000_SWFW_PHY1_SM 0x4 178 #define E1000_SWFW_CSR_SM 0x8 179 180 /* Device Control */ 181 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 182 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 183 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 185 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 187 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 188 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 189 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 190 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 191 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 192 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 193 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 194 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 195 #define E1000_CTRL_MEHE 0x00080000 /* Memory Error Handling Enable */ 196 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 197 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 198 #define E1000_CTRL_ADVD3WUC 0x00100000 /* D3 WUC */ 199 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000 /* PHY PM enable */ 200 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 201 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 202 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 203 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 204 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 205 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 206 207 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 208 209 #define E1000_PCS_LSTS_AN_COMPLETE 0x10000 210 211 /* Device Status */ 212 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 213 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 214 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 215 #define E1000_STATUS_FUNC_SHIFT 2 216 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 217 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 218 #define E1000_STATUS_SPEED_MASK 0x000000C0 219 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 220 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 221 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 222 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion by NVM */ 223 #define E1000_STATUS_PHYRA 0x00000400 /* PHY Reset Asserted */ 224 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Master Req status */ 225 226 /* PCIm function state */ 227 #define E1000_STATUS_PCIM_STATE 0x40000000 228 229 #define HALF_DUPLEX 1 230 #define FULL_DUPLEX 2 231 232 #define ADVERTISE_10_HALF 0x0001 233 #define ADVERTISE_10_FULL 0x0002 234 #define ADVERTISE_100_HALF 0x0004 235 #define ADVERTISE_100_FULL 0x0008 236 #define ADVERTISE_1000_HALF 0x0010 /* Not used, just FYI */ 237 #define ADVERTISE_1000_FULL 0x0020 238 239 /* 1000/H is not supported, nor spec-compliant. */ 240 #define E1000_ALL_SPEED_DUPLEX ( \ 241 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 242 ADVERTISE_100_FULL | ADVERTISE_1000_FULL) 243 #define E1000_ALL_NOT_GIG ( \ 244 ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \ 245 ADVERTISE_100_FULL) 246 #define E1000_ALL_100_SPEED (ADVERTISE_100_HALF | ADVERTISE_100_FULL) 247 #define E1000_ALL_10_SPEED (ADVERTISE_10_HALF | ADVERTISE_10_FULL) 248 #define E1000_ALL_HALF_DUPLEX (ADVERTISE_10_HALF | ADVERTISE_100_HALF) 249 250 #define AUTONEG_ADVERTISE_SPEED_DEFAULT E1000_ALL_SPEED_DUPLEX 251 252 /* LED Control */ 253 #define E1000_PHY_LED0_MODE_MASK 0x00000007 254 #define E1000_PHY_LED0_IVRT 0x00000008 255 #define E1000_PHY_LED0_MASK 0x0000001F 256 257 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 258 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 259 #define E1000_LEDCTL_LED0_IVRT 0x00000040 260 #define E1000_LEDCTL_LED0_BLINK 0x00000080 261 262 #define E1000_LEDCTL_MODE_LINK_UP 0x2 263 #define E1000_LEDCTL_MODE_LED_ON 0xE 264 #define E1000_LEDCTL_MODE_LED_OFF 0xF 265 266 /* Transmit Descriptor bit definitions */ 267 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 268 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 269 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 270 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 271 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 272 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 273 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 274 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 275 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 276 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 277 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 278 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 279 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 280 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 281 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 282 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 283 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 284 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 285 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 286 #define E1000_TXD_EXTCMD_TSTAMP 0x00000010 /* IEEE1588 Timestamp packet */ 287 288 /* Transmit Control */ 289 #define E1000_TCTL_EN 0x00000002 /* enable Tx */ 290 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 291 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 292 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 293 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 294 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 295 296 /* SerDes Control */ 297 #define E1000_SCTL_DISABLE_SERDES_LOOPBACK 0x0400 298 #define E1000_SCTL_ENABLE_SERDES_LOOPBACK 0x0410 299 300 /* Receive Checksum Control */ 301 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 302 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 303 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 304 305 /* Header split receive */ 306 #define E1000_RFCTL_NFSW_DIS 0x00000040 307 #define E1000_RFCTL_NFSR_DIS 0x00000080 308 #define E1000_RFCTL_ACK_DIS 0x00001000 309 #define E1000_RFCTL_EXTEN 0x00008000 310 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 311 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 312 313 /* Collision related configuration parameters */ 314 #define E1000_COLLISION_THRESHOLD 15 315 #define E1000_CT_SHIFT 4 316 #define E1000_COLLISION_DISTANCE 63 317 #define E1000_COLD_SHIFT 12 318 319 /* Default values for the transmit IPG register */ 320 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 321 322 #define E1000_TIPG_IPGT_MASK 0x000003FF 323 324 #define DEFAULT_82543_TIPG_IPGR1 8 325 #define E1000_TIPG_IPGR1_SHIFT 10 326 327 #define DEFAULT_82543_TIPG_IPGR2 6 328 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 329 #define E1000_TIPG_IPGR2_SHIFT 20 330 331 #define MAX_JUMBO_FRAME_SIZE 0x3F00 332 #define E1000_TX_PTR_GAP 0x1F 333 334 /* Extended Configuration Control and Size */ 335 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 336 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 337 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 338 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 339 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 340 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 341 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 342 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 343 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 344 345 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 346 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 347 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 348 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 349 350 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 351 352 /* Low Power IDLE Control */ 353 #define E1000_LPIC_LPIET_SHIFT 24 /* Low Power Idle Entry Time */ 354 355 /* PBA constants */ 356 #define E1000_PBA_8K 0x0008 /* 8KB */ 357 #define E1000_PBA_16K 0x0010 /* 16KB */ 358 359 #define E1000_PBA_RXA_MASK 0xFFFF 360 361 #define E1000_PBS_16K E1000_PBA_16K 362 363 /* Uncorrectable/correctable ECC Error counts and enable bits */ 364 #define E1000_PBECCSTS_CORR_ERR_CNT_MASK 0x000000FF 365 #define E1000_PBECCSTS_UNCORR_ERR_CNT_MASK 0x0000FF00 366 #define E1000_PBECCSTS_UNCORR_ERR_CNT_SHIFT 8 367 #define E1000_PBECCSTS_ECC_ENABLE 0x00010000 368 369 #define IFS_MAX 80 370 #define IFS_MIN 40 371 #define IFS_RATIO 4 372 #define IFS_STEP 10 373 #define MIN_NUM_XMITS 1000 374 375 /* SW Semaphore Register */ 376 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 377 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 378 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 379 380 #define E1000_SWSM2_LOCK 0x00000002 /* Secondary driver semaphore bit */ 381 382 /* Interrupt Cause Read */ 383 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 384 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 385 #define E1000_ICR_RXSEQ 0x00000008 /* Rx sequence error */ 386 #define E1000_ICR_RXDMT0 0x00000010 /* Rx desc min. threshold (0) */ 387 #define E1000_ICR_RXO 0x00000040 /* Receiver Overrun */ 388 #define E1000_ICR_RXT0 0x00000080 /* Rx timer intr (ring 0) */ 389 #define E1000_ICR_MDAC 0x00000200 /* MDIO Access Complete */ 390 #define E1000_ICR_SRPD 0x00010000 /* Small Receive Packet Detected */ 391 #define E1000_ICR_ACK 0x00020000 /* Receive ACK Frame Detected */ 392 #define E1000_ICR_MNG 0x00040000 /* Manageability Event Detected */ 393 #define E1000_ICR_ECCER 0x00400000 /* Uncorrectable ECC Error */ 394 /* If this bit asserted, the driver should claim the interrupt */ 395 #define E1000_ICR_INT_ASSERTED 0x80000000 396 #define E1000_ICR_RXQ0 0x00100000 /* Rx Queue 0 Interrupt */ 397 #define E1000_ICR_RXQ1 0x00200000 /* Rx Queue 1 Interrupt */ 398 #define E1000_ICR_TXQ0 0x00400000 /* Tx Queue 0 Interrupt */ 399 #define E1000_ICR_TXQ1 0x00800000 /* Tx Queue 1 Interrupt */ 400 #define E1000_ICR_OTHER 0x01000000 /* Other Interrupt */ 401 402 /* PBA ECC Register */ 403 #define E1000_PBA_ECC_COUNTER_MASK 0xFFF00000 /* ECC counter mask */ 404 #define E1000_PBA_ECC_COUNTER_SHIFT 20 /* ECC counter shift value */ 405 #define E1000_PBA_ECC_CORR_EN 0x00000001 /* ECC correction enable */ 406 #define E1000_PBA_ECC_STAT_CLR 0x00000002 /* Clear ECC error counter */ 407 #define E1000_PBA_ECC_INT_EN 0x00000004 /* Enable ICR bit 5 for ECC */ 408 409 /* This defines the bits that are set in the Interrupt Mask 410 * Set/Read Register. Each bit is documented below: 411 * o RXT0 = Receiver Timer Interrupt (ring 0) 412 * o TXDW = Transmit Descriptor Written Back 413 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 414 * o RXSEQ = Receive Sequence Error 415 * o LSC = Link Status Change 416 */ 417 #define IMS_ENABLE_MASK ( \ 418 E1000_IMS_RXT0 | \ 419 E1000_IMS_TXDW | \ 420 E1000_IMS_RXDMT0 | \ 421 E1000_IMS_RXSEQ | \ 422 E1000_IMS_LSC) 423 424 /* These are all of the events related to the OTHER interrupt. 425 */ 426 #define IMS_OTHER_MASK ( \ 427 E1000_IMS_LSC | \ 428 E1000_IMS_RXO | \ 429 E1000_IMS_MDAC | \ 430 E1000_IMS_SRPD | \ 431 E1000_IMS_ACK | \ 432 E1000_IMS_MNG) 433 434 /* Interrupt Mask Set */ 435 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 436 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 437 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 438 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 439 #define E1000_IMS_RXO E1000_ICR_RXO /* Receiver Overrun */ 440 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* Rx timer intr */ 441 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO Access Complete */ 442 #define E1000_IMS_SRPD E1000_ICR_SRPD /* Small Receive Packet */ 443 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive ACK Frame Detected */ 444 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability Event */ 445 #define E1000_IMS_ECCER E1000_ICR_ECCER /* Uncorrectable ECC Error */ 446 #define E1000_IMS_RXQ0 E1000_ICR_RXQ0 /* Rx Queue 0 Interrupt */ 447 #define E1000_IMS_RXQ1 E1000_ICR_RXQ1 /* Rx Queue 1 Interrupt */ 448 #define E1000_IMS_TXQ0 E1000_ICR_TXQ0 /* Tx Queue 0 Interrupt */ 449 #define E1000_IMS_TXQ1 E1000_ICR_TXQ1 /* Tx Queue 1 Interrupt */ 450 #define E1000_IMS_OTHER E1000_ICR_OTHER /* Other Interrupt */ 451 452 /* Interrupt Cause Set */ 453 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 454 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* Rx sequence error */ 455 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* Rx desc min. threshold */ 456 #define E1000_ICS_OTHER E1000_ICR_OTHER /* Other Interrupt */ 457 458 /* Transmit Descriptor Control */ 459 #define E1000_TXDCTL_PTHRESH 0x0000003F /* TXDCTL Prefetch Threshold */ 460 #define E1000_TXDCTL_HTHRESH 0x00003F00 /* TXDCTL Host Threshold */ 461 #define E1000_TXDCTL_WTHRESH 0x003F0000 /* TXDCTL Writeback Threshold */ 462 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 463 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 464 #define E1000_TXDCTL_MAX_TX_DESC_PREFETCH 0x0100001F /* GRAN=1, PTHRESH=31 */ 465 /* Enable the counting of desc. still to be processed. */ 466 #define E1000_TXDCTL_COUNT_DESC 0x00400000 467 468 /* Flow Control Constants */ 469 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 470 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 471 #define FLOW_CONTROL_TYPE 0x8808 472 473 /* 802.1q VLAN Packet Size */ 474 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 475 476 /* Receive Address 477 * Number of high/low register pairs in the RAR. The RAR (Receive Address 478 * Registers) holds the directed and multicast addresses that we monitor. 479 * Technically, we have 16 spots. However, we reserve one of these spots 480 * (RAR[15]) for our directed address used by controllers with 481 * manageability enabled, allowing us room for 15 multicast addresses. 482 */ 483 #define E1000_RAR_ENTRIES 15 484 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 485 #define E1000_RAL_MAC_ADDR_LEN 4 486 #define E1000_RAH_MAC_ADDR_LEN 2 487 488 /* Error Codes */ 489 #define E1000_ERR_NVM 1 490 #define E1000_ERR_PHY 2 491 #define E1000_ERR_CONFIG 3 492 #define E1000_ERR_PARAM 4 493 #define E1000_ERR_MAC_INIT 5 494 #define E1000_ERR_PHY_TYPE 6 495 #define E1000_ERR_RESET 9 496 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 497 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 498 #define E1000_BLK_PHY_RESET 12 499 #define E1000_ERR_SWFW_SYNC 13 500 #define E1000_NOT_IMPLEMENTED 14 501 #define E1000_ERR_INVALID_ARGUMENT 16 502 #define E1000_ERR_NO_SPACE 17 503 #define E1000_ERR_NVM_PBA_SECTION 18 504 505 /* Loop limit on how long we wait for auto-negotiation to complete */ 506 #define FIBER_LINK_UP_LIMIT 50 507 #define COPPER_LINK_UP_LIMIT 10 508 #define PHY_AUTO_NEG_LIMIT 45 509 #define PHY_FORCE_LIMIT 20 510 /* Number of 100 microseconds we wait for PCI Express master disable */ 511 #define MASTER_DISABLE_TIMEOUT 800 512 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 513 #define PHY_CFG_TIMEOUT 100 514 /* Number of 2 milliseconds we wait for acquiring MDIO ownership. */ 515 #define MDIO_OWNERSHIP_TIMEOUT 10 516 /* Number of milliseconds for NVM auto read done after MAC reset. */ 517 #define AUTO_READ_DONE_TIMEOUT 10 518 519 /* Flow Control */ 520 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 521 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 522 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 523 524 /* Transmit Configuration Word */ 525 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 526 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 527 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 528 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 529 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 530 531 /* Receive Configuration Word */ 532 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 533 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 534 #define E1000_RXCW_C 0x20000000 /* Receive config */ 535 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 536 537 /* HH Time Sync */ 538 #define E1000_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK 0x0000F000 /* max delay */ 539 #define E1000_TSYNCTXCTL_SYNC_COMP 0x40000000 /* sync complete */ 540 #define E1000_TSYNCTXCTL_START_SYNC 0x80000000 /* initiate sync */ 541 542 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 543 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable Tx timestamping */ 544 545 #define E1000_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 546 #define E1000_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 547 #define E1000_TSYNCRXCTL_TYPE_L2_V2 0x00 548 #define E1000_TSYNCRXCTL_TYPE_L4_V1 0x02 549 #define E1000_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 550 #define E1000_TSYNCRXCTL_TYPE_ALL 0x08 551 #define E1000_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 552 #define E1000_TSYNCRXCTL_ENABLED 0x00000010 /* enable Rx timestamping */ 553 #define E1000_TSYNCRXCTL_SYSCFI 0x00000020 /* Sys clock frequency */ 554 555 #define E1000_RXMTRL_PTP_V1_SYNC_MESSAGE 0x00000000 556 #define E1000_RXMTRL_PTP_V1_DELAY_REQ_MESSAGE 0x00010000 557 558 #define E1000_RXMTRL_PTP_V2_SYNC_MESSAGE 0x00000000 559 #define E1000_RXMTRL_PTP_V2_DELAY_REQ_MESSAGE 0x01000000 560 561 #define E1000_TIMINCA_INCPERIOD_SHIFT 24 562 #define E1000_TIMINCA_INCVALUE_MASK 0x00FFFFFF 563 564 /* PCI Express Control */ 565 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 566 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 567 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 568 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 569 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 570 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 571 572 #define PCIE_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 573 E1000_GCR_RXDSCW_NO_SNOOP | \ 574 E1000_GCR_RXDSCR_NO_SNOOP | \ 575 E1000_GCR_TXD_NO_SNOOP | \ 576 E1000_GCR_TXDSCW_NO_SNOOP | \ 577 E1000_GCR_TXDSCR_NO_SNOOP) 578 579 /* NVM Control */ 580 #define E1000_EECD_SK 0x00000001 /* NVM Clock */ 581 #define E1000_EECD_CS 0x00000002 /* NVM Chip Select */ 582 #define E1000_EECD_DI 0x00000004 /* NVM Data In */ 583 #define E1000_EECD_DO 0x00000008 /* NVM Data Out */ 584 #define E1000_EECD_REQ 0x00000040 /* NVM Access Request */ 585 #define E1000_EECD_GNT 0x00000080 /* NVM Access Grant */ 586 #define E1000_EECD_PRES 0x00000100 /* NVM Present */ 587 #define E1000_EECD_SIZE 0x00000200 /* NVM Size (0=64 word 1=256 word) */ 588 /* NVM Addressing bits based on type (0-small, 1-large) */ 589 #define E1000_EECD_ADDR_BITS 0x00000400 590 #define E1000_NVM_GRANT_ATTEMPTS 1000 /* NVM # attempts to gain grant */ 591 #define E1000_EECD_AUTO_RD 0x00000200 /* NVM Auto Read done */ 592 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* NVM Size */ 593 #define E1000_EECD_SIZE_EX_SHIFT 11 594 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 595 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 596 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 597 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 598 599 #define E1000_NVM_RW_REG_DATA 16 /* Offset to data in NVM r/w regs */ 600 #define E1000_NVM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 601 #define E1000_NVM_RW_REG_START 1 /* Start operation */ 602 #define E1000_NVM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 603 #define E1000_NVM_POLL_WRITE 1 /* Flag for polling write complete */ 604 #define E1000_NVM_POLL_READ 0 /* Flag for polling read complete */ 605 #define E1000_FLASH_UPDATES 2000 606 607 /* NVM Word Offsets */ 608 #define NVM_COMPAT 0x0003 609 #define NVM_ID_LED_SETTINGS 0x0004 610 #define NVM_FUTURE_INIT_WORD1 0x0019 611 #define NVM_COMPAT_VALID_CSUM 0x0001 612 #define NVM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 613 614 #define NVM_INIT_CONTROL2_REG 0x000F 615 #define NVM_INIT_CONTROL3_PORT_B 0x0014 616 #define NVM_INIT_3GIO_3 0x001A 617 #define NVM_INIT_CONTROL3_PORT_A 0x0024 618 #define NVM_CFG 0x0012 619 #define NVM_ALT_MAC_ADDR_PTR 0x0037 620 #define NVM_CHECKSUM_REG 0x003F 621 622 #define E1000_NVM_CFG_DONE_PORT_0 0x40000 /* MNG config cycle done */ 623 #define E1000_NVM_CFG_DONE_PORT_1 0x80000 /* ...for second port */ 624 625 /* Mask bits for fields in Word 0x0f of the NVM */ 626 #define NVM_WORD0F_PAUSE_MASK 0x3000 627 #define NVM_WORD0F_PAUSE 0x1000 628 #define NVM_WORD0F_ASM_DIR 0x2000 629 630 /* Mask bits for fields in Word 0x1a of the NVM */ 631 #define NVM_WORD1A_ASPM_MASK 0x000C 632 633 /* Mask bits for fields in Word 0x03 of the EEPROM */ 634 #define NVM_COMPAT_LOM 0x0800 635 636 /* length of string needed to store PBA number */ 637 #define E1000_PBANUM_LENGTH 11 638 639 /* For checksumming, the sum of all words in the NVM should equal 0xBABA. */ 640 #define NVM_SUM 0xBABA 641 642 /* Uninitialized ("empty") checksum word value */ 643 #define NVM_CHECKSUM_UNINITIALIZED 0xFFFF 644 645 /* PBA (printed board assembly) number words */ 646 #define NVM_PBA_OFFSET_0 8 647 #define NVM_PBA_OFFSET_1 9 648 #define NVM_PBA_PTR_GUARD 0xFAFA 649 #define NVM_WORD_SIZE_BASE_SHIFT 6 650 651 /* NVM Commands - SPI */ 652 #define NVM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 653 #define NVM_READ_OPCODE_SPI 0x03 /* NVM read opcode */ 654 #define NVM_WRITE_OPCODE_SPI 0x02 /* NVM write opcode */ 655 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 656 #define NVM_WREN_OPCODE_SPI 0x06 /* NVM set Write Enable latch */ 657 #define NVM_RDSR_OPCODE_SPI 0x05 /* NVM read Status register */ 658 659 /* SPI NVM Status Register */ 660 #define NVM_STATUS_RDY_SPI 0x01 661 662 /* Word definitions for ID LED Settings */ 663 #define ID_LED_RESERVED_0000 0x0000 664 #define ID_LED_RESERVED_FFFF 0xFFFF 665 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 666 (ID_LED_OFF1_OFF2 << 8) | \ 667 (ID_LED_DEF1_DEF2 << 4) | \ 668 (ID_LED_DEF1_DEF2)) 669 #define ID_LED_DEF1_DEF2 0x1 670 #define ID_LED_DEF1_ON2 0x2 671 #define ID_LED_DEF1_OFF2 0x3 672 #define ID_LED_ON1_DEF2 0x4 673 #define ID_LED_ON1_ON2 0x5 674 #define ID_LED_ON1_OFF2 0x6 675 #define ID_LED_OFF1_DEF2 0x7 676 #define ID_LED_OFF1_ON2 0x8 677 #define ID_LED_OFF1_OFF2 0x9 678 679 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 680 #define IGP_ACTIVITY_LED_ENABLE 0x0300 681 #define IGP_LED3_MODE 0x07000000 682 683 /* PCI/PCI-X/PCI-EX Config space */ 684 #define PCI_HEADER_TYPE_REGISTER 0x0E 685 686 #define PHY_REVISION_MASK 0xFFFFFFF0 687 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 688 #define MAX_PHY_MULTI_PAGE_REG 0xF 689 690 /* Bit definitions for valid PHY IDs. 691 * I = Integrated 692 * E = External 693 */ 694 #define M88E1000_E_PHY_ID 0x01410C50 695 #define M88E1000_I_PHY_ID 0x01410C30 696 #define M88E1011_I_PHY_ID 0x01410C20 697 #define IGP01E1000_I_PHY_ID 0x02A80380 698 #define M88E1111_I_PHY_ID 0x01410CC0 699 #define GG82563_E_PHY_ID 0x01410CA0 700 #define IGP03E1000_E_PHY_ID 0x02A80390 701 #define IFE_E_PHY_ID 0x02A80330 702 #define IFE_PLUS_E_PHY_ID 0x02A80320 703 #define IFE_C_E_PHY_ID 0x02A80310 704 #define BME1000_E_PHY_ID 0x01410CB0 705 #define BME1000_E_PHY_ID_R2 0x01410CB1 706 #define I82577_E_PHY_ID 0x01540050 707 #define I82578_E_PHY_ID 0x004DD040 708 #define I82579_E_PHY_ID 0x01540090 709 #define I217_E_PHY_ID 0x015400A0 710 711 /* M88E1000 Specific Registers */ 712 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 713 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 714 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 715 716 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 717 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 718 719 /* M88E1000 PHY Specific Control Register */ 720 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 721 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 722 /* Manual MDI configuration */ 723 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 724 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */ 725 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 726 /* Auto crossover enabled all speeds */ 727 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 728 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 729 730 /* M88E1000 PHY Specific Status Register */ 731 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 732 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 733 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 734 /* 0=<50M; 1=50-80M; 2=80-110M; 3=110-140M; 4=>140M */ 735 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 736 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 737 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 738 739 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 740 741 /* Number of times we will attempt to autonegotiate before downshifting if we 742 * are the master 743 */ 744 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 745 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 746 /* Number of times we will attempt to autonegotiate before downshifting if we 747 * are the slave 748 */ 749 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 750 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 751 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 752 753 /* M88EC018 Rev 2 specific DownShift settings */ 754 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 755 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 756 757 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 758 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 759 760 /* BME1000 PHY Specific Control Register */ 761 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 762 763 /* Bits... 764 * 15-5: page 765 * 4-0: register offset 766 */ 767 #define GG82563_PAGE_SHIFT 5 768 #define GG82563_REG(page, reg) \ 769 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 770 #define GG82563_MIN_ALT_REG 30 771 772 /* GG82563 Specific Registers */ 773 #define GG82563_PHY_SPEC_CTRL \ 774 GG82563_REG(0, 16) /* PHY Specific Control */ 775 #define GG82563_PHY_PAGE_SELECT \ 776 GG82563_REG(0, 22) /* Page Select */ 777 #define GG82563_PHY_SPEC_CTRL_2 \ 778 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 779 #define GG82563_PHY_PAGE_SELECT_ALT \ 780 GG82563_REG(0, 29) /* Alternate Page Select */ 781 782 #define GG82563_PHY_MAC_SPEC_CTRL \ 783 GG82563_REG(2, 21) /* MAC Specific Control Register */ 784 785 #define GG82563_PHY_DSP_DISTANCE \ 786 GG82563_REG(5, 26) /* DSP Distance */ 787 788 /* Page 193 - Port Control Registers */ 789 #define GG82563_PHY_KMRN_MODE_CTRL \ 790 GG82563_REG(193, 16) /* Kumeran Mode Control */ 791 #define GG82563_PHY_PWR_MGMT_CTRL \ 792 GG82563_REG(193, 20) /* Power Management Control */ 793 794 /* Page 194 - KMRN Registers */ 795 #define GG82563_PHY_INBAND_CTRL \ 796 GG82563_REG(194, 18) /* Inband Control */ 797 798 /* MDI Control */ 799 #define E1000_MDIC_REG_MASK 0x001F0000 800 #define E1000_MDIC_REG_SHIFT 16 801 #define E1000_MDIC_PHY_SHIFT 21 802 #define E1000_MDIC_OP_WRITE 0x04000000 803 #define E1000_MDIC_OP_READ 0x08000000 804 #define E1000_MDIC_READY 0x10000000 805 #define E1000_MDIC_ERROR 0x40000000 806 807 /* SerDes Control */ 808 #define E1000_GEN_POLL_TIMEOUT 640 809 810 #define E1000_FEXTNVM12_PHYPD_CTRL_MASK 0x00C00000 811 #define E1000_FEXTNVM12_PHYPD_CTRL_P1 0x00800000 812 813 #endif /* _E1000_DEFINES_H_ */ 814