xref: /linux/drivers/gpu/drm/nouveau/include/nvhw/class/cl837d.h (revision 4b4193256c8d3bc3a5397b5cd9494c2ad386317d)
1 /*
2  * Copyright (c) 1993-2014, NVIDIA CORPORATION. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20  * DEALINGS IN THE SOFTWARE.
21  */
22 
23 
24 #ifndef _cl837d_h_
25 #define _cl837d_h_
26 
27 // class methods
28 #define NV837D_SOR_SET_CONTROL(a)                                               (0x00000600 + (a)*0x00000040)
29 #define NV837D_SOR_SET_CONTROL_OWNER                                            3:0
30 #define NV837D_SOR_SET_CONTROL_OWNER_NONE                                       (0x00000000)
31 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD0                                      (0x00000001)
32 #define NV837D_SOR_SET_CONTROL_OWNER_HEAD1                                      (0x00000002)
33 #define NV837D_SOR_SET_CONTROL_SUB_OWNER                                        5:4
34 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_NONE                                   (0x00000000)
35 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                               (0x00000001)
36 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                               (0x00000002)
37 #define NV837D_SOR_SET_CONTROL_SUB_OWNER_BOTH                                   (0x00000003)
38 #define NV837D_SOR_SET_CONTROL_PROTOCOL                                         11:8
39 #define NV837D_SOR_SET_CONTROL_PROTOCOL_LVDS_CUSTOM                             (0x00000000)
40 #define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_A                           (0x00000001)
41 #define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_B                           (0x00000002)
42 #define NV837D_SOR_SET_CONTROL_PROTOCOL_SINGLE_TMDS_AB                          (0x00000003)
43 #define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_SINGLE_TMDS                        (0x00000004)
44 #define NV837D_SOR_SET_CONTROL_PROTOCOL_DUAL_TMDS                               (0x00000005)
45 #define NV837D_SOR_SET_CONTROL_PROTOCOL_DDI_OUT                                 (0x00000007)
46 #define NV837D_SOR_SET_CONTROL_PROTOCOL_CUSTOM                                  (0x0000000F)
47 #define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY                                   12:12
48 #define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
49 #define NV837D_SOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
50 #define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY                                   13:13
51 #define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                     (0x00000000)
52 #define NV837D_SOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                     (0x00000001)
53 #define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY                                 14:14
54 #define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                   (0x00000000)
55 #define NV837D_SOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                   (0x00000001)
56 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH                                      19:16
57 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                              (0x00000000)
58 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                           (0x00000001)
59 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                           (0x00000002)
60 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                           (0x00000003)
61 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                           (0x00000004)
62 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                           (0x00000005)
63 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                           (0x00000006)
64 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                           (0x00000007)
65 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                           (0x00000008)
66 #define NV837D_SOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                           (0x00000009)
67 
68 #define NV837D_PIOR_SET_CONTROL(a)                                              (0x00000700 + (a)*0x00000040)
69 #define NV837D_PIOR_SET_CONTROL_OWNER                                           3:0
70 #define NV837D_PIOR_SET_CONTROL_OWNER_NONE                                      (0x00000000)
71 #define NV837D_PIOR_SET_CONTROL_OWNER_HEAD0                                     (0x00000001)
72 #define NV837D_PIOR_SET_CONTROL_OWNER_HEAD1                                     (0x00000002)
73 #define NV837D_PIOR_SET_CONTROL_SUB_OWNER                                       5:4
74 #define NV837D_PIOR_SET_CONTROL_SUB_OWNER_NONE                                  (0x00000000)
75 #define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD0                              (0x00000001)
76 #define NV837D_PIOR_SET_CONTROL_SUB_OWNER_SUBHEAD1                              (0x00000002)
77 #define NV837D_PIOR_SET_CONTROL_SUB_OWNER_BOTH                                  (0x00000003)
78 #define NV837D_PIOR_SET_CONTROL_PROTOCOL                                        11:8
79 #define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TMDS_ENC                           (0x00000000)
80 #define NV837D_PIOR_SET_CONTROL_PROTOCOL_EXT_TV_ENC                             (0x00000001)
81 #define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY                                  12:12
82 #define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
83 #define NV837D_PIOR_SET_CONTROL_HSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
84 #define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY                                  13:13
85 #define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_POSITIVE_TRUE                    (0x00000000)
86 #define NV837D_PIOR_SET_CONTROL_VSYNC_POLARITY_NEGATIVE_TRUE                    (0x00000001)
87 #define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY                                14:14
88 #define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_POSITIVE_TRUE                  (0x00000000)
89 #define NV837D_PIOR_SET_CONTROL_DE_SYNC_POLARITY_NEGATIVE_TRUE                  (0x00000001)
90 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH                                     19:16
91 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_DEFAULT                             (0x00000000)
92 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_16_422                          (0x00000001)
93 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_18_444                          (0x00000002)
94 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_20_422                          (0x00000003)
95 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_422                          (0x00000004)
96 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_24_444                          (0x00000005)
97 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_30_444                          (0x00000006)
98 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_32_422                          (0x00000007)
99 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_36_444                          (0x00000008)
100 #define NV837D_PIOR_SET_CONTROL_PIXEL_DEPTH_BPP_48_444                          (0x00000009)
101 #endif // _cl837d_h
102