Home
last modified time | relevance | path

Searched refs:NUM_BANKS (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v8_0.c76 #define NUM_BANKS(x) ((x) << GB_MACROTILE_MODE0__NUM_BANKS__SHIFT) macro
2201 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2205 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2209 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2213 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2217 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2221 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2225 NUM_BANKS(ADDR_SURF_8_BANK)); in gfx_v8_0_tiling_mode_table_init()
2229 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init()
2233 NUM_BANKS(ADDR_SURF_16_BANK)); in gfx_v8_0_tiling_mode_table_init()
[all …]
H A Dsdma_v4_4_2.c167 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG, NUM_BANKS, 4); in sdma_v4_4_2_inst_init_golden_registers()
173 val = REG_SET_FIELD(val, SDMA_GB_ADDR_CONFIG_READ, NUM_BANKS, in sdma_v4_4_2_inst_init_golden_registers()
H A Dgfx_v9_4_3.c878 NUM_BANKS); in gfx_v9_4_3_gpu_early_init()
H A Dgfx_v9_0.c2130 NUM_BANKS); in gfx_v9_0_gpu_early_init()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm_plane.c244 tiling_info->gfx8.num_banks = AMD_FMT_MOD_GET(NUM_BANKS, modifier); in amdgpu_dm_plane_fill_gfx6_tiling_info_from_modifier()
637 AMD_FMT_MOD_SET(NUM_BANKS, (gb_tile_mode >> 20) & 0x3); in amdgpu_dm_plane_calc_gfx6_mod()
646 AMD_FMT_MOD_SET(NUM_BANKS, (gb_macrotile_mode >> 6) & 0x3); in amdgpu_dm_plane_calc_gfx6_mod()
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1275 # define NUM_BANKS(x) ((x) << 6) macro
/linux/drivers/gpu/drm/amd/include/
H A Dnavi10_enum.h1549 typedef enum NUM_BANKS { enum
1555 } NUM_BANKS; typedef