1 /*
2 *
3 * Copyright (c) 2012 Gilles Dartiguelongue, Thomas Richter
4 *
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 */
28
29 #include "intel_display_types.h"
30 #include "intel_dvo_dev.h"
31
32 #define NS2501_VID 0x1305
33 #define NS2501_DID 0x6726
34
35 #define NS2501_VID_LO 0x00
36 #define NS2501_VID_HI 0x01
37 #define NS2501_DID_LO 0x02
38 #define NS2501_DID_HI 0x03
39 #define NS2501_REV 0x04
40 #define NS2501_RSVD 0x05
41 #define NS2501_FREQ_LO 0x06
42 #define NS2501_FREQ_HI 0x07
43
44 #define NS2501_REG8 0x08
45 #define NS2501_8_VEN (1<<5)
46 #define NS2501_8_HEN (1<<4)
47 #define NS2501_8_DSEL (1<<3)
48 #define NS2501_8_BPAS (1<<2)
49 #define NS2501_8_RSVD (1<<1)
50 #define NS2501_8_PD (1<<0)
51
52 #define NS2501_REG9 0x09
53 #define NS2501_9_VLOW (1<<7)
54 #define NS2501_9_MSEL_MASK (0x7<<4)
55 #define NS2501_9_TSEL (1<<3)
56 #define NS2501_9_RSEN (1<<2)
57 #define NS2501_9_RSVD (1<<1)
58 #define NS2501_9_MDI (1<<0)
59
60 #define NS2501_REGC 0x0c
61
62 /*
63 * The following registers are not part of the official datasheet
64 * and are the result of reverse engineering.
65 */
66
67 /*
68 * Register c0 controls how the DVO synchronizes with
69 * its input.
70 */
71 #define NS2501_REGC0 0xc0
72 #define NS2501_C0_ENABLE (1<<0) /* enable the DVO sync in general */
73 #define NS2501_C0_HSYNC (1<<1) /* synchronize horizontal with input */
74 #define NS2501_C0_VSYNC (1<<2) /* synchronize vertical with input */
75 #define NS2501_C0_RESET (1<<7) /* reset the synchronization flip/flops */
76
77 /*
78 * Register 41 is somehow related to the sync register and sync
79 * configuration. It should be 0x32 whenever regC0 is 0x05 (hsync off)
80 * and 0x00 otherwise.
81 */
82 #define NS2501_REG41 0x41
83
84 /*
85 * this register controls the dithering of the DVO
86 * One bit enables it, the other define the dithering depth.
87 * The higher the value, the lower the dithering depth.
88 */
89 #define NS2501_F9_REG 0xf9
90 #define NS2501_F9_ENABLE (1<<0) /* if set, dithering is enabled */
91 #define NS2501_F9_DITHER_MASK (0x7f<<1) /* controls the dither depth */
92 #define NS2501_F9_DITHER_SHIFT 1 /* shifts the dither mask */
93
94 /*
95 * PLL configuration register. This is a pair of registers,
96 * one single byte register at 1B, and a pair at 1C,1D.
97 * These registers are counters/dividers.
98 */
99 #define NS2501_REG1B 0x1b /* one byte PLL control register */
100 #define NS2501_REG1C 0x1c /* low-part of the second register */
101 #define NS2501_REG1D 0x1d /* high-part of the second register */
102
103 /*
104 * Scaler control registers. Horizontal at b8,b9,
105 * vertical at 10,11. The scale factor is computed as
106 * 2^16/control-value. The low-byte comes first.
107 */
108 #define NS2501_REG10 0x10 /* low-byte vertical scaler */
109 #define NS2501_REG11 0x11 /* high-byte vertical scaler */
110 #define NS2501_REGB8 0xb8 /* low-byte horizontal scaler */
111 #define NS2501_REGB9 0xb9 /* high-byte horizontal scaler */
112
113 /*
114 * Display window definition. This consists of four registers
115 * per dimension. One register pair defines the start of the
116 * display, one the end.
117 * As far as I understand, this defines the window within which
118 * the scaler samples the input.
119 */
120 #define NS2501_REGC1 0xc1 /* low-byte horizontal display start */
121 #define NS2501_REGC2 0xc2 /* high-byte horizontal display start */
122 #define NS2501_REGC3 0xc3 /* low-byte horizontal display stop */
123 #define NS2501_REGC4 0xc4 /* high-byte horizontal display stop */
124 #define NS2501_REGC5 0xc5 /* low-byte vertical display start */
125 #define NS2501_REGC6 0xc6 /* high-byte vertical display start */
126 #define NS2501_REGC7 0xc7 /* low-byte vertical display stop */
127 #define NS2501_REGC8 0xc8 /* high-byte vertical display stop */
128
129 /*
130 * The following register pair seems to define the start of
131 * the vertical sync. If automatic syncing is enabled, and the
132 * register value defines a sync pulse that is later than the
133 * incoming sync, then the register value is ignored and the
134 * external hsync triggers the synchronization.
135 */
136 #define NS2501_REG80 0x80 /* low-byte vsync-start */
137 #define NS2501_REG81 0x81 /* high-byte vsync-start */
138
139 /*
140 * The following register pair seems to define the total number
141 * of lines created at the output side of the scaler.
142 * This is again a low-high register pair.
143 */
144 #define NS2501_REG82 0x82 /* output display height, low byte */
145 #define NS2501_REG83 0x83 /* output display height, high byte */
146
147 /*
148 * The following registers define the end of the front-porch
149 * in horizontal and vertical position and hence allow to shift
150 * the image left/right or up/down.
151 */
152 #define NS2501_REG98 0x98 /* horizontal start of display + 256, low */
153 #define NS2501_REG99 0x99 /* horizontal start of display + 256, high */
154 #define NS2501_REG8E 0x8e /* vertical start of the display, low byte */
155 #define NS2501_REG8F 0x8f /* vertical start of the display, high byte */
156
157 /*
158 * The following register pair control the function of the
159 * backlight and the DVO output. To enable the corresponding
160 * function, the corresponding bit must be set in both registers.
161 */
162 #define NS2501_REG34 0x34 /* DVO enable functions, first register */
163 #define NS2501_REG35 0x35 /* DVO enable functions, second register */
164 #define NS2501_34_ENABLE_OUTPUT (1<<0) /* enable DVO output */
165 #define NS2501_34_ENABLE_BACKLIGHT (1<<1) /* enable backlight */
166
167 /*
168 * Registers 9C and 9D define the vertical output offset
169 * of the visible region.
170 */
171 #define NS2501_REG9C 0x9c
172 #define NS2501_REG9D 0x9d
173
174 /*
175 * The register 9F defines the dithering. This requires the
176 * scaler to be ON. Bit 0 enables dithering, the remaining
177 * bits control the depth of the dither. The higher the value,
178 * the LOWER the dithering amplitude. A good value seems to be
179 * 15 (total register value).
180 */
181 #define NS2501_REGF9 0xf9
182 #define NS2501_F9_ENABLE_DITHER (1<<0) /* enable dithering */
183 #define NS2501_F9_DITHER_MASK (0x7f<<1) /* dither masking */
184 #define NS2501_F9_DITHER_SHIFT 1 /* upshift of the dither mask */
185
186 enum {
187 MODE_640x480,
188 MODE_800x600,
189 MODE_1024x768,
190 };
191
192 struct ns2501_reg {
193 u8 offset;
194 u8 value;
195 };
196
197 /*
198 * The following structure keeps the complete configuration of
199 * the DVO, given a specific output configuration.
200 * This is pretty much guess-work from reverse-engineering, so
201 * read all this with a grain of salt.
202 */
203 struct ns2501_configuration {
204 u8 sync; /* configuration of the C0 register */
205 u8 conf; /* configuration register 8 */
206 u8 syncb; /* configuration register 41 */
207 u8 dither; /* configuration of the dithering */
208 u8 pll_a; /* PLL configuration, register A, 1B */
209 u16 pll_b; /* PLL configuration, register B, 1C/1D */
210 u16 hstart; /* horizontal start, registers C1/C2 */
211 u16 hstop; /* horizontal total, registers C3/C4 */
212 u16 vstart; /* vertical start, registers C5/C6 */
213 u16 vstop; /* vertical total, registers C7/C8 */
214 u16 vsync; /* manual vertical sync start, 80/81 */
215 u16 vtotal; /* number of lines generated, 82/83 */
216 u16 hpos; /* horizontal position + 256, 98/99 */
217 u16 vpos; /* vertical position, 8e/8f */
218 u16 voffs; /* vertical output offset, 9c/9d */
219 u16 hscale; /* horizontal scaling factor, b8/b9 */
220 u16 vscale; /* vertical scaling factor, 10/11 */
221 };
222
223 /*
224 * DVO configuration values, partially based on what the BIOS
225 * of the Fujitsu Lifebook S6010 writes into registers,
226 * partially found by manual tweaking. These configurations assume
227 * a 1024x768 panel.
228 */
229 static const struct ns2501_configuration ns2501_modes[] = {
230 [MODE_640x480] = {
231 .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC,
232 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD,
233 .syncb = 0x32,
234 .dither = 0x0f,
235 .pll_a = 17,
236 .pll_b = 852,
237 .hstart = 144,
238 .hstop = 783,
239 .vstart = 22,
240 .vstop = 514,
241 .vsync = 2047, /* actually, ignored with this config */
242 .vtotal = 1341,
243 .hpos = 0,
244 .vpos = 16,
245 .voffs = 36,
246 .hscale = 40960,
247 .vscale = 40960
248 },
249 [MODE_800x600] = {
250 .sync = NS2501_C0_ENABLE |
251 NS2501_C0_HSYNC | NS2501_C0_VSYNC,
252 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD,
253 .syncb = 0x00,
254 .dither = 0x0f,
255 .pll_a = 25,
256 .pll_b = 612,
257 .hstart = 215,
258 .hstop = 1016,
259 .vstart = 26,
260 .vstop = 627,
261 .vsync = 807,
262 .vtotal = 1341,
263 .hpos = 0,
264 .vpos = 4,
265 .voffs = 35,
266 .hscale = 51248,
267 .vscale = 51232
268 },
269 [MODE_1024x768] = {
270 .sync = NS2501_C0_ENABLE | NS2501_C0_VSYNC,
271 .conf = NS2501_8_VEN | NS2501_8_HEN | NS2501_8_PD,
272 .syncb = 0x32,
273 .dither = 0x0f,
274 .pll_a = 11,
275 .pll_b = 1350,
276 .hstart = 276,
277 .hstop = 1299,
278 .vstart = 15,
279 .vstop = 1056,
280 .vsync = 2047,
281 .vtotal = 1341,
282 .hpos = 0,
283 .vpos = 7,
284 .voffs = 27,
285 .hscale = 65535,
286 .vscale = 65535
287 }
288 };
289
290 /*
291 * Other configuration values left by the BIOS of the
292 * Fujitsu S6010 in the DVO control registers. Their
293 * value does not depend on the BIOS and their meaning
294 * is unknown.
295 */
296
297 static const struct ns2501_reg mode_agnostic_values[] = {
298 /* 08 is mode specific */
299 [0] = { .offset = 0x0a, .value = 0x81, },
300 /* 10,11 are part of the mode specific configuration */
301 [1] = { .offset = 0x12, .value = 0x02, },
302 [2] = { .offset = 0x18, .value = 0x07, },
303 [3] = { .offset = 0x19, .value = 0x00, },
304 [4] = { .offset = 0x1a, .value = 0x00, }, /* PLL?, ignored */
305 /* 1b,1c,1d are part of the mode specific configuration */
306 [5] = { .offset = 0x1e, .value = 0x02, },
307 [6] = { .offset = 0x1f, .value = 0x40, },
308 [7] = { .offset = 0x20, .value = 0x00, },
309 [8] = { .offset = 0x21, .value = 0x00, },
310 [9] = { .offset = 0x22, .value = 0x00, },
311 [10] = { .offset = 0x23, .value = 0x00, },
312 [11] = { .offset = 0x24, .value = 0x00, },
313 [12] = { .offset = 0x25, .value = 0x00, },
314 [13] = { .offset = 0x26, .value = 0x00, },
315 [14] = { .offset = 0x27, .value = 0x00, },
316 [15] = { .offset = 0x7e, .value = 0x18, },
317 /* 80-84 are part of the mode-specific configuration */
318 [16] = { .offset = 0x84, .value = 0x00, },
319 [17] = { .offset = 0x85, .value = 0x00, },
320 [18] = { .offset = 0x86, .value = 0x00, },
321 [19] = { .offset = 0x87, .value = 0x00, },
322 [20] = { .offset = 0x88, .value = 0x00, },
323 [21] = { .offset = 0x89, .value = 0x00, },
324 [22] = { .offset = 0x8a, .value = 0x00, },
325 [23] = { .offset = 0x8b, .value = 0x00, },
326 [24] = { .offset = 0x8c, .value = 0x10, },
327 [25] = { .offset = 0x8d, .value = 0x02, },
328 /* 8e,8f are part of the mode-specific configuration */
329 [26] = { .offset = 0x90, .value = 0xff, },
330 [27] = { .offset = 0x91, .value = 0x07, },
331 [28] = { .offset = 0x92, .value = 0xa0, },
332 [29] = { .offset = 0x93, .value = 0x02, },
333 [30] = { .offset = 0x94, .value = 0x00, },
334 [31] = { .offset = 0x95, .value = 0x00, },
335 [32] = { .offset = 0x96, .value = 0x05, },
336 [33] = { .offset = 0x97, .value = 0x00, },
337 /* 98,99 are part of the mode-specific configuration */
338 [34] = { .offset = 0x9a, .value = 0x88, },
339 [35] = { .offset = 0x9b, .value = 0x00, },
340 /* 9c,9d are part of the mode-specific configuration */
341 [36] = { .offset = 0x9e, .value = 0x25, },
342 [37] = { .offset = 0x9f, .value = 0x03, },
343 [38] = { .offset = 0xa0, .value = 0x28, },
344 [39] = { .offset = 0xa1, .value = 0x01, },
345 [40] = { .offset = 0xa2, .value = 0x28, },
346 [41] = { .offset = 0xa3, .value = 0x05, },
347 /* register 0xa4 is mode specific, but 0x80..0x84 works always */
348 [42] = { .offset = 0xa4, .value = 0x84, },
349 [43] = { .offset = 0xa5, .value = 0x00, },
350 [44] = { .offset = 0xa6, .value = 0x00, },
351 [45] = { .offset = 0xa7, .value = 0x00, },
352 [46] = { .offset = 0xa8, .value = 0x00, },
353 /* 0xa9 to 0xab are mode specific, but have no visible effect */
354 [47] = { .offset = 0xa9, .value = 0x04, },
355 [48] = { .offset = 0xaa, .value = 0x70, },
356 [49] = { .offset = 0xab, .value = 0x4f, },
357 [50] = { .offset = 0xac, .value = 0x00, },
358 [51] = { .offset = 0xad, .value = 0x00, },
359 [52] = { .offset = 0xb6, .value = 0x09, },
360 [53] = { .offset = 0xb7, .value = 0x03, },
361 /* b8,b9 are part of the mode-specific configuration */
362 [54] = { .offset = 0xba, .value = 0x00, },
363 [55] = { .offset = 0xbb, .value = 0x20, },
364 [56] = { .offset = 0xf3, .value = 0x90, },
365 [57] = { .offset = 0xf4, .value = 0x00, },
366 [58] = { .offset = 0xf7, .value = 0x88, },
367 /* f8 is mode specific, but the value does not matter */
368 [59] = { .offset = 0xf8, .value = 0x0a, },
369 [60] = { .offset = 0xf9, .value = 0x00, }
370 };
371
372 static const struct ns2501_reg regs_init[] = {
373 [0] = { .offset = 0x35, .value = 0xff, },
374 [1] = { .offset = 0x34, .value = 0x00, },
375 [2] = { .offset = 0x08, .value = 0x30, },
376 };
377
378 struct ns2501_priv {
379 bool quiet;
380 const struct ns2501_configuration *conf;
381 };
382
383 #define NSPTR(d) ((NS2501Ptr)(d->DriverPrivate.ptr))
384
385 /*
386 ** Read a register from the ns2501.
387 ** Returns true if successful, false otherwise.
388 ** If it returns false, it might be wise to enable the
389 ** DVO with the above function.
390 */
ns2501_readb(struct intel_dvo_device * dvo,int addr,u8 * ch)391 static bool ns2501_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
392 {
393 struct ns2501_priv *ns = dvo->dev_priv;
394 struct i2c_adapter *adapter = dvo->i2c_bus;
395 u8 out_buf[2];
396 u8 in_buf[2];
397
398 struct i2c_msg msgs[] = {
399 {
400 .addr = dvo->target_addr,
401 .flags = 0,
402 .len = 1,
403 .buf = out_buf,
404 },
405 {
406 .addr = dvo->target_addr,
407 .flags = I2C_M_RD,
408 .len = 1,
409 .buf = in_buf,
410 }
411 };
412
413 out_buf[0] = addr;
414 out_buf[1] = 0;
415
416 if (i2c_transfer(adapter, msgs, 2) == 2) {
417 *ch = in_buf[0];
418 return true;
419 }
420
421 if (!ns->quiet) {
422 DRM_DEBUG_KMS
423 ("Unable to read register 0x%02x from %s:0x%02x.\n", addr,
424 adapter->name, dvo->target_addr);
425 }
426
427 return false;
428 }
429
430 /*
431 ** Write a register to the ns2501.
432 ** Returns true if successful, false otherwise.
433 ** If it returns false, it might be wise to enable the
434 ** DVO with the above function.
435 */
ns2501_writeb(struct intel_dvo_device * dvo,int addr,u8 ch)436 static bool ns2501_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
437 {
438 struct ns2501_priv *ns = dvo->dev_priv;
439 struct i2c_adapter *adapter = dvo->i2c_bus;
440 u8 out_buf[2];
441
442 struct i2c_msg msg = {
443 .addr = dvo->target_addr,
444 .flags = 0,
445 .len = 2,
446 .buf = out_buf,
447 };
448
449 out_buf[0] = addr;
450 out_buf[1] = ch;
451
452 if (i2c_transfer(adapter, &msg, 1) == 1) {
453 return true;
454 }
455
456 if (!ns->quiet) {
457 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d\n",
458 addr, adapter->name, dvo->target_addr);
459 }
460
461 return false;
462 }
463
464 /* National Semiconductor 2501 driver for chip on i2c bus
465 * scan for the chip on the bus.
466 * Hope the VBIOS initialized the PLL correctly so we can
467 * talk to it. If not, it will not be seen and not detected.
468 * Bummer!
469 */
ns2501_init(struct intel_dvo_device * dvo,struct i2c_adapter * adapter)470 static bool ns2501_init(struct intel_dvo_device *dvo,
471 struct i2c_adapter *adapter)
472 {
473 /* this will detect the NS2501 chip on the specified i2c bus */
474 struct ns2501_priv *ns;
475 unsigned char ch;
476
477 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
478 if (ns == NULL)
479 return false;
480
481 dvo->i2c_bus = adapter;
482 dvo->dev_priv = ns;
483 ns->quiet = true;
484
485 if (!ns2501_readb(dvo, NS2501_VID_LO, &ch))
486 goto out;
487
488 if (ch != (NS2501_VID & 0xff)) {
489 DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n",
490 ch, adapter->name, dvo->target_addr);
491 goto out;
492 }
493
494 if (!ns2501_readb(dvo, NS2501_DID_LO, &ch))
495 goto out;
496
497 if (ch != (NS2501_DID & 0xff)) {
498 DRM_DEBUG_KMS("ns2501 not detected got %d: from %s Target %d.\n",
499 ch, adapter->name, dvo->target_addr);
500 goto out;
501 }
502 ns->quiet = false;
503
504 DRM_DEBUG_KMS("init ns2501 dvo controller successfully!\n");
505
506 return true;
507
508 out:
509 kfree(ns);
510 return false;
511 }
512
ns2501_detect(struct intel_dvo_device * dvo)513 static enum drm_connector_status ns2501_detect(struct intel_dvo_device *dvo)
514 {
515 /*
516 * This is a Laptop display, it doesn't have hotplugging.
517 * Even if not, the detection bit of the 2501 is unreliable as
518 * it only works for some display types.
519 * It is even more unreliable as the PLL must be active for
520 * allowing reading from the chiop.
521 */
522 return connector_status_connected;
523 }
524
ns2501_mode_valid(struct intel_dvo_device * dvo,struct drm_display_mode * mode)525 static enum drm_mode_status ns2501_mode_valid(struct intel_dvo_device *dvo,
526 struct drm_display_mode *mode)
527 {
528 DRM_DEBUG_KMS
529 ("is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d)\n",
530 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
531
532 /*
533 * Currently, these are all the modes I have data from.
534 * More might exist. Unclear how to find the native resolution
535 * of the panel in here so we could always accept it
536 * by disabling the scaler.
537 */
538 if ((mode->hdisplay == 640 && mode->vdisplay == 480 && mode->clock == 25175) ||
539 (mode->hdisplay == 800 && mode->vdisplay == 600 && mode->clock == 40000) ||
540 (mode->hdisplay == 1024 && mode->vdisplay == 768 && mode->clock == 65000)) {
541 return MODE_OK;
542 } else {
543 return MODE_ONE_SIZE; /* Is this a reasonable error? */
544 }
545 }
546
ns2501_mode_set(struct intel_dvo_device * dvo,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)547 static void ns2501_mode_set(struct intel_dvo_device *dvo,
548 const struct drm_display_mode *mode,
549 const struct drm_display_mode *adjusted_mode)
550 {
551 const struct ns2501_configuration *conf;
552 struct ns2501_priv *ns = dvo->dev_priv;
553 int mode_idx, i;
554
555 DRM_DEBUG_KMS
556 ("set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d).\n",
557 mode->hdisplay, mode->htotal, mode->vdisplay, mode->vtotal);
558
559 DRM_DEBUG_KMS("Detailed requested mode settings are:\n"
560 "clock : %d kHz\n"
561 "hdisplay : %d\n"
562 "hblank start : %d\n"
563 "hblank end : %d\n"
564 "hsync start : %d\n"
565 "hsync end : %d\n"
566 "htotal : %d\n"
567 "hskew : %d\n"
568 "vdisplay : %d\n"
569 "vblank start : %d\n"
570 "hblank end : %d\n"
571 "vsync start : %d\n"
572 "vsync end : %d\n"
573 "vtotal : %d\n",
574 adjusted_mode->crtc_clock,
575 adjusted_mode->crtc_hdisplay,
576 adjusted_mode->crtc_hblank_start,
577 adjusted_mode->crtc_hblank_end,
578 adjusted_mode->crtc_hsync_start,
579 adjusted_mode->crtc_hsync_end,
580 adjusted_mode->crtc_htotal,
581 adjusted_mode->crtc_hskew,
582 adjusted_mode->crtc_vdisplay,
583 adjusted_mode->crtc_vblank_start,
584 adjusted_mode->crtc_vblank_end,
585 adjusted_mode->crtc_vsync_start,
586 adjusted_mode->crtc_vsync_end,
587 adjusted_mode->crtc_vtotal);
588
589 if (mode->hdisplay == 640 && mode->vdisplay == 480)
590 mode_idx = MODE_640x480;
591 else if (mode->hdisplay == 800 && mode->vdisplay == 600)
592 mode_idx = MODE_800x600;
593 else if (mode->hdisplay == 1024 && mode->vdisplay == 768)
594 mode_idx = MODE_1024x768;
595 else
596 return;
597
598 /* Hopefully doing it every time won't hurt... */
599 for (i = 0; i < ARRAY_SIZE(regs_init); i++)
600 ns2501_writeb(dvo, regs_init[i].offset, regs_init[i].value);
601
602 /* Write the mode-agnostic values */
603 for (i = 0; i < ARRAY_SIZE(mode_agnostic_values); i++)
604 ns2501_writeb(dvo, mode_agnostic_values[i].offset,
605 mode_agnostic_values[i].value);
606
607 /* Write now the mode-specific configuration */
608 conf = ns2501_modes + mode_idx;
609 ns->conf = conf;
610
611 ns2501_writeb(dvo, NS2501_REG8, conf->conf);
612 ns2501_writeb(dvo, NS2501_REG1B, conf->pll_a);
613 ns2501_writeb(dvo, NS2501_REG1C, conf->pll_b & 0xff);
614 ns2501_writeb(dvo, NS2501_REG1D, conf->pll_b >> 8);
615 ns2501_writeb(dvo, NS2501_REGC1, conf->hstart & 0xff);
616 ns2501_writeb(dvo, NS2501_REGC2, conf->hstart >> 8);
617 ns2501_writeb(dvo, NS2501_REGC3, conf->hstop & 0xff);
618 ns2501_writeb(dvo, NS2501_REGC4, conf->hstop >> 8);
619 ns2501_writeb(dvo, NS2501_REGC5, conf->vstart & 0xff);
620 ns2501_writeb(dvo, NS2501_REGC6, conf->vstart >> 8);
621 ns2501_writeb(dvo, NS2501_REGC7, conf->vstop & 0xff);
622 ns2501_writeb(dvo, NS2501_REGC8, conf->vstop >> 8);
623 ns2501_writeb(dvo, NS2501_REG80, conf->vsync & 0xff);
624 ns2501_writeb(dvo, NS2501_REG81, conf->vsync >> 8);
625 ns2501_writeb(dvo, NS2501_REG82, conf->vtotal & 0xff);
626 ns2501_writeb(dvo, NS2501_REG83, conf->vtotal >> 8);
627 ns2501_writeb(dvo, NS2501_REG98, conf->hpos & 0xff);
628 ns2501_writeb(dvo, NS2501_REG99, conf->hpos >> 8);
629 ns2501_writeb(dvo, NS2501_REG8E, conf->vpos & 0xff);
630 ns2501_writeb(dvo, NS2501_REG8F, conf->vpos >> 8);
631 ns2501_writeb(dvo, NS2501_REG9C, conf->voffs & 0xff);
632 ns2501_writeb(dvo, NS2501_REG9D, conf->voffs >> 8);
633 ns2501_writeb(dvo, NS2501_REGB8, conf->hscale & 0xff);
634 ns2501_writeb(dvo, NS2501_REGB9, conf->hscale >> 8);
635 ns2501_writeb(dvo, NS2501_REG10, conf->vscale & 0xff);
636 ns2501_writeb(dvo, NS2501_REG11, conf->vscale >> 8);
637 ns2501_writeb(dvo, NS2501_REGF9, conf->dither);
638 ns2501_writeb(dvo, NS2501_REG41, conf->syncb);
639 ns2501_writeb(dvo, NS2501_REGC0, conf->sync);
640 }
641
642 /* set the NS2501 power state */
ns2501_get_hw_state(struct intel_dvo_device * dvo)643 static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
644 {
645 unsigned char ch;
646
647 if (!ns2501_readb(dvo, NS2501_REG8, &ch))
648 return false;
649
650 return ch & NS2501_8_PD;
651 }
652
653 /* set the NS2501 power state */
ns2501_dpms(struct intel_dvo_device * dvo,bool enable)654 static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
655 {
656 struct ns2501_priv *ns = dvo->dev_priv;
657
658 DRM_DEBUG_KMS("Trying set the dpms of the DVO to %i\n", enable);
659
660 if (enable) {
661 ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync | 0x08);
662
663 ns2501_writeb(dvo, NS2501_REG41, ns->conf->syncb);
664
665 ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT);
666 msleep(15);
667
668 ns2501_writeb(dvo, NS2501_REG8,
669 ns->conf->conf | NS2501_8_BPAS);
670 if (!(ns->conf->conf & NS2501_8_BPAS))
671 ns2501_writeb(dvo, NS2501_REG8, ns->conf->conf);
672 msleep(200);
673
674 ns2501_writeb(dvo, NS2501_REG34,
675 NS2501_34_ENABLE_OUTPUT | NS2501_34_ENABLE_BACKLIGHT);
676
677 ns2501_writeb(dvo, NS2501_REGC0, ns->conf->sync);
678 } else {
679 ns2501_writeb(dvo, NS2501_REG34, NS2501_34_ENABLE_OUTPUT);
680 msleep(200);
681
682 ns2501_writeb(dvo, NS2501_REG8, NS2501_8_VEN | NS2501_8_HEN |
683 NS2501_8_BPAS);
684 msleep(15);
685
686 ns2501_writeb(dvo, NS2501_REG34, 0x00);
687 }
688 }
689
ns2501_destroy(struct intel_dvo_device * dvo)690 static void ns2501_destroy(struct intel_dvo_device *dvo)
691 {
692 struct ns2501_priv *ns = dvo->dev_priv;
693
694 if (ns) {
695 kfree(ns);
696 dvo->dev_priv = NULL;
697 }
698 }
699
700 const struct intel_dvo_dev_ops ns2501_ops = {
701 .init = ns2501_init,
702 .detect = ns2501_detect,
703 .mode_valid = ns2501_mode_valid,
704 .mode_set = ns2501_mode_set,
705 .dpms = ns2501_dpms,
706 .get_hw_state = ns2501_get_hw_state,
707 .destroy = ns2501_destroy,
708 };
709