1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Marvell RVU Admin Function driver
3 *
4 * Copyright (C) 2018 Marvell.
5 */
6
7 #ifndef COMMON_H
8 #define COMMON_H
9
10 #include <linux/dma-mapping.h>
11 #include <linux/gfp.h>
12 #include <linux/mm.h>
13
14 #include "rvu_struct.h"
15
16 #define OTX2_ALIGN 128 /* Align to cacheline */
17
18 #define Q_SIZE_16 0ULL /* 16 entries */
19 #define Q_SIZE_64 1ULL /* 64 entries */
20 #define Q_SIZE_256 2ULL
21 #define Q_SIZE_1K 3ULL
22 #define Q_SIZE_4K 4ULL
23 #define Q_SIZE_16K 5ULL
24 #define Q_SIZE_64K 6ULL
25 #define Q_SIZE_256K 7ULL
26 #define Q_SIZE_1M 8ULL /* Million entries */
27 #define Q_SIZE_MIN Q_SIZE_16
28 #define Q_SIZE_MAX Q_SIZE_1M
29
30 #define Q_COUNT(x) (16ULL << (2 * x))
31 #define Q_SIZE(x, n) ((ilog2(x) - (n)) / 2)
32
33 /* Admin queue info */
34
35 /* Since we intend to add only one instruction at a time,
36 * keep queue size to it's minimum.
37 */
38 #define AQ_SIZE Q_SIZE_16
39 /* HW head & tail pointer mask */
40 #define AQ_PTR_MASK 0xFFFFF
41
42 struct qmem {
43 void *base;
44 dma_addr_t iova;
45 int alloc_sz;
46 u32 entry_sz;
47 u8 align;
48 u32 qsize;
49 };
50
otx2_dma_alloc_coherent(struct device * dev,size_t size,dma_addr_t * dma_handle)51 static inline void *otx2_dma_alloc_coherent(struct device *dev, size_t size,
52 dma_addr_t *dma_handle)
53 {
54 dma_addr_t dma_addr;
55 void *vaddr;
56
57 vaddr = kzalloc(size, GFP_KERNEL);
58 if (!vaddr)
59 return NULL;
60
61 dma_addr = dma_map_single(dev, vaddr, size, DMA_BIDIRECTIONAL);
62 if (dma_mapping_error(dev, dma_addr)) {
63 kfree(vaddr);
64 return NULL;
65 }
66
67 *dma_handle = dma_addr;
68 return vaddr;
69 }
70
otx2_dma_free_coherent(struct device * dev,size_t size,void * vaddr,dma_addr_t dma_handle)71 static inline void otx2_dma_free_coherent(struct device *dev, size_t size,
72 void *vaddr, dma_addr_t dma_handle)
73 {
74 dma_unmap_single(dev, dma_handle, size, DMA_BIDIRECTIONAL);
75 kfree(vaddr);
76 }
77
qmem_alloc(struct device * dev,struct qmem ** q,int qsize,int entry_sz)78 static inline int qmem_alloc(struct device *dev, struct qmem **q,
79 int qsize, int entry_sz)
80 {
81 struct qmem *qmem;
82 int aligned_addr;
83
84 if (!qsize)
85 return -EINVAL;
86
87 *q = devm_kzalloc(dev, sizeof(*qmem), GFP_KERNEL);
88 if (!*q)
89 return -ENOMEM;
90 qmem = *q;
91
92 qmem->entry_sz = entry_sz;
93 qmem->alloc_sz = (qsize * entry_sz) + OTX2_ALIGN;
94
95 if (get_order(PAGE_ALIGN(qmem->alloc_sz)) > MAX_PAGE_ORDER)
96 return -ENOMEM;
97
98 qmem->base = otx2_dma_alloc_coherent(dev, qmem->alloc_sz, &qmem->iova);
99 if (!qmem->base)
100 return -ENOMEM;
101
102 qmem->qsize = qsize;
103
104 aligned_addr = ALIGN((u64)qmem->iova, OTX2_ALIGN);
105 qmem->align = (aligned_addr - qmem->iova);
106 qmem->base += qmem->align;
107 qmem->iova += qmem->align;
108 return 0;
109 }
110
qmem_free(struct device * dev,struct qmem * qmem)111 static inline void qmem_free(struct device *dev, struct qmem *qmem)
112 {
113 if (!qmem)
114 return;
115
116 if (qmem->base)
117 otx2_dma_free_coherent(dev, qmem->alloc_sz,
118 qmem->base - qmem->align,
119 qmem->iova - qmem->align);
120 devm_kfree(dev, qmem);
121 }
122
123 struct admin_queue {
124 struct qmem *inst;
125 struct qmem *res;
126 spinlock_t lock; /* Serialize inst enqueue from PFs */
127 };
128
129 /* NPA aura count */
130 enum npa_aura_sz {
131 NPA_AURA_SZ_0,
132 NPA_AURA_SZ_128,
133 NPA_AURA_SZ_256,
134 NPA_AURA_SZ_512,
135 NPA_AURA_SZ_1K,
136 NPA_AURA_SZ_2K,
137 NPA_AURA_SZ_4K,
138 NPA_AURA_SZ_8K,
139 NPA_AURA_SZ_16K,
140 NPA_AURA_SZ_32K,
141 NPA_AURA_SZ_64K,
142 NPA_AURA_SZ_128K,
143 NPA_AURA_SZ_256K,
144 NPA_AURA_SZ_512K,
145 NPA_AURA_SZ_1M,
146 NPA_AURA_SZ_MAX,
147 };
148
149 #define NPA_AURA_COUNT(x) (1ULL << ((x) + 6))
150
151 /* NPA AQ result structure for init/read/write of aura HW contexts */
152 struct npa_aq_aura_res {
153 struct npa_aq_res_s res;
154 struct npa_aura_s aura_ctx;
155 struct npa_aura_s ctx_mask;
156 };
157
158 /* NPA AQ result structure for init/read/write of pool HW contexts */
159 struct npa_aq_pool_res {
160 struct npa_aq_res_s res;
161 struct npa_pool_s pool_ctx;
162 struct npa_pool_s ctx_mask;
163 };
164
165 /* NIX Transmit schedulers */
166 enum nix_scheduler {
167 NIX_TXSCH_LVL_SMQ = 0x0,
168 NIX_TXSCH_LVL_MDQ = 0x0,
169 NIX_TXSCH_LVL_TL4 = 0x1,
170 NIX_TXSCH_LVL_TL3 = 0x2,
171 NIX_TXSCH_LVL_TL2 = 0x3,
172 NIX_TXSCH_LVL_TL1 = 0x4,
173 NIX_TXSCH_LVL_CNT = 0x5,
174 };
175
176 #define TXSCH_RR_QTM_MAX ((1 << 24) - 1)
177 #define TXSCH_TL1_DFLT_RR_QTM TXSCH_RR_QTM_MAX
178 #define TXSCH_TL1_DFLT_RR_PRIO (0x7ull)
179 #define CN10K_MAX_DWRR_WEIGHT 16384 /* Weight is 14bit on CN10K */
180
181 /* Don't change the order as on CN10K (except CN10KB)
182 * SMQX_CFG[SDP] value should be 1 for SDP flows.
183 */
184 #define SMQ_LINK_TYPE_RPM 0
185 #define SMQ_LINK_TYPE_SDP 1
186 #define SMQ_LINK_TYPE_LBK 2
187
188 /* Min/Max packet sizes, excluding FCS */
189 #define NIC_HW_MIN_FRS 40
190 #define NIC_HW_MAX_FRS 9212
191 #define SDP_HW_MAX_FRS 65535
192 #define SDP_HW_MIN_FRS 16
193 #define CN10K_LMAC_LINK_MAX_FRS 16380 /* 16k - FCS */
194 #define CN10K_LBK_LINK_MAX_FRS 65535 /* 64k */
195 #define SDP_LINK_CREDIT 0x320202
196
197 /* NIX RX action operation*/
198 #define NIX_RX_ACTIONOP_DROP (0x0ull)
199 #define NIX_RX_ACTIONOP_UCAST (0x1ull)
200 #define NIX_RX_ACTIONOP_UCAST_IPSEC (0x2ull)
201 #define NIX_RX_ACTIONOP_MCAST (0x3ull)
202 #define NIX_RX_ACTIONOP_RSS (0x4ull)
203 /* Use the RX action set in the default unicast entry */
204 #define NIX_RX_ACTION_DEFAULT (0xfull)
205
206 /* NIX TX action operation*/
207 #define NIX_TX_ACTIONOP_DROP (0x0ull)
208 #define NIX_TX_ACTIONOP_UCAST_DEFAULT (0x1ull)
209 #define NIX_TX_ACTIONOP_UCAST_CHAN (0x2ull)
210 #define NIX_TX_ACTIONOP_MCAST (0x3ull)
211 #define NIX_TX_ACTIONOP_DROP_VIOL (0x5ull)
212
213 #define NIX_INTFX_RX(a) (0x0ull | (a) << 1)
214 #define NIX_INTFX_TX(a) (0x1ull | (a) << 1)
215
216 /* Default interfaces are NIX0_RX and NIX0_TX */
217 #define NIX_INTF_RX NIX_INTFX_RX(0)
218 #define NIX_INTF_TX NIX_INTFX_TX(0)
219
220 #define NIX_INTF_TYPE_CGX 0
221 #define NIX_INTF_TYPE_LBK 1
222 #define NIX_INTF_TYPE_SDP 2
223
224 #define MAX_LMAC_PKIND 12
225 #define NIX_LINK_CGX_LMAC(a, b) (0 + 4 * (a) + (b))
226 #define NIX_LINK_LBK(a) (12 + (a))
227 #define NIX_CHAN_CGX_LMAC_CHX(a, b, c) (0x800 + 0x100 * (a) + 0x10 * (b) + (c))
228 #define NIX_CHAN_LBK_CHX(a, b) (0 + 0x100 * (a) + (b))
229 #define NIX_CHAN_SDP_CH_START (0x700ull)
230 #define NIX_CHAN_SDP_CHX(a) (NIX_CHAN_SDP_CH_START + (a))
231 #define NIX_CHAN_SDP_NUM_CHANS 256
232 #define NIX_CHAN_CPT_CH_START (0x800ull)
233
234 /* The mask is to extract lower 10-bits of channel number
235 * which CPT will pass to X2P.
236 */
237 #define NIX_CHAN_CPT_X2P_MASK (0x3ffull)
238
239 /* NIX LSO format indices.
240 * As of now TSO is the only one using, so statically assigning indices.
241 */
242 #define NIX_LSO_FORMAT_IDX_TSOV4 0
243 #define NIX_LSO_FORMAT_IDX_TSOV6 1
244
245 /* RSS info */
246 #define MAX_RSS_GROUPS 8
247 /* Group 0 has to be used in default pkt forwarding MCAM entries
248 * reserved for NIXLFs. Groups 1-7 can be used for RSS for ntuple
249 * filters.
250 */
251 #define DEFAULT_RSS_CONTEXT_GROUP 0
252 #define MAX_RSS_INDIR_TBL_SIZE 256 /* 1 << Max adder bits */
253
254 /* NDC info */
255 enum ndc_idx_e {
256 NIX0_RX = 0x0,
257 NIX0_TX = 0x1,
258 NPA0_U = 0x2,
259 NIX1_RX = 0x4,
260 NIX1_TX = 0x5,
261 };
262
263 enum ndc_ctype_e {
264 CACHING = 0x0,
265 BYPASS = 0x1,
266 };
267
268 #define NDC_MAX_PORT 6
269 #define NDC_READ_TRANS 0
270 #define NDC_WRITE_TRANS 1
271
272 #endif /* COMMON_H */
273