1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * AMD MP2 common macros and structures
4 *
5 * Copyright (c) 2022, Advanced Micro Devices, Inc.
6 * All Rights Reserved.
7 *
8 * Author: Basavaraj Natikar <Basavaraj.Natikar@amd.com>
9 */
10 #ifndef AMD_SFH_COMMON_H
11 #define AMD_SFH_COMMON_H
12
13 #include <linux/auxiliary_bus.h>
14 #include <linux/mutex.h>
15 #include <linux/pci.h>
16 #include <linux/sizes.h>
17 #include "amd_sfh_hid.h"
18
19 #define PCI_DEVICE_ID_AMD_MP2 0x15E4
20 #define PCI_DEVICE_ID_AMD_MP2_1_1 0x164A
21
22 /* The BAR 2 size must cover the highest register offset (0x10958) */
23 #define AMD_SFH_MIN_BAR_SIZE SZ_128K
24
25 #define AMD_C2P_MSG(regno) (0x10500 + ((regno) * 4))
26 #define AMD_P2C_MSG(regno) (0x10680 + ((regno) * 4))
27
28 #define AMD_C2P_MSG_V1(regno) (0x10900 + ((regno) * 4))
29 #define AMD_P2C_MSG_V1(regno) (0x10500 + ((regno) * 4))
30
31 #define SENSOR_ENABLED 4
32 #define SENSOR_DISABLED 5
33
34 #define AMD_SFH_IDLE_LOOP 200
35
36 enum cmd_id {
37 NO_OP,
38 ENABLE_SENSOR,
39 DISABLE_SENSOR,
40 STOP_ALL_SENSORS = 8,
41 };
42
43 enum amd_mp2_version {
44 MP2_VER_V2 = 1,
45 MP2_VER_1_1 = 2,
46 };
47
48 struct amd_mp2_sensor_info {
49 u8 sensor_idx;
50 u32 period;
51 dma_addr_t dma_address;
52 };
53
54 struct sfh_dev_status {
55 bool is_hpd_present;
56 bool is_hpd_enabled;
57 bool is_als_present;
58 bool is_sra_present;
59 };
60
61 struct amd_mp2_dev {
62 struct pci_dev *pdev;
63 struct amdtp_cl_data *cl_data;
64 void __iomem *mmio;
65 void __iomem *vsbase;
66 const struct amd_sfh1_1_ops *sfh1_1_ops;
67 struct amd_mp2_ops *mp2_ops;
68 struct amd_input_data in_data;
69 /* mp2 active control status */
70 u32 mp2_acs;
71 struct sfh_dev_status dev_en;
72 struct work_struct work;
73 /* mp2 to protect data */
74 struct mutex lock;
75 u8 init_done;
76 u8 rver;
77 u8 mp2_ver;
78 struct auxiliary_device *tm_auxdev;
79 };
80
81 struct amd_mp2_ops {
82 void (*start)(struct amd_mp2_dev *privdata, struct amd_mp2_sensor_info info);
83 void (*stop)(struct amd_mp2_dev *privdata, u16 sensor_idx);
84 void (*stop_all)(struct amd_mp2_dev *privdata);
85 int (*response)(struct amd_mp2_dev *mp2, u8 sid, u32 sensor_sts);
86 void (*clear_intr)(struct amd_mp2_dev *privdata);
87 int (*init_intr)(struct amd_mp2_dev *privdata);
88 int (*discovery_status)(struct amd_mp2_dev *privdata);
89 void (*suspend)(struct amd_mp2_dev *mp2);
90 void (*resume)(struct amd_mp2_dev *mp2);
91 void (*remove)(void *privdata);
92 int (*get_rep_desc)(int sensor_idx, u8 rep_desc[]);
93 u32 (*get_desc_sz)(int sensor_idx, int descriptor_name);
94 u8 (*get_feat_rep)(int sensor_idx, int report_id, u8 *feature_report);
95 u8 (*get_in_rep)(u8 current_index, int sensor_idx, int report_id,
96 struct amd_input_data *in_data);
97 };
98
99 void amd_sfh_work(struct work_struct *work);
100 void amd_sfh_work_buffer(struct work_struct *work);
101 void amd_sfh_clear_intr_v2(struct amd_mp2_dev *privdata);
102 int amd_sfh_irq_init_v2(struct amd_mp2_dev *privdata);
103 void amd_sfh_clear_intr(struct amd_mp2_dev *privdata);
104 int amd_sfh_irq_init(struct amd_mp2_dev *privdata);
105
amd_get_c2p_val(struct amd_mp2_dev * mp2,u32 idx)106 static inline u64 amd_get_c2p_val(struct amd_mp2_dev *mp2, u32 idx)
107 {
108 return mp2->rver == 1 ? AMD_C2P_MSG_V1(idx) : AMD_C2P_MSG(idx);
109 }
110
amd_get_p2c_val(struct amd_mp2_dev * mp2,u32 idx)111 static inline u64 amd_get_p2c_val(struct amd_mp2_dev *mp2, u32 idx)
112 {
113 return mp2->rver == 1 ? AMD_P2C_MSG_V1(idx) : AMD_P2C_MSG(idx);
114 }
115
116 bool amd_sfh_op_idx_enabled(struct amd_mp2_dev *mp2);
117 void sfh_set_emp2(struct amd_mp2_dev *mp2);
118 void sfh_deinit_emp2(void);
119
120 #endif
121