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Searched refs:NBIO_HWIP (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dcyan_skillfish_reg_init.c42 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in cyan_skillfish_reg_base_init()
H A Ddimgrey_cavefish_reg_init.c39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
H A Darct_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIF0_BASE.instance[i])); in arct_reg_base_init()
H A Dvega10_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
H A Dvega20_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
H A Damdgpu_discovery.c224 [NBIO_HWIP] = NBIF_HWID,
2644 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 1, 0); in amdgpu_discovery_set_ip_blocks()
2673 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(6, 2, 0); in amdgpu_discovery_set_ip_blocks()
2703 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 1); in amdgpu_discovery_set_ip_blocks()
2720 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 0, 0); in amdgpu_discovery_set_ip_blocks()
2750 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 0); in amdgpu_discovery_set_ip_blocks()
2787 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 1); in amdgpu_discovery_set_ip_blocks()
2819 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(7, 4, 4); in amdgpu_discovery_set_ip_blocks()
2852 adev->ip_versions[NBIO_HWIP][0] = IP_VERSION(2, 1, 1); in amdgpu_discovery_set_ip_blocks()
2965 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in amdgpu_discovery_set_ip_blocks()
H A Dnbio_v7_11.c277 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in nbio_v7_11_init_registers()
H A Damdgpu_dev_coredump.c51 [NBIO_HWIP] = "NBIO",
H A Dsoc21.c965 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc21_common_set_clockgating_state()
H A Dsoc15.c1421 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in soc15_common_set_clockgating_state()
H A Damdgpu.h777 NBIO_HWIP, enumerator
H A Damdgpu_ras.c4304 switch (amdgpu_ip_version(adev, NBIO_HWIP, 0)) { in amdgpu_ras_init()
/linux/drivers/gpu/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c1987 init_data.nbio_reg_offsets = adev->reg_offset[NBIO_HWIP][0]; in amdgpu_dm_init()