| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | vega20_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
49 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
|
| H A D | cyan_skillfish_reg_init.c | 42 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in cyan_skillfish_reg_base_init()
|
| H A D | dimgrey_cavefish_reg_init.c | 39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
|
| H A D | aldebaran_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
|
| H A D | vega10_reg_init.c | 38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
|
| /linux/drivers/gpu/drm/amd/include/ |
| H A D | cyan_skillfish_ip_offset.h | 97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x000… variable
|
| H A D | navi10_ip_offset.h | 97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x000… variable
|
| H A D | dimgrey_cavefish_ip_offset.h | 121 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
|
| H A D | vega20_ip_offset.h | 97 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, … variable
|
| H A D | sienna_cichlid_ip_offset.h | 128 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
|
| H A D | beige_goby_ip_offset.h | 136 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
|
| H A D | vega10_ip_offset.h | 41 static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, … variable
|
| H A D | yellow_carp_offset.h | 131 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
|
| H A D | vangogh_ip_offset.h | 160 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
|
| H A D | aldebaran_ip_offset.h | 147 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.c | 202 #define NBIO_BASE(seg) \ macro
206 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
210 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
|
| /linux/drivers/gpu/drm/amd/display/dc/resource/dcn351/ |
| H A D | dcn351_resource.c | 182 #define NBIO_BASE(seg) \ macro
186 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
190 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX1_ ## reg_name ## _BASE_IDX) + \
|