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Searched refs:NBIO_BASE (Results 1 – 25 of 32) sorted by relevance

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/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvega20_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
49 adev->reg_offset[NBIF_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega20_reg_base_init()
H A Ddimgrey_cavefish_reg_init.c39 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
H A Daldebaran_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in aldebaran_reg_base_init()
H A Dvega10_reg_init.c38 adev->reg_offset[NBIO_HWIP][i] = (uint32_t *)(&(NBIO_BASE.instance[i])); in vega10_reg_base_init()
/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
H A Ddcn315_smu.c52 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
71 …(NBIO_BASE.instance[0].segment[regBIF_BX_PF2_ ## reg_name ## _BASE_IDX] + regBIF_BX_PF2_ ## reg_na…
/linux/drivers/gpu/drm/amd/display/dc/resource/dce120/
H A Ddce120_resource.c129 #define NBIO_BASE(seg) \ macro
493 .BIOS_SCRATCH_3 = mmBIOS_SCRATCH_3 + NBIO_BASE(mmBIOS_SCRATCH_3_BASE_IDX),
494 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6 + NBIO_BASE(mmBIOS_SCRATCH_6_BASE_IDX)
/linux/drivers/gpu/drm/amd/include/
H A Dcyan_skillfish_ip_offset.h97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x000… variable
H A Dnavi10_ip_offset.h97 static const struct IP_BASE NBIO_BASE ={ { { { 0x00000000, 0x00000014, 0x00000D20, 0x000… variable
H A Ddimgrey_cavefish_ip_offset.h121 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
H A Dvega20_ip_offset.h97 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0, … variable
H A Dsienna_cichlid_ip_offset.h128 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
H A Dbeige_goby_ip_offset.h136 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
H A Dvega10_ip_offset.h41 static const struct IP_BASE __maybe_unused NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, … variable
H A Dyellow_carp_offset.h131 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
H A Dvangogh_ip_offset.h160 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
H A Daldebaran_ip_offset.h147 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0… variable
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn201/
H A Ddcn201_resource.c282 #define NBIO_BASE(seg) \ macro
286 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn321/
H A Ddcn321_resource.c186 #define NBIO_BASE(seg) \ macro
190 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
193 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.c202 #define NBIO_BASE(seg) \ macro
206 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
210 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX2_ ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn10/
H A Ddcn10_resource.c136 #define NBIO_BASE(seg) \ macro
140 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn302/
H A Ddcn302_resource.c164 #define NBIO_BASE(seg) \ macro
168 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn303/
H A Ddcn303_resource.c161 #define NBIO_BASE(seg) \ macro
165 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.c177 #define NBIO_BASE(seg) \ macro
181 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
184 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn301/
H A Ddcn301_resource.c164 #define NBIO_BASE(seg) \ macro
168 .reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c129 #define NBIO_BASE(seg) \ macro
133 .reg_name = NBIO_BASE(mm ## reg_name ## _BASE_IDX) + \

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