1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * mt8188-afe-common.h -- MediaTek 8188 audio driver definitions 4 * 5 * Copyright (c) 2022 MediaTek Inc. 6 * Author: Bicycle Tsai <bicycle.tsai@mediatek.com> 7 * Trevor Wu <trevor.wu@mediatek.com> 8 * Chun-Chia Chiu <chun-chia.chiu@mediatek.com> 9 */ 10 11 #ifndef _MT_8188_AFE_COMMON_H_ 12 #define _MT_8188_AFE_COMMON_H_ 13 14 #include <linux/list.h> 15 #include <linux/regmap.h> 16 #include <sound/soc.h> 17 #include "../common/mtk-base-afe.h" 18 19 enum { 20 MT8188_DAI_START, 21 MT8188_AFE_MEMIF_START = MT8188_DAI_START, 22 MT8188_AFE_MEMIF_DL2 = MT8188_AFE_MEMIF_START, 23 MT8188_AFE_MEMIF_DL3, 24 MT8188_AFE_MEMIF_DL6, 25 MT8188_AFE_MEMIF_DL7, 26 MT8188_AFE_MEMIF_DL8, 27 MT8188_AFE_MEMIF_DL10, 28 MT8188_AFE_MEMIF_DL11, 29 MT8188_AFE_MEMIF_UL_START, 30 MT8188_AFE_MEMIF_UL1 = MT8188_AFE_MEMIF_UL_START, 31 MT8188_AFE_MEMIF_UL2, 32 MT8188_AFE_MEMIF_UL3, 33 MT8188_AFE_MEMIF_UL4, 34 MT8188_AFE_MEMIF_UL5, 35 MT8188_AFE_MEMIF_UL6, 36 MT8188_AFE_MEMIF_UL8, 37 MT8188_AFE_MEMIF_UL9, 38 MT8188_AFE_MEMIF_UL10, 39 MT8188_AFE_MEMIF_END, 40 MT8188_AFE_MEMIF_NUM = (MT8188_AFE_MEMIF_END - MT8188_AFE_MEMIF_START), 41 MT8188_AFE_IO_START = MT8188_AFE_MEMIF_END, 42 MT8188_AFE_IO_DL_SRC = MT8188_AFE_IO_START, 43 MT8188_AFE_IO_DMIC_IN, 44 MT8188_AFE_IO_DPTX, 45 MT8188_AFE_IO_ETDM_START, 46 MT8188_AFE_IO_ETDM1_IN = MT8188_AFE_IO_ETDM_START, 47 MT8188_AFE_IO_ETDM2_IN, 48 MT8188_AFE_IO_ETDM1_OUT, 49 MT8188_AFE_IO_ETDM2_OUT, 50 MT8188_AFE_IO_ETDM3_OUT, 51 MT8188_AFE_IO_ETDM_END, 52 MT8188_AFE_IO_ETDM_NUM = 53 (MT8188_AFE_IO_ETDM_END - MT8188_AFE_IO_ETDM_START), 54 MT8188_AFE_IO_PCM = MT8188_AFE_IO_ETDM_END, 55 MT8188_AFE_IO_UL_SRC, 56 MT8188_AFE_IO_END, 57 MT8188_AFE_IO_NUM = (MT8188_AFE_IO_END - MT8188_AFE_IO_START), 58 MT8188_DAI_END = MT8188_AFE_IO_END, 59 MT8188_DAI_NUM = (MT8188_DAI_END - MT8188_DAI_START), 60 }; 61 62 enum { 63 MT8188_TOP_CG_A1SYS_TIMING, 64 MT8188_TOP_CG_A2SYS_TIMING, 65 MT8188_TOP_CG_26M_TIMING, 66 MT8188_TOP_CG_NUM, 67 }; 68 69 enum { 70 MT8188_AFE_IRQ_1, 71 MT8188_AFE_IRQ_2, 72 MT8188_AFE_IRQ_3, 73 MT8188_AFE_IRQ_8, 74 MT8188_AFE_IRQ_9, 75 MT8188_AFE_IRQ_10, 76 MT8188_AFE_IRQ_13, 77 MT8188_AFE_IRQ_14, 78 MT8188_AFE_IRQ_15, 79 MT8188_AFE_IRQ_16, 80 MT8188_AFE_IRQ_17, 81 MT8188_AFE_IRQ_18, 82 MT8188_AFE_IRQ_19, 83 MT8188_AFE_IRQ_20, 84 MT8188_AFE_IRQ_21, 85 MT8188_AFE_IRQ_22, 86 MT8188_AFE_IRQ_23, 87 MT8188_AFE_IRQ_24, 88 MT8188_AFE_IRQ_25, 89 MT8188_AFE_IRQ_26, 90 MT8188_AFE_IRQ_27, 91 MT8188_AFE_IRQ_28, 92 MT8188_AFE_IRQ_NUM, 93 }; 94 95 enum { 96 MT8188_ETDM_OUT1_1X_EN = 9, 97 MT8188_ETDM_OUT2_1X_EN = 10, 98 MT8188_ETDM_OUT3_1X_EN = 11, 99 MT8188_ETDM_IN1_1X_EN = 12, 100 MT8188_ETDM_IN2_1X_EN = 13, 101 MT8188_ETDM_IN1_NX_EN = 25, 102 MT8188_ETDM_IN2_NX_EN = 26, 103 }; 104 105 enum { 106 MT8188_MTKAIF_MISO_0, 107 MT8188_MTKAIF_MISO_1, 108 MT8188_MTKAIF_MISO_NUM, 109 }; 110 111 struct mtk_dai_memif_irq_priv { 112 unsigned int asys_timing_sel; 113 }; 114 115 struct mtkaif_param { 116 bool mtkaif_calibration_ok; 117 int mtkaif_chosen_phase[MT8188_MTKAIF_MISO_NUM]; 118 int mtkaif_phase_cycle[MT8188_MTKAIF_MISO_NUM]; 119 int mtkaif_dmic_on; 120 }; 121 122 struct clk; 123 124 struct mt8188_afe_private { 125 struct clk **clk; 126 struct clk_lookup **lookup; 127 struct regmap *topckgen; 128 int pm_runtime_bypass_reg_ctl; 129 spinlock_t afe_ctrl_lock; /* Lock for afe control */ 130 struct mtk_dai_memif_irq_priv irq_priv[MT8188_AFE_IRQ_NUM]; 131 struct mtkaif_param mtkaif_params; 132 133 /* dai */ 134 void *dai_priv[MT8188_DAI_NUM]; 135 }; 136 137 int mt8188_afe_fs_timing(unsigned int rate); 138 /* dai register */ 139 int mt8188_dai_adda_register(struct mtk_base_afe *afe); 140 int mt8188_dai_etdm_register(struct mtk_base_afe *afe); 141 int mt8188_dai_pcm_register(struct mtk_base_afe *afe); 142 143 #define MT8188_SOC_ENUM_EXT(xname, xenum, xhandler_get, xhandler_put, id) \ 144 { \ 145 .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \ 146 .info = snd_soc_info_enum_double, \ 147 .get = xhandler_get, .put = xhandler_put, \ 148 .device = id, \ 149 .private_value = (unsigned long)&(xenum), \ 150 } 151 152 #endif 153