1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3 * Copyright (C) 2022 MediaTek Inc.
4 */
5
6 #ifndef __MT7996_H
7 #define __MT7996_H
8
9 #include <linux/interrupt.h>
10 #include <linux/ktime.h>
11 #include "../mt76_connac.h"
12 #include "regs.h"
13
14 #define MT7996_MAX_RADIOS 3
15 #define MT7996_MAX_INTERFACES 19 /* per-band */
16 #define MT7996_MAX_WMM_SETS 4
17 #define MT7996_WTBL_BMC_SIZE (is_mt7996(&dev->mt76) ? 64 : 32)
18 #define MT7996_WTBL_RESERVED (mt7996_wtbl_size(dev) - 1)
19 #define MT7996_WTBL_STA (MT7996_WTBL_RESERVED - \
20 mt7996_max_interface_num(dev))
21
22 #define MT7996_WATCHDOG_TIME (HZ / 10)
23 #define MT7996_RESET_TIMEOUT (30 * HZ)
24
25 #define MT7996_TX_RING_SIZE 2048
26 #define MT7996_TX_MCU_RING_SIZE 256
27 #define MT7996_TX_FWDL_RING_SIZE 128
28
29 #define MT7996_RX_RING_SIZE 1536
30 #define MT7996_RX_MCU_RING_SIZE 512
31 #define MT7996_RX_MCU_RING_SIZE_WA 1024
32 #define MT7996_NPU_TX_RING_SIZE 1024
33 #define MT7996_NPU_RX_RING_SIZE 1024
34 #define MT7996_NPU_TXD_SIZE 3
35
36 /* scatter-gather of mcu event is not supported in connac3 */
37 #define MT7996_RX_MCU_BUF_SIZE (2048 + \
38 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
39
40 #define MT7996_DEVICE_ID 0x7990
41 #define MT7996_DEVICE_ID_2 0x7991
42 #define MT7992_DEVICE_ID 0x7992
43 #define MT7992_DEVICE_ID_2 0x799a
44 #define MT7990_DEVICE_ID 0x7993
45 #define MT7990_DEVICE_ID_2 0x799b
46
47 #define MT7996_FIRMWARE_WA "mediatek/mt7996/mt7996_wa.bin"
48 #define MT7996_FIRMWARE_WM "mediatek/mt7996/mt7996_wm.bin"
49 #define MT7996_FIRMWARE_DSP "mediatek/mt7996/mt7996_dsp.bin"
50 #define MT7996_ROM_PATCH "mediatek/mt7996/mt7996_rom_patch.bin"
51
52 #define MT7996_FIRMWARE_WA_233 "mediatek/mt7996/mt7996_wa_233.bin"
53 #define MT7996_FIRMWARE_WM_233 "mediatek/mt7996/mt7996_wm_233.bin"
54 #define MT7996_FIRMWARE_DSP_233 MT7996_FIRMWARE_DSP
55 #define MT7996_ROM_PATCH_233 "mediatek/mt7996/mt7996_rom_patch_233.bin"
56
57 #define MT7992_FIRMWARE_WA "mediatek/mt7996/mt7992_wa.bin"
58 #define MT7992_FIRMWARE_WM "mediatek/mt7996/mt7992_wm.bin"
59 #define MT7992_FIRMWARE_DSP "mediatek/mt7996/mt7992_dsp.bin"
60 #define MT7992_ROM_PATCH "mediatek/mt7996/mt7992_rom_patch.bin"
61
62 #define MT7992_FIRMWARE_WA_23 "mediatek/mt7996/mt7992_wa_23.bin"
63 #define MT7992_FIRMWARE_WM_23 "mediatek/mt7996/mt7992_wm_23.bin"
64 #define MT7992_FIRMWARE_DSP_23 "mediatek/mt7996/mt7992_dsp_23.bin"
65 #define MT7992_ROM_PATCH_23 "mediatek/mt7996/mt7992_rom_patch_23.bin"
66
67 #define MT7992_FIRMWARE_WA_24 "mediatek/mt7996/mt7992_wa_24.bin"
68 #define MT7992_FIRMWARE_WM_24 "mediatek/mt7996/mt7992_wm_24.bin"
69 #define MT7992_FIRMWARE_DSP_24 "mediatek/mt7996/mt7992_dsp_24.bin"
70 #define MT7992_ROM_PATCH_24 "mediatek/mt7996/mt7992_rom_patch_24.bin"
71
72 #define MT7990_FIRMWARE_WA ""
73 #define MT7990_FIRMWARE_WM "mediatek/mt7996/mt7990_wm.bin"
74 #define MT7990_FIRMWARE_DSP ""
75 #define MT7990_ROM_PATCH "mediatek/mt7996/mt7990_rom_patch.bin"
76
77 #define MT7996_EEPROM_DEFAULT "mediatek/mt7996/mt7996_eeprom.bin"
78 #define MT7996_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7996_eeprom_2i5i6i.bin"
79 #define MT7996_EEPROM_DEFAULT_233 "mediatek/mt7996/mt7996_eeprom_233.bin"
80 #define MT7996_EEPROM_DEFAULT_233_INT "mediatek/mt7996/mt7996_eeprom_233_2i5i6i.bin"
81
82 #define MT7992_EEPROM_DEFAULT "mediatek/mt7996/mt7992_eeprom.bin"
83 #define MT7992_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7992_eeprom_2i5i.bin"
84 #define MT7992_EEPROM_DEFAULT_MIX "mediatek/mt7996/mt7992_eeprom_2i5e.bin"
85 #define MT7992_EEPROM_DEFAULT_23 "mediatek/mt7996/mt7992_eeprom_23.bin"
86 #define MT7992_EEPROM_DEFAULT_23_INT "mediatek/mt7996/mt7992_eeprom_23_2i5i.bin"
87 #define MT7992_EEPROM_DEFAULT_24 "mediatek/mt7996/mt7992_eeprom_24_2i5i.bin"
88
89 #define MT7990_EEPROM_DEFAULT "mediatek/mt7996/mt7990_eeprom.bin"
90 #define MT7990_EEPROM_DEFAULT_INT "mediatek/mt7996/mt7990_eeprom_2i5i.bin"
91
92 #define MT7996_EEPROM_SIZE 7680
93 #define MT7996_EEPROM_BLOCK_SIZE 16
94 #define MT7996_EXT_EEPROM_BLOCK_SIZE 1024
95 #define MT7996_TOKEN_SIZE 16384
96 #define MT7996_HW_TOKEN_SIZE 8192
97
98 #define MT7996_CFEND_RATE_DEFAULT 0x49 /* OFDM 24M */
99 #define MT7996_CFEND_RATE_11B 0x03 /* 11B LP, 11M */
100 #define MT7996_IBF_MAX_NC 2
101 #define MT7996_IBF_TIMEOUT 0x18
102 #define MT7996_IBF_TIMEOUT_LEGACY 0x48
103
104 #define MT7992_CFEND_RATE_DEFAULT 0x4b /* OFDM 6M */
105 #define MT7992_IBF_TIMEOUT 0xff
106
107 #define MT7996_SKU_RATE_NUM 417
108 #define MT7996_SKU_PATH_NUM 494
109
110 #define MT7996_MAX_TWT_AGRT 16
111 #define MT7996_MAX_STA_TWT_AGRT 8
112 #define MT7996_MIN_TWT_DUR 64
113 #define MT7996_MAX_QUEUE (__MT_RXQ_MAX + __MT_MCUQ_MAX + 3)
114
115 /* NOTE: used to map mt76_rates. idx may change if firmware expands table */
116 #define MT7996_BASIC_RATES_TBL 31
117 #define MT7996_BEACON_RATES_TBL 25
118
119 #define MT7996_THERMAL_THROTTLE_MAX 100
120 #define MT7996_CDEV_THROTTLE_MAX 99
121 #define MT7996_CRIT_TEMP_IDX 0
122 #define MT7996_MAX_TEMP_IDX 1
123 #define MT7996_CRIT_TEMP 110
124 #define MT7996_MAX_TEMP 120
125
126 #define MT7996_MAX_HIF_RXD_IN_PG 5
127 #define MT7996_RRO_MSDU_PG_HASH_SIZE 127
128 #define MT7996_RRO_MAX_SESSION 1024
129 #define MT7996_RRO_WINDOW_MAX_LEN 1024
130 #define MT7996_RRO_ADDR_ELEM_LEN 128
131 #define MT7996_RRO_BA_BITMAP_LEN 2
132 #define MT7996_RRO_BA_BITMAP_CR_SIZE ((MT7996_RRO_MAX_SESSION * 128) / \
133 MT7996_RRO_BA_BITMAP_LEN)
134 #define MT7996_RRO_BA_BITMAP_SESSION_SIZE (MT7996_RRO_MAX_SESSION / \
135 MT7996_RRO_ADDR_ELEM_LEN)
136 #define MT7996_RRO_WINDOW_MAX_SIZE (MT7996_RRO_WINDOW_MAX_LEN * \
137 MT7996_RRO_BA_BITMAP_SESSION_SIZE)
138
139 #define MT7996_RX_BUF_SIZE (1800 + \
140 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
141 #define MT7996_RX_MSDU_PAGE_SIZE (128 + \
142 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
143
144 /* RRO 3.1 */
145 #define MT7996_RRO_MSDU_PG_CR_CNT 8
146 #define MT7996_RRO_MSDU_PG_SIZE_PER_CR 0x10000
147
148 struct mt7996_vif;
149 struct mt7996_sta;
150 struct mt7996_dfs_pulse;
151 struct mt7996_dfs_pattern;
152
153 enum mt7996_ram_type {
154 MT7996_RAM_TYPE_WM,
155 MT7996_RAM_TYPE_WA,
156 MT7996_RAM_TYPE_DSP,
157 };
158
159 enum mt7996_var_type {
160 MT7996_VAR_TYPE_444,
161 MT7996_VAR_TYPE_233,
162 };
163
164 enum mt7992_var_type {
165 MT7992_VAR_TYPE_44,
166 MT7992_VAR_TYPE_23,
167 MT7992_VAR_TYPE_24,
168 };
169
170 enum mt7990_var_type {
171 MT7990_VAR_TYPE_23,
172 };
173
174 enum mt7996_fem_type {
175 MT7996_FEM_EXT,
176 MT7996_FEM_INT,
177 MT7996_FEM_MIX,
178 };
179
180 enum mt7996_eeprom_mode {
181 EEPROM_MODE_DEFAULT_BIN,
182 EEPROM_MODE_EFUSE,
183 EEPROM_MODE_FLASH,
184 EEPROM_MODE_EXT,
185 };
186
187 #define MT7996_EFUSE_BASE_OFFS_ADIE0 0x400
188 #define MT7996_EFUSE_BASE_OFFS_ADIE1 0x1e00
189 #define MT7996_EFUSE_BASE_OFFS_ADIE2 0x1200
190 #define MT7992_EFUSE_BASE_OFFS_ADIE1 0x1200
191
192 enum mt7996_txq_id {
193 MT7996_TXQ_FWDL = 16,
194 MT7996_TXQ_MCU_WM,
195 MT7996_TXQ_BAND0,
196 MT7996_TXQ_BAND1,
197 MT7996_TXQ_MCU_WA,
198 MT7996_TXQ_BAND2,
199 };
200
201 enum mt7996_rxq_id {
202 MT7996_RXQ_MCU_WM = 0,
203 MT7996_RXQ_MCU_WA,
204 MT7996_RXQ_MCU_WA_MAIN = 2,
205 MT7996_RXQ_MCU_WA_EXT = 3, /* for mt7992 */
206 MT7996_RXQ_MCU_WA_TRI = 3,
207 MT7996_RXQ_BAND0 = 4,
208 MT7996_RXQ_BAND1 = 5, /* for mt7992 */
209 MT7996_RXQ_BAND2 = 5,
210 MT7996_RXQ_RRO_BAND0 = 8,
211 MT7996_RXQ_RRO_BAND1 = 9,
212 MT7996_RXQ_RRO_BAND2 = 6,
213 MT7996_RXQ_MSDU_PG_BAND0 = 10,
214 MT7996_RXQ_MSDU_PG_BAND1 = 11,
215 MT7996_RXQ_MSDU_PG_BAND2 = 12,
216 MT7996_RXQ_TXFREE0 = 9,
217 MT7996_RXQ_TXFREE1 = 9,
218 MT7996_RXQ_TXFREE2 = 7,
219 MT7996_RXQ_RRO_IND = 0,
220 MT7996_RXQ_RRO_RXDMAD_C = 0,
221 MT7990_RXQ_TXFREE0 = 6,
222 MT7990_RXQ_TXFREE1 = 7,
223 };
224
225 struct mt7996_twt_flow {
226 struct list_head list;
227 u64 start_tsf;
228 u64 tsf;
229 u32 duration;
230 u16 wcid;
231 __le16 mantissa;
232 u8 exp;
233 u8 table_id;
234 u8 id;
235 u8 protection:1;
236 u8 flowtype:1;
237 u8 trigger:1;
238 u8 sched:1;
239 };
240
241 DECLARE_EWMA(avg_signal, 10, 8)
242
243 struct mt7996_sta_link {
244 struct mt76_wcid wcid; /* must be first */
245
246 struct mt7996_sta *sta;
247
248 struct list_head rc_list;
249 u32 airtime_ac[8];
250
251 int ack_signal;
252 struct ewma_avg_signal avg_ack_signal;
253
254 unsigned long changed;
255
256 struct mt76_connac_sta_key_conf bip;
257
258 struct {
259 u8 flowid_mask;
260 struct mt7996_twt_flow flow[MT7996_MAX_STA_TWT_AGRT];
261 } twt;
262
263 struct rcu_head rcu_head;
264 };
265
266 struct mt7996_sta {
267 struct mt7996_sta_link deflink; /* must be first */
268 struct mt7996_sta_link __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
269 u8 deflink_id;
270 u8 seclink_id;
271
272 struct mt7996_vif *vif;
273 };
274
275 struct mt7996_vif_link {
276 struct mt76_vif_link mt76; /* must be first */
277
278 struct mt7996_sta_link msta_link;
279 struct cfg80211_bitrate_mask bitrate_mask;
280
281 u8 mld_idx;
282 };
283
284 struct mt7996_vif_link_info {
285 struct ieee80211_tx_queue_params queue_params[IEEE80211_NUM_ACS];
286 };
287
288 struct mt7996_vif {
289 struct mt7996_vif_link deflink; /* must be first */
290 struct mt76_vif_data mt76;
291
292 struct mt7996_vif_link_info link_info[IEEE80211_MLD_MAX_NUM_LINKS];
293
294 u8 mld_group_idx;
295 u8 mld_remap_idx;
296 };
297
298 /* crash-dump */
299 struct mt7996_crash_data {
300 guid_t guid;
301 struct timespec64 timestamp;
302
303 u8 *memdump_buf;
304 size_t memdump_buf_len;
305 };
306
307 struct mt7996_hif {
308 struct list_head list;
309
310 struct device *dev;
311 void __iomem *regs;
312 int irq;
313
314 enum pci_bus_speed speed;
315 enum pcie_link_width width;
316 };
317
318 #define WED_RRO_ADDR_SIGNATURE_MASK GENMASK(31, 24)
319 #define WED_RRO_ADDR_COUNT_MASK GENMASK(14, 4)
320 #define WED_RRO_ADDR_HEAD_HIGH_MASK GENMASK(3, 0)
321 struct mt7996_wed_rro_addr {
322 __le32 head_low;
323 __le32 data;
324 };
325
326 struct mt7996_wed_rro_session_id {
327 struct list_head list;
328 u16 id;
329 };
330
331 struct mt7996_msdu_page {
332 struct list_head list;
333
334 struct mt76_queue *q;
335 dma_addr_t dma_addr;
336 void *buf;
337 };
338
339 /* data1 */
340 #define RRO_HIF_DATA1_LS_MASK BIT(30)
341 #define RRO_HIF_DATA1_SDL_MASK GENMASK(29, 16)
342 /* data4 */
343 #define RRO_HIF_DATA4_RX_TOKEN_ID_MASK GENMASK(15, 0)
344 struct mt7996_rro_hif {
345 __le32 data0;
346 __le32 data1;
347 __le32 data2;
348 __le32 data3;
349 __le32 data4;
350 __le32 data5;
351 };
352
353 #define MSDU_PAGE_INFO_OWNER_MASK BIT(31)
354 #define MSDU_PAGE_INFO_PG_HIGH_MASK GENMASK(3, 0)
355 struct mt7996_msdu_page_info {
356 struct mt7996_rro_hif rxd[MT7996_MAX_HIF_RXD_IN_PG];
357 __le32 pg_low;
358 __le32 data;
359 };
360
361 #define MT7996_MAX_RRO_RRS_RING 4
362 struct mt7996_rro_queue_regs_emi {
363 struct {
364 __le16 idx;
365 __le16 rsv;
366 } ring[MT7996_MAX_RRO_RRS_RING];
367 };
368
369 struct mt7996_phy {
370 struct mt76_phy *mt76;
371 struct mt7996_dev *dev;
372
373 struct ieee80211_sband_iftype_data iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
374
375 struct thermal_cooling_device *cdev;
376 u8 cdev_state;
377 u8 throttle_state;
378 u32 throttle_temp[2]; /* 0: critical high, 1: maximum */
379
380 u32 rxfilter;
381 u64 omac_mask;
382
383 u16 noise;
384
385 s16 coverage_class;
386 u8 slottime;
387
388 u16 beacon_rate;
389
390 u32 rx_ampdu_ts;
391 u32 ampdu_ref;
392 int txpower;
393
394 struct mt76_mib_stats mib;
395 struct mt76_channel_state state_ts;
396
397 u16 orig_chainmask;
398 u16 orig_antenna_mask;
399
400 bool has_aux_rx;
401 bool counter_reset;
402 bool rdd_tx_paused;
403 };
404
405 struct mt7996_dev {
406 union { /* must be first */
407 struct mt76_dev mt76;
408 struct mt76_phy mphy;
409 };
410
411 struct mt7996_phy *radio_phy[MT7996_MAX_RADIOS];
412 struct wiphy_radio radios[MT7996_MAX_RADIOS];
413 struct wiphy_radio_freq_range radio_freqs[MT7996_MAX_RADIOS];
414 struct mac_address radio_addrs[MT7996_MAX_RADIOS];
415
416 struct mt7996_hif *hif2;
417 struct mt7996_reg_desc reg;
418 u8 q_id[MT7996_MAX_QUEUE];
419 u32 q_int_mask[MT7996_MAX_QUEUE];
420 u32 q_wfdma_mask;
421
422 u64 mld_idx_mask;
423 u64 mld_remap_idx_mask;
424
425 const struct mt76_bus_ops *bus_ops;
426 struct mt7996_phy phy;
427
428 /* monitor rx chain configured channel */
429 struct cfg80211_chan_def rdd2_chandef;
430 struct mt7996_phy *rdd2_phy;
431
432 u16 chainmask;
433 u8 chainshift[__MT_MAX_BAND];
434 u32 hif_idx;
435
436 struct work_struct init_work;
437 struct work_struct rc_work;
438 struct work_struct dump_work;
439 struct work_struct reset_work;
440 wait_queue_head_t reset_wait;
441 struct {
442 u32 state;
443 u32 wa_reset_count;
444 u32 wm_reset_count;
445 bool hw_full_reset:1;
446 bool hw_init_done:1;
447 bool restart:1;
448 } recovery;
449
450 /* protects coredump data */
451 struct mutex dump_mutex;
452 #ifdef CONFIG_DEV_COREDUMP
453 struct {
454 struct mt7996_crash_data *crash_data;
455 } coredump;
456 #endif
457
458 struct list_head sta_rc_list;
459 struct list_head twt_list;
460
461 u32 hw_pattern;
462
463 u8 eeprom_mode;
464 bool has_eht:1;
465
466 struct {
467 struct {
468 void *ptr;
469 dma_addr_t phy_addr;
470 } ba_bitmap[MT7996_RRO_BA_BITMAP_LEN];
471 struct {
472 void *ptr;
473 dma_addr_t phy_addr;
474 } addr_elem[MT7996_RRO_ADDR_ELEM_LEN];
475 struct {
476 void *ptr;
477 dma_addr_t phy_addr;
478 } session;
479 struct {
480 void *ptr;
481 dma_addr_t phy_addr;
482 } msdu_pg[MT7996_RRO_MSDU_PG_CR_CNT];
483 struct {
484 struct mt7996_rro_queue_regs_emi *ptr;
485 dma_addr_t phy_addr;
486 } emi_rings_cpu;
487 struct {
488 struct mt7996_rro_queue_regs_emi *ptr;
489 dma_addr_t phy_addr;
490 } emi_rings_dma;
491
492 struct work_struct work;
493 struct list_head poll_list;
494 spinlock_t lock;
495
496 struct list_head page_cache;
497 struct list_head page_map[MT7996_RRO_MSDU_PG_HASH_SIZE];
498 } wed_rro;
499
500 dma_addr_t npu_txd_addr[2 * MT7996_NPU_TXD_SIZE];
501
502 bool ibf;
503 u8 fw_debug_wm;
504 u8 fw_debug_wa;
505 u8 fw_debug_bin;
506 u16 fw_debug_seq;
507
508 struct dentry *debugfs_dir;
509 struct rchan *relay_fwlog;
510
511 struct {
512 u16 table_mask;
513 u8 n_agrt;
514 } twt;
515
516 spinlock_t reg_lock;
517
518 u8 wtbl_size_group;
519 struct {
520 u8 type:4;
521 u8 fem:4;
522 } var;
523 };
524
525 enum {
526 WFDMA0 = 0x0,
527 WFDMA1,
528 WFDMA_EXT,
529 __MT_WFDMA_MAX,
530 };
531
532 enum rdd_idx {
533 MT_RDD_IDX_BAND2, /* RDD idx for band idx 2 */
534 MT_RDD_IDX_BAND1, /* RDD idx for band idx 1 */
535 MT_RDD_IDX_BACKGROUND, /* RDD idx for background chain */
536 };
537
538 enum mt7996_rdd_cmd {
539 RDD_STOP,
540 RDD_START,
541 RDD_DET_MODE,
542 RDD_RADAR_EMULATE,
543 RDD_START_TXQ = 20,
544 RDD_CAC_START = 50,
545 RDD_CAC_END,
546 RDD_NORMAL_START,
547 RDD_DISABLE_DFS_CAL,
548 RDD_PULSE_DBG,
549 RDD_READ_PULSE,
550 RDD_RESUME_BF,
551 RDD_IRQ_OFF,
552 };
553
554 static inline int
mt7996_get_rdd_idx(struct mt7996_phy * phy,bool is_background)555 mt7996_get_rdd_idx(struct mt7996_phy *phy, bool is_background)
556 {
557 if (!phy->mt76->cap.has_5ghz)
558 return -1;
559
560 if (is_background)
561 return MT_RDD_IDX_BACKGROUND;
562
563 if (phy->mt76->band_idx == MT_BAND2)
564 return MT_RDD_IDX_BAND2;
565
566 return MT_RDD_IDX_BAND1;
567 }
568
569 static inline struct mt7996_dev *
mt7996_hw_dev(struct ieee80211_hw * hw)570 mt7996_hw_dev(struct ieee80211_hw *hw)
571 {
572 struct mt76_phy *phy = hw->priv;
573
574 return container_of(phy->dev, struct mt7996_dev, mt76);
575 }
576
577 static inline struct mt7996_phy *
__mt7996_phy(struct mt7996_dev * dev,enum mt76_band_id band)578 __mt7996_phy(struct mt7996_dev *dev, enum mt76_band_id band)
579 {
580 struct mt76_phy *phy = dev->mt76.phys[band];
581
582 if (!phy)
583 return NULL;
584
585 return phy->priv;
586 }
587
588 static inline struct mt7996_phy *
mt7996_phy2(struct mt7996_dev * dev)589 mt7996_phy2(struct mt7996_dev *dev)
590 {
591 return __mt7996_phy(dev, MT_BAND1);
592 }
593
594 static inline struct mt7996_phy *
mt7996_phy3(struct mt7996_dev * dev)595 mt7996_phy3(struct mt7996_dev *dev)
596 {
597 return __mt7996_phy(dev, MT_BAND2);
598 }
599
600 static inline bool
mt7996_band_valid(struct mt7996_dev * dev,u8 band)601 mt7996_band_valid(struct mt7996_dev *dev, u8 band)
602 {
603 if (!is_mt7996(&dev->mt76))
604 return band <= MT_BAND1;
605
606 return band <= MT_BAND2;
607 }
608
609 static inline struct mt7996_phy *
mt7996_band_phy(struct mt7996_dev * dev,enum nl80211_band band)610 mt7996_band_phy(struct mt7996_dev *dev, enum nl80211_band band)
611 {
612 struct mt76_phy *mphy;
613
614 mphy = dev->mt76.band_phys[band];
615 if (!mphy)
616 return NULL;
617
618 return mphy->priv;
619 }
620
621 static inline struct mt7996_vif_link *
mt7996_vif_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,int link_id)622 mt7996_vif_link(struct mt7996_dev *dev, struct ieee80211_vif *vif, int link_id)
623 {
624 return (struct mt7996_vif_link *)mt76_vif_link(&dev->mt76, vif, link_id);
625 }
626
627 static inline struct mt7996_phy *
mt7996_vif_link_phy(struct mt7996_vif_link * link)628 mt7996_vif_link_phy(struct mt7996_vif_link *link)
629 {
630 struct mt76_phy *mphy = mt76_vif_link_phy(&link->mt76);
631
632 if (!mphy)
633 return NULL;
634
635 return mphy->priv;
636 }
637
638 static inline struct mt7996_vif_link *
mt7996_vif_conf_link(struct mt7996_dev * dev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * link_conf)639 mt7996_vif_conf_link(struct mt7996_dev *dev, struct ieee80211_vif *vif,
640 struct ieee80211_bss_conf *link_conf)
641 {
642 return (struct mt7996_vif_link *)mt76_vif_conf_link(&dev->mt76, vif,
643 link_conf);
644 }
645
646 static inline struct mt7996_sta_link *
mt7996_sta_link(struct mt7996_sta * msta,u8 link_id)647 mt7996_sta_link(struct mt7996_sta *msta, u8 link_id)
648 {
649 if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS)
650 return NULL;
651
652 return rcu_dereference(msta->link[link_id]);
653 }
654
655 static inline struct mt7996_sta_link *
mt7996_sta_link_protected(struct mt7996_dev * dev,struct mt7996_sta * msta,u8 link_id)656 mt7996_sta_link_protected(struct mt7996_dev *dev, struct mt7996_sta *msta,
657 u8 link_id)
658 {
659 if (link_id >= IEEE80211_MLD_MAX_NUM_LINKS)
660 return NULL;
661
662 return mt76_dereference(msta->link[link_id], &dev->mt76);
663 }
664
665 #define mt7996_for_each_phy(dev, phy) \
666 for (int __i = 0; __i < ARRAY_SIZE((dev)->radio_phy); __i++) \
667 if (((phy) = (dev)->radio_phy[__i]) != NULL)
668
669 extern const struct ieee80211_ops mt7996_ops;
670 extern struct pci_driver mt7996_pci_driver;
671 extern struct pci_driver mt7996_hif_driver;
672
673 struct mt7996_dev *mt7996_mmio_probe(struct device *pdev,
674 void __iomem *mem_base, u32 device_id);
675 void mt7996_rro_hw_init(struct mt7996_dev *dev);
676 void mt7996_wfsys_reset(struct mt7996_dev *dev);
677 irqreturn_t mt7996_irq_handler(int irq, void *dev_instance);
678 u64 __mt7996_get_tsf(struct ieee80211_hw *hw, struct mt7996_vif_link *link);
679 int mt7996_register_device(struct mt7996_dev *dev);
680 void mt7996_unregister_device(struct mt7996_dev *dev);
681 int mt7996_vif_link_add(struct mt76_phy *mphy, struct ieee80211_vif *vif,
682 struct ieee80211_bss_conf *link_conf,
683 struct mt76_vif_link *mlink);
684 void mt7996_vif_link_remove(struct mt76_phy *mphy, struct ieee80211_vif *vif,
685 struct ieee80211_bss_conf *link_conf,
686 struct mt76_vif_link *mlink);
687 int mt7996_eeprom_init(struct mt7996_dev *dev);
688 int mt7996_eeprom_parse_hw_cap(struct mt7996_dev *dev, struct mt7996_phy *phy);
689 int mt7996_eeprom_get_target_power(struct mt7996_dev *dev,
690 struct ieee80211_channel *chan);
691 s8 mt7996_eeprom_get_power_delta(struct mt7996_dev *dev, int band);
692 bool mt7996_eeprom_has_background_radar(struct mt7996_dev *dev);
693 int mt7996_dma_init(struct mt7996_dev *dev);
694 void mt7996_dma_reset(struct mt7996_dev *dev, bool force);
695 void mt7996_dma_prefetch(struct mt7996_dev *dev);
696 void mt7996_dma_cleanup(struct mt7996_dev *dev);
697 void mt7996_dma_start(struct mt7996_dev *dev, bool reset, bool wed_reset);
698 int mt7996_init_tx_queues(struct mt7996_phy *phy, int idx,
699 int n_desc, int ring_base, struct mtk_wed_device *wed);
700 void mt7996_init_txpower(struct mt7996_phy *phy);
701 int mt7996_txbf_init(struct mt7996_dev *dev);
702 void mt7996_reset(struct mt7996_dev *dev);
703 int mt7996_run(struct mt7996_phy *phy);
704 int mt7996_mcu_init(struct mt7996_dev *dev);
705 int mt7996_mcu_init_firmware(struct mt7996_dev *dev);
706 int mt7996_mcu_twt_agrt_update(struct mt7996_dev *dev,
707 struct mt7996_vif_link *link,
708 struct mt7996_twt_flow *flow,
709 int cmd);
710 int mt7996_mcu_add_dev_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
711 struct ieee80211_bss_conf *link_conf,
712 struct mt76_vif_link *mlink, bool enable);
713 int mt7996_mcu_add_bss_info(struct mt7996_phy *phy, struct ieee80211_vif *vif,
714 struct ieee80211_bss_conf *link_conf,
715 struct mt76_vif_link *mlink,
716 struct mt7996_sta_link *msta_link, int enable);
717 int mt7996_mcu_update_bss_rfch(struct mt7996_phy *phy,
718 struct mt7996_vif_link *link);
719 int mt7996_mcu_add_sta(struct mt7996_dev *dev,
720 struct ieee80211_bss_conf *link_conf,
721 struct ieee80211_link_sta *link_sta,
722 struct mt7996_vif_link *link,
723 struct mt7996_sta_link *msta_link,
724 int conn_state, bool newly);
725 int mt7996_mcu_teardown_mld_sta(struct mt7996_dev *dev,
726 struct mt7996_vif_link *link,
727 struct mt7996_sta_link *msta_link);
728 void mt7996_mcu_update_sta_rec_bw(void *data, struct ieee80211_sta *sta);
729 int mt7996_mcu_add_tx_ba(struct mt7996_dev *dev,
730 struct ieee80211_ampdu_params *params,
731 struct ieee80211_vif *vif, bool enable);
732 int mt7996_mcu_add_rx_ba(struct mt7996_dev *dev,
733 struct ieee80211_ampdu_params *params,
734 struct ieee80211_vif *vif, bool enable);
735 int mt7996_mcu_update_bss_color(struct mt7996_dev *dev,
736 struct mt76_vif_link *mlink,
737 struct cfg80211_he_bss_color *he_bss_color);
738 int mt7996_mcu_add_beacon(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
739 struct ieee80211_bss_conf *link_conf, bool enabled);
740 int mt7996_mcu_beacon_inband_discov(struct mt7996_dev *dev,
741 struct ieee80211_bss_conf *link_conf,
742 struct mt7996_vif_link *link, u32 changed);
743 int mt7996_mcu_add_obss_spr(struct mt7996_phy *phy,
744 struct mt7996_vif_link *link,
745 struct ieee80211_he_obss_pd *he_obss_pd);
746 int mt7996_mcu_add_rate_ctrl(struct mt7996_dev *dev, struct mt7996_sta *msta,
747 struct ieee80211_vif *vif, u8 link_id,
748 bool changed);
749 int mt7996_set_channel(struct mt76_phy *mphy);
750 int mt7996_mcu_set_chan_info(struct mt7996_phy *phy, u16 tag);
751 int mt7996_mcu_set_tx(struct mt7996_dev *dev, struct ieee80211_vif *vif,
752 struct ieee80211_bss_conf *link_conf);
753 int mt7996_mcu_set_fixed_rate_ctrl(struct mt7996_dev *dev,
754 void *data, u16 version);
755 int mt7996_mcu_set_fixed_field(struct mt7996_dev *dev, struct mt7996_sta *msta,
756 void *data, u8 link_id, u32 field);
757 int mt7996_mcu_set_eeprom(struct mt7996_dev *dev);
758 int mt7996_mcu_get_eeprom(struct mt7996_dev *dev, u32 offset, u8 *buf, u32 buf_len,
759 enum mt7996_eeprom_mode mode);
760 int mt7996_mcu_get_efuse_free_block(struct mt7996_dev *dev, u8 *block_num);
761 int mt7996_mcu_get_chip_config(struct mt7996_dev *dev, u32 *cap);
762 int mt7996_mcu_set_ser(struct mt7996_dev *dev, u8 action, u8 set, u8 band);
763 int mt7996_mcu_set_txbf(struct mt7996_dev *dev, u8 action);
764 int mt7996_mcu_set_fcc5_lpn(struct mt7996_dev *dev, int val);
765 int mt7996_mcu_set_pulse_th(struct mt7996_dev *dev,
766 const struct mt7996_dfs_pulse *pulse);
767 int mt7996_mcu_set_radar_th(struct mt7996_dev *dev, int index,
768 const struct mt7996_dfs_pattern *pattern);
769 int mt7996_mcu_set_radio_en(struct mt7996_phy *phy, bool enable);
770 int mt7996_mcu_set_rts_thresh(struct mt7996_phy *phy, u32 val);
771 int mt7996_mcu_set_protection(struct mt7996_phy *phy, struct mt7996_vif_link *link,
772 u8 ht_mode, bool use_cts_prot);
773 int mt7996_mcu_set_timing(struct mt7996_phy *phy, struct ieee80211_vif *vif,
774 struct ieee80211_bss_conf *link_conf);
775 int mt7996_mcu_set_bssid_mapping_addr(struct mt76_dev *dev, u8 band_idx);
776 int mt7996_mcu_get_chan_mib_info(struct mt7996_phy *phy, bool chan_switch);
777 int mt7996_mcu_get_temperature(struct mt7996_phy *phy);
778 int mt7996_mcu_set_thermal_throttling(struct mt7996_phy *phy, u8 state);
779 int mt7996_mcu_set_thermal_protect(struct mt7996_phy *phy, bool enable);
780 int mt7996_mcu_set_txpower_sku(struct mt7996_phy *phy);
781 int mt7996_mcu_rdd_resume_tx(struct mt7996_phy *phy);
782 int mt7996_mcu_rdd_cmd(struct mt7996_dev *dev, int cmd, u8 rdd_idx, u8 val);
783 int mt7996_mcu_rdd_background_enable(struct mt7996_phy *phy,
784 struct cfg80211_chan_def *chandef);
785 int mt7996_mcu_set_fixed_rate_table(struct mt7996_phy *phy, u8 table_idx,
786 u16 rate_idx, bool beacon);
787 int mt7996_mcu_rf_regval(struct mt7996_dev *dev, u32 regidx, u32 *val, bool set);
788 int mt7996_mcu_set_hdr_trans(struct mt7996_dev *dev, bool hdr_trans);
789 int mt7996_mcu_set_rro(struct mt7996_dev *dev, u16 tag, u16 val);
790 int mt7996_mcu_wa_cmd(struct mt7996_dev *dev, int cmd, u32 a1, u32 a2, u32 a3);
791 int mt7996_mcu_fw_log_2_host(struct mt7996_dev *dev, u8 type, u8 ctrl);
792 int mt7996_mcu_fw_dbg_ctrl(struct mt7996_dev *dev, u32 module, u8 level);
793 int mt7996_mcu_trigger_assert(struct mt7996_dev *dev);
794 void mt7996_mcu_rx_event(struct mt7996_dev *dev, struct sk_buff *skb);
795 void mt7996_mcu_exit(struct mt7996_dev *dev);
796 int mt7996_mcu_get_all_sta_info(struct mt7996_phy *phy, u16 tag);
797 int mt7996_mcu_wed_rro_reset_sessions(struct mt7996_dev *dev, u16 id);
798 int mt7996_mcu_set_sniffer_mode(struct mt7996_phy *phy, bool enabled);
799 int mt7996_mcu_set_dup_wtbl(struct mt7996_dev *dev);
800 int mt7996_mcu_mld_reconf_stop_link(struct mt7996_dev *dev,
801 struct ieee80211_vif *vif,
802 u16 removed_links);
803 int mt7996_mcu_mld_link_oper(struct mt7996_dev *dev,
804 struct ieee80211_bss_conf *link_conf,
805 struct mt7996_vif_link *link, bool add);
806
mt7996_has_hwrro(struct mt7996_dev * dev)807 static inline bool mt7996_has_hwrro(struct mt7996_dev *dev)
808 {
809 return dev->mt76.hwrro_mode != MT76_HWRRO_OFF;
810 }
811
mt7996_max_interface_num(struct mt7996_dev * dev)812 static inline u8 mt7996_max_interface_num(struct mt7996_dev *dev)
813 {
814 return min(MT7996_MAX_INTERFACES * (1 + mt7996_band_valid(dev, MT_BAND1) +
815 mt7996_band_valid(dev, MT_BAND2)),
816 MT7996_WTBL_BMC_SIZE);
817 }
818
mt7996_wtbl_size(struct mt7996_dev * dev)819 static inline u16 mt7996_wtbl_size(struct mt7996_dev *dev)
820 {
821 return (dev->wtbl_size_group << 8) + MT7996_WTBL_BMC_SIZE;
822 }
823
824 void mt7996_dual_hif_set_irq_mask(struct mt7996_dev *dev, bool write_reg,
825 u32 clear, u32 set);
826
mt7996_irq_enable(struct mt7996_dev * dev,u32 mask)827 static inline void mt7996_irq_enable(struct mt7996_dev *dev, u32 mask)
828 {
829 if (dev->hif2)
830 mt7996_dual_hif_set_irq_mask(dev, false, 0, mask);
831 else
832 mt76_set_irq_mask(&dev->mt76, 0, 0, mask);
833
834 tasklet_schedule(&dev->mt76.irq_tasklet);
835 }
836
mt7996_irq_disable(struct mt7996_dev * dev,u32 mask)837 static inline void mt7996_irq_disable(struct mt7996_dev *dev, u32 mask)
838 {
839 if (dev->hif2)
840 mt7996_dual_hif_set_irq_mask(dev, true, mask, 0);
841 else
842 mt76_set_irq_mask(&dev->mt76, MT_INT_MASK_CSR, mask, 0);
843 }
844
845 void mt7996_memcpy_fromio(struct mt7996_dev *dev, void *buf, u32 offset,
846 size_t len);
847
mt7996_rx_chainmask(struct mt7996_phy * phy)848 static inline u16 mt7996_rx_chainmask(struct mt7996_phy *phy)
849 {
850 int max_nss = hweight16(phy->orig_antenna_mask);
851 int cur_nss = hweight8(phy->mt76->antenna_mask);
852 u16 tx_chainmask = phy->mt76->chainmask;
853
854 if (cur_nss != max_nss)
855 return tx_chainmask;
856
857 return tx_chainmask | (BIT(fls(tx_chainmask)) * phy->has_aux_rx);
858 }
859
mt7996_has_wa(struct mt7996_dev * dev)860 static inline bool mt7996_has_wa(struct mt7996_dev *dev)
861 {
862 return !is_mt7990(&dev->mt76);
863 }
864
mt7996_has_ext_eeprom(struct mt7996_dev * dev)865 static inline bool mt7996_has_ext_eeprom(struct mt7996_dev *dev)
866 {
867 return !is_mt7996(&dev->mt76);
868 }
869
870 void mt7996_mac_init(struct mt7996_dev *dev);
871 u32 mt7996_mac_wtbl_lmac_addr(struct mt7996_dev *dev, u16 wcid, u8 dw);
872 bool mt7996_mac_wtbl_update(struct mt7996_dev *dev, int idx, u32 mask);
873 void mt7996_mac_reset_counters(struct mt7996_phy *phy);
874 void mt7996_mac_cca_stats_reset(struct mt7996_phy *phy);
875 void mt7996_mac_enable_nf(struct mt7996_dev *dev, u8 band);
876 struct mt76_wcid *mt7996_get_tx_wcid(struct mt76_wcid *wcid);
877 void mt7996_mac_write_txwi(struct mt7996_dev *dev, __le32 *txwi,
878 struct sk_buff *skb, struct mt76_wcid *wcid,
879 struct ieee80211_key_conf *key, int pid,
880 enum mt76_txq_id qid, u32 changed,
881 unsigned int link_id);
882 void mt7996_mac_update_beacons(struct mt7996_phy *phy);
883 void mt7996_mac_set_coverage_class(struct mt7996_phy *phy);
884 void mt7996_mac_work(struct work_struct *work);
885 void mt7996_mac_reset_work(struct work_struct *work);
886 void mt7996_mac_dump_work(struct work_struct *work);
887 void mt7996_mac_sta_rc_work(struct work_struct *work);
888 void mt7996_mac_update_stats(struct mt7996_phy *phy);
889 void mt7996_mac_twt_teardown_flow(struct mt7996_dev *dev,
890 struct mt7996_vif_link *link,
891 struct mt7996_sta_link *msta_link,
892 u8 flowid);
893 void mt7996_mac_sta_remove_link(struct mt7996_dev *dev,
894 struct ieee80211_sta *sta,
895 unsigned int link_id, bool flush);
896 void mt7996_mac_add_twt_setup(struct ieee80211_hw *hw,
897 struct ieee80211_sta *sta,
898 struct ieee80211_twt_setup *twt);
899 int mt7996_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
900 enum mt76_txq_id qid, struct mt76_wcid *wcid,
901 struct ieee80211_sta *sta,
902 struct mt76_tx_info *tx_info);
903 void mt7996_tx_token_put(struct mt7996_dev *dev);
904 void mt7996_queue_rx_skb(struct mt76_dev *mdev, enum mt76_rxq_id q,
905 struct sk_buff *skb, u32 *info);
906 void mt7996_rro_msdu_page_map_free(struct mt7996_dev *dev);
907 int mt7996_rro_msdu_page_add(struct mt76_dev *mdev, struct mt76_queue *q,
908 dma_addr_t dma_addr, void *data);
909 void mt7996_rro_rx_process(struct mt76_dev *mdev, void *data);
910 bool mt7996_rx_check(struct mt76_dev *mdev, void *data, int len);
911 void mt7996_stats_work(struct work_struct *work);
912 int mt76_dfs_start_rdd(struct mt7996_dev *dev, bool force);
913 int mt7996_dfs_init_radar_detector(struct mt7996_phy *phy);
914 void mt7996_set_stream_he_eht_caps(struct mt7996_phy *phy);
915 void mt7996_set_stream_vht_txbf_caps(struct mt7996_phy *phy);
916 void mt7996_update_channel(struct mt76_phy *mphy);
917 int mt7996_init_debugfs(struct mt7996_dev *dev);
918 void mt7996_debugfs_rx_fw_monitor(struct mt7996_dev *dev, const void *data, int len);
919 bool mt7996_debugfs_rx_log(struct mt7996_dev *dev, const void *data, int len);
920 int mt7996_mcu_add_key(struct mt76_dev *dev, struct mt7996_vif_link *link,
921 struct ieee80211_key_conf *key, int mcu_cmd,
922 struct mt76_wcid *wcid, enum set_key_cmd cmd);
923 int mt7996_mcu_bcn_prot_enable(struct mt7996_dev *dev,
924 struct mt7996_vif_link *link,
925 struct mt7996_sta_link *msta_link,
926 struct ieee80211_key_conf *key);
927 int mt7996_mcu_wtbl_update_hdr_trans(struct mt7996_dev *dev,
928 struct ieee80211_vif *vif,
929 struct mt7996_vif_link *link,
930 struct mt7996_sta_link *msta_link);
931 int mt7996_mcu_ps_leave(struct mt7996_dev *dev, struct mt7996_vif_link *link,
932 struct mt7996_sta_link *msta_link);
933 int mt7996_mcu_cp_support(struct mt7996_dev *dev, u8 mode);
934 int mt7996_mcu_set_emlsr_mode(struct mt7996_dev *dev,
935 struct ieee80211_vif *vif,
936 struct ieee80211_sta *sta,
937 struct ieee80211_eml_params *eml_params);
938 #ifdef CONFIG_MAC80211_DEBUGFS
939 void mt7996_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
940 struct ieee80211_sta *sta, struct dentry *dir);
941 void mt7996_link_sta_add_debugfs(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
942 struct ieee80211_link_sta *link_sta,
943 struct dentry *dir);
944 #endif
945 int mt7996_mmio_wed_init(struct mt7996_dev *dev, void *pdev_ptr,
946 bool hif2, int *irq);
947 u32 mt7996_wed_init_buf(void *ptr, dma_addr_t phys, int token_id);
948
949 int mt7996_dma_rro_init(struct mt7996_dev *dev);
950 void mt7996_dma_rro_start(struct mt7996_dev *dev);
951
952 #ifdef CONFIG_MT7996_NPU
953 int __mt7996_npu_hw_init(struct mt7996_dev *dev);
954 int mt7996_npu_hw_init(struct mt7996_dev *dev);
955 int mt7996_npu_hw_stop(struct mt7996_dev *dev);
956 int mt7996_npu_rx_queues_init(struct mt7996_dev *dev);
957 #else
__mt7996_npu_hw_init(struct mt7996_dev * dev)958 static inline int __mt7996_npu_hw_init(struct mt7996_dev *dev)
959 {
960 return 0;
961 }
962
mt7996_npu_hw_init(struct mt7996_dev * dev)963 static inline int mt7996_npu_hw_init(struct mt7996_dev *dev)
964 {
965 return 0;
966 }
967
mt7996_npu_hw_stop(struct mt7996_dev * dev)968 static inline int mt7996_npu_hw_stop(struct mt7996_dev *dev)
969 {
970 return 0;
971 }
972
mt7996_npu_rx_queues_init(struct mt7996_dev * dev)973 static inline int mt7996_npu_rx_queues_init(struct mt7996_dev *dev)
974 {
975 return 0;
976 }
977 #endif /* CONFIG_MT7996_NPU */
978
979 #endif
980