1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2020 MediaTek Inc. 4 */ 5 6 #ifndef __MFD_MT6358_REGISTERS_H__ 7 #define __MFD_MT6358_REGISTERS_H__ 8 9 /* PMIC Registers */ 10 #define MT6358_SWCID 0xa 11 #define MT6358_TOPSTATUS 0x28 12 #define MT6358_TOP_RST_MISC 0x14c 13 #define MT6358_MISC_TOP_INT_CON0 0x188 14 #define MT6358_MISC_TOP_INT_STATUS0 0x194 15 #define MT6358_TOP_INT_STATUS0 0x19e 16 #define MT6358_SCK_TOP_INT_CON0 0x52e 17 #define MT6358_SCK_TOP_INT_STATUS0 0x53a 18 #define MT6358_EOSC_CALI_CON0 0x540 19 #define MT6358_EOSC_CALI_CON1 0x542 20 #define MT6358_RTC_MIX_CON0 0x544 21 #define MT6358_RTC_MIX_CON1 0x546 22 #define MT6358_RTC_MIX_CON2 0x548 23 #define MT6358_RTC_DSN_ID 0x580 24 #define MT6358_RTC_DSN_REV0 0x582 25 #define MT6358_RTC_DBI 0x584 26 #define MT6358_RTC_DXI 0x586 27 #define MT6358_RTC_BBPU 0x588 28 #define MT6358_RTC_IRQ_STA 0x58a 29 #define MT6358_RTC_IRQ_EN 0x58c 30 #define MT6358_RTC_CII_EN 0x58e 31 #define MT6358_RTC_AL_MASK 0x590 32 #define MT6358_RTC_TC_SEC 0x592 33 #define MT6358_RTC_TC_MIN 0x594 34 #define MT6358_RTC_TC_HOU 0x596 35 #define MT6358_RTC_TC_DOM 0x598 36 #define MT6358_RTC_TC_DOW 0x59a 37 #define MT6358_RTC_TC_MTH 0x59c 38 #define MT6358_RTC_TC_YEA 0x59e 39 #define MT6358_RTC_AL_SEC 0x5a0 40 #define MT6358_RTC_AL_MIN 0x5a2 41 #define MT6358_RTC_AL_HOU 0x5a4 42 #define MT6358_RTC_AL_DOM 0x5a6 43 #define MT6358_RTC_AL_DOW 0x5a8 44 #define MT6358_RTC_AL_MTH 0x5aa 45 #define MT6358_RTC_AL_YEA 0x5ac 46 #define MT6358_RTC_OSC32CON 0x5ae 47 #define MT6358_RTC_POWERKEY1 0x5b0 48 #define MT6358_RTC_POWERKEY2 0x5b2 49 #define MT6358_RTC_PDN1 0x5b4 50 #define MT6358_RTC_PDN2 0x5b6 51 #define MT6358_RTC_SPAR0 0x5b8 52 #define MT6358_RTC_SPAR1 0x5ba 53 #define MT6358_RTC_PROT 0x5bc 54 #define MT6358_RTC_DIFF 0x5be 55 #define MT6358_RTC_CALI 0x5c0 56 #define MT6358_RTC_WRTGR 0x5c2 57 #define MT6358_RTC_CON 0x5c4 58 #define MT6358_RTC_SEC_CTRL 0x5c6 59 #define MT6358_RTC_INT_CNT 0x5c8 60 #define MT6358_RTC_SEC_DAT0 0x5ca 61 #define MT6358_RTC_SEC_DAT1 0x5cc 62 #define MT6358_RTC_SEC_DAT2 0x5ce 63 #define MT6358_RTC_SEC_DSN_ID 0x600 64 #define MT6358_RTC_SEC_DSN_REV0 0x602 65 #define MT6358_RTC_SEC_DBI 0x604 66 #define MT6358_RTC_SEC_DXI 0x606 67 #define MT6358_RTC_TC_SEC_SEC 0x608 68 #define MT6358_RTC_TC_MIN_SEC 0x60a 69 #define MT6358_RTC_TC_HOU_SEC 0x60c 70 #define MT6358_RTC_TC_DOM_SEC 0x60e 71 #define MT6358_RTC_TC_DOW_SEC 0x610 72 #define MT6358_RTC_TC_MTH_SEC 0x612 73 #define MT6358_RTC_TC_YEA_SEC 0x614 74 #define MT6358_RTC_SEC_CK_PDN 0x616 75 #define MT6358_RTC_SEC_WRTGR 0x618 76 #define MT6358_PSC_TOP_INT_CON0 0x910 77 #define MT6358_PSC_TOP_INT_STATUS0 0x91c 78 #define MT6358_BM_TOP_INT_CON0 0xc32 79 #define MT6358_BM_TOP_INT_CON1 0xc38 80 #define MT6358_BM_TOP_INT_STATUS0 0xc4a 81 #define MT6358_BM_TOP_INT_STATUS1 0xc4c 82 #define MT6358_HK_TOP_INT_CON0 0xf92 83 #define MT6358_HK_TOP_INT_STATUS0 0xf9e 84 #define MT6358_BUCK_TOP_INT_CON0 0x1318 85 #define MT6358_BUCK_TOP_INT_STATUS0 0x1324 86 #define MT6358_BUCK_VPROC11_CON0 0x1388 87 #define MT6358_BUCK_VPROC11_DBG0 0x139e 88 #define MT6358_BUCK_VPROC11_DBG1 0x13a0 89 #define MT6358_BUCK_VPROC11_ELR0 0x13a6 90 #define MT6358_BUCK_VPROC12_CON0 0x1408 91 #define MT6358_BUCK_VPROC12_DBG0 0x141e 92 #define MT6358_BUCK_VPROC12_DBG1 0x1420 93 #define MT6358_BUCK_VPROC12_ELR0 0x1426 94 #define MT6358_BUCK_VCORE_CON0 0x1488 95 #define MT6358_BUCK_VCORE_DBG0 0x149e 96 #define MT6358_BUCK_VCORE_DBG1 0x14a0 97 #define MT6358_BUCK_VCORE_SSHUB_CON0 0x14a4 98 #define MT6358_BUCK_VCORE_SSHUB_CON1 0x14a6 99 #define MT6358_BUCK_VCORE_SSHUB_ELR0 MT6358_BUCK_VCORE_SSHUB_CON1 100 #define MT6358_BUCK_VCORE_SSHUB_DBG1 MT6358_BUCK_VCORE_DBG1 101 #define MT6358_BUCK_VCORE_ELR0 0x14aa 102 #define MT6358_BUCK_VGPU_CON0 0x1508 103 #define MT6358_BUCK_VGPU_DBG0 0x151e 104 #define MT6358_BUCK_VGPU_DBG1 0x1520 105 #define MT6358_BUCK_VGPU_ELR0 0x1526 106 #define MT6358_BUCK_VMODEM_CON0 0x1588 107 #define MT6358_BUCK_VMODEM_DBG0 0x159e 108 #define MT6358_BUCK_VMODEM_DBG1 0x15a0 109 #define MT6358_BUCK_VMODEM_ELR0 0x15a6 110 #define MT6358_BUCK_VDRAM1_CON0 0x1608 111 #define MT6358_BUCK_VDRAM1_DBG0 0x161e 112 #define MT6358_BUCK_VDRAM1_DBG1 0x1620 113 #define MT6358_BUCK_VDRAM1_ELR0 0x1626 114 #define MT6358_BUCK_VS1_CON0 0x1688 115 #define MT6358_BUCK_VS1_DBG0 0x169e 116 #define MT6358_BUCK_VS1_DBG1 0x16a0 117 #define MT6358_BUCK_VS1_ELR0 0x16ae 118 #define MT6358_BUCK_VS2_CON0 0x1708 119 #define MT6358_BUCK_VS2_DBG0 0x171e 120 #define MT6358_BUCK_VS2_DBG1 0x1720 121 #define MT6358_BUCK_VS2_ELR0 0x172e 122 #define MT6358_BUCK_VPA_CON0 0x1788 123 #define MT6358_BUCK_VPA_CON1 0x178a 124 #define MT6358_BUCK_VPA_ELR0 MT6358_BUCK_VPA_CON1 125 #define MT6358_BUCK_VPA_DBG0 0x1792 126 #define MT6358_BUCK_VPA_DBG1 0x1794 127 #define MT6358_VPROC_ANA_CON0 0x180c 128 #define MT6358_VCORE_VGPU_ANA_CON0 0x1828 129 #define MT6358_VMODEM_ANA_CON0 0x1888 130 #define MT6358_VDRAM1_ANA_CON0 0x1896 131 #define MT6358_VS1_ANA_CON0 0x18a2 132 #define MT6358_VS2_ANA_CON0 0x18ae 133 #define MT6358_VPA_ANA_CON0 0x18ba 134 #define MT6358_LDO_TOP_INT_CON0 0x1a50 135 #define MT6358_LDO_TOP_INT_CON1 0x1a56 136 #define MT6358_LDO_TOP_INT_STATUS0 0x1a68 137 #define MT6358_LDO_TOP_INT_STATUS1 0x1a6a 138 #define MT6358_LDO_VXO22_CON0 0x1a88 139 #define MT6358_LDO_VXO22_CON1 0x1a96 140 #define MT6358_LDO_VA12_CON0 0x1a9c 141 #define MT6358_LDO_VA12_CON1 0x1aaa 142 #define MT6358_LDO_VAUX18_CON0 0x1ab0 143 #define MT6358_LDO_VAUX18_CON1 0x1abe 144 #define MT6358_LDO_VAUD28_CON0 0x1ac4 145 #define MT6358_LDO_VAUD28_CON1 0x1ad2 146 #define MT6358_LDO_VIO28_CON0 0x1ad8 147 #define MT6358_LDO_VIO28_CON1 0x1ae6 148 #define MT6358_LDO_VIO18_CON0 0x1aec 149 #define MT6358_LDO_VIO18_CON1 0x1afa 150 #define MT6358_LDO_VDRAM2_CON0 0x1b08 151 #define MT6358_LDO_VDRAM2_CON1 0x1b16 152 #define MT6358_LDO_VEMC_CON0 0x1b1c 153 #define MT6358_LDO_VEMC_CON1 0x1b2a 154 #define MT6358_LDO_VUSB_CON0_0 0x1b30 155 #define MT6358_LDO_VUSB_CON1 0x1b40 156 #define MT6358_LDO_VSRAM_PROC11_CON0 0x1b46 157 #define MT6358_LDO_VSRAM_PROC11_DBG0 0x1b60 158 #define MT6358_LDO_VSRAM_PROC11_DBG1 0x1b62 159 #define MT6358_LDO_VSRAM_PROC11_TRACKING_CON0 0x1b64 160 #define MT6358_LDO_VSRAM_PROC11_TRACKING_CON1 0x1b66 161 #define MT6358_LDO_VSRAM_PROC11_TRACKING_CON2 0x1b68 162 #define MT6358_LDO_VSRAM_PROC11_TRACKING_CON3 0x1b6a 163 #define MT6358_LDO_VSRAM_PROC12_TRACKING_CON0 0x1b6c 164 #define MT6358_LDO_VSRAM_PROC12_TRACKING_CON1 0x1b6e 165 #define MT6358_LDO_VSRAM_PROC12_TRACKING_CON2 0x1b70 166 #define MT6358_LDO_VSRAM_PROC12_TRACKING_CON3 0x1b72 167 #define MT6358_LDO_VSRAM_WAKEUP_CON0 0x1b74 168 #define MT6358_LDO_GON1_ELR_NUM 0x1b76 169 #define MT6358_LDO_VDRAM2_ELR0 0x1b78 170 #define MT6358_LDO_VSRAM_PROC12_CON0 0x1b88 171 #define MT6358_LDO_VSRAM_PROC12_DBG0 0x1ba2 172 #define MT6358_LDO_VSRAM_PROC12_DBG1 0x1ba4 173 #define MT6358_LDO_VSRAM_OTHERS_CON0 0x1ba6 174 #define MT6358_LDO_VSRAM_OTHERS_DBG0 0x1bc0 175 #define MT6358_LDO_VSRAM_OTHERS_DBG1 0x1bc2 176 #define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON0 0x1bc4 177 #define MT6358_LDO_VSRAM_OTHERS_SSHUB_CON1 0x1bc6 178 #define MT6358_LDO_VSRAM_OTHERS_SSHUB_DBG1 MT6358_LDO_VSRAM_OTHERS_DBG1 179 #define MT6358_LDO_VSRAM_GPU_CON0 0x1bc8 180 #define MT6358_LDO_VSRAM_GPU_DBG0 0x1be2 181 #define MT6358_LDO_VSRAM_GPU_DBG1 0x1be4 182 #define MT6358_LDO_VSRAM_CON0 0x1bee 183 #define MT6358_LDO_VSRAM_CON1 0x1bf0 184 #define MT6358_LDO_VSRAM_CON2 0x1bf2 185 #define MT6358_LDO_VSRAM_CON3 0x1bf4 186 #define MT6358_LDO_VFE28_CON0 0x1c08 187 #define MT6358_LDO_VFE28_CON1 0x1c16 188 #define MT6358_LDO_VFE28_CON2 0x1c18 189 #define MT6358_LDO_VFE28_CON3 0x1c1a 190 #define MT6358_LDO_VRF18_CON0 0x1c1c 191 #define MT6358_LDO_VRF18_CON1 0x1c2a 192 #define MT6358_LDO_VRF18_CON2 0x1c2c 193 #define MT6358_LDO_VRF18_CON3 0x1c2e 194 #define MT6358_LDO_VRF12_CON0 0x1c30 195 #define MT6358_LDO_VRF12_CON1 0x1c3e 196 #define MT6358_LDO_VRF12_CON2 0x1c40 197 #define MT6358_LDO_VRF12_CON3 0x1c42 198 #define MT6358_LDO_VEFUSE_CON0 0x1c44 199 #define MT6358_LDO_VEFUSE_CON1 0x1c52 200 #define MT6358_LDO_VEFUSE_CON2 0x1c54 201 #define MT6358_LDO_VEFUSE_CON3 0x1c56 202 #define MT6358_LDO_VCN18_CON0 0x1c58 203 #define MT6358_LDO_VCN18_CON1 0x1c66 204 #define MT6358_LDO_VCN18_CON2 0x1c68 205 #define MT6358_LDO_VCN18_CON3 0x1c6a 206 #define MT6358_LDO_VCAMA1_CON0 0x1c6c 207 #define MT6358_LDO_VCAMA1_CON1 0x1c7a 208 #define MT6358_LDO_VCAMA1_CON2 0x1c7c 209 #define MT6358_LDO_VCAMA1_CON3 0x1c7e 210 #define MT6358_LDO_VCAMA2_CON0 0x1c88 211 #define MT6358_LDO_VCAMA2_CON1 0x1c96 212 #define MT6358_LDO_VCAMA2_CON2 0x1c98 213 #define MT6358_LDO_VCAMA2_CON3 0x1c9a 214 #define MT6358_LDO_VCAMD_CON0 0x1c9c 215 #define MT6358_LDO_VCAMD_CON1 0x1caa 216 #define MT6358_LDO_VCAMD_CON2 0x1cac 217 #define MT6358_LDO_VCAMD_CON3 0x1cae 218 #define MT6358_LDO_VCAMIO_CON0 0x1cb0 219 #define MT6358_LDO_VCAMIO_CON1 0x1cbe 220 #define MT6358_LDO_VCAMIO_CON2 0x1cc0 221 #define MT6358_LDO_VCAMIO_CON3 0x1cc2 222 #define MT6358_LDO_VMC_CON0 0x1cc4 223 #define MT6358_LDO_VMC_CON1 0x1cd2 224 #define MT6358_LDO_VMC_CON2 0x1cd4 225 #define MT6358_LDO_VMC_CON3 0x1cd6 226 #define MT6358_LDO_VMCH_CON0 0x1cd8 227 #define MT6358_LDO_VMCH_CON1 0x1ce6 228 #define MT6358_LDO_VMCH_CON2 0x1ce8 229 #define MT6358_LDO_VMCH_CON3 0x1cea 230 #define MT6358_LDO_VIBR_CON0 0x1d08 231 #define MT6358_LDO_VIBR_CON1 0x1d16 232 #define MT6358_LDO_VIBR_CON2 0x1d18 233 #define MT6358_LDO_VIBR_CON3 0x1d1a 234 #define MT6358_LDO_VCN33_CON0_0 0x1d1c 235 #define MT6358_LDO_VCN33_CON0_1 0x1d2a 236 #define MT6358_LDO_VCN33_CON1 0x1d2c 237 #define MT6358_LDO_VCN33_BT_CON1 MT6358_LDO_VCN33_CON1 238 #define MT6358_LDO_VCN33_WIFI_CON1 MT6358_LDO_VCN33_CON1 239 #define MT6358_LDO_VCN33_CON2 0x1d2e 240 #define MT6358_LDO_VCN33_CON3 0x1d30 241 #define MT6358_LDO_VLDO28_CON0_0 0x1d32 242 #define MT6358_LDO_VLDO28_CON0_1 0x1d40 243 #define MT6358_LDO_VLDO28_CON1 0x1d42 244 #define MT6358_LDO_VLDO28_CON2 0x1d44 245 #define MT6358_LDO_VLDO28_CON3 0x1d46 246 #define MT6358_LDO_VSIM1_CON0 0x1d48 247 #define MT6358_LDO_VSIM1_CON1 0x1d56 248 #define MT6358_LDO_VSIM1_CON2 0x1d58 249 #define MT6358_LDO_VSIM1_CON3 0x1d5a 250 #define MT6358_LDO_VSIM2_CON0 0x1d5c 251 #define MT6358_LDO_VSIM2_CON1 0x1d6a 252 #define MT6358_LDO_VSIM2_CON2 0x1d6c 253 #define MT6358_LDO_VSIM2_CON3 0x1d6e 254 #define MT6358_LDO_VCN28_CON0 0x1d88 255 #define MT6358_LDO_VCN28_CON1 0x1d96 256 #define MT6358_LDO_VCN28_CON2 0x1d98 257 #define MT6358_LDO_VCN28_CON3 0x1d9a 258 #define MT6358_VRTC28_CON0 0x1d9c 259 #define MT6358_LDO_VBIF28_CON0 0x1d9e 260 #define MT6358_LDO_VBIF28_CON1 0x1dac 261 #define MT6358_LDO_VBIF28_CON2 0x1dae 262 #define MT6358_LDO_VBIF28_CON3 0x1db0 263 #define MT6358_VCAMA1_ANA_CON0 0x1e08 264 #define MT6358_VCAMA2_ANA_CON0 0x1e0c 265 #define MT6358_VFE28_ANA_CON0 0x1e10 266 #define MT6358_VCN28_ANA_CON0 0x1e14 267 #define MT6358_VBIF28_ANA_CON0 0x1e18 268 #define MT6358_VAUD28_ANA_CON0 0x1e1c 269 #define MT6358_VAUX18_ANA_CON0 0x1e20 270 #define MT6358_VXO22_ANA_CON0 0x1e24 271 #define MT6358_VCN33_ANA_CON0 0x1e28 272 #define MT6358_VSIM1_ANA_CON0 0x1e2c 273 #define MT6358_VSIM2_ANA_CON0 0x1e30 274 #define MT6358_VUSB_ANA_CON0 0x1e34 275 #define MT6358_VEMC_ANA_CON0 0x1e38 276 #define MT6358_VLDO28_ANA_CON0 0x1e3c 277 #define MT6358_VIO28_ANA_CON0 0x1e40 278 #define MT6358_VIBR_ANA_CON0 0x1e44 279 #define MT6358_VMCH_ANA_CON0 0x1e48 280 #define MT6358_VMC_ANA_CON0 0x1e4c 281 #define MT6358_VRF18_ANA_CON0 0x1e88 282 #define MT6358_VCN18_ANA_CON0 0x1e8c 283 #define MT6358_VCAMIO_ANA_CON0 0x1e90 284 #define MT6358_VIO18_ANA_CON0 0x1e94 285 #define MT6358_VEFUSE_ANA_CON0 0x1e98 286 #define MT6358_VRF12_ANA_CON0 0x1e9c 287 #define MT6358_VSRAM_PROC11_ANA_CON0 0x1ea0 288 #define MT6358_VSRAM_PROC12_ANA_CON0 0x1ea4 289 #define MT6358_VSRAM_OTHERS_ANA_CON0 0x1ea6 290 #define MT6358_VSRAM_GPU_ANA_CON0 0x1ea8 291 #define MT6358_VDRAM2_ANA_CON0 0x1eaa 292 #define MT6358_VCAMD_ANA_CON0 0x1eae 293 #define MT6358_VA12_ANA_CON0 0x1eb2 294 #define MT6358_AUD_TOP_INT_CON0 0x2228 295 #define MT6358_AUD_TOP_INT_STATUS0 0x2234 296 297 /* 298 * MT6366 has no VCAM*, but has other regulators in its place. The names 299 * keep the MT6358 prefix for ease of use in the regulator driver. 300 */ 301 #define MT6358_LDO_VSRAM_CON5 0x1bf8 302 #define MT6358_LDO_VM18_CON0 MT6358_LDO_VCAMA1_CON0 303 #define MT6358_LDO_VM18_CON1 MT6358_LDO_VCAMA1_CON1 304 #define MT6358_LDO_VM18_CON2 MT6358_LDO_VCAMA1_CON2 305 #define MT6358_LDO_VMDDR_CON0 MT6358_LDO_VCAMA2_CON0 306 #define MT6358_LDO_VMDDR_CON1 MT6358_LDO_VCAMA2_CON1 307 #define MT6358_LDO_VMDDR_CON2 MT6358_LDO_VCAMA2_CON2 308 #define MT6358_LDO_VSRAM_CORE_CON0 MT6358_LDO_VCAMD_CON0 309 #define MT6358_LDO_VSRAM_CORE_DBG0 0x1cb6 310 #define MT6358_LDO_VSRAM_CORE_DBG1 0x1cb8 311 #define MT6358_VM18_ANA_CON0 MT6358_VCAMA1_ANA_CON0 312 #define MT6358_VMDDR_ANA_CON0 MT6358_VCAMD_ANA_CON0 313 314 #endif /* __MFD_MT6358_REGISTERS_H__ */ 315