1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
3
4 #include <linux/module.h>
5 #include <linux/init.h>
6 #include <linux/clk.h>
7 #include <linux/io.h>
8 #include <linux/platform_device.h>
9 #include <linux/pm_clock.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/regmap.h>
12 #include <sound/soc.h>
13 #include <sound/soc-dapm.h>
14 #include <sound/tlv.h>
15 #include <linux/of_clk.h>
16 #include <linux/clk-provider.h>
17
18 #include "lpass-macro-common.h"
19
20 #define CDC_TX_CLK_RST_CTRL_MCLK_CONTROL (0x0000)
21 #define CDC_TX_MCLK_EN_MASK BIT(0)
22 #define CDC_TX_MCLK_ENABLE BIT(0)
23 #define CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL (0x0004)
24 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
25 #define CDC_TX_FS_CNT_ENABLE BIT(0)
26 #define CDC_TX_CLK_RST_CTRL_SWR_CONTROL (0x0008)
27 #define CDC_TX_SWR_RESET_MASK BIT(1)
28 #define CDC_TX_SWR_RESET_ENABLE BIT(1)
29 #define CDC_TX_SWR_CLK_EN_MASK BIT(0)
30 #define CDC_TX_SWR_CLK_ENABLE BIT(0)
31 #define CDC_TX_TOP_CSR_TOP_CFG0 (0x0080)
32 #define CDC_TX_TOP_CSR_ANC_CFG (0x0084)
33 #define CDC_TX_TOP_CSR_SWR_CTRL (0x0088)
34 #define CDC_TX_TOP_CSR_FREQ_MCLK (0x0090)
35 #define CDC_TX_TOP_CSR_DEBUG_BUS (0x0094)
36 #define CDC_TX_TOP_CSR_DEBUG_EN (0x0098)
37 #define CDC_TX_TOP_CSR_TX_I2S_CTL (0x00A4)
38 #define CDC_TX_TOP_CSR_I2S_CLK (0x00A8)
39 #define CDC_TX_TOP_CSR_I2S_RESET (0x00AC)
40 #define CDC_TX_TOP_CSR_SWR_DMICn_CTL(n) (0x00C0 + n * 0x4)
41 #define CDC_TX_TOP_CSR_SWR_DMIC0_CTL (0x00C0)
42 /* Default divider for AMIC and DMIC clock: DIV2 */
43 #define CDC_TX_SWR_MIC_CLK_DEFAULT 0
44 #define CDC_TX_SWR_DMIC_CLK_SEL_MASK GENMASK(3, 1)
45 #define CDC_TX_TOP_CSR_SWR_DMIC1_CTL (0x00C4)
46 #define CDC_TX_TOP_CSR_SWR_DMIC2_CTL (0x00C8)
47 #define CDC_TX_TOP_CSR_SWR_DMIC3_CTL (0x00CC)
48 #define CDC_TX_TOP_CSR_SWR_AMIC0_CTL (0x00D0)
49 #define CDC_TX_TOP_CSR_SWR_AMIC1_CTL (0x00D4)
50 #define CDC_TX_INP_MUX_ADC_MUXn_CFG0(n) (0x0100 + 0x8 * n)
51 #define CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK GENMASK(3, 0)
52 #define CDC_TX_MACRO_DMIC_MUX_SEL_MASK GENMASK(7, 4)
53 #define CDC_TX_INP_MUX_ADC_MUX0_CFG0 (0x0100)
54 #define CDC_TX_INP_MUX_ADC_MUXn_CFG1(n) (0x0104 + 0x8 * n)
55 #define CDC_TX_INP_MUX_ADC_MUX0_CFG1 (0x0104)
56 #define CDC_TX_INP_MUX_ADC_MUX1_CFG0 (0x0108)
57 #define CDC_TX_INP_MUX_ADC_MUX1_CFG1 (0x010C)
58 #define CDC_TX_INP_MUX_ADC_MUX2_CFG0 (0x0110)
59 #define CDC_TX_INP_MUX_ADC_MUX2_CFG1 (0x0114)
60 #define CDC_TX_INP_MUX_ADC_MUX3_CFG0 (0x0118)
61 #define CDC_TX_INP_MUX_ADC_MUX3_CFG1 (0x011C)
62 #define CDC_TX_INP_MUX_ADC_MUX4_CFG0 (0x0120)
63 #define CDC_TX_INP_MUX_ADC_MUX4_CFG1 (0x0124)
64 #define CDC_TX_INP_MUX_ADC_MUX5_CFG0 (0x0128)
65 #define CDC_TX_INP_MUX_ADC_MUX5_CFG1 (0x012C)
66 #define CDC_TX_INP_MUX_ADC_MUX6_CFG0 (0x0130)
67 #define CDC_TX_INP_MUX_ADC_MUX6_CFG1 (0x0134)
68 #define CDC_TX_INP_MUX_ADC_MUX7_CFG0 (0x0138)
69 #define CDC_TX_INP_MUX_ADC_MUX7_CFG1 (0x013C)
70 #define CDC_TX_ANC0_CLK_RESET_CTL (0x0200)
71 #define CDC_TX_ANC0_MODE_1_CTL (0x0204)
72 #define CDC_TX_ANC0_MODE_2_CTL (0x0208)
73 #define CDC_TX_ANC0_FF_SHIFT (0x020C)
74 #define CDC_TX_ANC0_FB_SHIFT (0x0210)
75 #define CDC_TX_ANC0_LPF_FF_A_CTL (0x0214)
76 #define CDC_TX_ANC0_LPF_FF_B_CTL (0x0218)
77 #define CDC_TX_ANC0_LPF_FB_CTL (0x021C)
78 #define CDC_TX_ANC0_SMLPF_CTL (0x0220)
79 #define CDC_TX_ANC0_DCFLT_SHIFT_CTL (0x0224)
80 #define CDC_TX_ANC0_IIR_ADAPT_CTL (0x0228)
81 #define CDC_TX_ANC0_IIR_COEFF_1_CTL (0x022C)
82 #define CDC_TX_ANC0_IIR_COEFF_2_CTL (0x0230)
83 #define CDC_TX_ANC0_FF_A_GAIN_CTL (0x0234)
84 #define CDC_TX_ANC0_FF_B_GAIN_CTL (0x0238)
85 #define CDC_TX_ANC0_FB_GAIN_CTL (0x023C)
86 #define CDC_TXn_TX_PATH_CTL(n) (0x0400 + 0x80 * n)
87 #define CDC_TXn_PCM_RATE_MASK GENMASK(3, 0)
88 #define CDC_TXn_PGA_MUTE_MASK BIT(4)
89 #define CDC_TXn_CLK_EN_MASK BIT(5)
90 #define CDC_TX0_TX_PATH_CTL (0x0400)
91 #define CDC_TXn_TX_PATH_CFG0(n) (0x0404 + 0x80 * n)
92 #define CDC_TX0_TX_PATH_CFG0 (0x0404)
93 #define CDC_TXn_PH_EN_MASK BIT(0)
94 #define CDC_TXn_ADC_MODE_MASK GENMASK(2, 1)
95 #define CDC_TXn_HPF_CUT_FREQ_MASK GENMASK(6, 5)
96 #define CDC_TXn_ADC_DMIC_SEL_MASK BIT(7)
97 #define CDC_TX0_TX_PATH_CFG1 (0x0408)
98 #define CDC_TXn_TX_VOL_CTL(n) (0x040C + 0x80 * n)
99 #define CDC_TX0_TX_VOL_CTL (0x040C)
100 #define CDC_TX0_TX_PATH_SEC0 (0x0410)
101 #define CDC_TX0_TX_PATH_SEC1 (0x0414)
102 #define CDC_TXn_TX_PATH_SEC2(n) (0x0418 + 0x80 * n)
103 #define CDC_TXn_HPF_F_CHANGE_MASK BIT(1)
104 #define CDC_TXn_HPF_ZERO_GATE_MASK BIT(0)
105 #define CDC_TX0_TX_PATH_SEC2 (0x0418)
106 #define CDC_TX0_TX_PATH_SEC3 (0x041C)
107 #define CDC_TX0_TX_PATH_SEC4 (0x0420)
108 #define CDC_TX0_TX_PATH_SEC5 (0x0424)
109 #define CDC_TX0_TX_PATH_SEC6 (0x0428)
110 #define CDC_TX0_TX_PATH_SEC7 (0x042C)
111 #define CDC_TX0_MBHC_CTL_EN_MASK BIT(6)
112 #define CDC_TX1_TX_PATH_CTL (0x0480)
113 #define CDC_TX1_TX_PATH_CFG0 (0x0484)
114 #define CDC_TX1_TX_PATH_CFG1 (0x0488)
115 #define CDC_TX1_TX_VOL_CTL (0x048C)
116 #define CDC_TX1_TX_PATH_SEC0 (0x0490)
117 #define CDC_TX1_TX_PATH_SEC1 (0x0494)
118 #define CDC_TX1_TX_PATH_SEC2 (0x0498)
119 #define CDC_TX1_TX_PATH_SEC3 (0x049C)
120 #define CDC_TX1_TX_PATH_SEC4 (0x04A0)
121 #define CDC_TX1_TX_PATH_SEC5 (0x04A4)
122 #define CDC_TX1_TX_PATH_SEC6 (0x04A8)
123 #define CDC_TX2_TX_PATH_CTL (0x0500)
124 #define CDC_TX2_TX_PATH_CFG0 (0x0504)
125 #define CDC_TX2_TX_PATH_CFG1 (0x0508)
126 #define CDC_TX2_TX_VOL_CTL (0x050C)
127 #define CDC_TX2_TX_PATH_SEC0 (0x0510)
128 #define CDC_TX2_TX_PATH_SEC1 (0x0514)
129 #define CDC_TX2_TX_PATH_SEC2 (0x0518)
130 #define CDC_TX2_TX_PATH_SEC3 (0x051C)
131 #define CDC_TX2_TX_PATH_SEC4 (0x0520)
132 #define CDC_TX2_TX_PATH_SEC5 (0x0524)
133 #define CDC_TX2_TX_PATH_SEC6 (0x0528)
134 #define CDC_TX3_TX_PATH_CTL (0x0580)
135 #define CDC_TX3_TX_PATH_CFG0 (0x0584)
136 #define CDC_TX3_TX_PATH_CFG1 (0x0588)
137 #define CDC_TX3_TX_VOL_CTL (0x058C)
138 #define CDC_TX3_TX_PATH_SEC0 (0x0590)
139 #define CDC_TX3_TX_PATH_SEC1 (0x0594)
140 #define CDC_TX3_TX_PATH_SEC2 (0x0598)
141 #define CDC_TX3_TX_PATH_SEC3 (0x059C)
142 #define CDC_TX3_TX_PATH_SEC4 (0x05A0)
143 #define CDC_TX3_TX_PATH_SEC5 (0x05A4)
144 #define CDC_TX3_TX_PATH_SEC6 (0x05A8)
145 #define CDC_TX4_TX_PATH_CTL (0x0600)
146 #define CDC_TX4_TX_PATH_CFG0 (0x0604)
147 #define CDC_TX4_TX_PATH_CFG1 (0x0608)
148 #define CDC_TX4_TX_VOL_CTL (0x060C)
149 #define CDC_TX4_TX_PATH_SEC0 (0x0610)
150 #define CDC_TX4_TX_PATH_SEC1 (0x0614)
151 #define CDC_TX4_TX_PATH_SEC2 (0x0618)
152 #define CDC_TX4_TX_PATH_SEC3 (0x061C)
153 #define CDC_TX4_TX_PATH_SEC4 (0x0620)
154 #define CDC_TX4_TX_PATH_SEC5 (0x0624)
155 #define CDC_TX4_TX_PATH_SEC6 (0x0628)
156 #define CDC_TX5_TX_PATH_CTL (0x0680)
157 #define CDC_TX5_TX_PATH_CFG0 (0x0684)
158 #define CDC_TX5_TX_PATH_CFG1 (0x0688)
159 #define CDC_TX5_TX_VOL_CTL (0x068C)
160 #define CDC_TX5_TX_PATH_SEC0 (0x0690)
161 #define CDC_TX5_TX_PATH_SEC1 (0x0694)
162 #define CDC_TX5_TX_PATH_SEC2 (0x0698)
163 #define CDC_TX5_TX_PATH_SEC3 (0x069C)
164 #define CDC_TX5_TX_PATH_SEC4 (0x06A0)
165 #define CDC_TX5_TX_PATH_SEC5 (0x06A4)
166 #define CDC_TX5_TX_PATH_SEC6 (0x06A8)
167 #define CDC_TX6_TX_PATH_CTL (0x0700)
168 #define CDC_TX6_TX_PATH_CFG0 (0x0704)
169 #define CDC_TX6_TX_PATH_CFG1 (0x0708)
170 #define CDC_TX6_TX_VOL_CTL (0x070C)
171 #define CDC_TX6_TX_PATH_SEC0 (0x0710)
172 #define CDC_TX6_TX_PATH_SEC1 (0x0714)
173 #define CDC_TX6_TX_PATH_SEC2 (0x0718)
174 #define CDC_TX6_TX_PATH_SEC3 (0x071C)
175 #define CDC_TX6_TX_PATH_SEC4 (0x0720)
176 #define CDC_TX6_TX_PATH_SEC5 (0x0724)
177 #define CDC_TX6_TX_PATH_SEC6 (0x0728)
178 #define CDC_TX7_TX_PATH_CTL (0x0780)
179 #define CDC_TX7_TX_PATH_CFG0 (0x0784)
180 #define CDC_TX7_TX_PATH_CFG1 (0x0788)
181 #define CDC_TX7_TX_VOL_CTL (0x078C)
182 #define CDC_TX7_TX_PATH_SEC0 (0x0790)
183 #define CDC_TX7_TX_PATH_SEC1 (0x0794)
184 #define CDC_TX7_TX_PATH_SEC2 (0x0798)
185 #define CDC_TX7_TX_PATH_SEC3 (0x079C)
186 #define CDC_TX7_TX_PATH_SEC4 (0x07A0)
187 #define CDC_TX7_TX_PATH_SEC5 (0x07A4)
188 #define CDC_TX7_TX_PATH_SEC6 (0x07A8)
189 #define TX_MAX_OFFSET (0x07A8)
190
191 #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
192 SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
193 SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
194 #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\
195 SNDRV_PCM_FMTBIT_S24_LE |\
196 SNDRV_PCM_FMTBIT_S24_3LE)
197
198 #define CF_MIN_3DB_4HZ 0x0
199 #define CF_MIN_3DB_75HZ 0x1
200 #define CF_MIN_3DB_150HZ 0x2
201 #define TX_ADC_MAX 5
202 #define TX_ADC_TO_DMIC(n) ((n - TX_ADC_MAX)/2)
203 #define NUM_DECIMATORS 8
204 #define TX_NUM_CLKS_MAX 5
205 #define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40
206 #define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100
207 #define TX_MACRO_DMIC_HPF_DELAY_MS 300
208 #define TX_MACRO_AMIC_HPF_DELAY_MS 300
209 #define MCLK_FREQ 19200000
210
211 enum {
212 TX_MACRO_AIF1_CAP,
213 TX_MACRO_AIF2_CAP,
214 TX_MACRO_AIF3_CAP,
215 TX_MACRO_MAX_DAIS
216 };
217
218 enum {
219 TX_MACRO_DEC0,
220 TX_MACRO_DEC1,
221 TX_MACRO_DEC2,
222 TX_MACRO_DEC3,
223 TX_MACRO_DEC4,
224 TX_MACRO_DEC5,
225 TX_MACRO_DEC6,
226 TX_MACRO_DEC7,
227 TX_MACRO_DEC_MAX,
228 };
229
230 enum {
231 TX_MACRO_CLK_DIV_2,
232 TX_MACRO_CLK_DIV_3,
233 TX_MACRO_CLK_DIV_4,
234 TX_MACRO_CLK_DIV_6,
235 TX_MACRO_CLK_DIV_8,
236 TX_MACRO_CLK_DIV_16,
237 };
238
239 enum {
240 MSM_DMIC,
241 SWR_MIC,
242 ANC_FB_TUNE1
243 };
244
245 struct tx_mute_work {
246 struct tx_macro *tx;
247 u8 decimator;
248 struct delayed_work dwork;
249 };
250
251 struct hpf_work {
252 struct tx_macro *tx;
253 u8 decimator;
254 u8 hpf_cut_off_freq;
255 struct delayed_work dwork;
256 };
257
258 struct tx_macro_data {
259 unsigned int flags;
260 unsigned int ver;
261 const struct snd_soc_dapm_widget *extra_widgets;
262 size_t extra_widgets_num;
263 const struct snd_soc_dapm_route *extra_routes;
264 size_t extra_routes_num;
265 };
266
267 struct tx_macro {
268 struct device *dev;
269 const struct tx_macro_data *data;
270 struct snd_soc_component *component;
271 struct hpf_work tx_hpf_work[NUM_DECIMATORS];
272 struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS];
273 unsigned long active_ch_mask[TX_MACRO_MAX_DAIS];
274 unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS];
275 int active_decimator[TX_MACRO_MAX_DAIS];
276 struct regmap *regmap;
277 struct clk *mclk;
278 struct clk *npl;
279 struct clk *macro;
280 struct clk *dcodec;
281 struct clk *fsgen;
282 struct clk_hw hw;
283 bool dec_active[NUM_DECIMATORS];
284 int tx_mclk_users;
285 bool bcs_enable;
286 int dec_mode[NUM_DECIMATORS];
287 struct lpass_macro *pds;
288 bool bcs_clk_en;
289 };
290 #define to_tx_macro(_hw) container_of(_hw, struct tx_macro, hw)
291
292 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
293
294 static struct reg_default tx_defaults[] = {
295 /* TX Macro */
296 { CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, 0x00 },
297 { CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, 0x00 },
298 { CDC_TX_CLK_RST_CTRL_SWR_CONTROL, 0x00},
299 { CDC_TX_TOP_CSR_TOP_CFG0, 0x00},
300 { CDC_TX_TOP_CSR_ANC_CFG, 0x00},
301 { CDC_TX_TOP_CSR_SWR_CTRL, 0x00},
302 { CDC_TX_TOP_CSR_FREQ_MCLK, 0x00},
303 { CDC_TX_TOP_CSR_DEBUG_BUS, 0x00},
304 { CDC_TX_TOP_CSR_DEBUG_EN, 0x00},
305 { CDC_TX_TOP_CSR_TX_I2S_CTL, 0x0C},
306 { CDC_TX_TOP_CSR_I2S_CLK, 0x00},
307 { CDC_TX_TOP_CSR_I2S_RESET, 0x00},
308 { CDC_TX_TOP_CSR_SWR_DMIC0_CTL, 0x00},
309 { CDC_TX_TOP_CSR_SWR_DMIC1_CTL, 0x00},
310 { CDC_TX_TOP_CSR_SWR_DMIC2_CTL, 0x00},
311 { CDC_TX_TOP_CSR_SWR_DMIC3_CTL, 0x00},
312 { CDC_TX_TOP_CSR_SWR_AMIC0_CTL, 0x00},
313 { CDC_TX_TOP_CSR_SWR_AMIC1_CTL, 0x00},
314 { CDC_TX_INP_MUX_ADC_MUX0_CFG0, 0x00},
315 { CDC_TX_INP_MUX_ADC_MUX0_CFG1, 0x00},
316 { CDC_TX_INP_MUX_ADC_MUX1_CFG0, 0x00},
317 { CDC_TX_INP_MUX_ADC_MUX1_CFG1, 0x00},
318 { CDC_TX_INP_MUX_ADC_MUX2_CFG0, 0x00},
319 { CDC_TX_INP_MUX_ADC_MUX2_CFG1, 0x00},
320 { CDC_TX_INP_MUX_ADC_MUX3_CFG0, 0x00},
321 { CDC_TX_INP_MUX_ADC_MUX3_CFG1, 0x00},
322 { CDC_TX_INP_MUX_ADC_MUX4_CFG0, 0x00},
323 { CDC_TX_INP_MUX_ADC_MUX4_CFG1, 0x00},
324 { CDC_TX_INP_MUX_ADC_MUX5_CFG0, 0x00},
325 { CDC_TX_INP_MUX_ADC_MUX5_CFG1, 0x00},
326 { CDC_TX_INP_MUX_ADC_MUX6_CFG0, 0x00},
327 { CDC_TX_INP_MUX_ADC_MUX6_CFG1, 0x00},
328 { CDC_TX_INP_MUX_ADC_MUX7_CFG0, 0x00},
329 { CDC_TX_INP_MUX_ADC_MUX7_CFG1, 0x00},
330 { CDC_TX_ANC0_CLK_RESET_CTL, 0x00},
331 { CDC_TX_ANC0_MODE_1_CTL, 0x00},
332 { CDC_TX_ANC0_MODE_2_CTL, 0x00},
333 { CDC_TX_ANC0_FF_SHIFT, 0x00},
334 { CDC_TX_ANC0_FB_SHIFT, 0x00},
335 { CDC_TX_ANC0_LPF_FF_A_CTL, 0x00},
336 { CDC_TX_ANC0_LPF_FF_B_CTL, 0x00},
337 { CDC_TX_ANC0_LPF_FB_CTL, 0x00},
338 { CDC_TX_ANC0_SMLPF_CTL, 0x00},
339 { CDC_TX_ANC0_DCFLT_SHIFT_CTL, 0x00},
340 { CDC_TX_ANC0_IIR_ADAPT_CTL, 0x00},
341 { CDC_TX_ANC0_IIR_COEFF_1_CTL, 0x00},
342 { CDC_TX_ANC0_IIR_COEFF_2_CTL, 0x00},
343 { CDC_TX_ANC0_FF_A_GAIN_CTL, 0x00},
344 { CDC_TX_ANC0_FF_B_GAIN_CTL, 0x00},
345 { CDC_TX_ANC0_FB_GAIN_CTL, 0x00},
346 { CDC_TX0_TX_PATH_CTL, 0x04},
347 { CDC_TX0_TX_PATH_CFG0, 0x10},
348 { CDC_TX0_TX_PATH_CFG1, 0x0B},
349 { CDC_TX0_TX_VOL_CTL, 0x00},
350 { CDC_TX0_TX_PATH_SEC0, 0x00},
351 { CDC_TX0_TX_PATH_SEC1, 0x00},
352 { CDC_TX0_TX_PATH_SEC2, 0x01},
353 { CDC_TX0_TX_PATH_SEC3, 0x3C},
354 { CDC_TX0_TX_PATH_SEC4, 0x20},
355 { CDC_TX0_TX_PATH_SEC5, 0x00},
356 { CDC_TX0_TX_PATH_SEC6, 0x00},
357 { CDC_TX0_TX_PATH_SEC7, 0x25},
358 { CDC_TX1_TX_PATH_CTL, 0x04},
359 { CDC_TX1_TX_PATH_CFG0, 0x10},
360 { CDC_TX1_TX_PATH_CFG1, 0x0B},
361 { CDC_TX1_TX_VOL_CTL, 0x00},
362 { CDC_TX1_TX_PATH_SEC0, 0x00},
363 { CDC_TX1_TX_PATH_SEC1, 0x00},
364 { CDC_TX1_TX_PATH_SEC2, 0x01},
365 { CDC_TX1_TX_PATH_SEC3, 0x3C},
366 { CDC_TX1_TX_PATH_SEC4, 0x20},
367 { CDC_TX1_TX_PATH_SEC5, 0x00},
368 { CDC_TX1_TX_PATH_SEC6, 0x00},
369 { CDC_TX2_TX_PATH_CTL, 0x04},
370 { CDC_TX2_TX_PATH_CFG0, 0x10},
371 { CDC_TX2_TX_PATH_CFG1, 0x0B},
372 { CDC_TX2_TX_VOL_CTL, 0x00},
373 { CDC_TX2_TX_PATH_SEC0, 0x00},
374 { CDC_TX2_TX_PATH_SEC1, 0x00},
375 { CDC_TX2_TX_PATH_SEC2, 0x01},
376 { CDC_TX2_TX_PATH_SEC3, 0x3C},
377 { CDC_TX2_TX_PATH_SEC4, 0x20},
378 { CDC_TX2_TX_PATH_SEC5, 0x00},
379 { CDC_TX2_TX_PATH_SEC6, 0x00},
380 { CDC_TX3_TX_PATH_CTL, 0x04},
381 { CDC_TX3_TX_PATH_CFG0, 0x10},
382 { CDC_TX3_TX_PATH_CFG1, 0x0B},
383 { CDC_TX3_TX_VOL_CTL, 0x00},
384 { CDC_TX3_TX_PATH_SEC0, 0x00},
385 { CDC_TX3_TX_PATH_SEC1, 0x00},
386 { CDC_TX3_TX_PATH_SEC2, 0x01},
387 { CDC_TX3_TX_PATH_SEC3, 0x3C},
388 { CDC_TX3_TX_PATH_SEC4, 0x20},
389 { CDC_TX3_TX_PATH_SEC5, 0x00},
390 { CDC_TX3_TX_PATH_SEC6, 0x00},
391 { CDC_TX4_TX_PATH_CTL, 0x04},
392 { CDC_TX4_TX_PATH_CFG0, 0x10},
393 { CDC_TX4_TX_PATH_CFG1, 0x0B},
394 { CDC_TX4_TX_VOL_CTL, 0x00},
395 { CDC_TX4_TX_PATH_SEC0, 0x00},
396 { CDC_TX4_TX_PATH_SEC1, 0x00},
397 { CDC_TX4_TX_PATH_SEC2, 0x01},
398 { CDC_TX4_TX_PATH_SEC3, 0x3C},
399 { CDC_TX4_TX_PATH_SEC4, 0x20},
400 { CDC_TX4_TX_PATH_SEC5, 0x00},
401 { CDC_TX4_TX_PATH_SEC6, 0x00},
402 { CDC_TX5_TX_PATH_CTL, 0x04},
403 { CDC_TX5_TX_PATH_CFG0, 0x10},
404 { CDC_TX5_TX_PATH_CFG1, 0x0B},
405 { CDC_TX5_TX_VOL_CTL, 0x00},
406 { CDC_TX5_TX_PATH_SEC0, 0x00},
407 { CDC_TX5_TX_PATH_SEC1, 0x00},
408 { CDC_TX5_TX_PATH_SEC2, 0x01},
409 { CDC_TX5_TX_PATH_SEC3, 0x3C},
410 { CDC_TX5_TX_PATH_SEC4, 0x20},
411 { CDC_TX5_TX_PATH_SEC5, 0x00},
412 { CDC_TX5_TX_PATH_SEC6, 0x00},
413 { CDC_TX6_TX_PATH_CTL, 0x04},
414 { CDC_TX6_TX_PATH_CFG0, 0x10},
415 { CDC_TX6_TX_PATH_CFG1, 0x0B},
416 { CDC_TX6_TX_VOL_CTL, 0x00},
417 { CDC_TX6_TX_PATH_SEC0, 0x00},
418 { CDC_TX6_TX_PATH_SEC1, 0x00},
419 { CDC_TX6_TX_PATH_SEC2, 0x01},
420 { CDC_TX6_TX_PATH_SEC3, 0x3C},
421 { CDC_TX6_TX_PATH_SEC4, 0x20},
422 { CDC_TX6_TX_PATH_SEC5, 0x00},
423 { CDC_TX6_TX_PATH_SEC6, 0x00},
424 { CDC_TX7_TX_PATH_CTL, 0x04},
425 { CDC_TX7_TX_PATH_CFG0, 0x10},
426 { CDC_TX7_TX_PATH_CFG1, 0x0B},
427 { CDC_TX7_TX_VOL_CTL, 0x00},
428 { CDC_TX7_TX_PATH_SEC0, 0x00},
429 { CDC_TX7_TX_PATH_SEC1, 0x00},
430 { CDC_TX7_TX_PATH_SEC2, 0x01},
431 { CDC_TX7_TX_PATH_SEC3, 0x3C},
432 { CDC_TX7_TX_PATH_SEC4, 0x20},
433 { CDC_TX7_TX_PATH_SEC5, 0x00},
434 { CDC_TX7_TX_PATH_SEC6, 0x00},
435 };
436
tx_is_volatile_register(struct device * dev,unsigned int reg)437 static bool tx_is_volatile_register(struct device *dev, unsigned int reg)
438 {
439 /* Update volatile list for tx/tx macros */
440 switch (reg) {
441 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
442 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
443 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
444 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
445 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
446 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
447 return true;
448 }
449 return false;
450 }
451
tx_is_rw_register(struct device * dev,unsigned int reg)452 static bool tx_is_rw_register(struct device *dev, unsigned int reg)
453 {
454 switch (reg) {
455 case CDC_TX_CLK_RST_CTRL_MCLK_CONTROL:
456 case CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL:
457 case CDC_TX_CLK_RST_CTRL_SWR_CONTROL:
458 case CDC_TX_TOP_CSR_TOP_CFG0:
459 case CDC_TX_TOP_CSR_ANC_CFG:
460 case CDC_TX_TOP_CSR_SWR_CTRL:
461 case CDC_TX_TOP_CSR_FREQ_MCLK:
462 case CDC_TX_TOP_CSR_DEBUG_BUS:
463 case CDC_TX_TOP_CSR_DEBUG_EN:
464 case CDC_TX_TOP_CSR_TX_I2S_CTL:
465 case CDC_TX_TOP_CSR_I2S_CLK:
466 case CDC_TX_TOP_CSR_I2S_RESET:
467 case CDC_TX_TOP_CSR_SWR_DMIC0_CTL:
468 case CDC_TX_TOP_CSR_SWR_DMIC1_CTL:
469 case CDC_TX_TOP_CSR_SWR_DMIC2_CTL:
470 case CDC_TX_TOP_CSR_SWR_DMIC3_CTL:
471 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
472 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
473 case CDC_TX_ANC0_CLK_RESET_CTL:
474 case CDC_TX_ANC0_MODE_1_CTL:
475 case CDC_TX_ANC0_MODE_2_CTL:
476 case CDC_TX_ANC0_FF_SHIFT:
477 case CDC_TX_ANC0_FB_SHIFT:
478 case CDC_TX_ANC0_LPF_FF_A_CTL:
479 case CDC_TX_ANC0_LPF_FF_B_CTL:
480 case CDC_TX_ANC0_LPF_FB_CTL:
481 case CDC_TX_ANC0_SMLPF_CTL:
482 case CDC_TX_ANC0_DCFLT_SHIFT_CTL:
483 case CDC_TX_ANC0_IIR_ADAPT_CTL:
484 case CDC_TX_ANC0_IIR_COEFF_1_CTL:
485 case CDC_TX_ANC0_IIR_COEFF_2_CTL:
486 case CDC_TX_ANC0_FF_A_GAIN_CTL:
487 case CDC_TX_ANC0_FF_B_GAIN_CTL:
488 case CDC_TX_ANC0_FB_GAIN_CTL:
489 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
490 case CDC_TX_INP_MUX_ADC_MUX0_CFG1:
491 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
492 case CDC_TX_INP_MUX_ADC_MUX1_CFG1:
493 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
494 case CDC_TX_INP_MUX_ADC_MUX2_CFG1:
495 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
496 case CDC_TX_INP_MUX_ADC_MUX3_CFG1:
497 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
498 case CDC_TX_INP_MUX_ADC_MUX4_CFG1:
499 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
500 case CDC_TX_INP_MUX_ADC_MUX5_CFG1:
501 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
502 case CDC_TX_INP_MUX_ADC_MUX6_CFG1:
503 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
504 case CDC_TX_INP_MUX_ADC_MUX7_CFG1:
505 case CDC_TX0_TX_PATH_CTL:
506 case CDC_TX0_TX_PATH_CFG0:
507 case CDC_TX0_TX_PATH_CFG1:
508 case CDC_TX0_TX_VOL_CTL:
509 case CDC_TX0_TX_PATH_SEC0:
510 case CDC_TX0_TX_PATH_SEC1:
511 case CDC_TX0_TX_PATH_SEC2:
512 case CDC_TX0_TX_PATH_SEC3:
513 case CDC_TX0_TX_PATH_SEC4:
514 case CDC_TX0_TX_PATH_SEC5:
515 case CDC_TX0_TX_PATH_SEC6:
516 case CDC_TX0_TX_PATH_SEC7:
517 case CDC_TX1_TX_PATH_CTL:
518 case CDC_TX1_TX_PATH_CFG0:
519 case CDC_TX1_TX_PATH_CFG1:
520 case CDC_TX1_TX_VOL_CTL:
521 case CDC_TX1_TX_PATH_SEC0:
522 case CDC_TX1_TX_PATH_SEC1:
523 case CDC_TX1_TX_PATH_SEC2:
524 case CDC_TX1_TX_PATH_SEC3:
525 case CDC_TX1_TX_PATH_SEC4:
526 case CDC_TX1_TX_PATH_SEC5:
527 case CDC_TX1_TX_PATH_SEC6:
528 case CDC_TX2_TX_PATH_CTL:
529 case CDC_TX2_TX_PATH_CFG0:
530 case CDC_TX2_TX_PATH_CFG1:
531 case CDC_TX2_TX_VOL_CTL:
532 case CDC_TX2_TX_PATH_SEC0:
533 case CDC_TX2_TX_PATH_SEC1:
534 case CDC_TX2_TX_PATH_SEC2:
535 case CDC_TX2_TX_PATH_SEC3:
536 case CDC_TX2_TX_PATH_SEC4:
537 case CDC_TX2_TX_PATH_SEC5:
538 case CDC_TX2_TX_PATH_SEC6:
539 case CDC_TX3_TX_PATH_CTL:
540 case CDC_TX3_TX_PATH_CFG0:
541 case CDC_TX3_TX_PATH_CFG1:
542 case CDC_TX3_TX_VOL_CTL:
543 case CDC_TX3_TX_PATH_SEC0:
544 case CDC_TX3_TX_PATH_SEC1:
545 case CDC_TX3_TX_PATH_SEC2:
546 case CDC_TX3_TX_PATH_SEC3:
547 case CDC_TX3_TX_PATH_SEC4:
548 case CDC_TX3_TX_PATH_SEC5:
549 case CDC_TX3_TX_PATH_SEC6:
550 case CDC_TX4_TX_PATH_CTL:
551 case CDC_TX4_TX_PATH_CFG0:
552 case CDC_TX4_TX_PATH_CFG1:
553 case CDC_TX4_TX_VOL_CTL:
554 case CDC_TX4_TX_PATH_SEC0:
555 case CDC_TX4_TX_PATH_SEC1:
556 case CDC_TX4_TX_PATH_SEC2:
557 case CDC_TX4_TX_PATH_SEC3:
558 case CDC_TX4_TX_PATH_SEC4:
559 case CDC_TX4_TX_PATH_SEC5:
560 case CDC_TX4_TX_PATH_SEC6:
561 case CDC_TX5_TX_PATH_CTL:
562 case CDC_TX5_TX_PATH_CFG0:
563 case CDC_TX5_TX_PATH_CFG1:
564 case CDC_TX5_TX_VOL_CTL:
565 case CDC_TX5_TX_PATH_SEC0:
566 case CDC_TX5_TX_PATH_SEC1:
567 case CDC_TX5_TX_PATH_SEC2:
568 case CDC_TX5_TX_PATH_SEC3:
569 case CDC_TX5_TX_PATH_SEC4:
570 case CDC_TX5_TX_PATH_SEC5:
571 case CDC_TX5_TX_PATH_SEC6:
572 case CDC_TX6_TX_PATH_CTL:
573 case CDC_TX6_TX_PATH_CFG0:
574 case CDC_TX6_TX_PATH_CFG1:
575 case CDC_TX6_TX_VOL_CTL:
576 case CDC_TX6_TX_PATH_SEC0:
577 case CDC_TX6_TX_PATH_SEC1:
578 case CDC_TX6_TX_PATH_SEC2:
579 case CDC_TX6_TX_PATH_SEC3:
580 case CDC_TX6_TX_PATH_SEC4:
581 case CDC_TX6_TX_PATH_SEC5:
582 case CDC_TX6_TX_PATH_SEC6:
583 case CDC_TX7_TX_PATH_CTL:
584 case CDC_TX7_TX_PATH_CFG0:
585 case CDC_TX7_TX_PATH_CFG1:
586 case CDC_TX7_TX_VOL_CTL:
587 case CDC_TX7_TX_PATH_SEC0:
588 case CDC_TX7_TX_PATH_SEC1:
589 case CDC_TX7_TX_PATH_SEC2:
590 case CDC_TX7_TX_PATH_SEC3:
591 case CDC_TX7_TX_PATH_SEC4:
592 case CDC_TX7_TX_PATH_SEC5:
593 case CDC_TX7_TX_PATH_SEC6:
594 return true;
595 }
596
597 return false;
598 }
599
600 static const struct regmap_config tx_regmap_config = {
601 .name = "tx_macro",
602 .reg_bits = 16,
603 .val_bits = 32,
604 .reg_stride = 4,
605 .cache_type = REGCACHE_FLAT,
606 .max_register = TX_MAX_OFFSET,
607 .reg_defaults = tx_defaults,
608 .num_reg_defaults = ARRAY_SIZE(tx_defaults),
609 .writeable_reg = tx_is_rw_register,
610 .volatile_reg = tx_is_volatile_register,
611 .readable_reg = tx_is_rw_register,
612 };
613
tx_macro_mclk_enable(struct tx_macro * tx,bool mclk_enable)614 static int tx_macro_mclk_enable(struct tx_macro *tx,
615 bool mclk_enable)
616 {
617 struct regmap *regmap = tx->regmap;
618 int ret;
619
620 if (mclk_enable) {
621 if (tx->tx_mclk_users == 0) {
622 /* 9.6MHz MCLK, set value 0x00 if other frequency */
623 regmap_update_bits(regmap, CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01);
624 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
625 CDC_TX_MCLK_EN_MASK,
626 CDC_TX_MCLK_ENABLE);
627 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
628 CDC_TX_FS_CNT_EN_MASK,
629 CDC_TX_FS_CNT_ENABLE);
630 regcache_mark_dirty(regmap);
631 ret = regcache_sync(regmap);
632 if (ret)
633 return ret;
634 }
635 tx->tx_mclk_users++;
636 } else {
637 if (tx->tx_mclk_users <= 0) {
638 dev_err(tx->dev, "clock already disabled\n");
639 tx->tx_mclk_users = 0;
640 goto exit;
641 }
642 tx->tx_mclk_users--;
643 if (tx->tx_mclk_users == 0) {
644 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL,
645 CDC_TX_FS_CNT_EN_MASK, 0x0);
646 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_MCLK_CONTROL,
647 CDC_TX_MCLK_EN_MASK, 0x0);
648 }
649 }
650 exit:
651 return 0;
652 }
653
is_amic_enabled(struct snd_soc_component * component,struct tx_macro * tx,u8 decimator)654 static bool is_amic_enabled(struct snd_soc_component *component,
655 struct tx_macro *tx, u8 decimator)
656 {
657 u16 adc_mux_reg, adc_reg, adc_n;
658
659 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
660
661 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
662 if (tx->data->ver > LPASS_VER_9_0_0)
663 return true;
664
665 /* else: LPASS <= v9.0.0 */
666 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
667 adc_n = snd_soc_component_read_field(component, adc_reg,
668 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK);
669 if (adc_n < TX_ADC_MAX)
670 return true;
671 }
672
673 return false;
674 }
675
tx_macro_tx_hpf_corner_freq_callback(struct work_struct * work)676 static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work)
677 {
678 struct delayed_work *hpf_delayed_work;
679 struct hpf_work *hpf_work;
680 struct tx_macro *tx;
681 struct snd_soc_component *component;
682 u16 dec_cfg_reg, hpf_gate_reg;
683 u8 hpf_cut_off_freq;
684
685 hpf_delayed_work = to_delayed_work(work);
686 hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork);
687 tx = hpf_work->tx;
688 component = tx->component;
689 hpf_cut_off_freq = hpf_work->hpf_cut_off_freq;
690
691 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(hpf_work->decimator);
692 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(hpf_work->decimator);
693
694 if (is_amic_enabled(component, tx, hpf_work->decimator)) {
695 snd_soc_component_write_field(component,
696 dec_cfg_reg,
697 CDC_TXn_HPF_CUT_FREQ_MASK,
698 hpf_cut_off_freq);
699 snd_soc_component_update_bits(component, hpf_gate_reg,
700 CDC_TXn_HPF_F_CHANGE_MASK |
701 CDC_TXn_HPF_ZERO_GATE_MASK,
702 0x02);
703 snd_soc_component_update_bits(component, hpf_gate_reg,
704 CDC_TXn_HPF_F_CHANGE_MASK |
705 CDC_TXn_HPF_ZERO_GATE_MASK,
706 0x01);
707 } else {
708 snd_soc_component_write_field(component, dec_cfg_reg,
709 CDC_TXn_HPF_CUT_FREQ_MASK,
710 hpf_cut_off_freq);
711 snd_soc_component_write_field(component, hpf_gate_reg,
712 CDC_TXn_HPF_F_CHANGE_MASK, 0x1);
713 /* Minimum 1 clk cycle delay is required as per HW spec */
714 usleep_range(1000, 1010);
715 snd_soc_component_write_field(component, hpf_gate_reg,
716 CDC_TXn_HPF_F_CHANGE_MASK, 0x0);
717 }
718 }
719
tx_macro_mute_update_callback(struct work_struct * work)720 static void tx_macro_mute_update_callback(struct work_struct *work)
721 {
722 struct tx_mute_work *tx_mute_dwork;
723 struct snd_soc_component *component;
724 struct tx_macro *tx;
725 struct delayed_work *delayed_work;
726 u8 decimator;
727
728 delayed_work = to_delayed_work(work);
729 tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork);
730 tx = tx_mute_dwork->tx;
731 component = tx->component;
732 decimator = tx_mute_dwork->decimator;
733
734 snd_soc_component_write_field(component, CDC_TXn_TX_PATH_CTL(decimator),
735 CDC_TXn_PGA_MUTE_MASK, 0x0);
736 }
737
tx_macro_mclk_event(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)738 static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w,
739 struct snd_kcontrol *kcontrol, int event)
740 {
741 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
742 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
743
744 switch (event) {
745 case SND_SOC_DAPM_PRE_PMU:
746 return tx_macro_mclk_enable(tx, true);
747 case SND_SOC_DAPM_POST_PMD:
748 return tx_macro_mclk_enable(tx, false);
749 default:
750 break;
751 }
752
753 return 0;
754 }
755
tx_macro_update_smic_sel_v9(struct snd_soc_component * component,struct snd_soc_dapm_widget * widget,struct tx_macro * tx,u16 mic_sel_reg,unsigned int val)756 static void tx_macro_update_smic_sel_v9(struct snd_soc_component *component,
757 struct snd_soc_dapm_widget *widget,
758 struct tx_macro *tx, u16 mic_sel_reg,
759 unsigned int val)
760 {
761 unsigned int dmic;
762 u16 dmic_clk_reg;
763
764 if (val < 5) {
765 snd_soc_component_write_field(component, mic_sel_reg,
766 CDC_TXn_ADC_DMIC_SEL_MASK, 0);
767 } else {
768 snd_soc_component_write_field(component, mic_sel_reg,
769 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
770 dmic = TX_ADC_TO_DMIC(val);
771 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
772 snd_soc_component_write_field(component, dmic_clk_reg,
773 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
774 CDC_TX_SWR_MIC_CLK_DEFAULT);
775 }
776 }
777
tx_macro_update_smic_sel_v9_2(struct snd_soc_component * component,struct snd_soc_dapm_widget * widget,struct tx_macro * tx,u16 mic_sel_reg,unsigned int val)778 static void tx_macro_update_smic_sel_v9_2(struct snd_soc_component *component,
779 struct snd_soc_dapm_widget *widget,
780 struct tx_macro *tx, u16 mic_sel_reg,
781 unsigned int val)
782 {
783 unsigned int dmic;
784 u16 dmic_clk_reg;
785
786 if (widget->shift) {
787 /* MSM DMIC */
788 snd_soc_component_write_field(component, mic_sel_reg,
789 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
790
791 dmic = TX_ADC_TO_DMIC(val);
792 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
793 snd_soc_component_write_field(component, dmic_clk_reg,
794 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
795 CDC_TX_SWR_MIC_CLK_DEFAULT);
796 } else {
797 snd_soc_component_write_field(component, mic_sel_reg,
798 CDC_TXn_ADC_DMIC_SEL_MASK, 0);
799 }
800 }
801
tx_macro_put_dec_enum(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)802 static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol,
803 struct snd_ctl_elem_value *ucontrol)
804 {
805 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
806 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
807 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
808 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
809 unsigned int val;
810 u16 mic_sel_reg;
811
812 val = ucontrol->value.enumerated.item[0];
813 if (val >= e->items)
814 return -EINVAL;
815
816 switch (e->reg) {
817 case CDC_TX_INP_MUX_ADC_MUX0_CFG0:
818 mic_sel_reg = CDC_TX0_TX_PATH_CFG0;
819 break;
820 case CDC_TX_INP_MUX_ADC_MUX1_CFG0:
821 mic_sel_reg = CDC_TX1_TX_PATH_CFG0;
822 break;
823 case CDC_TX_INP_MUX_ADC_MUX2_CFG0:
824 mic_sel_reg = CDC_TX2_TX_PATH_CFG0;
825 break;
826 case CDC_TX_INP_MUX_ADC_MUX3_CFG0:
827 mic_sel_reg = CDC_TX3_TX_PATH_CFG0;
828 break;
829 case CDC_TX_INP_MUX_ADC_MUX4_CFG0:
830 mic_sel_reg = CDC_TX4_TX_PATH_CFG0;
831 break;
832 case CDC_TX_INP_MUX_ADC_MUX5_CFG0:
833 mic_sel_reg = CDC_TX5_TX_PATH_CFG0;
834 break;
835 case CDC_TX_INP_MUX_ADC_MUX6_CFG0:
836 mic_sel_reg = CDC_TX6_TX_PATH_CFG0;
837 break;
838 case CDC_TX_INP_MUX_ADC_MUX7_CFG0:
839 mic_sel_reg = CDC_TX7_TX_PATH_CFG0;
840 break;
841 default:
842 dev_err(component->dev, "Error in configuration!!\n");
843 return -EINVAL;
844 }
845
846 if (val != 0) {
847 if (widget->shift) /* MSM DMIC */
848 snd_soc_component_write_field(component, mic_sel_reg,
849 CDC_TXn_ADC_DMIC_SEL_MASK, 1);
850 else if (tx->data->ver <= LPASS_VER_9_0_0)
851 tx_macro_update_smic_sel_v9(component, widget, tx,
852 mic_sel_reg, val);
853 else
854 tx_macro_update_smic_sel_v9_2(component, widget, tx,
855 mic_sel_reg, val);
856 }
857
858 return snd_soc_dapm_put_enum_double(kcontrol, ucontrol);
859 }
860
tx_macro_tx_mixer_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)861 static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol,
862 struct snd_ctl_elem_value *ucontrol)
863 {
864 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
865 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
866 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
867 u32 dai_id = widget->shift;
868 u32 dec_id = mc->shift;
869 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
870
871 if (test_bit(dec_id, &tx->active_ch_mask[dai_id]))
872 ucontrol->value.integer.value[0] = 1;
873 else
874 ucontrol->value.integer.value[0] = 0;
875
876 return 0;
877 }
878
tx_macro_tx_mixer_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)879 static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol,
880 struct snd_ctl_elem_value *ucontrol)
881 {
882 struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_to_widget(kcontrol);
883 struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
884 struct snd_soc_dapm_update *update = NULL;
885 struct soc_mixer_control *mc = (struct soc_mixer_control *)kcontrol->private_value;
886 u32 dai_id = widget->shift;
887 u32 dec_id = mc->shift;
888 u32 enable = ucontrol->value.integer.value[0];
889 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
890
891 if (enable) {
892 if (tx->active_decimator[dai_id] == dec_id)
893 return 0;
894
895 set_bit(dec_id, &tx->active_ch_mask[dai_id]);
896 tx->active_ch_cnt[dai_id]++;
897 tx->active_decimator[dai_id] = dec_id;
898 } else {
899 if (tx->active_decimator[dai_id] == -1)
900 return 0;
901
902 tx->active_ch_cnt[dai_id]--;
903 clear_bit(dec_id, &tx->active_ch_mask[dai_id]);
904 tx->active_decimator[dai_id] = -1;
905 }
906 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
907
908 return 1;
909 }
910
tx_macro_enable_dec(struct snd_soc_dapm_widget * w,struct snd_kcontrol * kcontrol,int event)911 static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w,
912 struct snd_kcontrol *kcontrol, int event)
913 {
914 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
915 u8 decimator;
916 u16 tx_vol_ctl_reg, dec_cfg_reg, hpf_gate_reg, tx_gain_ctl_reg;
917 u8 hpf_cut_off_freq;
918 int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS;
919 int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS;
920 u16 adc_mux_reg, adc_reg, adc_n, dmic;
921 u16 dmic_clk_reg;
922 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
923
924 decimator = w->shift;
925 tx_vol_ctl_reg = CDC_TXn_TX_PATH_CTL(decimator);
926 hpf_gate_reg = CDC_TXn_TX_PATH_SEC2(decimator);
927 dec_cfg_reg = CDC_TXn_TX_PATH_CFG0(decimator);
928 tx_gain_ctl_reg = CDC_TXn_TX_VOL_CTL(decimator);
929
930 switch (event) {
931 case SND_SOC_DAPM_PRE_PMU:
932 adc_mux_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG1(decimator);
933 if (snd_soc_component_read(component, adc_mux_reg) & SWR_MIC) {
934 adc_reg = CDC_TX_INP_MUX_ADC_MUXn_CFG0(decimator);
935 adc_n = snd_soc_component_read(component, adc_reg) &
936 CDC_TX_MACRO_SWR_MIC_MUX_SEL_MASK;
937 if (adc_n >= TX_ADC_MAX) {
938 dmic = TX_ADC_TO_DMIC(adc_n);
939 dmic_clk_reg = CDC_TX_TOP_CSR_SWR_DMICn_CTL(dmic);
940
941 snd_soc_component_write_field(component, dmic_clk_reg,
942 CDC_TX_SWR_DMIC_CLK_SEL_MASK,
943 CDC_TX_SWR_MIC_CLK_DEFAULT);
944 }
945 }
946 snd_soc_component_write_field(component, dec_cfg_reg,
947 CDC_TXn_ADC_MODE_MASK,
948 tx->dec_mode[decimator]);
949 /* Enable TX PGA Mute */
950 snd_soc_component_write_field(component, tx_vol_ctl_reg,
951 CDC_TXn_PGA_MUTE_MASK, 0x1);
952 break;
953 case SND_SOC_DAPM_POST_PMU:
954 snd_soc_component_write_field(component, tx_vol_ctl_reg,
955 CDC_TXn_CLK_EN_MASK, 0x1);
956 if (!is_amic_enabled(component, tx, decimator)) {
957 snd_soc_component_update_bits(component, hpf_gate_reg, 0x01, 0x00);
958 /* Minimum 1 clk cycle delay is required as per HW spec */
959 usleep_range(1000, 1010);
960 }
961 hpf_cut_off_freq = snd_soc_component_read_field(component, dec_cfg_reg,
962 CDC_TXn_HPF_CUT_FREQ_MASK);
963
964 tx->tx_hpf_work[decimator].hpf_cut_off_freq =
965 hpf_cut_off_freq;
966
967 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ)
968 snd_soc_component_write_field(component, dec_cfg_reg,
969 CDC_TXn_HPF_CUT_FREQ_MASK,
970 CF_MIN_3DB_150HZ);
971
972 if (is_amic_enabled(component, tx, decimator)) {
973 hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS;
974 unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS;
975 }
976 /* schedule work queue to Remove Mute */
977 queue_delayed_work(system_freezable_wq,
978 &tx->tx_mute_dwork[decimator].dwork,
979 msecs_to_jiffies(unmute_delay));
980 if (tx->tx_hpf_work[decimator].hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
981 queue_delayed_work(system_freezable_wq,
982 &tx->tx_hpf_work[decimator].dwork,
983 msecs_to_jiffies(hpf_delay));
984 snd_soc_component_update_bits(component, hpf_gate_reg,
985 CDC_TXn_HPF_F_CHANGE_MASK |
986 CDC_TXn_HPF_ZERO_GATE_MASK,
987 0x02);
988 if (!is_amic_enabled(component, tx, decimator))
989 snd_soc_component_update_bits(component, hpf_gate_reg,
990 CDC_TXn_HPF_F_CHANGE_MASK |
991 CDC_TXn_HPF_ZERO_GATE_MASK,
992 0x00);
993 snd_soc_component_update_bits(component, hpf_gate_reg,
994 CDC_TXn_HPF_F_CHANGE_MASK |
995 CDC_TXn_HPF_ZERO_GATE_MASK,
996 0x01);
997
998 /*
999 * 6ms delay is required as per HW spec
1000 */
1001 usleep_range(6000, 6010);
1002 }
1003 /* apply gain after decimator is enabled */
1004 snd_soc_component_write(component, tx_gain_ctl_reg,
1005 snd_soc_component_read(component,
1006 tx_gain_ctl_reg));
1007 if (tx->bcs_enable) {
1008 snd_soc_component_update_bits(component, dec_cfg_reg,
1009 0x01, 0x01);
1010 tx->bcs_clk_en = true;
1011 }
1012 break;
1013 case SND_SOC_DAPM_PRE_PMD:
1014 hpf_cut_off_freq =
1015 tx->tx_hpf_work[decimator].hpf_cut_off_freq;
1016 snd_soc_component_write_field(component, tx_vol_ctl_reg,
1017 CDC_TXn_PGA_MUTE_MASK, 0x1);
1018 if (cancel_delayed_work_sync(
1019 &tx->tx_hpf_work[decimator].dwork)) {
1020 if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) {
1021 snd_soc_component_write_field(
1022 component, dec_cfg_reg,
1023 CDC_TXn_HPF_CUT_FREQ_MASK,
1024 hpf_cut_off_freq);
1025 if (is_amic_enabled(component, tx, decimator))
1026 snd_soc_component_update_bits(component,
1027 hpf_gate_reg,
1028 CDC_TXn_HPF_F_CHANGE_MASK |
1029 CDC_TXn_HPF_ZERO_GATE_MASK,
1030 0x02);
1031 else
1032 snd_soc_component_update_bits(component,
1033 hpf_gate_reg,
1034 CDC_TXn_HPF_F_CHANGE_MASK |
1035 CDC_TXn_HPF_ZERO_GATE_MASK,
1036 0x03);
1037
1038 /*
1039 * Minimum 1 clk cycle delay is required
1040 * as per HW spec
1041 */
1042 usleep_range(1000, 1010);
1043 snd_soc_component_update_bits(component, hpf_gate_reg,
1044 CDC_TXn_HPF_F_CHANGE_MASK |
1045 CDC_TXn_HPF_ZERO_GATE_MASK,
1046 0x1);
1047 }
1048 }
1049 cancel_delayed_work_sync(&tx->tx_mute_dwork[decimator].dwork);
1050 break;
1051 case SND_SOC_DAPM_POST_PMD:
1052 snd_soc_component_write_field(component, tx_vol_ctl_reg,
1053 CDC_TXn_CLK_EN_MASK, 0x0);
1054 snd_soc_component_write_field(component, dec_cfg_reg,
1055 CDC_TXn_ADC_MODE_MASK, 0x0);
1056 snd_soc_component_write_field(component, tx_vol_ctl_reg,
1057 CDC_TXn_PGA_MUTE_MASK, 0x0);
1058 if (tx->bcs_enable) {
1059 snd_soc_component_write_field(component, dec_cfg_reg,
1060 CDC_TXn_PH_EN_MASK, 0x0);
1061 snd_soc_component_write_field(component,
1062 CDC_TX0_TX_PATH_SEC7,
1063 CDC_TX0_MBHC_CTL_EN_MASK,
1064 0x0);
1065 tx->bcs_clk_en = false;
1066 }
1067 break;
1068 }
1069 return 0;
1070 }
1071
tx_macro_dec_mode_get(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1072 static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol,
1073 struct snd_ctl_elem_value *ucontrol)
1074 {
1075 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1076 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1077 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1078 int path = e->shift_l;
1079
1080 ucontrol->value.enumerated.item[0] = tx->dec_mode[path];
1081
1082 return 0;
1083 }
1084
tx_macro_dec_mode_put(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1085 static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol,
1086 struct snd_ctl_elem_value *ucontrol)
1087 {
1088 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1089 int value = ucontrol->value.enumerated.item[0];
1090 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
1091 int path = e->shift_l;
1092 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1093
1094 if (tx->dec_mode[path] == value)
1095 return 0;
1096
1097 tx->dec_mode[path] = value;
1098
1099 return 1;
1100 }
1101
tx_macro_get_bcs(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1102 static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol,
1103 struct snd_ctl_elem_value *ucontrol)
1104 {
1105 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1106 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1107
1108 ucontrol->value.integer.value[0] = tx->bcs_enable;
1109
1110 return 0;
1111 }
1112
tx_macro_set_bcs(struct snd_kcontrol * kcontrol,struct snd_ctl_elem_value * ucontrol)1113 static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol,
1114 struct snd_ctl_elem_value *ucontrol)
1115 {
1116 struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
1117 int value = ucontrol->value.integer.value[0];
1118 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1119
1120 tx->bcs_enable = value;
1121
1122 return 0;
1123 }
1124
tx_macro_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)1125 static int tx_macro_hw_params(struct snd_pcm_substream *substream,
1126 struct snd_pcm_hw_params *params,
1127 struct snd_soc_dai *dai)
1128 {
1129 struct snd_soc_component *component = dai->component;
1130 u32 sample_rate;
1131 u8 decimator;
1132 int tx_fs_rate;
1133 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1134
1135 sample_rate = params_rate(params);
1136 switch (sample_rate) {
1137 case 8000:
1138 tx_fs_rate = 0;
1139 break;
1140 case 16000:
1141 tx_fs_rate = 1;
1142 break;
1143 case 32000:
1144 tx_fs_rate = 3;
1145 break;
1146 case 48000:
1147 tx_fs_rate = 4;
1148 break;
1149 case 96000:
1150 tx_fs_rate = 5;
1151 break;
1152 case 192000:
1153 tx_fs_rate = 6;
1154 break;
1155 case 384000:
1156 tx_fs_rate = 7;
1157 break;
1158 default:
1159 dev_err(component->dev, "%s: Invalid TX sample rate: %d\n",
1160 __func__, params_rate(params));
1161 return -EINVAL;
1162 }
1163
1164 for_each_set_bit(decimator, &tx->active_ch_mask[dai->id], TX_MACRO_DEC_MAX)
1165 snd_soc_component_update_bits(component, CDC_TXn_TX_PATH_CTL(decimator),
1166 CDC_TXn_PCM_RATE_MASK,
1167 tx_fs_rate);
1168 return 0;
1169 }
1170
tx_macro_get_channel_map(const struct snd_soc_dai * dai,unsigned int * tx_num,unsigned int * tx_slot,unsigned int * rx_num,unsigned int * rx_slot)1171 static int tx_macro_get_channel_map(const struct snd_soc_dai *dai,
1172 unsigned int *tx_num, unsigned int *tx_slot,
1173 unsigned int *rx_num, unsigned int *rx_slot)
1174 {
1175 struct snd_soc_component *component = dai->component;
1176 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1177
1178 switch (dai->id) {
1179 case TX_MACRO_AIF1_CAP:
1180 case TX_MACRO_AIF2_CAP:
1181 case TX_MACRO_AIF3_CAP:
1182 *tx_slot = tx->active_ch_mask[dai->id];
1183 *tx_num = tx->active_ch_cnt[dai->id];
1184 break;
1185 default:
1186 break;
1187 }
1188 return 0;
1189 }
1190
tx_macro_digital_mute(struct snd_soc_dai * dai,int mute,int stream)1191 static int tx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
1192 {
1193 struct snd_soc_component *component = dai->component;
1194 struct tx_macro *tx = snd_soc_component_get_drvdata(component);
1195 u8 decimator;
1196
1197 /* active decimator not set yet */
1198 if (tx->active_decimator[dai->id] == -1)
1199 return 0;
1200
1201 decimator = tx->active_decimator[dai->id];
1202
1203 if (mute)
1204 snd_soc_component_write_field(component,
1205 CDC_TXn_TX_PATH_CTL(decimator),
1206 CDC_TXn_PGA_MUTE_MASK, 0x1);
1207 else
1208 snd_soc_component_update_bits(component,
1209 CDC_TXn_TX_PATH_CTL(decimator),
1210 CDC_TXn_PGA_MUTE_MASK, 0x0);
1211
1212 return 0;
1213 }
1214
1215 static const struct snd_soc_dai_ops tx_macro_dai_ops = {
1216 .hw_params = tx_macro_hw_params,
1217 .get_channel_map = tx_macro_get_channel_map,
1218 .mute_stream = tx_macro_digital_mute,
1219 };
1220
1221 static struct snd_soc_dai_driver tx_macro_dai[] = {
1222 {
1223 .name = "tx_macro_tx1",
1224 .id = TX_MACRO_AIF1_CAP,
1225 .capture = {
1226 .stream_name = "TX_AIF1 Capture",
1227 .rates = TX_MACRO_RATES,
1228 .formats = TX_MACRO_FORMATS,
1229 .rate_max = 192000,
1230 .rate_min = 8000,
1231 .channels_min = 1,
1232 .channels_max = 8,
1233 },
1234 .ops = &tx_macro_dai_ops,
1235 },
1236 {
1237 .name = "tx_macro_tx2",
1238 .id = TX_MACRO_AIF2_CAP,
1239 .capture = {
1240 .stream_name = "TX_AIF2 Capture",
1241 .rates = TX_MACRO_RATES,
1242 .formats = TX_MACRO_FORMATS,
1243 .rate_max = 192000,
1244 .rate_min = 8000,
1245 .channels_min = 1,
1246 .channels_max = 8,
1247 },
1248 .ops = &tx_macro_dai_ops,
1249 },
1250 {
1251 .name = "tx_macro_tx3",
1252 .id = TX_MACRO_AIF3_CAP,
1253 .capture = {
1254 .stream_name = "TX_AIF3 Capture",
1255 .rates = TX_MACRO_RATES,
1256 .formats = TX_MACRO_FORMATS,
1257 .rate_max = 192000,
1258 .rate_min = 8000,
1259 .channels_min = 1,
1260 .channels_max = 8,
1261 },
1262 .ops = &tx_macro_dai_ops,
1263 },
1264 };
1265
1266 static const char * const adc_mux_text[] = {
1267 "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1"
1268 };
1269
1270 static SOC_ENUM_SINGLE_DECL(tx_dec0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG1,
1271 0, adc_mux_text);
1272 static SOC_ENUM_SINGLE_DECL(tx_dec1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG1,
1273 0, adc_mux_text);
1274 static SOC_ENUM_SINGLE_DECL(tx_dec2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG1,
1275 0, adc_mux_text);
1276 static SOC_ENUM_SINGLE_DECL(tx_dec3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG1,
1277 0, adc_mux_text);
1278 static SOC_ENUM_SINGLE_DECL(tx_dec4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG1,
1279 0, adc_mux_text);
1280 static SOC_ENUM_SINGLE_DECL(tx_dec5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG1,
1281 0, adc_mux_text);
1282 static SOC_ENUM_SINGLE_DECL(tx_dec6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG1,
1283 0, adc_mux_text);
1284 static SOC_ENUM_SINGLE_DECL(tx_dec7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG1,
1285 0, adc_mux_text);
1286
1287 static const struct snd_kcontrol_new tx_dec0_mux = SOC_DAPM_ENUM("tx_dec0", tx_dec0_enum);
1288 static const struct snd_kcontrol_new tx_dec1_mux = SOC_DAPM_ENUM("tx_dec1", tx_dec1_enum);
1289 static const struct snd_kcontrol_new tx_dec2_mux = SOC_DAPM_ENUM("tx_dec2", tx_dec2_enum);
1290 static const struct snd_kcontrol_new tx_dec3_mux = SOC_DAPM_ENUM("tx_dec3", tx_dec3_enum);
1291 static const struct snd_kcontrol_new tx_dec4_mux = SOC_DAPM_ENUM("tx_dec4", tx_dec4_enum);
1292 static const struct snd_kcontrol_new tx_dec5_mux = SOC_DAPM_ENUM("tx_dec5", tx_dec5_enum);
1293 static const struct snd_kcontrol_new tx_dec6_mux = SOC_DAPM_ENUM("tx_dec6", tx_dec6_enum);
1294 static const struct snd_kcontrol_new tx_dec7_mux = SOC_DAPM_ENUM("tx_dec7", tx_dec7_enum);
1295
1296 static const char * const dmic_mux_text[] = {
1297 "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3",
1298 "DMIC4", "DMIC5", "DMIC6", "DMIC7"
1299 };
1300
1301 static SOC_ENUM_SINGLE_DECL(tx_dmic0_enum, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1302 4, dmic_mux_text);
1303
1304 static SOC_ENUM_SINGLE_DECL(tx_dmic1_enum, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1305 4, dmic_mux_text);
1306
1307 static SOC_ENUM_SINGLE_DECL(tx_dmic2_enum, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1308 4, dmic_mux_text);
1309
1310 static SOC_ENUM_SINGLE_DECL(tx_dmic3_enum, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1311 4, dmic_mux_text);
1312
1313 static SOC_ENUM_SINGLE_DECL(tx_dmic4_enum, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1314 4, dmic_mux_text);
1315
1316 static SOC_ENUM_SINGLE_DECL(tx_dmic5_enum, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1317 4, dmic_mux_text);
1318
1319 static SOC_ENUM_SINGLE_DECL(tx_dmic6_enum, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1320 4, dmic_mux_text);
1321
1322 static SOC_ENUM_SINGLE_DECL(tx_dmic7_enum, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1323 4, dmic_mux_text);
1324
1325 static const struct snd_kcontrol_new tx_dmic0_mux = SOC_DAPM_ENUM_EXT("tx_dmic0", tx_dmic0_enum,
1326 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1327 static const struct snd_kcontrol_new tx_dmic1_mux = SOC_DAPM_ENUM_EXT("tx_dmic1", tx_dmic1_enum,
1328 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1329 static const struct snd_kcontrol_new tx_dmic2_mux = SOC_DAPM_ENUM_EXT("tx_dmic2", tx_dmic2_enum,
1330 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1331 static const struct snd_kcontrol_new tx_dmic3_mux = SOC_DAPM_ENUM_EXT("tx_dmic3", tx_dmic3_enum,
1332 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1333 static const struct snd_kcontrol_new tx_dmic4_mux = SOC_DAPM_ENUM_EXT("tx_dmic4", tx_dmic4_enum,
1334 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1335 static const struct snd_kcontrol_new tx_dmic5_mux = SOC_DAPM_ENUM_EXT("tx_dmic5", tx_dmic5_enum,
1336 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1337 static const struct snd_kcontrol_new tx_dmic6_mux = SOC_DAPM_ENUM_EXT("tx_dmic6", tx_dmic6_enum,
1338 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1339 static const struct snd_kcontrol_new tx_dmic7_mux = SOC_DAPM_ENUM_EXT("tx_dmic7", tx_dmic7_enum,
1340 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1341
1342 static const char * const dec_mode_mux_text[] = {
1343 "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF",
1344 };
1345
1346 static const struct soc_enum dec_mode_mux_enum[] = {
1347 SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(dec_mode_mux_text),
1348 dec_mode_mux_text),
1349 SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(dec_mode_mux_text),
1350 dec_mode_mux_text),
1351 SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(dec_mode_mux_text),
1352 dec_mode_mux_text),
1353 SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(dec_mode_mux_text),
1354 dec_mode_mux_text),
1355 SOC_ENUM_SINGLE(SND_SOC_NOPM, 4, ARRAY_SIZE(dec_mode_mux_text),
1356 dec_mode_mux_text),
1357 SOC_ENUM_SINGLE(SND_SOC_NOPM, 5, ARRAY_SIZE(dec_mode_mux_text),
1358 dec_mode_mux_text),
1359 SOC_ENUM_SINGLE(SND_SOC_NOPM, 6, ARRAY_SIZE(dec_mode_mux_text),
1360 dec_mode_mux_text),
1361 SOC_ENUM_SINGLE(SND_SOC_NOPM, 7, ARRAY_SIZE(dec_mode_mux_text),
1362 dec_mode_mux_text),
1363 };
1364
1365 static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = {
1366 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1367 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1368 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1369 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1370 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1371 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1372 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1373 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1374 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1375 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1376 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1377 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1378 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1379 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1380 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1381 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1382 };
1383
1384 static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = {
1385 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1386 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1387 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1388 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1389 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1390 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1391 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1392 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1393 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1394 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1395 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1396 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1397 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1398 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1399 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1400 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1401 };
1402
1403 static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = {
1404 SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0,
1405 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1406 SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0,
1407 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1408 SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0,
1409 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1410 SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0,
1411 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1412 SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0,
1413 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1414 SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0,
1415 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1416 SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0,
1417 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1418 SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0,
1419 tx_macro_tx_mixer_get, tx_macro_tx_mixer_put),
1420 };
1421
1422 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = {
1423 SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0,
1424 SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0),
1425
1426 SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0,
1427 SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0),
1428
1429 SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0,
1430 SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0),
1431
1432 SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0,
1433 tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)),
1434
1435 SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0,
1436 tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)),
1437
1438 SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0,
1439 tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)),
1440
1441 SND_SOC_DAPM_MUX("TX DMIC MUX0", SND_SOC_NOPM, 4, 0, &tx_dmic0_mux),
1442 SND_SOC_DAPM_MUX("TX DMIC MUX1", SND_SOC_NOPM, 4, 0, &tx_dmic1_mux),
1443 SND_SOC_DAPM_MUX("TX DMIC MUX2", SND_SOC_NOPM, 4, 0, &tx_dmic2_mux),
1444 SND_SOC_DAPM_MUX("TX DMIC MUX3", SND_SOC_NOPM, 4, 0, &tx_dmic3_mux),
1445 SND_SOC_DAPM_MUX("TX DMIC MUX4", SND_SOC_NOPM, 4, 0, &tx_dmic4_mux),
1446 SND_SOC_DAPM_MUX("TX DMIC MUX5", SND_SOC_NOPM, 4, 0, &tx_dmic5_mux),
1447 SND_SOC_DAPM_MUX("TX DMIC MUX6", SND_SOC_NOPM, 4, 0, &tx_dmic6_mux),
1448 SND_SOC_DAPM_MUX("TX DMIC MUX7", SND_SOC_NOPM, 4, 0, &tx_dmic7_mux),
1449
1450 SND_SOC_DAPM_INPUT("TX DMIC0"),
1451 SND_SOC_DAPM_INPUT("TX DMIC1"),
1452 SND_SOC_DAPM_INPUT("TX DMIC2"),
1453 SND_SOC_DAPM_INPUT("TX DMIC3"),
1454 SND_SOC_DAPM_INPUT("TX DMIC4"),
1455 SND_SOC_DAPM_INPUT("TX DMIC5"),
1456 SND_SOC_DAPM_INPUT("TX DMIC6"),
1457 SND_SOC_DAPM_INPUT("TX DMIC7"),
1458
1459 SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM,
1460 TX_MACRO_DEC0, 0,
1461 &tx_dec0_mux, tx_macro_enable_dec,
1462 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1463 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1464
1465 SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM,
1466 TX_MACRO_DEC1, 0,
1467 &tx_dec1_mux, tx_macro_enable_dec,
1468 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1469 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1470
1471 SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM,
1472 TX_MACRO_DEC2, 0,
1473 &tx_dec2_mux, tx_macro_enable_dec,
1474 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1475 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1476
1477 SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM,
1478 TX_MACRO_DEC3, 0,
1479 &tx_dec3_mux, tx_macro_enable_dec,
1480 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1481 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1482
1483 SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM,
1484 TX_MACRO_DEC4, 0,
1485 &tx_dec4_mux, tx_macro_enable_dec,
1486 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1487 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1488
1489 SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM,
1490 TX_MACRO_DEC5, 0,
1491 &tx_dec5_mux, tx_macro_enable_dec,
1492 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1493 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1494
1495 SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM,
1496 TX_MACRO_DEC6, 0,
1497 &tx_dec6_mux, tx_macro_enable_dec,
1498 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1499 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1500
1501 SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM,
1502 TX_MACRO_DEC7, 0,
1503 &tx_dec7_mux, tx_macro_enable_dec,
1504 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
1505 SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
1506
1507 SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0,
1508 tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
1509
1510 SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, NULL, 0),
1511
1512 SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0,
1513 NULL, 0),
1514 };
1515
1516 static const struct snd_soc_dapm_route tx_audio_map[] = {
1517 {"TX_AIF1 CAP", NULL, "TX_MCLK"},
1518 {"TX_AIF2 CAP", NULL, "TX_MCLK"},
1519 {"TX_AIF3 CAP", NULL, "TX_MCLK"},
1520
1521 {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"},
1522 {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"},
1523 {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"},
1524
1525 {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1526 {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1527 {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1528 {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1529 {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1530 {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1531 {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1532 {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1533
1534 {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1535 {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1536 {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1537 {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1538 {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1539 {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1540 {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1541 {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1542
1543 {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"},
1544 {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"},
1545 {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"},
1546 {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"},
1547 {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"},
1548 {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"},
1549 {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"},
1550 {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"},
1551
1552 {"TX DEC0 MUX", NULL, "TX_MCLK"},
1553 {"TX DEC1 MUX", NULL, "TX_MCLK"},
1554 {"TX DEC2 MUX", NULL, "TX_MCLK"},
1555 {"TX DEC3 MUX", NULL, "TX_MCLK"},
1556 {"TX DEC4 MUX", NULL, "TX_MCLK"},
1557 {"TX DEC5 MUX", NULL, "TX_MCLK"},
1558 {"TX DEC6 MUX", NULL, "TX_MCLK"},
1559 {"TX DEC7 MUX", NULL, "TX_MCLK"},
1560
1561 {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"},
1562 {"TX DMIC MUX0", "DMIC0", "TX DMIC0"},
1563 {"TX DMIC MUX0", "DMIC1", "TX DMIC1"},
1564 {"TX DMIC MUX0", "DMIC2", "TX DMIC2"},
1565 {"TX DMIC MUX0", "DMIC3", "TX DMIC3"},
1566 {"TX DMIC MUX0", "DMIC4", "TX DMIC4"},
1567 {"TX DMIC MUX0", "DMIC5", "TX DMIC5"},
1568 {"TX DMIC MUX0", "DMIC6", "TX DMIC6"},
1569 {"TX DMIC MUX0", "DMIC7", "TX DMIC7"},
1570
1571 {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"},
1572 {"TX DMIC MUX1", "DMIC0", "TX DMIC0"},
1573 {"TX DMIC MUX1", "DMIC1", "TX DMIC1"},
1574 {"TX DMIC MUX1", "DMIC2", "TX DMIC2"},
1575 {"TX DMIC MUX1", "DMIC3", "TX DMIC3"},
1576 {"TX DMIC MUX1", "DMIC4", "TX DMIC4"},
1577 {"TX DMIC MUX1", "DMIC5", "TX DMIC5"},
1578 {"TX DMIC MUX1", "DMIC6", "TX DMIC6"},
1579 {"TX DMIC MUX1", "DMIC7", "TX DMIC7"},
1580
1581 {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"},
1582 {"TX DMIC MUX2", "DMIC0", "TX DMIC0"},
1583 {"TX DMIC MUX2", "DMIC1", "TX DMIC1"},
1584 {"TX DMIC MUX2", "DMIC2", "TX DMIC2"},
1585 {"TX DMIC MUX2", "DMIC3", "TX DMIC3"},
1586 {"TX DMIC MUX2", "DMIC4", "TX DMIC4"},
1587 {"TX DMIC MUX2", "DMIC5", "TX DMIC5"},
1588 {"TX DMIC MUX2", "DMIC6", "TX DMIC6"},
1589 {"TX DMIC MUX2", "DMIC7", "TX DMIC7"},
1590
1591 {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"},
1592 {"TX DMIC MUX3", "DMIC0", "TX DMIC0"},
1593 {"TX DMIC MUX3", "DMIC1", "TX DMIC1"},
1594 {"TX DMIC MUX3", "DMIC2", "TX DMIC2"},
1595 {"TX DMIC MUX3", "DMIC3", "TX DMIC3"},
1596 {"TX DMIC MUX3", "DMIC4", "TX DMIC4"},
1597 {"TX DMIC MUX3", "DMIC5", "TX DMIC5"},
1598 {"TX DMIC MUX3", "DMIC6", "TX DMIC6"},
1599 {"TX DMIC MUX3", "DMIC7", "TX DMIC7"},
1600
1601 {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"},
1602 {"TX DMIC MUX4", "DMIC0", "TX DMIC0"},
1603 {"TX DMIC MUX4", "DMIC1", "TX DMIC1"},
1604 {"TX DMIC MUX4", "DMIC2", "TX DMIC2"},
1605 {"TX DMIC MUX4", "DMIC3", "TX DMIC3"},
1606 {"TX DMIC MUX4", "DMIC4", "TX DMIC4"},
1607 {"TX DMIC MUX4", "DMIC5", "TX DMIC5"},
1608 {"TX DMIC MUX4", "DMIC6", "TX DMIC6"},
1609 {"TX DMIC MUX4", "DMIC7", "TX DMIC7"},
1610
1611 {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"},
1612 {"TX DMIC MUX5", "DMIC0", "TX DMIC0"},
1613 {"TX DMIC MUX5", "DMIC1", "TX DMIC1"},
1614 {"TX DMIC MUX5", "DMIC2", "TX DMIC2"},
1615 {"TX DMIC MUX5", "DMIC3", "TX DMIC3"},
1616 {"TX DMIC MUX5", "DMIC4", "TX DMIC4"},
1617 {"TX DMIC MUX5", "DMIC5", "TX DMIC5"},
1618 {"TX DMIC MUX5", "DMIC6", "TX DMIC6"},
1619 {"TX DMIC MUX5", "DMIC7", "TX DMIC7"},
1620
1621 {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"},
1622 {"TX DMIC MUX6", "DMIC0", "TX DMIC0"},
1623 {"TX DMIC MUX6", "DMIC1", "TX DMIC1"},
1624 {"TX DMIC MUX6", "DMIC2", "TX DMIC2"},
1625 {"TX DMIC MUX6", "DMIC3", "TX DMIC3"},
1626 {"TX DMIC MUX6", "DMIC4", "TX DMIC4"},
1627 {"TX DMIC MUX6", "DMIC5", "TX DMIC5"},
1628 {"TX DMIC MUX6", "DMIC6", "TX DMIC6"},
1629 {"TX DMIC MUX6", "DMIC7", "TX DMIC7"},
1630
1631 {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"},
1632 {"TX DMIC MUX7", "DMIC0", "TX DMIC0"},
1633 {"TX DMIC MUX7", "DMIC1", "TX DMIC1"},
1634 {"TX DMIC MUX7", "DMIC2", "TX DMIC2"},
1635 {"TX DMIC MUX7", "DMIC3", "TX DMIC3"},
1636 {"TX DMIC MUX7", "DMIC4", "TX DMIC4"},
1637 {"TX DMIC MUX7", "DMIC5", "TX DMIC5"},
1638 {"TX DMIC MUX7", "DMIC6", "TX DMIC6"},
1639 {"TX DMIC MUX7", "DMIC7", "TX DMIC7"},
1640 };
1641
1642 /* Controls and routes specific to LPASS <= v9.0.0 */
1643 static const char * const smic_mux_text_v9[] = {
1644 "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0",
1645 "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4",
1646 "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7"
1647 };
1648
1649 static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1650 0, smic_mux_text_v9);
1651
1652 static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1653 0, smic_mux_text_v9);
1654
1655 static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1656 0, smic_mux_text_v9);
1657
1658 static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1659 0, smic_mux_text_v9);
1660
1661 static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1662 0, smic_mux_text_v9);
1663
1664 static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1665 0, smic_mux_text_v9);
1666
1667 static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1668 0, smic_mux_text_v9);
1669
1670 static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1671 0, smic_mux_text_v9);
1672
1673 static const struct snd_kcontrol_new tx_smic0_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum_v9,
1674 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1675 static const struct snd_kcontrol_new tx_smic1_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum_v9,
1676 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1677 static const struct snd_kcontrol_new tx_smic2_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum_v9,
1678 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1679 static const struct snd_kcontrol_new tx_smic3_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum_v9,
1680 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1681 static const struct snd_kcontrol_new tx_smic4_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum_v9,
1682 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1683 static const struct snd_kcontrol_new tx_smic5_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum_v9,
1684 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1685 static const struct snd_kcontrol_new tx_smic6_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum_v9,
1686 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1687 static const struct snd_kcontrol_new tx_smic7_mux_v9 = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum_v9,
1688 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1689
1690 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v9[] = {
1691 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9),
1692 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9),
1693 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9),
1694 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9),
1695 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9),
1696 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9),
1697 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9),
1698 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9),
1699
1700 SND_SOC_DAPM_INPUT("TX SWR_ADC0"),
1701 SND_SOC_DAPM_INPUT("TX SWR_ADC1"),
1702 SND_SOC_DAPM_INPUT("TX SWR_ADC2"),
1703 SND_SOC_DAPM_INPUT("TX SWR_ADC3"),
1704 SND_SOC_DAPM_INPUT("TX SWR_DMIC0"),
1705 SND_SOC_DAPM_INPUT("TX SWR_DMIC1"),
1706 SND_SOC_DAPM_INPUT("TX SWR_DMIC2"),
1707 SND_SOC_DAPM_INPUT("TX SWR_DMIC3"),
1708 SND_SOC_DAPM_INPUT("TX SWR_DMIC4"),
1709 SND_SOC_DAPM_INPUT("TX SWR_DMIC5"),
1710 SND_SOC_DAPM_INPUT("TX SWR_DMIC6"),
1711 SND_SOC_DAPM_INPUT("TX SWR_DMIC7"),
1712 };
1713
1714 static const struct snd_soc_dapm_route tx_audio_map_v9[] = {
1715 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1716 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1717 {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"},
1718 {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"},
1719 {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"},
1720 {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"},
1721 {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"},
1722 {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"},
1723 {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"},
1724 {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"},
1725 {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"},
1726 {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"},
1727 {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"},
1728 {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"},
1729
1730 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1731 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1732 {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"},
1733 {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"},
1734 {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"},
1735 {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"},
1736 {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"},
1737 {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"},
1738 {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"},
1739 {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"},
1740 {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"},
1741 {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"},
1742 {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"},
1743 {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"},
1744
1745 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1746 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1747 {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"},
1748 {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"},
1749 {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"},
1750 {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"},
1751 {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"},
1752 {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"},
1753 {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"},
1754 {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"},
1755 {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"},
1756 {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"},
1757 {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"},
1758 {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"},
1759
1760 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1761 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1762 {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"},
1763 {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"},
1764 {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"},
1765 {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"},
1766 {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"},
1767 {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"},
1768 {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"},
1769 {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"},
1770 {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"},
1771 {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"},
1772 {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"},
1773 {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"},
1774
1775 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1776 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1777 {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"},
1778 {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"},
1779 {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"},
1780 {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"},
1781 {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"},
1782 {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"},
1783 {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"},
1784 {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"},
1785 {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"},
1786 {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"},
1787 {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"},
1788 {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"},
1789
1790 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1791 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1792 {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"},
1793 {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"},
1794 {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"},
1795 {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"},
1796 {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"},
1797 {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"},
1798 {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"},
1799 {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"},
1800 {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"},
1801 {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"},
1802 {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"},
1803 {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"},
1804
1805 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
1806 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
1807 {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"},
1808 {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"},
1809 {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"},
1810 {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"},
1811 {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"},
1812 {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"},
1813 {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"},
1814 {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"},
1815 {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"},
1816 {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"},
1817 {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"},
1818 {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"},
1819
1820 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
1821 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
1822 {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"},
1823 {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"},
1824 {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"},
1825 {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"},
1826 {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"},
1827 {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"},
1828 {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"},
1829 {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"},
1830 {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"},
1831 {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"},
1832 {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"},
1833 {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"},
1834 };
1835
1836 /* Controls and routes specific to LPASS >= v9.2.0 */
1837 static const char * const smic_mux_text_v9_2[] = {
1838 "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3",
1839 "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7",
1840 "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11"
1841 };
1842
1843 static SOC_ENUM_SINGLE_DECL(tx_smic0_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX0_CFG0,
1844 0, smic_mux_text_v9_2);
1845
1846 static SOC_ENUM_SINGLE_DECL(tx_smic1_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX1_CFG0,
1847 0, smic_mux_text_v9_2);
1848
1849 static SOC_ENUM_SINGLE_DECL(tx_smic2_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX2_CFG0,
1850 0, smic_mux_text_v9_2);
1851
1852 static SOC_ENUM_SINGLE_DECL(tx_smic3_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX3_CFG0,
1853 0, smic_mux_text_v9_2);
1854
1855 static SOC_ENUM_SINGLE_DECL(tx_smic4_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX4_CFG0,
1856 0, smic_mux_text_v9_2);
1857
1858 static SOC_ENUM_SINGLE_DECL(tx_smic5_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX5_CFG0,
1859 0, smic_mux_text_v9_2);
1860
1861 static SOC_ENUM_SINGLE_DECL(tx_smic6_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX6_CFG0,
1862 0, smic_mux_text_v9_2);
1863
1864 static SOC_ENUM_SINGLE_DECL(tx_smic7_enum_v9_2, CDC_TX_INP_MUX_ADC_MUX7_CFG0,
1865 0, smic_mux_text_v9_2);
1866
1867 static const struct snd_kcontrol_new tx_smic0_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic0", tx_smic0_enum_v9_2,
1868 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1869 static const struct snd_kcontrol_new tx_smic1_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic1", tx_smic1_enum_v9_2,
1870 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1871 static const struct snd_kcontrol_new tx_smic2_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic2", tx_smic2_enum_v9_2,
1872 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1873 static const struct snd_kcontrol_new tx_smic3_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic3", tx_smic3_enum_v9_2,
1874 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1875 static const struct snd_kcontrol_new tx_smic4_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic4", tx_smic4_enum_v9_2,
1876 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1877 static const struct snd_kcontrol_new tx_smic5_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic5", tx_smic5_enum_v9_2,
1878 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1879 static const struct snd_kcontrol_new tx_smic6_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic6", tx_smic6_enum_v9_2,
1880 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1881 static const struct snd_kcontrol_new tx_smic7_mux_v9_2 = SOC_DAPM_ENUM_EXT("tx_smic7", tx_smic7_enum_v9_2,
1882 snd_soc_dapm_get_enum_double, tx_macro_put_dec_enum);
1883
1884 static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v9_2[] = {
1885 SND_SOC_DAPM_MUX("TX SMIC MUX0", SND_SOC_NOPM, 0, 0, &tx_smic0_mux_v9_2),
1886 SND_SOC_DAPM_MUX("TX SMIC MUX1", SND_SOC_NOPM, 0, 0, &tx_smic1_mux_v9_2),
1887 SND_SOC_DAPM_MUX("TX SMIC MUX2", SND_SOC_NOPM, 0, 0, &tx_smic2_mux_v9_2),
1888 SND_SOC_DAPM_MUX("TX SMIC MUX3", SND_SOC_NOPM, 0, 0, &tx_smic3_mux_v9_2),
1889 SND_SOC_DAPM_MUX("TX SMIC MUX4", SND_SOC_NOPM, 0, 0, &tx_smic4_mux_v9_2),
1890 SND_SOC_DAPM_MUX("TX SMIC MUX5", SND_SOC_NOPM, 0, 0, &tx_smic5_mux_v9_2),
1891 SND_SOC_DAPM_MUX("TX SMIC MUX6", SND_SOC_NOPM, 0, 0, &tx_smic6_mux_v9_2),
1892 SND_SOC_DAPM_MUX("TX SMIC MUX7", SND_SOC_NOPM, 0, 0, &tx_smic7_mux_v9_2),
1893
1894 SND_SOC_DAPM_INPUT("TX SWR_INPUT0"),
1895 SND_SOC_DAPM_INPUT("TX SWR_INPUT1"),
1896 SND_SOC_DAPM_INPUT("TX SWR_INPUT2"),
1897 SND_SOC_DAPM_INPUT("TX SWR_INPUT3"),
1898 SND_SOC_DAPM_INPUT("TX SWR_INPUT4"),
1899 SND_SOC_DAPM_INPUT("TX SWR_INPUT5"),
1900 SND_SOC_DAPM_INPUT("TX SWR_INPUT6"),
1901 SND_SOC_DAPM_INPUT("TX SWR_INPUT7"),
1902 SND_SOC_DAPM_INPUT("TX SWR_INPUT8"),
1903 SND_SOC_DAPM_INPUT("TX SWR_INPUT9"),
1904 SND_SOC_DAPM_INPUT("TX SWR_INPUT10"),
1905 SND_SOC_DAPM_INPUT("TX SWR_INPUT11"),
1906 };
1907
1908 static const struct snd_soc_dapm_route tx_audio_map_v9_2[] = {
1909 {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"},
1910 {"TX SMIC MUX0", NULL, "TX_SWR_CLK"},
1911 {"TX SMIC MUX0", "SWR_MIC0", "TX SWR_INPUT0"},
1912 {"TX SMIC MUX0", "SWR_MIC1", "TX SWR_INPUT1"},
1913 {"TX SMIC MUX0", "SWR_MIC2", "TX SWR_INPUT2"},
1914 {"TX SMIC MUX0", "SWR_MIC3", "TX SWR_INPUT3"},
1915 {"TX SMIC MUX0", "SWR_MIC4", "TX SWR_INPUT4"},
1916 {"TX SMIC MUX0", "SWR_MIC5", "TX SWR_INPUT5"},
1917 {"TX SMIC MUX0", "SWR_MIC6", "TX SWR_INPUT6"},
1918 {"TX SMIC MUX0", "SWR_MIC7", "TX SWR_INPUT7"},
1919 {"TX SMIC MUX0", "SWR_MIC8", "TX SWR_INPUT8"},
1920 {"TX SMIC MUX0", "SWR_MIC9", "TX SWR_INPUT9"},
1921 {"TX SMIC MUX0", "SWR_MIC10", "TX SWR_INPUT11"},
1922 {"TX SMIC MUX0", "SWR_MIC11", "TX SWR_INPUT10"},
1923
1924 {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"},
1925 {"TX SMIC MUX1", NULL, "TX_SWR_CLK"},
1926 {"TX SMIC MUX1", "SWR_MIC0", "TX SWR_INPUT0"},
1927 {"TX SMIC MUX1", "SWR_MIC1", "TX SWR_INPUT1"},
1928 {"TX SMIC MUX1", "SWR_MIC2", "TX SWR_INPUT2"},
1929 {"TX SMIC MUX1", "SWR_MIC3", "TX SWR_INPUT3"},
1930 {"TX SMIC MUX1", "SWR_MIC4", "TX SWR_INPUT4"},
1931 {"TX SMIC MUX1", "SWR_MIC5", "TX SWR_INPUT5"},
1932 {"TX SMIC MUX1", "SWR_MIC6", "TX SWR_INPUT6"},
1933 {"TX SMIC MUX1", "SWR_MIC7", "TX SWR_INPUT7"},
1934 {"TX SMIC MUX1", "SWR_MIC8", "TX SWR_INPUT8"},
1935 {"TX SMIC MUX1", "SWR_MIC9", "TX SWR_INPUT9"},
1936 {"TX SMIC MUX1", "SWR_MIC10", "TX SWR_INPUT10"},
1937 {"TX SMIC MUX1", "SWR_MIC11", "TX SWR_INPUT11"},
1938
1939 {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"},
1940 {"TX SMIC MUX2", NULL, "TX_SWR_CLK"},
1941 {"TX SMIC MUX2", "SWR_MIC0", "TX SWR_INPUT0"},
1942 {"TX SMIC MUX2", "SWR_MIC1", "TX SWR_INPUT1"},
1943 {"TX SMIC MUX2", "SWR_MIC2", "TX SWR_INPUT2"},
1944 {"TX SMIC MUX2", "SWR_MIC3", "TX SWR_INPUT3"},
1945 {"TX SMIC MUX2", "SWR_MIC4", "TX SWR_INPUT4"},
1946 {"TX SMIC MUX2", "SWR_MIC5", "TX SWR_INPUT5"},
1947 {"TX SMIC MUX2", "SWR_MIC6", "TX SWR_INPUT6"},
1948 {"TX SMIC MUX2", "SWR_MIC7", "TX SWR_INPUT7"},
1949 {"TX SMIC MUX2", "SWR_MIC8", "TX SWR_INPUT8"},
1950 {"TX SMIC MUX2", "SWR_MIC9", "TX SWR_INPUT9"},
1951 {"TX SMIC MUX2", "SWR_MIC10", "TX SWR_INPUT10"},
1952 {"TX SMIC MUX2", "SWR_MIC11", "TX SWR_INPUT11"},
1953
1954 {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"},
1955 {"TX SMIC MUX3", NULL, "TX_SWR_CLK"},
1956 {"TX SMIC MUX3", "SWR_MIC0", "TX SWR_INPUT0"},
1957 {"TX SMIC MUX3", "SWR_MIC1", "TX SWR_INPUT1"},
1958 {"TX SMIC MUX3", "SWR_MIC2", "TX SWR_INPUT2"},
1959 {"TX SMIC MUX3", "SWR_MIC3", "TX SWR_INPUT3"},
1960 {"TX SMIC MUX3", "SWR_MIC4", "TX SWR_INPUT4"},
1961 {"TX SMIC MUX3", "SWR_MIC5", "TX SWR_INPUT5"},
1962 {"TX SMIC MUX3", "SWR_MIC6", "TX SWR_INPUT6"},
1963 {"TX SMIC MUX3", "SWR_MIC7", "TX SWR_INPUT7"},
1964 {"TX SMIC MUX3", "SWR_MIC8", "TX SWR_INPUT8"},
1965 {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_INPUT9"},
1966 {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_INPUT10"},
1967 {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_INPUT11"},
1968
1969 {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"},
1970 {"TX SMIC MUX4", NULL, "TX_SWR_CLK"},
1971 {"TX SMIC MUX4", "SWR_MIC0", "TX SWR_INPUT0"},
1972 {"TX SMIC MUX4", "SWR_MIC1", "TX SWR_INPUT1"},
1973 {"TX SMIC MUX4", "SWR_MIC2", "TX SWR_INPUT2"},
1974 {"TX SMIC MUX4", "SWR_MIC3", "TX SWR_INPUT3"},
1975 {"TX SMIC MUX4", "SWR_MIC4", "TX SWR_INPUT4"},
1976 {"TX SMIC MUX4", "SWR_MIC5", "TX SWR_INPUT5"},
1977 {"TX SMIC MUX4", "SWR_MIC6", "TX SWR_INPUT6"},
1978 {"TX SMIC MUX4", "SWR_MIC7", "TX SWR_INPUT7"},
1979 {"TX SMIC MUX4", "SWR_MIC8", "TX SWR_INPUT8"},
1980 {"TX SMIC MUX4", "SWR_MIC9", "TX SWR_INPUT9"},
1981 {"TX SMIC MUX4", "SWR_MIC10", "TX SWR_INPUT10"},
1982 {"TX SMIC MUX4", "SWR_MIC11", "TX SWR_INPUT11"},
1983
1984 {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"},
1985 {"TX SMIC MUX5", NULL, "TX_SWR_CLK"},
1986 {"TX SMIC MUX5", "SWR_MIC0", "TX SWR_INPUT0"},
1987 {"TX SMIC MUX5", "SWR_MIC1", "TX SWR_INPUT1"},
1988 {"TX SMIC MUX5", "SWR_MIC2", "TX SWR_INPUT2"},
1989 {"TX SMIC MUX5", "SWR_MIC3", "TX SWR_INPUT3"},
1990 {"TX SMIC MUX5", "SWR_MIC4", "TX SWR_INPUT4"},
1991 {"TX SMIC MUX5", "SWR_MIC5", "TX SWR_INPUT5"},
1992 {"TX SMIC MUX5", "SWR_MIC6", "TX SWR_INPUT6"},
1993 {"TX SMIC MUX5", "SWR_MIC7", "TX SWR_INPUT7"},
1994 {"TX SMIC MUX5", "SWR_MIC8", "TX SWR_INPUT8"},
1995 {"TX SMIC MUX5", "SWR_MIC9", "TX SWR_INPUT9"},
1996 {"TX SMIC MUX5", "SWR_MIC10", "TX SWR_INPUT10"},
1997 {"TX SMIC MUX5", "SWR_MIC11", "TX SWR_INPUT11"},
1998
1999 {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"},
2000 {"TX SMIC MUX6", NULL, "TX_SWR_CLK"},
2001 {"TX SMIC MUX6", "SWR_MIC0", "TX SWR_INPUT0"},
2002 {"TX SMIC MUX6", "SWR_MIC1", "TX SWR_INPUT1"},
2003 {"TX SMIC MUX6", "SWR_MIC2", "TX SWR_INPUT2"},
2004 {"TX SMIC MUX6", "SWR_MIC3", "TX SWR_INPUT3"},
2005 {"TX SMIC MUX6", "SWR_MIC4", "TX SWR_INPUT4"},
2006 {"TX SMIC MUX6", "SWR_MIC5", "TX SWR_INPUT5"},
2007 {"TX SMIC MUX6", "SWR_MIC6", "TX SWR_INPUT6"},
2008 {"TX SMIC MUX6", "SWR_MIC7", "TX SWR_INPUT7"},
2009 {"TX SMIC MUX6", "SWR_MIC8", "TX SWR_INPUT8"},
2010 {"TX SMIC MUX6", "SWR_MIC9", "TX SWR_INPUT9"},
2011 {"TX SMIC MUX6", "SWR_MIC10", "TX SWR_INPUT10"},
2012 {"TX SMIC MUX6", "SWR_MIC11", "TX SWR_INPUT11"},
2013
2014 {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"},
2015 {"TX SMIC MUX7", NULL, "TX_SWR_CLK"},
2016 {"TX SMIC MUX7", "SWR_MIC0", "TX SWR_INPUT0"},
2017 {"TX SMIC MUX7", "SWR_MIC1", "TX SWR_INPUT1"},
2018 {"TX SMIC MUX7", "SWR_MIC2", "TX SWR_INPUT2"},
2019 {"TX SMIC MUX7", "SWR_MIC3", "TX SWR_INPUT3"},
2020 {"TX SMIC MUX7", "SWR_MIC4", "TX SWR_INPUT4"},
2021 {"TX SMIC MUX7", "SWR_MIC5", "TX SWR_INPUT5"},
2022 {"TX SMIC MUX7", "SWR_MIC6", "TX SWR_INPUT6"},
2023 {"TX SMIC MUX7", "SWR_MIC7", "TX SWR_INPUT7"},
2024 {"TX SMIC MUX7", "SWR_MIC8", "TX SWR_INPUT8"},
2025 {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_INPUT9"},
2026 {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_INPUT10"},
2027 {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_INPUT11"},
2028 };
2029
2030 static const struct snd_kcontrol_new tx_macro_snd_controls[] = {
2031 SOC_SINGLE_S8_TLV("TX_DEC0 Volume",
2032 CDC_TX0_TX_VOL_CTL,
2033 -84, 40, digital_gain),
2034 SOC_SINGLE_S8_TLV("TX_DEC1 Volume",
2035 CDC_TX1_TX_VOL_CTL,
2036 -84, 40, digital_gain),
2037 SOC_SINGLE_S8_TLV("TX_DEC2 Volume",
2038 CDC_TX2_TX_VOL_CTL,
2039 -84, 40, digital_gain),
2040 SOC_SINGLE_S8_TLV("TX_DEC3 Volume",
2041 CDC_TX3_TX_VOL_CTL,
2042 -84, 40, digital_gain),
2043 SOC_SINGLE_S8_TLV("TX_DEC4 Volume",
2044 CDC_TX4_TX_VOL_CTL,
2045 -84, 40, digital_gain),
2046 SOC_SINGLE_S8_TLV("TX_DEC5 Volume",
2047 CDC_TX5_TX_VOL_CTL,
2048 -84, 40, digital_gain),
2049 SOC_SINGLE_S8_TLV("TX_DEC6 Volume",
2050 CDC_TX6_TX_VOL_CTL,
2051 -84, 40, digital_gain),
2052 SOC_SINGLE_S8_TLV("TX_DEC7 Volume",
2053 CDC_TX7_TX_VOL_CTL,
2054 -84, 40, digital_gain),
2055
2056 SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum[0],
2057 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2058
2059 SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum[1],
2060 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2061
2062 SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum[2],
2063 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2064
2065 SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum[3],
2066 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2067
2068 SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum[4],
2069 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2070
2071 SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum[5],
2072 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2073
2074 SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum[6],
2075 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2076
2077 SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum[7],
2078 tx_macro_dec_mode_get, tx_macro_dec_mode_put),
2079
2080 SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0,
2081 tx_macro_get_bcs, tx_macro_set_bcs),
2082 };
2083
tx_macro_component_extend(struct snd_soc_component * comp)2084 static int tx_macro_component_extend(struct snd_soc_component *comp)
2085 {
2086 struct snd_soc_dapm_context *dapm = snd_soc_component_to_dapm(comp);
2087 struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
2088 int ret;
2089
2090 if (tx->data->extra_widgets_num) {
2091 ret = snd_soc_dapm_new_controls(dapm, tx->data->extra_widgets,
2092 tx->data->extra_widgets_num);
2093 if (ret) {
2094 dev_err(tx->dev, "failed to add extra widgets: %d\n", ret);
2095 return ret;
2096 }
2097 }
2098
2099 if (tx->data->extra_routes_num) {
2100 ret = snd_soc_dapm_add_routes(dapm, tx->data->extra_routes,
2101 tx->data->extra_routes_num);
2102 if (ret) {
2103 dev_err(tx->dev, "failed to add extra routes: %d\n", ret);
2104 return ret;
2105 }
2106 }
2107
2108 return 0;
2109 }
2110
tx_macro_component_probe(struct snd_soc_component * comp)2111 static int tx_macro_component_probe(struct snd_soc_component *comp)
2112 {
2113 struct tx_macro *tx = snd_soc_component_get_drvdata(comp);
2114 int i, ret;
2115
2116 ret = tx_macro_component_extend(comp);
2117 if (ret)
2118 return ret;
2119
2120 snd_soc_component_init_regmap(comp, tx->regmap);
2121
2122 for (i = 0; i < NUM_DECIMATORS; i++) {
2123 tx->tx_hpf_work[i].tx = tx;
2124 tx->tx_hpf_work[i].decimator = i;
2125 INIT_DELAYED_WORK(&tx->tx_hpf_work[i].dwork,
2126 tx_macro_tx_hpf_corner_freq_callback);
2127 }
2128
2129 for (i = 0; i < NUM_DECIMATORS; i++) {
2130 tx->tx_mute_dwork[i].tx = tx;
2131 tx->tx_mute_dwork[i].decimator = i;
2132 INIT_DELAYED_WORK(&tx->tx_mute_dwork[i].dwork,
2133 tx_macro_mute_update_callback);
2134 }
2135 tx->component = comp;
2136
2137 snd_soc_component_update_bits(comp, CDC_TX0_TX_PATH_SEC7, 0x3F,
2138 0x0A);
2139 /* Enable swr mic0 and mic1 clock */
2140 snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC0_CTL,
2141 CDC_TX_SWR_MIC_CLK_DEFAULT);
2142 snd_soc_component_write(comp, CDC_TX_TOP_CSR_SWR_AMIC1_CTL,
2143 CDC_TX_SWR_MIC_CLK_DEFAULT);
2144
2145 return 0;
2146 }
2147
swclk_gate_enable(struct clk_hw * hw)2148 static int swclk_gate_enable(struct clk_hw *hw)
2149 {
2150 struct tx_macro *tx = to_tx_macro(hw);
2151 struct regmap *regmap = tx->regmap;
2152 int ret;
2153
2154 ret = pm_runtime_resume_and_get(tx->dev);
2155 if (ret < 0)
2156 return ret;
2157
2158 ret = tx_macro_mclk_enable(tx, true);
2159 if (ret) {
2160 pm_runtime_put_autosuspend(tx->dev);
2161 return ret;
2162 }
2163
2164 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2165 CDC_TX_SWR_CLK_EN_MASK,
2166 CDC_TX_SWR_CLK_ENABLE);
2167
2168 return 0;
2169 }
2170
swclk_gate_disable(struct clk_hw * hw)2171 static void swclk_gate_disable(struct clk_hw *hw)
2172 {
2173 struct tx_macro *tx = to_tx_macro(hw);
2174 struct regmap *regmap = tx->regmap;
2175
2176 regmap_update_bits(regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2177 CDC_TX_SWR_CLK_EN_MASK, 0x0);
2178
2179 tx_macro_mclk_enable(tx, false);
2180 pm_runtime_put_autosuspend(tx->dev);
2181 }
2182
swclk_gate_is_enabled(struct clk_hw * hw)2183 static int swclk_gate_is_enabled(struct clk_hw *hw)
2184 {
2185 struct tx_macro *tx = to_tx_macro(hw);
2186 int ret, val;
2187
2188 regmap_read(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL, &val);
2189 ret = val & BIT(0);
2190
2191 return ret;
2192 }
2193
swclk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)2194 static unsigned long swclk_recalc_rate(struct clk_hw *hw,
2195 unsigned long parent_rate)
2196 {
2197 return parent_rate / 2;
2198 }
2199
2200 static const struct clk_ops swclk_gate_ops = {
2201 .prepare = swclk_gate_enable,
2202 .unprepare = swclk_gate_disable,
2203 .is_enabled = swclk_gate_is_enabled,
2204 .recalc_rate = swclk_recalc_rate,
2205
2206 };
2207
tx_macro_register_mclk_output(struct tx_macro * tx)2208 static int tx_macro_register_mclk_output(struct tx_macro *tx)
2209 {
2210 struct device *dev = tx->dev;
2211 const char *parent_clk_name = NULL;
2212 const char *clk_name = "lpass-tx-mclk";
2213 struct clk_hw *hw;
2214 struct clk_init_data init;
2215 int ret;
2216
2217 if (tx->npl)
2218 parent_clk_name = __clk_get_name(tx->npl);
2219 else
2220 parent_clk_name = __clk_get_name(tx->mclk);
2221
2222 init.name = clk_name;
2223 init.ops = &swclk_gate_ops;
2224 init.flags = 0;
2225 init.parent_names = &parent_clk_name;
2226 init.num_parents = 1;
2227 tx->hw.init = &init;
2228 hw = &tx->hw;
2229 ret = devm_clk_hw_register(dev, hw);
2230 if (ret)
2231 return ret;
2232
2233 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
2234 }
2235
2236 static const struct snd_soc_component_driver tx_macro_component_drv = {
2237 .name = "TX-MACRO",
2238 .probe = tx_macro_component_probe,
2239 .controls = tx_macro_snd_controls,
2240 .num_controls = ARRAY_SIZE(tx_macro_snd_controls),
2241 .dapm_widgets = tx_macro_dapm_widgets,
2242 .num_dapm_widgets = ARRAY_SIZE(tx_macro_dapm_widgets),
2243 .dapm_routes = tx_audio_map,
2244 .num_dapm_routes = ARRAY_SIZE(tx_audio_map),
2245 };
2246
tx_macro_probe(struct platform_device * pdev)2247 static int tx_macro_probe(struct platform_device *pdev)
2248 {
2249 struct device *dev = &pdev->dev;
2250 struct device_node *np = dev->of_node;
2251 struct tx_macro *tx;
2252 void __iomem *base;
2253 int ret, reg;
2254
2255 tx = devm_kzalloc(dev, sizeof(*tx), GFP_KERNEL);
2256 if (!tx)
2257 return -ENOMEM;
2258
2259 tx->data = device_get_match_data(dev);
2260
2261 tx->macro = devm_clk_get_optional(dev, "macro");
2262 if (IS_ERR(tx->macro))
2263 return dev_err_probe(dev, PTR_ERR(tx->macro), "unable to get macro clock\n");
2264
2265 tx->dcodec = devm_clk_get_optional(dev, "dcodec");
2266 if (IS_ERR(tx->dcodec))
2267 return dev_err_probe(dev, PTR_ERR(tx->dcodec), "unable to get dcodec clock\n");
2268
2269 tx->mclk = devm_clk_get(dev, "mclk");
2270 if (IS_ERR(tx->mclk))
2271 return dev_err_probe(dev, PTR_ERR(tx->mclk), "unable to get mclk clock\n");
2272
2273 if (tx->data->flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
2274 tx->npl = devm_clk_get(dev, "npl");
2275 if (IS_ERR(tx->npl))
2276 return dev_err_probe(dev, PTR_ERR(tx->npl), "unable to get npl clock\n");
2277 }
2278
2279 tx->fsgen = devm_clk_get(dev, "fsgen");
2280 if (IS_ERR(tx->fsgen))
2281 return dev_err_probe(dev, PTR_ERR(tx->fsgen), "unable to get fsgen clock\n");
2282
2283 tx->pds = lpass_macro_pds_init(dev);
2284 if (IS_ERR(tx->pds))
2285 return PTR_ERR(tx->pds);
2286
2287 base = devm_platform_ioremap_resource(pdev, 0);
2288 if (IS_ERR(base)) {
2289 ret = PTR_ERR(base);
2290 goto err;
2291 }
2292
2293 /* Update defaults for lpass sc7280 */
2294 if (of_device_is_compatible(np, "qcom,sc7280-lpass-tx-macro")) {
2295 for (reg = 0; reg < ARRAY_SIZE(tx_defaults); reg++) {
2296 switch (tx_defaults[reg].reg) {
2297 case CDC_TX_TOP_CSR_SWR_AMIC0_CTL:
2298 case CDC_TX_TOP_CSR_SWR_AMIC1_CTL:
2299 tx_defaults[reg].def = 0x0E;
2300 break;
2301 default:
2302 break;
2303 }
2304 }
2305 }
2306
2307 tx->regmap = devm_regmap_init_mmio(dev, base, &tx_regmap_config);
2308 if (IS_ERR(tx->regmap)) {
2309 ret = PTR_ERR(tx->regmap);
2310 goto err;
2311 }
2312
2313 dev_set_drvdata(dev, tx);
2314
2315 tx->dev = dev;
2316
2317 /* Set active_decimator default value */
2318 tx->active_decimator[TX_MACRO_AIF1_CAP] = -1;
2319 tx->active_decimator[TX_MACRO_AIF2_CAP] = -1;
2320 tx->active_decimator[TX_MACRO_AIF3_CAP] = -1;
2321
2322 /* set MCLK and NPL rates */
2323 ret = clk_set_rate(tx->mclk, MCLK_FREQ);
2324 if (ret)
2325 goto err;
2326
2327 ret = clk_set_rate(tx->npl, MCLK_FREQ);
2328 if (ret)
2329 goto err;
2330
2331 ret = devm_pm_clk_create(dev);
2332 if (ret)
2333 goto err;
2334
2335 ret = of_pm_clk_add_clks(dev);
2336 if (ret < 0)
2337 goto err;
2338
2339 pm_runtime_set_autosuspend_delay(dev, 100);
2340 pm_runtime_use_autosuspend(dev);
2341 ret = devm_pm_runtime_enable(dev);
2342 if (ret)
2343 goto err;
2344
2345 ret = pm_runtime_resume_and_get(dev);
2346 if (ret < 0)
2347 goto err;
2348
2349
2350 /* reset soundwire block */
2351 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR)
2352 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2353 CDC_TX_SWR_RESET_MASK, CDC_TX_SWR_RESET_ENABLE);
2354
2355 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2356 CDC_TX_SWR_CLK_EN_MASK,
2357 CDC_TX_SWR_CLK_ENABLE);
2358
2359 if (tx->data->flags & LPASS_MACRO_FLAG_RESET_SWR)
2360 regmap_update_bits(tx->regmap, CDC_TX_CLK_RST_CTRL_SWR_CONTROL,
2361 CDC_TX_SWR_RESET_MASK, 0x0);
2362
2363 ret = devm_snd_soc_register_component(dev, &tx_macro_component_drv,
2364 tx_macro_dai,
2365 ARRAY_SIZE(tx_macro_dai));
2366 if (ret)
2367 goto err_rpm_put;
2368
2369 ret = tx_macro_register_mclk_output(tx);
2370 if (ret)
2371 goto err_rpm_put;
2372
2373 ret = pm_runtime_put_autosuspend(dev);
2374 if (ret < 0)
2375 dev_warn(dev, "runtime PM put failed after probe: %d\n", ret);
2376
2377 return 0;
2378
2379 err_rpm_put:
2380 if (pm_runtime_put_sync_suspend(dev) < 0)
2381 dev_warn(dev, "runtime PM sync suspend failed in probe unwind\n");
2382 err:
2383 lpass_macro_pds_exit(tx->pds);
2384
2385 return ret;
2386 }
2387
tx_macro_remove(struct platform_device * pdev)2388 static void tx_macro_remove(struct platform_device *pdev)
2389 {
2390 struct tx_macro *tx = dev_get_drvdata(&pdev->dev);
2391
2392 lpass_macro_pds_exit(tx->pds);
2393 }
2394
tx_macro_runtime_suspend(struct device * dev)2395 static int tx_macro_runtime_suspend(struct device *dev)
2396 {
2397 struct tx_macro *tx = dev_get_drvdata(dev);
2398 int ret;
2399
2400 regcache_cache_only(tx->regmap, true);
2401
2402 ret = pm_clk_suspend(dev);
2403 if (ret) {
2404 regcache_cache_only(tx->regmap, false);
2405 return ret;
2406 }
2407
2408 regcache_mark_dirty(tx->regmap);
2409
2410 return 0;
2411 }
2412
tx_macro_runtime_resume(struct device * dev)2413 static int tx_macro_runtime_resume(struct device *dev)
2414 {
2415 struct tx_macro *tx = dev_get_drvdata(dev);
2416 int ret;
2417
2418 ret = pm_clk_resume(dev);
2419 if (ret) {
2420 regcache_cache_only(tx->regmap, true);
2421 regcache_mark_dirty(tx->regmap);
2422 return ret;
2423 }
2424
2425 regcache_cache_only(tx->regmap, false);
2426 ret = regcache_sync(tx->regmap);
2427 if (ret) {
2428 regcache_cache_only(tx->regmap, true);
2429 regcache_mark_dirty(tx->regmap);
2430 pm_clk_suspend(dev);
2431 return ret;
2432 }
2433
2434 return 0;
2435 }
2436
2437 static const struct dev_pm_ops tx_macro_pm_ops = {
2438 RUNTIME_PM_OPS(tx_macro_runtime_suspend, tx_macro_runtime_resume, NULL)
2439 };
2440
2441 static const struct tx_macro_data lpass_ver_9 = {
2442 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK |
2443 LPASS_MACRO_FLAG_RESET_SWR,
2444 .ver = LPASS_VER_9_0_0,
2445 .extra_widgets = tx_macro_dapm_widgets_v9,
2446 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9),
2447 .extra_routes = tx_audio_map_v9,
2448 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9),
2449 };
2450
2451 static const struct tx_macro_data lpass_ver_9_2 = {
2452 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK |
2453 LPASS_MACRO_FLAG_RESET_SWR,
2454 .ver = LPASS_VER_9_2_0,
2455 .extra_widgets = tx_macro_dapm_widgets_v9_2,
2456 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2),
2457 .extra_routes = tx_audio_map_v9_2,
2458 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2),
2459 };
2460
2461 static const struct tx_macro_data lpass_ver_10_sm6115 = {
2462 .flags = LPASS_MACRO_FLAG_HAS_NPL_CLOCK |
2463 LPASS_MACRO_FLAG_RESET_SWR,
2464 .ver = LPASS_VER_10_0_0,
2465 .extra_widgets = tx_macro_dapm_widgets_v9_2,
2466 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2),
2467 .extra_routes = tx_audio_map_v9_2,
2468 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2),
2469 };
2470
2471 static const struct tx_macro_data lpass_ver_11 = {
2472 .flags = LPASS_MACRO_FLAG_RESET_SWR,
2473 .ver = LPASS_VER_11_0_0,
2474 .extra_widgets = tx_macro_dapm_widgets_v9_2,
2475 .extra_widgets_num = ARRAY_SIZE(tx_macro_dapm_widgets_v9_2),
2476 .extra_routes = tx_audio_map_v9_2,
2477 .extra_routes_num = ARRAY_SIZE(tx_audio_map_v9_2),
2478 };
2479
2480 static const struct of_device_id tx_macro_dt_match[] = {
2481 {
2482 /*
2483 * The block is actually LPASS v9.4, but keep LPASS v9 match
2484 * data and audio widgets, due to compatibility reasons.
2485 * Microphones are working on SC7280 fine, so apparently the fix
2486 * is not necessary.
2487 */
2488 .compatible = "qcom,sc7280-lpass-tx-macro",
2489 .data = &lpass_ver_9,
2490 }, {
2491 .compatible = "qcom,sm6115-lpass-tx-macro",
2492 .data = &lpass_ver_10_sm6115,
2493 }, {
2494 .compatible = "qcom,sm8250-lpass-tx-macro",
2495 .data = &lpass_ver_9,
2496 }, {
2497 .compatible = "qcom,sm8450-lpass-tx-macro",
2498 .data = &lpass_ver_9_2,
2499 }, {
2500 .compatible = "qcom,sm8550-lpass-tx-macro",
2501 .data = &lpass_ver_11,
2502 }, {
2503 .compatible = "qcom,sc8280xp-lpass-tx-macro",
2504 /*
2505 * The block is actually LPASS v9.3, but keep LPASS v9 match
2506 * data and audio widgets, due to compatibility reasons.
2507 * Microphones are working on SC8280xp fine, so apparently the
2508 * fix is not necessary.
2509 */
2510 .data = &lpass_ver_9,
2511 },
2512 { }
2513 };
2514 MODULE_DEVICE_TABLE(of, tx_macro_dt_match);
2515 static struct platform_driver tx_macro_driver = {
2516 .driver = {
2517 .name = "tx_macro",
2518 .of_match_table = tx_macro_dt_match,
2519 .suppress_bind_attrs = true,
2520 .pm = pm_ptr(&tx_macro_pm_ops),
2521 },
2522 .probe = tx_macro_probe,
2523 .remove = tx_macro_remove,
2524 };
2525
2526 module_platform_driver(tx_macro_driver);
2527
2528 MODULE_DESCRIPTION("TX macro driver");
2529 MODULE_LICENSE("GPL");
2530