1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5 */
6
7 #include <linux/module.h>
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/clk.h>
11 #include <linux/delay.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/iopoll.h>
14 #include <linux/ioport.h>
15 #include <linux/irq.h>
16 #include <linux/of.h>
17 #include <linux/pinctrl/consumer.h>
18 #include <linux/platform_device.h>
19 #include <linux/pm.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pm_wakeirq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/slab.h>
24 #include <linux/spinlock.h>
25 #include <linux/interrupt.h>
26 #include <linux/reset.h>
27
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
35
36 #include "cqhci.h"
37 #include "mmc_hsq.h"
38
39 #define MAX_BD_NUM 1024
40 #define MSDC_NR_CLOCKS 3
41
42 /*--------------------------------------------------------------------------*/
43 /* Common Definition */
44 /*--------------------------------------------------------------------------*/
45 #define MSDC_BUS_1BITS 0x0
46 #define MSDC_BUS_4BITS 0x1
47 #define MSDC_BUS_8BITS 0x2
48
49 #define MSDC_BURST_64B 0x6
50
51 /*--------------------------------------------------------------------------*/
52 /* Register Offset */
53 /*--------------------------------------------------------------------------*/
54 #define MSDC_CFG 0x0
55 #define MSDC_IOCON 0x04
56 #define MSDC_PS 0x08
57 #define MSDC_INT 0x0c
58 #define MSDC_INTEN 0x10
59 #define MSDC_FIFOCS 0x14
60 #define SDC_CFG 0x30
61 #define SDC_CMD 0x34
62 #define SDC_ARG 0x38
63 #define SDC_STS 0x3c
64 #define SDC_RESP0 0x40
65 #define SDC_RESP1 0x44
66 #define SDC_RESP2 0x48
67 #define SDC_RESP3 0x4c
68 #define SDC_BLK_NUM 0x50
69 #define SDC_ADV_CFG0 0x64
70 #define MSDC_NEW_RX_CFG 0x68
71 #define EMMC_IOCON 0x7c
72 #define SDC_ACMD_RESP 0x80
73 #define DMA_SA_H4BIT 0x8c
74 #define MSDC_DMA_SA 0x90
75 #define MSDC_DMA_CTRL 0x98
76 #define MSDC_DMA_CFG 0x9c
77 #define MSDC_PATCH_BIT 0xb0
78 #define MSDC_PATCH_BIT1 0xb4
79 #define MSDC_PATCH_BIT2 0xb8
80 #define MSDC_PAD_TUNE 0xec
81 #define MSDC_PAD_TUNE0 0xf0
82 #define PAD_DS_TUNE 0x188
83 #define PAD_CMD_TUNE 0x18c
84 #define EMMC51_CFG0 0x204
85 #define EMMC50_CFG0 0x208
86 #define EMMC50_CFG1 0x20c
87 #define EMMC50_CFG2 0x21c
88 #define EMMC50_CFG3 0x220
89 #define SDC_FIFO_CFG 0x228
90 #define CQHCI_SETTING 0x7fc
91
92 /*--------------------------------------------------------------------------*/
93 /* Top Pad Register Offset */
94 /*--------------------------------------------------------------------------*/
95 #define EMMC_TOP_CONTROL 0x00
96 #define EMMC_TOP_CMD 0x04
97 #define EMMC50_PAD_DS_TUNE 0x0c
98 #define LOOP_TEST_CONTROL 0x30
99
100 /*--------------------------------------------------------------------------*/
101 /* Register Mask */
102 /*--------------------------------------------------------------------------*/
103
104 /* MSDC_CFG mask */
105 #define MSDC_CFG_MODE BIT(0) /* RW */
106 #define MSDC_CFG_CKPDN BIT(1) /* RW */
107 #define MSDC_CFG_RST BIT(2) /* RW */
108 #define MSDC_CFG_PIO BIT(3) /* RW */
109 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */
110 #define MSDC_CFG_BV18SDT BIT(5) /* RW */
111 #define MSDC_CFG_BV18PSS BIT(6) /* R */
112 #define MSDC_CFG_CKSTB BIT(7) /* R */
113 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */
114 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */
115 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */
116 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */
117 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */
118 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */
119
120 /* MSDC_IOCON mask */
121 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */
122 #define MSDC_IOCON_RSPL BIT(1) /* RW */
123 #define MSDC_IOCON_DSPL BIT(2) /* RW */
124 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */
125 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */
126 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */
127 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */
128 #define MSDC_IOCON_D0SPL BIT(16) /* RW */
129 #define MSDC_IOCON_D1SPL BIT(17) /* RW */
130 #define MSDC_IOCON_D2SPL BIT(18) /* RW */
131 #define MSDC_IOCON_D3SPL BIT(19) /* RW */
132 #define MSDC_IOCON_D4SPL BIT(20) /* RW */
133 #define MSDC_IOCON_D5SPL BIT(21) /* RW */
134 #define MSDC_IOCON_D6SPL BIT(22) /* RW */
135 #define MSDC_IOCON_D7SPL BIT(23) /* RW */
136 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */
137
138 /* MSDC_PS mask */
139 #define MSDC_PS_CDEN BIT(0) /* RW */
140 #define MSDC_PS_CDSTS BIT(1) /* R */
141 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */
142 #define MSDC_PS_DAT GENMASK(23, 16) /* R */
143 #define MSDC_PS_DATA1 BIT(17) /* R */
144 #define MSDC_PS_CMD BIT(24) /* R */
145 #define MSDC_PS_WP BIT(31) /* R */
146
147 /* MSDC_INT mask */
148 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */
149 #define MSDC_INT_CDSC BIT(1) /* W1C */
150 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */
151 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */
152 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */
153 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */
154 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */
155 #define MSDC_INT_CMDRDY BIT(8) /* W1C */
156 #define MSDC_INT_CMDTMO BIT(9) /* W1C */
157 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */
158 #define MSDC_INT_CSTA BIT(11) /* R */
159 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */
160 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */
161 #define MSDC_INT_DATTMO BIT(14) /* W1C */
162 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */
163 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */
164 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */
165 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */
166 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */
167 #define MSDC_INT_CMDQ BIT(28) /* W1C */
168
169 /* MSDC_INTEN mask */
170 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */
171 #define MSDC_INTEN_CDSC BIT(1) /* RW */
172 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */
173 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */
174 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */
175 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */
176 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */
177 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */
178 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */
179 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */
180 #define MSDC_INTEN_CSTA BIT(11) /* RW */
181 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */
182 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */
183 #define MSDC_INTEN_DATTMO BIT(14) /* RW */
184 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */
185 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */
186 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */
187 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */
188 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */
189
190 /* MSDC_FIFOCS mask */
191 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */
192 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */
193 #define MSDC_FIFOCS_CLR BIT(31) /* RW */
194
195 /* SDC_CFG mask */
196 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */
197 #define SDC_CFG_INSWKUP BIT(1) /* RW */
198 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */
199 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */
200 #define SDC_CFG_SDIO BIT(19) /* RW */
201 #define SDC_CFG_SDIOIDE BIT(20) /* RW */
202 #define SDC_CFG_INTATGAP BIT(21) /* RW */
203 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */
204
205 /* SDC_STS mask */
206 #define SDC_STS_SDCBUSY BIT(0) /* RW */
207 #define SDC_STS_CMDBUSY BIT(1) /* RW */
208 #define SDC_STS_SPM_RESOURCE_RELEASE BIT(3) /* RW */
209 #define SDC_STS_SWR_COMPL BIT(31) /* RW */
210
211 /* SDC_ADV_CFG0 mask */
212 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */
213 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */
214 #define SDC_NEW_TX_EN BIT(31) /* RW */
215
216 /* MSDC_NEW_RX_CFG mask */
217 #define MSDC_NEW_RX_PATH_SEL BIT(0) /* RW */
218
219 /* DMA_SA_H4BIT mask */
220 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */
221
222 /* MSDC_DMA_CTRL mask */
223 #define MSDC_DMA_CTRL_START BIT(0) /* W */
224 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */
225 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */
226 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */
227 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */
228 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */
229
230 /* MSDC_DMA_CFG mask */
231 #define MSDC_DMA_CFG_STS BIT(0) /* R */
232 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */
233 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */
234 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */
235 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */
236
237 /* MSDC_PATCH_BIT mask */
238 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */
239 #define MSDC_PATCH_BIT_DIS_WRMON BIT(2) /* RW */
240 #define MSDC_PATCH_BIT_RD_DAT_SEL BIT(3) /* RW */
241 #define MSDC_PATCH_BIT_DESCUP_SEL BIT(6) /* RW */
242 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
243 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10)
244 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */
245 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */
246 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */
247 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */
248 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */
249 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */
250 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */
251 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */
252 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */
253
254 /* MSDC_PATCH_BIT1 mask */
255 #define MSDC_PB1_WRDAT_CRC_TACNTR GENMASK(2, 0) /* RW */
256 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */
257 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */
258 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */
259 #define MSDC_PB1_DDR_CMD_FIX_SEL BIT(14) /* RW */
260 #define MSDC_PB1_SINGLE_BURST BIT(16) /* RW */
261 #define MSDC_PB1_RSVD20 GENMASK(18, 17) /* RW */
262 #define MSDC_PB1_AUTO_SYNCST_CLR BIT(19) /* RW */
263 #define MSDC_PB1_MARK_POP_WATER BIT(20) /* RW */
264 #define MSDC_PB1_LP_DCM_EN BIT(21) /* RW */
265 #define MSDC_PB1_RSVD3 BIT(22) /* RW */
266 #define MSDC_PB1_AHB_GDMA_HCLK BIT(23) /* RW */
267 #define MSDC_PB1_MSDC_CLK_ENFEAT GENMASK(31, 24) /* RW */
268
269 /* MSDC_PATCH_BIT2 mask */
270 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */
271 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */
272 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */
273 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */
274 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */
275 #define MSDC_PB2_POP_EN_CNT GENMASK(23, 20) /* RW */
276 #define MSDC_PB2_CFGCRCSTSEDGE BIT(25) /* RW */
277 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */
278
279 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */
280 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */
281 #define MSDC_PAD_TUNE_DATRRDLY2 GENMASK(12, 8) /* RW */
282 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */
283 #define MSDC_PAD_TUNE_CMDRDLY2 GENMASK(20, 16) /* RW */
284 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */
285 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */
286 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */
287 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */
288 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */
289 #define MSDC_PAD_TUNE_RD2_SEL BIT(13) /* RW */
290 #define MSDC_PAD_TUNE_CMD2_SEL BIT(21) /* RW */
291
292 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */
293 #define PAD_DS_TUNE_DLY2_SEL BIT(1) /* RW */
294 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */
295 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */
296 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */
297
298 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */
299
300 /* EMMC51_CFG0 mask */
301 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */
302
303 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */
304 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */
305 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */
306 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */
307
308 /* EMMC50_CFG1 mask */
309 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */
310
311 /* EMMC50_CFG2 mask */
312 #define EMMC50_CFG2_AXI_SET_LEN GENMASK(27, 24) /* RW */
313
314 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */
315
316 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */
317 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */
318
319 /* CQHCI_SETTING */
320 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */
321 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */
322
323 /* EMMC_TOP_CONTROL mask */
324 #define PAD_RXDLY_SEL BIT(0) /* RW */
325 #define DELAY_EN BIT(1) /* RW */
326 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */
327 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */
328 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */
329 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */
330 #define DATA_K_VALUE_SEL BIT(14) /* RW */
331 #define SDC_RX_ENH_EN BIT(15) /* TW */
332
333 /* EMMC_TOP_CMD mask */
334 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */
335 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */
336 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */
337 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */
338 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */
339
340 /* EMMC50_PAD_DS_TUNE mask */
341 #define PAD_DS_DLY_SEL BIT(16) /* RW */
342 #define PAD_DS_DLY2_SEL BIT(15) /* RW */
343 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */
344 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */
345
346 /* LOOP_TEST_CONTROL mask */
347 #define TEST_LOOP_DSCLK_MUX_SEL BIT(0) /* RW */
348 #define TEST_LOOP_LATCH_MUX_SEL BIT(1) /* RW */
349 #define LOOP_EN_SEL_CLK BIT(20) /* RW */
350 #define TEST_HS400_CMD_LOOP_MUX_SEL BIT(31) /* RW */
351
352 #define REQ_CMD_EIO BIT(0)
353 #define REQ_CMD_TMO BIT(1)
354 #define REQ_DAT_ERR BIT(2)
355 #define REQ_STOP_EIO BIT(3)
356 #define REQ_STOP_TMO BIT(4)
357 #define REQ_CMD_BUSY BIT(5)
358
359 #define MSDC_PREPARE_FLAG BIT(0)
360 #define MSDC_ASYNC_FLAG BIT(1)
361 #define MSDC_MMAP_FLAG BIT(2)
362
363 #define MTK_MMC_AUTOSUSPEND_DELAY 50
364 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */
365 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */
366
367 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */
368
369 #define TUNING_REG2_FIXED_OFFEST 4
370 #define PAD_DELAY_HALF 32 /* PAD delay cells */
371 #define PAD_DELAY_FULL 64
372 /*--------------------------------------------------------------------------*/
373 /* Descriptor Structure */
374 /*--------------------------------------------------------------------------*/
375 struct mt_gpdma_desc {
376 u32 gpd_info;
377 #define GPDMA_DESC_HWO BIT(0)
378 #define GPDMA_DESC_BDP BIT(1)
379 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8)
380 #define GPDMA_DESC_INT BIT(16)
381 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24)
382 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28)
383 u32 next;
384 u32 ptr;
385 u32 gpd_data_len;
386 #define GPDMA_DESC_BUFLEN GENMASK(15, 0)
387 #define GPDMA_DESC_EXTLEN GENMASK(23, 16)
388 u32 arg;
389 u32 blknum;
390 u32 cmd;
391 };
392
393 struct mt_bdma_desc {
394 u32 bd_info;
395 #define BDMA_DESC_EOL BIT(0)
396 #define BDMA_DESC_CHECKSUM GENMASK(15, 8)
397 #define BDMA_DESC_BLKPAD BIT(17)
398 #define BDMA_DESC_DWPAD BIT(18)
399 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24)
400 #define BDMA_DESC_PTR_H4 GENMASK(31, 28)
401 u32 next;
402 u32 ptr;
403 u32 bd_data_len;
404 #define BDMA_DESC_BUFLEN GENMASK(15, 0)
405 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0)
406 };
407
408 struct msdc_dma {
409 struct scatterlist *sg; /* I/O scatter list */
410 struct mt_gpdma_desc *gpd; /* pointer to gpd array */
411 struct mt_bdma_desc *bd; /* pointer to bd array */
412 dma_addr_t gpd_addr; /* the physical address of gpd array */
413 dma_addr_t bd_addr; /* the physical address of bd array */
414 };
415
416 struct msdc_save_para {
417 u32 msdc_cfg;
418 u32 iocon;
419 u32 sdc_cfg;
420 u32 pad_tune;
421 u32 patch_bit0;
422 u32 patch_bit1;
423 u32 patch_bit2;
424 u32 pad_ds_tune;
425 u32 pad_cmd_tune;
426 u32 emmc50_cfg0;
427 u32 emmc50_cfg3;
428 u32 sdc_fifo_cfg;
429 u32 emmc_top_control;
430 u32 emmc_top_cmd;
431 u32 emmc50_pad_ds_tune;
432 u32 loop_test_control;
433 };
434
435 struct mtk_mmc_compatible {
436 u8 clk_div_bits;
437 bool recheck_sdio_irq;
438 bool hs400_tune; /* only used for MT8173 */
439 bool needs_top_base;
440 u32 pad_tune_reg;
441 bool async_fifo;
442 bool data_tune;
443 bool busy_check;
444 bool stop_clk_fix;
445 u8 stop_dly_sel;
446 u8 pop_en_cnt;
447 bool enhance_rx;
448 bool support_64g;
449 bool use_internal_cd;
450 bool support_new_tx;
451 bool support_new_rx;
452 bool support_spm_res_release;
453 };
454
455 struct msdc_tune_para {
456 u32 iocon;
457 u32 pad_tune;
458 u32 pad_cmd_tune;
459 u32 emmc_top_control;
460 u32 emmc_top_cmd;
461 };
462
463 struct msdc_delay_phase {
464 u8 maxlen;
465 u8 start;
466 u8 final_phase;
467 };
468
469 struct msdc_host {
470 struct device *dev;
471 const struct mtk_mmc_compatible *dev_comp;
472 int cmd_rsp;
473
474 spinlock_t lock;
475 struct mmc_request *mrq;
476 struct mmc_command *cmd;
477 struct mmc_data *data;
478 int error;
479
480 void __iomem *base; /* host base address */
481 void __iomem *top_base; /* host top register base address */
482
483 struct msdc_dma dma; /* dma channel */
484 u64 dma_mask;
485
486 u32 timeout_ns; /* data timeout ns */
487 u32 timeout_clks; /* data timeout clks */
488
489 struct pinctrl *pinctrl;
490 struct pinctrl_state *pins_default;
491 struct pinctrl_state *pins_uhs;
492 struct pinctrl_state *pins_eint;
493 struct delayed_work req_timeout;
494 int irq; /* host interrupt */
495 int eint_irq; /* interrupt from sdio device for waking up system */
496 struct reset_control *reset;
497
498 struct clk *src_clk; /* msdc source clock */
499 struct clk *h_clk; /* msdc h_clk */
500 struct clk *bus_clk; /* bus clock which used to access register */
501 struct clk *src_clk_cg; /* msdc source clock control gate */
502 struct clk *sys_clk_cg; /* msdc subsys clock control gate */
503 struct clk *crypto_clk; /* msdc crypto clock control gate */
504 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
505 u32 mclk; /* mmc subsystem clock frequency */
506 u32 src_clk_freq; /* source clock frequency */
507 unsigned char timing;
508 bool vqmmc_enabled;
509 u32 latch_ck;
510 u32 hs400_ds_delay;
511 u32 hs400_ds_dly3;
512 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
513 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
514 u32 tuning_step;
515 bool hs400_cmd_resp_sel_rising;
516 /* cmd response sample selection for HS400 */
517 bool hs400_mode; /* current eMMC will run at hs400 mode */
518 bool hs400_tuning; /* hs400 mode online tuning */
519 bool internal_cd; /* Use internal card-detect logic */
520 bool cqhci; /* support eMMC hw cmdq */
521 bool hsq_en; /* Host Software Queue is enabled */
522 struct msdc_save_para save_para; /* used when gate HCLK */
523 struct msdc_tune_para def_tune_para; /* default tune setting */
524 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
525 struct cqhci_host *cq_host;
526 u32 cq_ssc1_time;
527 };
528
529 static const struct mtk_mmc_compatible mt2701_compat = {
530 .clk_div_bits = 12,
531 .recheck_sdio_irq = true,
532 .hs400_tune = false,
533 .pad_tune_reg = MSDC_PAD_TUNE0,
534 .async_fifo = true,
535 .data_tune = true,
536 .busy_check = false,
537 .stop_clk_fix = false,
538 .enhance_rx = false,
539 .support_64g = false,
540 };
541
542 static const struct mtk_mmc_compatible mt2712_compat = {
543 .clk_div_bits = 12,
544 .recheck_sdio_irq = false,
545 .hs400_tune = false,
546 .pad_tune_reg = MSDC_PAD_TUNE0,
547 .async_fifo = true,
548 .data_tune = true,
549 .busy_check = true,
550 .stop_clk_fix = true,
551 .stop_dly_sel = 3,
552 .enhance_rx = true,
553 .support_64g = true,
554 };
555
556 static const struct mtk_mmc_compatible mt6779_compat = {
557 .clk_div_bits = 12,
558 .recheck_sdio_irq = false,
559 .hs400_tune = false,
560 .pad_tune_reg = MSDC_PAD_TUNE0,
561 .async_fifo = true,
562 .data_tune = true,
563 .busy_check = true,
564 .stop_clk_fix = true,
565 .stop_dly_sel = 3,
566 .enhance_rx = true,
567 .support_64g = true,
568 };
569
570 static const struct mtk_mmc_compatible mt6795_compat = {
571 .clk_div_bits = 8,
572 .recheck_sdio_irq = false,
573 .hs400_tune = true,
574 .pad_tune_reg = MSDC_PAD_TUNE,
575 .async_fifo = false,
576 .data_tune = false,
577 .busy_check = false,
578 .stop_clk_fix = false,
579 .enhance_rx = false,
580 .support_64g = false,
581 };
582
583 static const struct mtk_mmc_compatible mt7620_compat = {
584 .clk_div_bits = 8,
585 .recheck_sdio_irq = true,
586 .hs400_tune = false,
587 .pad_tune_reg = MSDC_PAD_TUNE,
588 .async_fifo = false,
589 .data_tune = false,
590 .busy_check = false,
591 .stop_clk_fix = false,
592 .enhance_rx = false,
593 .use_internal_cd = true,
594 };
595
596 static const struct mtk_mmc_compatible mt7622_compat = {
597 .clk_div_bits = 12,
598 .recheck_sdio_irq = true,
599 .hs400_tune = false,
600 .pad_tune_reg = MSDC_PAD_TUNE0,
601 .async_fifo = true,
602 .data_tune = true,
603 .busy_check = true,
604 .stop_clk_fix = true,
605 .stop_dly_sel = 3,
606 .enhance_rx = true,
607 .support_64g = false,
608 };
609
610 static const struct mtk_mmc_compatible mt7986_compat = {
611 .clk_div_bits = 12,
612 .recheck_sdio_irq = true,
613 .hs400_tune = false,
614 .needs_top_base = true,
615 .pad_tune_reg = MSDC_PAD_TUNE0,
616 .async_fifo = true,
617 .data_tune = true,
618 .busy_check = true,
619 .stop_clk_fix = true,
620 .stop_dly_sel = 3,
621 .enhance_rx = true,
622 .support_64g = true,
623 };
624
625 static const struct mtk_mmc_compatible mt8135_compat = {
626 .clk_div_bits = 8,
627 .recheck_sdio_irq = true,
628 .hs400_tune = false,
629 .pad_tune_reg = MSDC_PAD_TUNE,
630 .async_fifo = false,
631 .data_tune = false,
632 .busy_check = false,
633 .stop_clk_fix = false,
634 .enhance_rx = false,
635 .support_64g = false,
636 };
637
638 static const struct mtk_mmc_compatible mt8173_compat = {
639 .clk_div_bits = 8,
640 .recheck_sdio_irq = true,
641 .hs400_tune = true,
642 .pad_tune_reg = MSDC_PAD_TUNE,
643 .async_fifo = false,
644 .data_tune = false,
645 .busy_check = false,
646 .stop_clk_fix = false,
647 .enhance_rx = false,
648 .support_64g = false,
649 };
650
651 static const struct mtk_mmc_compatible mt8183_compat = {
652 .clk_div_bits = 12,
653 .recheck_sdio_irq = false,
654 .hs400_tune = false,
655 .needs_top_base = true,
656 .pad_tune_reg = MSDC_PAD_TUNE0,
657 .async_fifo = true,
658 .data_tune = true,
659 .busy_check = true,
660 .stop_clk_fix = true,
661 .stop_dly_sel = 3,
662 .enhance_rx = true,
663 .support_64g = true,
664 };
665
666 static const struct mtk_mmc_compatible mt8516_compat = {
667 .clk_div_bits = 12,
668 .recheck_sdio_irq = true,
669 .hs400_tune = false,
670 .pad_tune_reg = MSDC_PAD_TUNE0,
671 .async_fifo = true,
672 .data_tune = true,
673 .busy_check = true,
674 .stop_clk_fix = true,
675 .stop_dly_sel = 3,
676 };
677
678 static const struct mtk_mmc_compatible mt8189_compat = {
679 .clk_div_bits = 12,
680 .recheck_sdio_irq = false,
681 .hs400_tune = false,
682 .needs_top_base = true,
683 .pad_tune_reg = MSDC_PAD_TUNE0,
684 .async_fifo = true,
685 .data_tune = false,
686 .busy_check = true,
687 .stop_clk_fix = true,
688 .stop_dly_sel = 3,
689 .pop_en_cnt = 8,
690 .enhance_rx = true,
691 .support_64g = true,
692 .support_new_tx = false,
693 .support_new_rx = false,
694 .support_spm_res_release = true,
695 };
696
697 static const struct mtk_mmc_compatible mt8196_compat = {
698 .clk_div_bits = 12,
699 .recheck_sdio_irq = false,
700 .hs400_tune = false,
701 .needs_top_base = true,
702 .pad_tune_reg = MSDC_PAD_TUNE0,
703 .async_fifo = true,
704 .data_tune = true,
705 .busy_check = true,
706 .stop_clk_fix = true,
707 .stop_dly_sel = 1,
708 .pop_en_cnt = 2,
709 .enhance_rx = true,
710 .support_64g = true,
711 .support_new_tx = true,
712 .support_new_rx = true,
713 };
714
715 static const struct of_device_id msdc_of_ids[] = {
716 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
717 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
718 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
719 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
720 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
721 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
722 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
723 { .compatible = "mediatek,mt7988-mmc", .data = &mt7986_compat},
724 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
725 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
726 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
727 { .compatible = "mediatek,mt8189-mmc", .data = &mt8189_compat},
728 { .compatible = "mediatek,mt8196-mmc", .data = &mt8196_compat},
729 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
730
731 {}
732 };
733 MODULE_DEVICE_TABLE(of, msdc_of_ids);
734
sdr_set_bits(void __iomem * reg,u32 bs)735 static void sdr_set_bits(void __iomem *reg, u32 bs)
736 {
737 u32 val = readl(reg);
738
739 val |= bs;
740 writel(val, reg);
741 }
742
sdr_clr_bits(void __iomem * reg,u32 bs)743 static void sdr_clr_bits(void __iomem *reg, u32 bs)
744 {
745 u32 val = readl(reg);
746
747 val &= ~bs;
748 writel(val, reg);
749 }
750
sdr_set_field(void __iomem * reg,u32 field,u32 val)751 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
752 {
753 unsigned int tv = readl(reg);
754
755 tv &= ~field;
756 tv |= ((val) << (ffs((unsigned int)field) - 1));
757 writel(tv, reg);
758 }
759
sdr_get_field(void __iomem * reg,u32 field,u32 * val)760 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
761 {
762 unsigned int tv = readl(reg);
763
764 *val = ((tv & field) >> (ffs((unsigned int)field) - 1));
765 }
766
msdc_reset_hw(struct msdc_host * host)767 static void msdc_reset_hw(struct msdc_host *host)
768 {
769 u32 val;
770
771 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
772 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
773
774 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
775 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
776 !(val & MSDC_FIFOCS_CLR), 0, 0);
777
778 val = readl(host->base + MSDC_INT);
779 writel(val, host->base + MSDC_INT);
780 }
781
782 static void msdc_cmd_next(struct msdc_host *host,
783 struct mmc_request *mrq, struct mmc_command *cmd);
784 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
785
786 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
787 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
788 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
789 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
790 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
791 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
792
msdc_dma_calcs(u8 * buf,u32 len)793 static u8 msdc_dma_calcs(u8 *buf, u32 len)
794 {
795 u32 i, sum = 0;
796
797 for (i = 0; i < len; i++)
798 sum += buf[i];
799 return 0xff - (u8) sum;
800 }
801
msdc_dma_setup(struct msdc_host * host,struct msdc_dma * dma,struct mmc_data * data)802 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
803 struct mmc_data *data)
804 {
805 unsigned int j, dma_len;
806 dma_addr_t dma_address;
807 u32 dma_ctrl;
808 struct scatterlist *sg;
809 struct mt_gpdma_desc *gpd;
810 struct mt_bdma_desc *bd;
811
812 sg = data->sg;
813
814 gpd = dma->gpd;
815 bd = dma->bd;
816
817 /* modify gpd */
818 gpd->gpd_info |= GPDMA_DESC_HWO;
819 gpd->gpd_info |= GPDMA_DESC_BDP;
820 /* need to clear first. use these bits to calc checksum */
821 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
822 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
823
824 /* modify bd */
825 for_each_sg(data->sg, sg, data->sg_count, j) {
826 dma_address = sg_dma_address(sg);
827 dma_len = sg_dma_len(sg);
828
829 /* init bd */
830 bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
831 bd[j].bd_info &= ~BDMA_DESC_DWPAD;
832 bd[j].ptr = lower_32_bits(dma_address);
833 if (host->dev_comp->support_64g) {
834 bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
835 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
836 << 28;
837 }
838
839 if (host->dev_comp->support_64g) {
840 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
841 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
842 } else {
843 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
844 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
845 }
846
847 if (j == data->sg_count - 1) /* the last bd */
848 bd[j].bd_info |= BDMA_DESC_EOL;
849 else
850 bd[j].bd_info &= ~BDMA_DESC_EOL;
851
852 /* checksum need to clear first */
853 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
854 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
855 }
856
857 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
858 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
859 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
860 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
861 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
862 if (host->dev_comp->support_64g)
863 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
864 upper_32_bits(dma->gpd_addr) & 0xf);
865 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
866 }
867
msdc_prepare_data(struct msdc_host * host,struct mmc_data * data)868 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
869 {
870 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
871 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
872 mmc_get_dma_dir(data));
873 if (data->sg_count)
874 data->host_cookie |= MSDC_PREPARE_FLAG;
875 }
876 }
877
msdc_data_prepared(struct mmc_data * data)878 static bool msdc_data_prepared(struct mmc_data *data)
879 {
880 return data->host_cookie & MSDC_PREPARE_FLAG;
881 }
882
msdc_unprepare_data(struct msdc_host * host,struct mmc_data * data)883 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
884 {
885 if (data->host_cookie & MSDC_ASYNC_FLAG)
886 return;
887
888 if (data->host_cookie & MSDC_PREPARE_FLAG) {
889 dma_unmap_sg(host->dev, data->sg, data->sg_len,
890 mmc_get_dma_dir(data));
891 data->host_cookie &= ~MSDC_PREPARE_FLAG;
892 }
893 }
894
msdc_timeout_cal(struct msdc_host * host,u64 ns,u64 clks)895 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
896 {
897 struct mmc_host *mmc = mmc_from_priv(host);
898 u64 timeout;
899 u32 clk_ns, mode = 0;
900
901 if (mmc->actual_clock == 0) {
902 timeout = 0;
903 } else {
904 clk_ns = 1000000000U / mmc->actual_clock;
905 timeout = ns + clk_ns - 1;
906 do_div(timeout, clk_ns);
907 timeout += clks;
908 /* in 1048576 sclk cycle unit */
909 timeout = DIV_ROUND_UP(timeout, BIT(20));
910 if (host->dev_comp->clk_div_bits == 8)
911 sdr_get_field(host->base + MSDC_CFG,
912 MSDC_CFG_CKMOD, &mode);
913 else
914 sdr_get_field(host->base + MSDC_CFG,
915 MSDC_CFG_CKMOD_EXTRA, &mode);
916 /*DDR mode will double the clk cycles for data timeout */
917 timeout = mode >= 2 ? timeout * 2 : timeout;
918 timeout = timeout > 1 ? timeout - 1 : 0;
919 }
920 return timeout;
921 }
922
923 /* clock control primitives */
msdc_set_timeout(struct msdc_host * host,u64 ns,u64 clks)924 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
925 {
926 u64 timeout;
927
928 host->timeout_ns = ns;
929 host->timeout_clks = clks;
930
931 timeout = msdc_timeout_cal(host, ns, clks);
932 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
933 min_t(u32, timeout, 255));
934 }
935
msdc_set_busy_timeout(struct msdc_host * host,u64 ns,u64 clks)936 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
937 {
938 u64 timeout;
939
940 timeout = msdc_timeout_cal(host, ns, clks);
941 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
942 min_t(u32, timeout, 8191));
943 }
944
msdc_gate_clock(struct msdc_host * host)945 static void msdc_gate_clock(struct msdc_host *host)
946 {
947 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
948 clk_disable_unprepare(host->crypto_clk);
949 clk_disable_unprepare(host->src_clk_cg);
950 clk_disable_unprepare(host->src_clk);
951 clk_disable_unprepare(host->bus_clk);
952 clk_disable_unprepare(host->h_clk);
953 }
954
msdc_ungate_clock(struct msdc_host * host)955 static int msdc_ungate_clock(struct msdc_host *host)
956 {
957 u32 val;
958 int ret;
959
960 clk_prepare_enable(host->h_clk);
961 clk_prepare_enable(host->bus_clk);
962 clk_prepare_enable(host->src_clk);
963 clk_prepare_enable(host->src_clk_cg);
964 clk_prepare_enable(host->crypto_clk);
965 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
966 if (ret) {
967 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
968 return ret;
969 }
970
971 return readl_poll_timeout(host->base + MSDC_CFG, val,
972 (val & MSDC_CFG_CKSTB), 1, 20000);
973 }
974
msdc_new_tx_setting(struct msdc_host * host)975 static void msdc_new_tx_setting(struct msdc_host *host)
976 {
977 u32 val;
978
979 if (!host->top_base)
980 return;
981
982 val = readl(host->top_base + LOOP_TEST_CONTROL);
983 val |= TEST_LOOP_DSCLK_MUX_SEL;
984 val |= TEST_LOOP_LATCH_MUX_SEL;
985 val &= ~TEST_HS400_CMD_LOOP_MUX_SEL;
986
987 switch (host->timing) {
988 case MMC_TIMING_LEGACY:
989 case MMC_TIMING_MMC_HS:
990 case MMC_TIMING_SD_HS:
991 case MMC_TIMING_UHS_SDR12:
992 case MMC_TIMING_UHS_SDR25:
993 case MMC_TIMING_UHS_DDR50:
994 case MMC_TIMING_MMC_DDR52:
995 val &= ~LOOP_EN_SEL_CLK;
996 break;
997 case MMC_TIMING_UHS_SDR50:
998 case MMC_TIMING_UHS_SDR104:
999 case MMC_TIMING_MMC_HS200:
1000 case MMC_TIMING_MMC_HS400:
1001 val |= LOOP_EN_SEL_CLK;
1002 break;
1003 default:
1004 break;
1005 }
1006 writel(val, host->top_base + LOOP_TEST_CONTROL);
1007 }
1008
msdc_set_mclk(struct msdc_host * host,unsigned char timing,u32 hz)1009 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
1010 {
1011 struct mmc_host *mmc = mmc_from_priv(host);
1012 u32 mode;
1013 u32 flags;
1014 u32 div;
1015 u32 sclk;
1016 u32 tune_reg = host->dev_comp->pad_tune_reg;
1017 u32 val;
1018 bool timing_changed;
1019
1020 if (!hz) {
1021 dev_dbg(host->dev, "set mclk to 0\n");
1022 host->mclk = 0;
1023 mmc->actual_clock = 0;
1024 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1025 return;
1026 }
1027
1028 if (host->timing != timing)
1029 timing_changed = true;
1030 else
1031 timing_changed = false;
1032
1033 flags = readl(host->base + MSDC_INTEN);
1034 sdr_clr_bits(host->base + MSDC_INTEN, flags);
1035 if (host->dev_comp->clk_div_bits == 8)
1036 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
1037 else
1038 sdr_clr_bits(host->base + MSDC_CFG,
1039 MSDC_CFG_HS400_CK_MODE_EXTRA);
1040 if (timing == MMC_TIMING_UHS_DDR50 ||
1041 timing == MMC_TIMING_MMC_DDR52 ||
1042 timing == MMC_TIMING_MMC_HS400) {
1043 if (timing == MMC_TIMING_MMC_HS400)
1044 mode = 0x3;
1045 else
1046 mode = 0x2; /* ddr mode and use divisor */
1047
1048 if (hz >= (host->src_clk_freq >> 2)) {
1049 div = 0; /* mean div = 1/4 */
1050 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
1051 } else {
1052 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1053 sclk = (host->src_clk_freq >> 2) / div;
1054 div = (div >> 1);
1055 }
1056
1057 if (timing == MMC_TIMING_MMC_HS400 &&
1058 hz >= (host->src_clk_freq >> 1)) {
1059 if (host->dev_comp->clk_div_bits == 8)
1060 sdr_set_bits(host->base + MSDC_CFG,
1061 MSDC_CFG_HS400_CK_MODE);
1062 else
1063 sdr_set_bits(host->base + MSDC_CFG,
1064 MSDC_CFG_HS400_CK_MODE_EXTRA);
1065 sclk = host->src_clk_freq >> 1;
1066 div = 0; /* div is ignore when bit18 is set */
1067 }
1068 } else if (hz >= host->src_clk_freq) {
1069 mode = 0x1; /* no divisor */
1070 div = 0;
1071 sclk = host->src_clk_freq;
1072 } else {
1073 mode = 0x0; /* use divisor */
1074 if (hz >= (host->src_clk_freq >> 1)) {
1075 div = 0; /* mean div = 1/2 */
1076 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
1077 } else {
1078 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
1079 sclk = (host->src_clk_freq >> 2) / div;
1080 }
1081 }
1082 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1083
1084 clk_disable_unprepare(host->src_clk_cg);
1085 if (host->dev_comp->clk_div_bits == 8)
1086 sdr_set_field(host->base + MSDC_CFG,
1087 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
1088 (mode << 8) | div);
1089 else
1090 sdr_set_field(host->base + MSDC_CFG,
1091 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
1092 (mode << 12) | div);
1093
1094 clk_prepare_enable(host->src_clk_cg);
1095 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
1096 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
1097 mmc->actual_clock = sclk;
1098 host->mclk = hz;
1099 host->timing = timing;
1100 /* need because clk changed. */
1101 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
1102 sdr_set_bits(host->base + MSDC_INTEN, flags);
1103
1104 /*
1105 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
1106 * tune result of hs200/200Mhz is not suitable for 50Mhz
1107 */
1108 if (mmc->actual_clock <= 52000000) {
1109 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
1110 if (host->top_base) {
1111 writel(host->def_tune_para.emmc_top_control,
1112 host->top_base + EMMC_TOP_CONTROL);
1113 writel(host->def_tune_para.emmc_top_cmd,
1114 host->top_base + EMMC_TOP_CMD);
1115 } else {
1116 writel(host->def_tune_para.pad_tune,
1117 host->base + tune_reg);
1118 }
1119 } else {
1120 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
1121 writel(host->saved_tune_para.pad_cmd_tune,
1122 host->base + PAD_CMD_TUNE);
1123 if (host->top_base) {
1124 writel(host->saved_tune_para.emmc_top_control,
1125 host->top_base + EMMC_TOP_CONTROL);
1126 writel(host->saved_tune_para.emmc_top_cmd,
1127 host->top_base + EMMC_TOP_CMD);
1128 } else {
1129 writel(host->saved_tune_para.pad_tune,
1130 host->base + tune_reg);
1131 }
1132 }
1133
1134 if (timing == MMC_TIMING_MMC_HS400 &&
1135 host->dev_comp->hs400_tune)
1136 sdr_set_field(host->base + tune_reg,
1137 MSDC_PAD_TUNE_CMDRRDLY,
1138 host->hs400_cmd_int_delay);
1139 if (host->dev_comp->support_new_tx && timing_changed)
1140 msdc_new_tx_setting(host);
1141
1142 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1143 timing);
1144 }
1145
msdc_cmd_find_resp(struct msdc_host * host,struct mmc_command * cmd)1146 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1147 struct mmc_command *cmd)
1148 {
1149 u32 resp;
1150
1151 switch (mmc_resp_type(cmd)) {
1152 /* Actually, R1, R5, R6, R7 are the same */
1153 case MMC_RSP_R1:
1154 resp = 0x1;
1155 break;
1156 case MMC_RSP_R1B:
1157 case MMC_RSP_R1B_NO_CRC:
1158 resp = 0x7;
1159 break;
1160 case MMC_RSP_R2:
1161 resp = 0x2;
1162 break;
1163 case MMC_RSP_R3:
1164 resp = 0x3;
1165 break;
1166 case MMC_RSP_NONE:
1167 default:
1168 resp = 0x0;
1169 break;
1170 }
1171
1172 return resp;
1173 }
1174
msdc_cmd_prepare_raw_cmd(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1175 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1176 struct mmc_request *mrq, struct mmc_command *cmd)
1177 {
1178 struct mmc_host *mmc = mmc_from_priv(host);
1179 /* rawcmd :
1180 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1181 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1182 */
1183 u32 opcode = cmd->opcode;
1184 u32 resp = msdc_cmd_find_resp(host, cmd);
1185 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1186
1187 host->cmd_rsp = resp;
1188
1189 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1190 opcode == MMC_STOP_TRANSMISSION)
1191 rawcmd |= BIT(14);
1192 else if (opcode == SD_SWITCH_VOLTAGE)
1193 rawcmd |= BIT(30);
1194 else if (opcode == SD_APP_SEND_SCR ||
1195 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1196 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1197 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1198 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1199 rawcmd |= BIT(11);
1200
1201 if (cmd->data) {
1202 struct mmc_data *data = cmd->data;
1203
1204 if (mmc_op_multi(opcode)) {
1205 if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1206 !(mrq->sbc->arg & 0xFFFF0000))
1207 rawcmd |= BIT(29); /* AutoCMD23 */
1208 }
1209
1210 rawcmd |= ((data->blksz & 0xFFF) << 16);
1211 if (data->flags & MMC_DATA_WRITE)
1212 rawcmd |= BIT(13);
1213 if (data->blocks > 1)
1214 rawcmd |= BIT(12);
1215 else
1216 rawcmd |= BIT(11);
1217 /* Always use dma mode */
1218 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1219
1220 if (host->timeout_ns != data->timeout_ns ||
1221 host->timeout_clks != data->timeout_clks)
1222 msdc_set_timeout(host, data->timeout_ns,
1223 data->timeout_clks);
1224
1225 writel(data->blocks, host->base + SDC_BLK_NUM);
1226 }
1227 return rawcmd;
1228 }
1229
msdc_start_data(struct msdc_host * host,struct mmc_command * cmd,struct mmc_data * data)1230 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1231 struct mmc_data *data)
1232 {
1233 bool read;
1234
1235 WARN_ON(host->data);
1236 host->data = data;
1237 read = data->flags & MMC_DATA_READ;
1238
1239 mod_delayed_work(system_percpu_wq, &host->req_timeout, DAT_TIMEOUT);
1240 msdc_dma_setup(host, &host->dma, data);
1241 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1242 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1243 dev_dbg(host->dev, "DMA start\n");
1244 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1245 __func__, cmd->opcode, data->blocks, read);
1246 }
1247
msdc_auto_cmd_done(struct msdc_host * host,int events,struct mmc_command * cmd)1248 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1249 struct mmc_command *cmd)
1250 {
1251 u32 *rsp = cmd->resp;
1252
1253 rsp[0] = readl(host->base + SDC_ACMD_RESP);
1254
1255 if (events & MSDC_INT_ACMDRDY) {
1256 cmd->error = 0;
1257 } else {
1258 msdc_reset_hw(host);
1259 if (events & MSDC_INT_ACMDCRCERR) {
1260 cmd->error = -EILSEQ;
1261 host->error |= REQ_STOP_EIO;
1262 } else if (events & MSDC_INT_ACMDTMO) {
1263 cmd->error = -ETIMEDOUT;
1264 host->error |= REQ_STOP_TMO;
1265 }
1266 dev_err(host->dev,
1267 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1268 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1269 }
1270 return cmd->error;
1271 }
1272
1273 /*
1274 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1275 *
1276 * Host controller may lost interrupt in some special case.
1277 * Add SDIO irq recheck mechanism to make sure all interrupts
1278 * can be processed immediately
1279 */
msdc_recheck_sdio_irq(struct msdc_host * host)1280 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1281 {
1282 struct mmc_host *mmc = mmc_from_priv(host);
1283 u32 reg_int, reg_inten, reg_ps;
1284
1285 if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1286 reg_inten = readl(host->base + MSDC_INTEN);
1287 if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1288 reg_int = readl(host->base + MSDC_INT);
1289 reg_ps = readl(host->base + MSDC_PS);
1290 if (!(reg_int & MSDC_INT_SDIOIRQ ||
1291 reg_ps & MSDC_PS_DATA1)) {
1292 __msdc_enable_sdio_irq(host, 0);
1293 sdio_signal_irq(mmc);
1294 }
1295 }
1296 }
1297 }
1298
msdc_track_cmd_data(struct msdc_host * host,struct mmc_command * cmd)1299 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1300 {
1301 if (host->error &&
1302 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1303 cmd->error == -ETIMEDOUT))
1304 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1305 __func__, cmd->opcode, cmd->arg, host->error);
1306 }
1307
msdc_request_done(struct msdc_host * host,struct mmc_request * mrq)1308 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1309 {
1310 struct mmc_host *mmc = mmc_from_priv(host);
1311 unsigned long flags;
1312 bool hsq_req_done;
1313
1314 /*
1315 * No need check the return value of cancel_delayed_work, as only ONE
1316 * path will go here!
1317 */
1318 cancel_delayed_work(&host->req_timeout);
1319
1320 /*
1321 * If the request was handled from Host Software Queue, there's almost
1322 * nothing to do here, and we also don't need to reset mrq as any race
1323 * condition would not have any room to happen, since HSQ stores the
1324 * "scheduled" mrqs in an internal array of mrq slots anyway.
1325 * However, if the controller experienced an error, we still want to
1326 * reset it as soon as possible.
1327 *
1328 * Note that non-HSQ requests will still be happening at times, even
1329 * though it is enabled, and that's what is going to reset host->mrq.
1330 * Also, msdc_unprepare_data() is going to be called by HSQ when needed
1331 * as HSQ request finalization will eventually call the .post_req()
1332 * callback of this driver which, in turn, unprepares the data.
1333 */
1334 hsq_req_done = host->hsq_en ? mmc_hsq_finalize_request(mmc, mrq) : false;
1335 if (hsq_req_done) {
1336 if (host->error)
1337 msdc_reset_hw(host);
1338 return;
1339 }
1340
1341 spin_lock_irqsave(&host->lock, flags);
1342 host->mrq = NULL;
1343 spin_unlock_irqrestore(&host->lock, flags);
1344
1345 msdc_track_cmd_data(host, mrq->cmd);
1346 if (mrq->data)
1347 msdc_unprepare_data(host, mrq->data);
1348 if (host->error)
1349 msdc_reset_hw(host);
1350 mmc_request_done(mmc, mrq);
1351 if (host->dev_comp->recheck_sdio_irq)
1352 msdc_recheck_sdio_irq(host);
1353 }
1354
1355 /* returns true if command is fully handled; returns false otherwise */
msdc_cmd_done(struct msdc_host * host,int events,struct mmc_request * mrq,struct mmc_command * cmd)1356 static bool msdc_cmd_done(struct msdc_host *host, int events,
1357 struct mmc_request *mrq, struct mmc_command *cmd)
1358 {
1359 bool done = false;
1360 bool sbc_error;
1361 unsigned long flags;
1362 u32 *rsp;
1363
1364 if (mrq->sbc && cmd == mrq->cmd &&
1365 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1366 | MSDC_INT_ACMDTMO)))
1367 msdc_auto_cmd_done(host, events, mrq->sbc);
1368
1369 sbc_error = mrq->sbc && mrq->sbc->error;
1370
1371 if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1372 | MSDC_INT_RSPCRCERR
1373 | MSDC_INT_CMDTMO)))
1374 return done;
1375
1376 spin_lock_irqsave(&host->lock, flags);
1377 done = !host->cmd;
1378 host->cmd = NULL;
1379 spin_unlock_irqrestore(&host->lock, flags);
1380
1381 if (done)
1382 return true;
1383 rsp = cmd->resp;
1384
1385 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1386
1387 if (cmd->flags & MMC_RSP_PRESENT) {
1388 if (cmd->flags & MMC_RSP_136) {
1389 rsp[0] = readl(host->base + SDC_RESP3);
1390 rsp[1] = readl(host->base + SDC_RESP2);
1391 rsp[2] = readl(host->base + SDC_RESP1);
1392 rsp[3] = readl(host->base + SDC_RESP0);
1393 } else {
1394 rsp[0] = readl(host->base + SDC_RESP0);
1395 }
1396 }
1397
1398 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1399 if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1400 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1401 /*
1402 * should not clear fifo/interrupt as the tune data
1403 * may have already come when cmd19/cmd21 gets response
1404 * CRC error.
1405 */
1406 msdc_reset_hw(host);
1407 if (events & MSDC_INT_RSPCRCERR &&
1408 mmc_resp_type(cmd) != MMC_RSP_R1B_NO_CRC) {
1409 cmd->error = -EILSEQ;
1410 host->error |= REQ_CMD_EIO;
1411 } else if (events & MSDC_INT_CMDTMO) {
1412 cmd->error = -ETIMEDOUT;
1413 host->error |= REQ_CMD_TMO;
1414 }
1415 }
1416 if (cmd->error)
1417 dev_dbg(host->dev,
1418 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1419 __func__, cmd->opcode, cmd->arg, rsp[0],
1420 cmd->error);
1421
1422 msdc_cmd_next(host, mrq, cmd);
1423 return true;
1424 }
1425
1426 /* It is the core layer's responsibility to ensure card status
1427 * is correct before issue a request. but host design do below
1428 * checks recommended.
1429 */
msdc_cmd_is_ready(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1430 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1431 struct mmc_request *mrq, struct mmc_command *cmd)
1432 {
1433 u32 val;
1434 int ret;
1435
1436 /* The max busy time we can endure is 20ms */
1437 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1438 !(val & SDC_STS_CMDBUSY), 1, 20000);
1439 if (ret) {
1440 dev_err(host->dev, "CMD bus busy detected\n");
1441 host->error |= REQ_CMD_BUSY;
1442 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1443 return false;
1444 }
1445
1446 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1447 /* R1B or with data, should check SDCBUSY */
1448 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1449 !(val & SDC_STS_SDCBUSY), 1, 20000);
1450 if (ret) {
1451 dev_err(host->dev, "Controller busy detected\n");
1452 host->error |= REQ_CMD_BUSY;
1453 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1454 return false;
1455 }
1456 }
1457 return true;
1458 }
1459
msdc_start_command(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1460 static void msdc_start_command(struct msdc_host *host,
1461 struct mmc_request *mrq, struct mmc_command *cmd)
1462 {
1463 u32 rawcmd;
1464 unsigned long flags;
1465
1466 WARN_ON(host->cmd);
1467 host->cmd = cmd;
1468
1469 mod_delayed_work(system_percpu_wq, &host->req_timeout, DAT_TIMEOUT);
1470 if (!msdc_cmd_is_ready(host, mrq, cmd))
1471 return;
1472
1473 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1474 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1475 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1476 msdc_reset_hw(host);
1477 }
1478
1479 cmd->error = 0;
1480 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1481
1482 spin_lock_irqsave(&host->lock, flags);
1483 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1484 spin_unlock_irqrestore(&host->lock, flags);
1485
1486 writel(cmd->arg, host->base + SDC_ARG);
1487 writel(rawcmd, host->base + SDC_CMD);
1488 }
1489
msdc_cmd_next(struct msdc_host * host,struct mmc_request * mrq,struct mmc_command * cmd)1490 static void msdc_cmd_next(struct msdc_host *host,
1491 struct mmc_request *mrq, struct mmc_command *cmd)
1492 {
1493 if ((cmd->error && !host->hs400_tuning &&
1494 !(cmd->error == -EILSEQ &&
1495 mmc_op_tuning(cmd->opcode))) ||
1496 (mrq->sbc && mrq->sbc->error))
1497 msdc_request_done(host, mrq);
1498 else if (cmd == mrq->sbc)
1499 msdc_start_command(host, mrq, mrq->cmd);
1500 else if (!cmd->data)
1501 msdc_request_done(host, mrq);
1502 else
1503 msdc_start_data(host, cmd, cmd->data);
1504 }
1505
msdc_ops_request(struct mmc_host * mmc,struct mmc_request * mrq)1506 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1507 {
1508 struct msdc_host *host = mmc_priv(mmc);
1509
1510 host->error = 0;
1511 WARN_ON(!host->hsq_en && host->mrq);
1512 host->mrq = mrq;
1513
1514 if (mrq->data) {
1515 msdc_prepare_data(host, mrq->data);
1516 if (!msdc_data_prepared(mrq->data)) {
1517 host->mrq = NULL;
1518 /*
1519 * Failed to prepare DMA area, fail fast before
1520 * starting any commands.
1521 */
1522 mrq->cmd->error = -ENOSPC;
1523 mmc_request_done(mmc_from_priv(host), mrq);
1524 return;
1525 }
1526 }
1527
1528 /* if SBC is required, we have HW option and SW option.
1529 * if HW option is enabled, and SBC does not have "special" flags,
1530 * use HW option, otherwise use SW option
1531 */
1532 if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1533 (mrq->sbc->arg & 0xFFFF0000)))
1534 msdc_start_command(host, mrq, mrq->sbc);
1535 else
1536 msdc_start_command(host, mrq, mrq->cmd);
1537 }
1538
msdc_pre_req(struct mmc_host * mmc,struct mmc_request * mrq)1539 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1540 {
1541 struct msdc_host *host = mmc_priv(mmc);
1542 struct mmc_data *data = mrq->data;
1543
1544 if (!data)
1545 return;
1546
1547 msdc_prepare_data(host, data);
1548 data->host_cookie |= MSDC_ASYNC_FLAG;
1549 }
1550
msdc_post_req(struct mmc_host * mmc,struct mmc_request * mrq,int err)1551 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1552 int err)
1553 {
1554 struct msdc_host *host = mmc_priv(mmc);
1555 struct mmc_data *data = mrq->data;
1556
1557 if (!data)
1558 return;
1559
1560 if (data->host_cookie) {
1561 data->host_cookie &= ~MSDC_ASYNC_FLAG;
1562 msdc_unprepare_data(host, data);
1563 }
1564 }
1565
msdc_data_xfer_next(struct msdc_host * host,struct mmc_request * mrq)1566 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1567 {
1568 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1569 !mrq->sbc)
1570 msdc_start_command(host, mrq, mrq->stop);
1571 else
1572 msdc_request_done(host, mrq);
1573 }
1574
msdc_data_xfer_done(struct msdc_host * host,u32 events,struct mmc_request * mrq,struct mmc_data * data)1575 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1576 struct mmc_request *mrq, struct mmc_data *data)
1577 {
1578 struct mmc_command *stop;
1579 unsigned long flags;
1580 bool done;
1581 unsigned int check_data = events &
1582 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1583 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1584 | MSDC_INT_DMA_PROTECT);
1585 u32 val;
1586 int ret;
1587
1588 spin_lock_irqsave(&host->lock, flags);
1589 done = !host->data;
1590 if (check_data)
1591 host->data = NULL;
1592 spin_unlock_irqrestore(&host->lock, flags);
1593
1594 if (done)
1595 return;
1596 stop = data->stop;
1597
1598 if (check_data || (stop && stop->error)) {
1599 dev_dbg(host->dev, "DMA status: 0x%8X\n",
1600 readl(host->base + MSDC_DMA_CFG));
1601 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1602 1);
1603
1604 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1605 !(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1606 if (ret)
1607 dev_dbg(host->dev, "DMA stop timed out\n");
1608
1609 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1610 !(val & MSDC_DMA_CFG_STS), 1, 20000);
1611 if (ret)
1612 dev_dbg(host->dev, "DMA inactive timed out\n");
1613
1614 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1615 dev_dbg(host->dev, "DMA stop\n");
1616
1617 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1618 data->bytes_xfered = data->blocks * data->blksz;
1619 } else {
1620 dev_dbg(host->dev, "interrupt events: %x\n", events);
1621 msdc_reset_hw(host);
1622 host->error |= REQ_DAT_ERR;
1623 data->bytes_xfered = 0;
1624
1625 if (events & MSDC_INT_DATTMO)
1626 data->error = -ETIMEDOUT;
1627 else if (events & MSDC_INT_DATCRCERR)
1628 data->error = -EILSEQ;
1629
1630 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1631 __func__, mrq->cmd->opcode, data->blocks);
1632 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1633 (int)data->error, data->bytes_xfered);
1634 }
1635
1636 msdc_data_xfer_next(host, mrq);
1637 }
1638 }
1639
msdc_set_buswidth(struct msdc_host * host,u32 width)1640 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1641 {
1642 u32 val = readl(host->base + SDC_CFG);
1643
1644 val &= ~SDC_CFG_BUSWIDTH;
1645
1646 switch (width) {
1647 default:
1648 case MMC_BUS_WIDTH_1:
1649 val |= (MSDC_BUS_1BITS << 16);
1650 break;
1651 case MMC_BUS_WIDTH_4:
1652 val |= (MSDC_BUS_4BITS << 16);
1653 break;
1654 case MMC_BUS_WIDTH_8:
1655 val |= (MSDC_BUS_8BITS << 16);
1656 break;
1657 }
1658
1659 writel(val, host->base + SDC_CFG);
1660 dev_dbg(host->dev, "Bus Width = %d", width);
1661 }
1662
msdc_ops_switch_volt(struct mmc_host * mmc,struct mmc_ios * ios)1663 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1664 {
1665 struct msdc_host *host = mmc_priv(mmc);
1666 int ret;
1667
1668 if (!IS_ERR(mmc->supply.vqmmc)) {
1669 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1670 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1671 dev_err(host->dev, "Unsupported signal voltage!\n");
1672 return -EINVAL;
1673 }
1674
1675 ret = mmc_regulator_set_vqmmc(mmc, ios);
1676 if (ret < 0) {
1677 dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1678 ret, ios->signal_voltage);
1679 return ret;
1680 }
1681
1682 /* Apply different pinctrl settings for different signal voltage */
1683 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1684 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1685 else
1686 pinctrl_select_state(host->pinctrl, host->pins_default);
1687 }
1688 return 0;
1689 }
1690
msdc_card_busy(struct mmc_host * mmc)1691 static int msdc_card_busy(struct mmc_host *mmc)
1692 {
1693 struct msdc_host *host = mmc_priv(mmc);
1694 u32 status = readl(host->base + MSDC_PS);
1695
1696 /* only check if data0 is low */
1697 return !(status & BIT(16));
1698 }
1699
msdc_request_timeout(struct work_struct * work)1700 static void msdc_request_timeout(struct work_struct *work)
1701 {
1702 struct msdc_host *host = container_of(work, struct msdc_host,
1703 req_timeout.work);
1704
1705 /* simulate HW timeout status */
1706 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1707 if (host->mrq) {
1708 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1709 host->mrq, host->mrq->cmd->opcode);
1710 if (host->cmd) {
1711 dev_err(host->dev, "%s: aborting cmd=%d\n",
1712 __func__, host->cmd->opcode);
1713 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1714 host->cmd);
1715 } else if (host->data) {
1716 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1717 __func__, host->mrq->cmd->opcode,
1718 host->data->blocks);
1719 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1720 host->data);
1721 }
1722 }
1723 }
1724
__msdc_enable_sdio_irq(struct msdc_host * host,int enb)1725 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1726 {
1727 if (enb) {
1728 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1729 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1730 if (host->dev_comp->recheck_sdio_irq)
1731 msdc_recheck_sdio_irq(host);
1732 } else {
1733 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1734 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1735 }
1736 }
1737
msdc_enable_sdio_irq(struct mmc_host * mmc,int enb)1738 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1739 {
1740 struct msdc_host *host = mmc_priv(mmc);
1741 unsigned long flags;
1742 int ret;
1743
1744 spin_lock_irqsave(&host->lock, flags);
1745 __msdc_enable_sdio_irq(host, enb);
1746 spin_unlock_irqrestore(&host->lock, flags);
1747
1748 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1749 if (enb) {
1750 /*
1751 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1752 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1753 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1754 * affect successfully, we change the pinstate to pins_eint firstly.
1755 */
1756 pinctrl_select_state(host->pinctrl, host->pins_eint);
1757 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1758
1759 if (ret) {
1760 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1761 host->pins_eint = NULL;
1762 pm_runtime_get_noresume(host->dev);
1763 } else {
1764 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1765 }
1766
1767 pinctrl_select_state(host->pinctrl, host->pins_uhs);
1768 } else {
1769 dev_pm_clear_wake_irq(host->dev);
1770 }
1771 } else {
1772 if (enb) {
1773 /* Ensure host->pins_eint is NULL */
1774 host->pins_eint = NULL;
1775 pm_runtime_get_noresume(host->dev);
1776 } else {
1777 pm_runtime_put_noidle(host->dev);
1778 }
1779 }
1780 }
1781
msdc_cmdq_irq(struct msdc_host * host,u32 intsts)1782 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1783 {
1784 struct mmc_host *mmc = mmc_from_priv(host);
1785 int cmd_err = 0, dat_err = 0;
1786
1787 if (intsts & MSDC_INT_RSPCRCERR) {
1788 cmd_err = -EILSEQ;
1789 dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1790 } else if (intsts & MSDC_INT_CMDTMO) {
1791 cmd_err = -ETIMEDOUT;
1792 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1793 }
1794
1795 if (intsts & MSDC_INT_DATCRCERR) {
1796 dat_err = -EILSEQ;
1797 dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1798 } else if (intsts & MSDC_INT_DATTMO) {
1799 dat_err = -ETIMEDOUT;
1800 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1801 }
1802
1803 if (cmd_err || dat_err) {
1804 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1805 cmd_err, dat_err, intsts);
1806 }
1807
1808 return cqhci_irq(mmc, cmd_err, dat_err);
1809 }
1810
msdc_irq(int irq,void * dev_id)1811 static irqreturn_t msdc_irq(int irq, void *dev_id)
1812 {
1813 struct msdc_host *host = (struct msdc_host *) dev_id;
1814 struct mmc_host *mmc = mmc_from_priv(host);
1815
1816 while (true) {
1817 struct mmc_request *mrq;
1818 struct mmc_command *cmd;
1819 struct mmc_data *data;
1820 u32 events, event_mask;
1821
1822 spin_lock(&host->lock);
1823 events = readl(host->base + MSDC_INT);
1824 event_mask = readl(host->base + MSDC_INTEN);
1825 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1826 __msdc_enable_sdio_irq(host, 0);
1827 /* clear interrupts */
1828 writel(events & event_mask, host->base + MSDC_INT);
1829
1830 mrq = host->mrq;
1831 cmd = host->cmd;
1832 data = host->data;
1833 spin_unlock(&host->lock);
1834
1835 if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1836 sdio_signal_irq(mmc);
1837
1838 if ((events & event_mask) & MSDC_INT_CDSC) {
1839 if (host->internal_cd)
1840 mmc_detect_change(mmc, msecs_to_jiffies(20));
1841 events &= ~MSDC_INT_CDSC;
1842 }
1843
1844 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1845 break;
1846
1847 if ((mmc->caps2 & MMC_CAP2_CQE) &&
1848 (events & MSDC_INT_CMDQ)) {
1849 msdc_cmdq_irq(host, events);
1850 /* clear interrupts */
1851 writel(events, host->base + MSDC_INT);
1852 return IRQ_HANDLED;
1853 }
1854
1855 if (!mrq) {
1856 dev_err(host->dev,
1857 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1858 __func__, events, event_mask);
1859 WARN_ON(1);
1860 break;
1861 }
1862
1863 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1864
1865 if (cmd)
1866 msdc_cmd_done(host, events, mrq, cmd);
1867 else if (data)
1868 msdc_data_xfer_done(host, events, mrq, data);
1869 }
1870
1871 return IRQ_HANDLED;
1872 }
1873
msdc_init_hw(struct msdc_host * host)1874 static void msdc_init_hw(struct msdc_host *host)
1875 {
1876 u32 val, pb1_val, pb2_val;
1877 u32 tune_reg = host->dev_comp->pad_tune_reg;
1878 struct mmc_host *mmc = mmc_from_priv(host);
1879
1880 if (host->reset) {
1881 reset_control_assert(host->reset);
1882 usleep_range(10, 50);
1883 reset_control_deassert(host->reset);
1884 }
1885
1886 /* New tx/rx enable bit need to be 0->1 for hardware check */
1887 if (host->dev_comp->support_new_tx) {
1888 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1889 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
1890 msdc_new_tx_setting(host);
1891 }
1892 if (host->dev_comp->support_new_rx) {
1893 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1894 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
1895 }
1896
1897 /* Configure to MMC/SD mode, clock free running */
1898 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1899
1900 /* Reset */
1901 msdc_reset_hw(host);
1902
1903 /* Disable and clear all interrupts */
1904 writel(0, host->base + MSDC_INTEN);
1905 val = readl(host->base + MSDC_INT);
1906 writel(val, host->base + MSDC_INT);
1907
1908 /* Configure card detection */
1909 if (host->internal_cd) {
1910 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1911 DEFAULT_DEBOUNCE);
1912 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1913 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1914 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1915 } else {
1916 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1917 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1918 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1919 }
1920
1921 if (host->top_base) {
1922 writel(0, host->top_base + EMMC_TOP_CONTROL);
1923 writel(0, host->top_base + EMMC_TOP_CMD);
1924 } else {
1925 writel(0, host->base + tune_reg);
1926 }
1927 writel(0, host->base + MSDC_IOCON);
1928 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1929
1930 /*
1931 * Patch bit 0 and 1 are completely rewritten, but for patch bit 2
1932 * defaults are retained and, if necessary, only some bits are fixed
1933 * up: read the PB2 register here for later usage in this function.
1934 */
1935 pb2_val = readl(host->base + MSDC_PATCH_BIT2);
1936
1937 /* Enable odd number support for 8-bit data bus */
1938 val = MSDC_PATCH_BIT_ODDSUPP;
1939
1940 /* Disable SD command register write monitor */
1941 val |= MSDC_PATCH_BIT_DIS_WRMON;
1942
1943 /* Issue transfer done interrupt after GPD update */
1944 val |= MSDC_PATCH_BIT_DESCUP_SEL;
1945
1946 /* Extend R1B busy detection delay (in clock cycles) */
1947 val |= FIELD_PREP(MSDC_PATCH_BIT_BUSYDLY, 15);
1948
1949 /* Enable CRC phase timeout during data write operation */
1950 val |= MSDC_PATCH_BIT_DECRCTMO;
1951
1952 /* Set CKGEN delay to one stage */
1953 val |= FIELD_PREP(MSDC_CKGEN_MSDC_DLY_SEL, 1);
1954
1955 /* First MSDC_PATCH_BIT setup is done: pull the trigger! */
1956 writel(val, host->base + MSDC_PATCH_BIT);
1957
1958 /* Set wr data, crc status, cmd response turnaround period for UHS104 */
1959 pb1_val = FIELD_PREP(MSDC_PB1_WRDAT_CRC_TACNTR, 1);
1960 pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_CMDTA, 1);
1961 pb1_val |= MSDC_PB1_DDR_CMD_FIX_SEL;
1962
1963 /* Support 'single' burst type only when AXI_LEN is 0 */
1964 sdr_get_field(host->base + EMMC50_CFG2, EMMC50_CFG2_AXI_SET_LEN, &val);
1965 if (!val)
1966 pb1_val |= MSDC_PB1_SINGLE_BURST;
1967
1968 /* Set auto sync state clear, block gap stop clk */
1969 pb1_val |= MSDC_PB1_RSVD20 | MSDC_PB1_AUTO_SYNCST_CLR | MSDC_PB1_MARK_POP_WATER;
1970
1971 /* Set low power DCM, use HCLK for GDMA, use MSDC CLK for everything else */
1972 pb1_val |= MSDC_PB1_LP_DCM_EN | MSDC_PB1_RSVD3 |
1973 MSDC_PB1_AHB_GDMA_HCLK | MSDC_PB1_MSDC_CLK_ENFEAT;
1974
1975 /* If needed, enable R1b command busy check at controller init time */
1976 if (!host->dev_comp->busy_check)
1977 pb1_val |= MSDC_PB1_BUSY_CHECK_SEL;
1978
1979 if (host->dev_comp->stop_clk_fix) {
1980 if (host->dev_comp->stop_dly_sel)
1981 pb1_val |= FIELD_PREP(MSDC_PATCH_BIT1_STOP_DLY,
1982 host->dev_comp->stop_dly_sel);
1983
1984 if (host->dev_comp->pop_en_cnt) {
1985 pb2_val &= ~MSDC_PB2_POP_EN_CNT;
1986 pb2_val |= FIELD_PREP(MSDC_PB2_POP_EN_CNT,
1987 host->dev_comp->pop_en_cnt);
1988 }
1989
1990 sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_WRVALIDSEL);
1991 sdr_clr_bits(host->base + SDC_FIFO_CFG, SDC_FIFO_CFG_RDVALIDSEL);
1992 }
1993
1994 if (host->dev_comp->async_fifo) {
1995 /* Set CMD response timeout multiplier to 65 + (16 * 3) cycles */
1996 pb2_val &= ~MSDC_PB2_RESPWAIT;
1997 pb2_val |= FIELD_PREP(MSDC_PB2_RESPWAIT, 3);
1998
1999 /* eMMC4.5: Select async FIFO path for CMD resp and CRC status */
2000 pb2_val &= ~MSDC_PATCH_BIT2_CFGRESP;
2001 pb2_val |= MSDC_PATCH_BIT2_CFGCRCSTS;
2002
2003 if (!host->dev_comp->enhance_rx) {
2004 /* eMMC4.5: Delay 2T for CMD resp and CRC status EN signals */
2005 pb2_val &= ~(MSDC_PB2_RESPSTSENSEL | MSDC_PB2_CRCSTSENSEL);
2006 pb2_val |= FIELD_PREP(MSDC_PB2_RESPSTSENSEL, 2);
2007 pb2_val |= FIELD_PREP(MSDC_PB2_CRCSTSENSEL, 2);
2008 } else if (host->top_base) {
2009 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, SDC_RX_ENH_EN);
2010 } else {
2011 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_RX_ENHANCE_EN);
2012 }
2013 }
2014
2015 if (host->dev_comp->support_64g)
2016 pb2_val |= MSDC_PB2_SUPPORT_64G;
2017
2018 /* Patch Bit 1/2 setup is done: pull the trigger! */
2019 writel(pb1_val, host->base + MSDC_PATCH_BIT1);
2020 writel(pb2_val, host->base + MSDC_PATCH_BIT2);
2021 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
2022
2023 if (host->dev_comp->data_tune) {
2024 if (host->top_base) {
2025 u32 top_ctl_val = readl(host->top_base + EMMC_TOP_CONTROL);
2026 u32 top_cmd_val = readl(host->top_base + EMMC_TOP_CMD);
2027
2028 top_cmd_val |= PAD_CMD_RD_RXDLY_SEL;
2029 top_ctl_val |= PAD_DAT_RD_RXDLY_SEL;
2030 top_ctl_val &= ~DATA_K_VALUE_SEL;
2031 if (host->tuning_step > PAD_DELAY_HALF) {
2032 top_cmd_val |= PAD_CMD_RD_RXDLY2_SEL;
2033 top_ctl_val |= PAD_DAT_RD_RXDLY2_SEL;
2034 }
2035
2036 writel(top_ctl_val, host->top_base + EMMC_TOP_CONTROL);
2037 writel(top_cmd_val, host->top_base + EMMC_TOP_CMD);
2038 } else {
2039 sdr_set_bits(host->base + tune_reg,
2040 MSDC_PAD_TUNE_RD_SEL |
2041 MSDC_PAD_TUNE_CMD_SEL);
2042 if (host->tuning_step > PAD_DELAY_HALF)
2043 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2044 MSDC_PAD_TUNE_RD2_SEL |
2045 MSDC_PAD_TUNE_CMD2_SEL);
2046 }
2047 } else {
2048 /* choose clock tune */
2049 if (host->top_base)
2050 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
2051 PAD_RXDLY_SEL);
2052 else
2053 sdr_set_bits(host->base + tune_reg,
2054 MSDC_PAD_TUNE_RXDLYSEL);
2055 }
2056
2057 if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
2058 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
2059 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
2060 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
2061 } else {
2062 /* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
2063 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
2064
2065 /* Config SDIO device detect interrupt function */
2066 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
2067 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
2068 }
2069
2070 /* Configure to default data timeout */
2071 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
2072
2073 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
2074 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2075 if (host->top_base) {
2076 host->def_tune_para.emmc_top_control =
2077 readl(host->top_base + EMMC_TOP_CONTROL);
2078 host->def_tune_para.emmc_top_cmd =
2079 readl(host->top_base + EMMC_TOP_CMD);
2080 host->saved_tune_para.emmc_top_control =
2081 readl(host->top_base + EMMC_TOP_CONTROL);
2082 host->saved_tune_para.emmc_top_cmd =
2083 readl(host->top_base + EMMC_TOP_CMD);
2084 } else {
2085 host->def_tune_para.pad_tune = readl(host->base + tune_reg);
2086 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2087 }
2088 dev_dbg(host->dev, "init hardware done!");
2089 }
2090
msdc_deinit_hw(struct msdc_host * host)2091 static void msdc_deinit_hw(struct msdc_host *host)
2092 {
2093 u32 val;
2094
2095 if (host->internal_cd) {
2096 /* Disabled card-detect */
2097 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
2098 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
2099 }
2100
2101 /* Disable and clear all interrupts */
2102 writel(0, host->base + MSDC_INTEN);
2103
2104 val = readl(host->base + MSDC_INT);
2105 writel(val, host->base + MSDC_INT);
2106 }
2107
2108 /* init gpd and bd list in msdc_drv_probe */
msdc_init_gpd_bd(struct msdc_host * host,struct msdc_dma * dma)2109 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
2110 {
2111 struct mt_gpdma_desc *gpd = dma->gpd;
2112 struct mt_bdma_desc *bd = dma->bd;
2113 dma_addr_t dma_addr;
2114 int i;
2115
2116 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
2117
2118 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
2119 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
2120 /* gpd->next is must set for desc DMA
2121 * That's why must alloc 2 gpd structure.
2122 */
2123 gpd->next = lower_32_bits(dma_addr);
2124 if (host->dev_comp->support_64g)
2125 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2126
2127 dma_addr = dma->bd_addr;
2128 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
2129 if (host->dev_comp->support_64g)
2130 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
2131
2132 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
2133 for (i = 0; i < (MAX_BD_NUM - 1); i++) {
2134 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
2135 bd[i].next = lower_32_bits(dma_addr);
2136 if (host->dev_comp->support_64g)
2137 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
2138 }
2139 }
2140
msdc_ops_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)2141 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
2142 {
2143 struct msdc_host *host = mmc_priv(mmc);
2144 int ret;
2145
2146 msdc_set_buswidth(host, ios->bus_width);
2147
2148 /* Suspend/Resume will do power off/on */
2149 switch (ios->power_mode) {
2150 case MMC_POWER_UP:
2151 if (!IS_ERR(mmc->supply.vmmc)) {
2152 msdc_init_hw(host);
2153 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
2154 ios->vdd);
2155 if (ret) {
2156 dev_err(host->dev, "Failed to set vmmc power!\n");
2157 return;
2158 }
2159 }
2160 break;
2161 case MMC_POWER_ON:
2162 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
2163 ret = regulator_enable(mmc->supply.vqmmc);
2164 if (ret)
2165 dev_err(host->dev, "Failed to set vqmmc power!\n");
2166 else
2167 host->vqmmc_enabled = true;
2168 }
2169 break;
2170 case MMC_POWER_OFF:
2171 if (!IS_ERR(mmc->supply.vmmc))
2172 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
2173
2174 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
2175 regulator_disable(mmc->supply.vqmmc);
2176 host->vqmmc_enabled = false;
2177 }
2178 break;
2179 default:
2180 break;
2181 }
2182
2183 if (host->mclk != ios->clock || host->timing != ios->timing)
2184 msdc_set_mclk(host, ios->timing, ios->clock);
2185 }
2186
test_delay_bit(u64 delay,u32 bit)2187 static u64 test_delay_bit(u64 delay, u32 bit)
2188 {
2189 bit %= PAD_DELAY_FULL;
2190 return delay & BIT_ULL(bit);
2191 }
2192
get_delay_len(u64 delay,u32 start_bit)2193 static int get_delay_len(u64 delay, u32 start_bit)
2194 {
2195 int i;
2196
2197 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
2198 if (test_delay_bit(delay, start_bit + i) == 0)
2199 return i;
2200 }
2201 return PAD_DELAY_FULL - start_bit;
2202 }
2203
get_best_delay(struct msdc_host * host,u64 delay)2204 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
2205 {
2206 int start = 0, len = 0;
2207 int start_final = 0, len_final = 0;
2208 u8 final_phase = 0xff;
2209 struct msdc_delay_phase delay_phase = { 0, };
2210
2211 if (delay == 0) {
2212 dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
2213 delay_phase.final_phase = final_phase;
2214 return delay_phase;
2215 }
2216
2217 while (start < PAD_DELAY_FULL) {
2218 len = get_delay_len(delay, start);
2219 if (len_final < len) {
2220 start_final = start;
2221 len_final = len;
2222 }
2223 start += len ? len : 1;
2224 if (!upper_32_bits(delay) && len >= 12 && start_final < 4)
2225 break;
2226 }
2227
2228 /* The rule is that to find the smallest delay cell */
2229 if (start_final == 0)
2230 final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;
2231 else
2232 final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;
2233 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
2234 delay, len_final, final_phase);
2235
2236 delay_phase.maxlen = len_final;
2237 delay_phase.start = start_final;
2238 delay_phase.final_phase = final_phase;
2239 return delay_phase;
2240 }
2241
msdc_set_cmd_delay(struct msdc_host * host,u32 value)2242 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2243 {
2244 u32 tune_reg = host->dev_comp->pad_tune_reg;
2245
2246 if (host->top_base) {
2247 u32 regval = readl(host->top_base + EMMC_TOP_CMD);
2248
2249 regval &= ~(PAD_CMD_RXDLY | PAD_CMD_RXDLY2);
2250
2251 if (value < PAD_DELAY_HALF) {
2252 regval |= FIELD_PREP(PAD_CMD_RXDLY, value);
2253 } else {
2254 regval |= FIELD_PREP(PAD_CMD_RXDLY, PAD_DELAY_HALF - 1);
2255 regval |= FIELD_PREP(PAD_CMD_RXDLY2, value - PAD_DELAY_HALF);
2256 }
2257 writel(regval, host->top_base + EMMC_TOP_CMD);
2258 } else {
2259 if (value < PAD_DELAY_HALF) {
2260 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2261 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2262 MSDC_PAD_TUNE_CMDRDLY2, 0);
2263 } else {
2264 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2265 PAD_DELAY_HALF - 1);
2266 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2267 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);
2268 }
2269 }
2270 }
2271
msdc_set_data_delay(struct msdc_host * host,u32 value)2272 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2273 {
2274 u32 tune_reg = host->dev_comp->pad_tune_reg;
2275
2276 if (host->top_base) {
2277 u32 regval = readl(host->top_base + EMMC_TOP_CONTROL);
2278
2279 regval &= ~(PAD_DAT_RD_RXDLY | PAD_DAT_RD_RXDLY2);
2280
2281 if (value < PAD_DELAY_HALF) {
2282 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, value);
2283 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value);
2284 } else {
2285 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);
2286 regval |= FIELD_PREP(PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);
2287 }
2288 writel(regval, host->top_base + EMMC_TOP_CONTROL);
2289 } else {
2290 if (value < PAD_DELAY_HALF) {
2291 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2292 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2293 MSDC_PAD_TUNE_DATRRDLY2, 0);
2294 } else {
2295 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2296 PAD_DELAY_HALF - 1);
2297 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2298 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);
2299 }
2300 }
2301 }
2302
msdc_set_data_sample_edge(struct msdc_host * host,bool rising)2303 static inline void msdc_set_data_sample_edge(struct msdc_host *host, bool rising)
2304 {
2305 u32 value = rising ? 0 : 1;
2306
2307 if (host->dev_comp->support_new_rx) {
2308 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_PATCH_BIT_RD_DAT_SEL, value);
2309 sdr_set_field(host->base + MSDC_PATCH_BIT2, MSDC_PB2_CFGCRCSTSEDGE, value);
2310 } else {
2311 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DSPL, value);
2312 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL, value);
2313 }
2314 }
2315
msdc_tune_response(struct mmc_host * mmc,u32 opcode)2316 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2317 {
2318 struct msdc_host *host = mmc_priv(mmc);
2319 u64 rise_delay = 0, fall_delay = 0;
2320 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2321 struct msdc_delay_phase internal_delay_phase;
2322 u8 final_delay, final_maxlen;
2323 u32 internal_delay = 0;
2324 u32 tune_reg = host->dev_comp->pad_tune_reg;
2325 int cmd_err;
2326 int i, j;
2327
2328 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2329 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2330 sdr_set_field(host->base + tune_reg,
2331 MSDC_PAD_TUNE_CMDRRDLY,
2332 host->hs200_cmd_int_delay);
2333
2334 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2335 for (i = 0; i < host->tuning_step; i++) {
2336 msdc_set_cmd_delay(host, i);
2337 /*
2338 * Using the same parameters, it may sometimes pass the test,
2339 * but sometimes it may fail. To make sure the parameters are
2340 * more stable, we test each set of parameters 3 times.
2341 */
2342 for (j = 0; j < 3; j++) {
2343 mmc_send_tuning(mmc, opcode, &cmd_err);
2344 if (!cmd_err) {
2345 rise_delay |= BIT_ULL(i);
2346 } else {
2347 rise_delay &= ~BIT_ULL(i);
2348 break;
2349 }
2350 }
2351 }
2352 final_rise_delay = get_best_delay(host, rise_delay);
2353 /* if rising edge has enough margin, then do not scan falling edge */
2354 if (final_rise_delay.maxlen >= 12 ||
2355 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2356 goto skip_fall;
2357
2358 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2359 for (i = 0; i < host->tuning_step; i++) {
2360 msdc_set_cmd_delay(host, i);
2361 /*
2362 * Using the same parameters, it may sometimes pass the test,
2363 * but sometimes it may fail. To make sure the parameters are
2364 * more stable, we test each set of parameters 3 times.
2365 */
2366 for (j = 0; j < 3; j++) {
2367 mmc_send_tuning(mmc, opcode, &cmd_err);
2368 if (!cmd_err) {
2369 fall_delay |= BIT_ULL(i);
2370 } else {
2371 fall_delay &= ~BIT_ULL(i);
2372 break;
2373 }
2374 }
2375 }
2376 final_fall_delay = get_best_delay(host, fall_delay);
2377
2378 skip_fall:
2379 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2380 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2381 final_maxlen = final_fall_delay.maxlen;
2382 if (final_maxlen == final_rise_delay.maxlen) {
2383 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2384 final_delay = final_rise_delay.final_phase;
2385 } else {
2386 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2387 final_delay = final_fall_delay.final_phase;
2388 }
2389 msdc_set_cmd_delay(host, final_delay);
2390
2391 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2392 goto skip_internal;
2393
2394 for (i = 0; i < host->tuning_step; i++) {
2395 sdr_set_field(host->base + tune_reg,
2396 MSDC_PAD_TUNE_CMDRRDLY, i);
2397 mmc_send_tuning(mmc, opcode, &cmd_err);
2398 if (!cmd_err)
2399 internal_delay |= BIT_ULL(i);
2400 }
2401 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2402 internal_delay_phase = get_best_delay(host, internal_delay);
2403 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2404 internal_delay_phase.final_phase);
2405 skip_internal:
2406 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2407 return final_delay == 0xff ? -EIO : 0;
2408 }
2409
hs400_tune_response(struct mmc_host * mmc,u32 opcode)2410 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2411 {
2412 struct msdc_host *host = mmc_priv(mmc);
2413 u32 cmd_delay = 0;
2414 struct msdc_delay_phase final_cmd_delay = { 0,};
2415 u8 final_delay;
2416 int cmd_err;
2417 int i, j;
2418
2419 /* select EMMC50 PAD CMD tune */
2420 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2421 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2422
2423 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2424 mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2425 sdr_set_field(host->base + MSDC_PAD_TUNE,
2426 MSDC_PAD_TUNE_CMDRRDLY,
2427 host->hs200_cmd_int_delay);
2428
2429 if (host->hs400_cmd_resp_sel_rising)
2430 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2431 else
2432 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2433
2434 for (i = 0; i < PAD_DELAY_HALF; i++) {
2435 sdr_set_field(host->base + PAD_CMD_TUNE,
2436 PAD_CMD_TUNE_RX_DLY3, i);
2437 /*
2438 * Using the same parameters, it may sometimes pass the test,
2439 * but sometimes it may fail. To make sure the parameters are
2440 * more stable, we test each set of parameters 3 times.
2441 */
2442 for (j = 0; j < 3; j++) {
2443 mmc_send_tuning(mmc, opcode, &cmd_err);
2444 if (!cmd_err) {
2445 cmd_delay |= BIT(i);
2446 } else {
2447 cmd_delay &= ~BIT(i);
2448 break;
2449 }
2450 }
2451 }
2452 final_cmd_delay = get_best_delay(host, cmd_delay);
2453 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2454 final_cmd_delay.final_phase);
2455 final_delay = final_cmd_delay.final_phase;
2456
2457 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2458 return final_delay == 0xff ? -EIO : 0;
2459 }
2460
msdc_tune_data(struct mmc_host * mmc,u32 opcode)2461 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2462 {
2463 struct msdc_host *host = mmc_priv(mmc);
2464 u64 rise_delay = 0, fall_delay = 0;
2465 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2466 u8 final_delay, final_maxlen;
2467 int i, ret;
2468
2469 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2470 host->latch_ck);
2471 msdc_set_data_sample_edge(host, true);
2472 for (i = 0; i < host->tuning_step; i++) {
2473 msdc_set_data_delay(host, i);
2474 ret = mmc_send_tuning(mmc, opcode, NULL);
2475 if (!ret)
2476 rise_delay |= BIT_ULL(i);
2477 }
2478 final_rise_delay = get_best_delay(host, rise_delay);
2479 /* if rising edge has enough margin, then do not scan falling edge */
2480 if (final_rise_delay.maxlen >= 12 ||
2481 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2482 goto skip_fall;
2483
2484 msdc_set_data_sample_edge(host, false);
2485 for (i = 0; i < host->tuning_step; i++) {
2486 msdc_set_data_delay(host, i);
2487 ret = mmc_send_tuning(mmc, opcode, NULL);
2488 if (!ret)
2489 fall_delay |= BIT_ULL(i);
2490 }
2491 final_fall_delay = get_best_delay(host, fall_delay);
2492
2493 skip_fall:
2494 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2495 if (final_maxlen == final_rise_delay.maxlen) {
2496 msdc_set_data_sample_edge(host, true);
2497 final_delay = final_rise_delay.final_phase;
2498 } else {
2499 msdc_set_data_sample_edge(host, false);
2500 final_delay = final_fall_delay.final_phase;
2501 }
2502 msdc_set_data_delay(host, final_delay);
2503
2504 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2505 return final_delay == 0xff ? -EIO : 0;
2506 }
2507
2508 /*
2509 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2510 * together, which can save the tuning time.
2511 */
msdc_tune_together(struct mmc_host * mmc,u32 opcode)2512 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2513 {
2514 struct msdc_host *host = mmc_priv(mmc);
2515 u64 rise_delay = 0, fall_delay = 0;
2516 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2517 u8 final_delay, final_maxlen;
2518 int i, ret;
2519
2520 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2521 host->latch_ck);
2522
2523 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2524 msdc_set_data_sample_edge(host, true);
2525 for (i = 0; i < host->tuning_step; i++) {
2526 msdc_set_cmd_delay(host, i);
2527 msdc_set_data_delay(host, i);
2528 ret = mmc_send_tuning(mmc, opcode, NULL);
2529 if (!ret)
2530 rise_delay |= BIT_ULL(i);
2531 }
2532 final_rise_delay = get_best_delay(host, rise_delay);
2533 /* if rising edge has enough margin, then do not scan falling edge */
2534 if (final_rise_delay.maxlen >= 12 ||
2535 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2536 goto skip_fall;
2537
2538 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2539 msdc_set_data_sample_edge(host, false);
2540 for (i = 0; i < host->tuning_step; i++) {
2541 msdc_set_cmd_delay(host, i);
2542 msdc_set_data_delay(host, i);
2543 ret = mmc_send_tuning(mmc, opcode, NULL);
2544 if (!ret)
2545 fall_delay |= BIT_ULL(i);
2546 }
2547 final_fall_delay = get_best_delay(host, fall_delay);
2548
2549 skip_fall:
2550 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2551 if (final_maxlen == final_rise_delay.maxlen) {
2552 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2553 msdc_set_data_sample_edge(host, true);
2554 final_delay = final_rise_delay.final_phase;
2555 } else {
2556 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2557 msdc_set_data_sample_edge(host, false);
2558 final_delay = final_fall_delay.final_phase;
2559 }
2560
2561 msdc_set_cmd_delay(host, final_delay);
2562 msdc_set_data_delay(host, final_delay);
2563
2564 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2565 return final_delay == 0xff ? -EIO : 0;
2566 }
2567
msdc_execute_tuning(struct mmc_host * mmc,u32 opcode)2568 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2569 {
2570 struct msdc_host *host = mmc_priv(mmc);
2571 int ret;
2572 u32 tune_reg = host->dev_comp->pad_tune_reg;
2573
2574 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2575 ret = msdc_tune_together(mmc, opcode);
2576 if (host->hs400_mode) {
2577 msdc_set_data_sample_edge(host, true);
2578 msdc_set_data_delay(host, 0);
2579 }
2580 goto tune_done;
2581 }
2582 if (host->hs400_mode &&
2583 host->dev_comp->hs400_tune)
2584 ret = hs400_tune_response(mmc, opcode);
2585 else
2586 ret = msdc_tune_response(mmc, opcode);
2587 if (ret == -EIO) {
2588 dev_err(host->dev, "Tune response fail!\n");
2589 return ret;
2590 }
2591 if (host->hs400_mode == false) {
2592 ret = msdc_tune_data(mmc, opcode);
2593 if (ret == -EIO)
2594 dev_err(host->dev, "Tune data fail!\n");
2595 }
2596
2597 tune_done:
2598 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2599 host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2600 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2601 if (host->top_base) {
2602 host->saved_tune_para.emmc_top_control = readl(host->top_base +
2603 EMMC_TOP_CONTROL);
2604 host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2605 EMMC_TOP_CMD);
2606 }
2607 return ret;
2608 }
2609
msdc_prepare_hs400_tuning(struct mmc_host * mmc,struct mmc_ios * ios)2610 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2611 {
2612 struct msdc_host *host = mmc_priv(mmc);
2613
2614 host->hs400_mode = true;
2615
2616 if (host->top_base) {
2617 if (host->hs400_ds_dly3)
2618 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2619 PAD_DS_DLY3, host->hs400_ds_dly3);
2620 if (host->hs400_ds_delay)
2621 writel(host->hs400_ds_delay,
2622 host->top_base + EMMC50_PAD_DS_TUNE);
2623 } else {
2624 if (host->hs400_ds_dly3)
2625 sdr_set_field(host->base + PAD_DS_TUNE,
2626 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2627 if (host->hs400_ds_delay)
2628 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2629 }
2630 /* hs400 mode must set it to 0 */
2631 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2632 /* to improve read performance, set outstanding to 2 */
2633 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2634
2635 return 0;
2636 }
2637
msdc_execute_hs400_tuning(struct mmc_host * mmc,struct mmc_card * card)2638 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2639 {
2640 struct msdc_host *host = mmc_priv(mmc);
2641 struct msdc_delay_phase dly1_delay;
2642 u32 val, result_dly1 = 0;
2643 u8 *ext_csd;
2644 int i, ret;
2645
2646 if (host->top_base) {
2647 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2648 PAD_DS_DLY_SEL);
2649 sdr_clr_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2650 PAD_DS_DLY2_SEL);
2651 } else {
2652 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2653 sdr_clr_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY2_SEL);
2654 }
2655
2656 host->hs400_tuning = true;
2657 for (i = 0; i < PAD_DELAY_HALF; i++) {
2658 if (host->top_base)
2659 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2660 PAD_DS_DLY1, i);
2661 else
2662 sdr_set_field(host->base + PAD_DS_TUNE,
2663 PAD_DS_TUNE_DLY1, i);
2664 ret = mmc_get_ext_csd(card, &ext_csd);
2665 if (!ret) {
2666 result_dly1 |= BIT(i);
2667 kfree(ext_csd);
2668 }
2669 }
2670 host->hs400_tuning = false;
2671
2672 dly1_delay = get_best_delay(host, result_dly1);
2673 if (dly1_delay.maxlen == 0) {
2674 dev_err(host->dev, "Failed to get DLY1 delay!\n");
2675 goto fail;
2676 }
2677 if (host->top_base)
2678 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2679 PAD_DS_DLY1, dly1_delay.final_phase);
2680 else
2681 sdr_set_field(host->base + PAD_DS_TUNE,
2682 PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2683
2684 if (host->top_base)
2685 val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2686 else
2687 val = readl(host->base + PAD_DS_TUNE);
2688
2689 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2690
2691 return 0;
2692
2693 fail:
2694 dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2695 return -EIO;
2696 }
2697
msdc_hw_reset(struct mmc_host * mmc)2698 static void msdc_hw_reset(struct mmc_host *mmc)
2699 {
2700 struct msdc_host *host = mmc_priv(mmc);
2701
2702 sdr_set_bits(host->base + EMMC_IOCON, 1);
2703 udelay(10); /* 10us is enough */
2704 sdr_clr_bits(host->base + EMMC_IOCON, 1);
2705 }
2706
msdc_ack_sdio_irq(struct mmc_host * mmc)2707 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2708 {
2709 unsigned long flags;
2710 struct msdc_host *host = mmc_priv(mmc);
2711
2712 spin_lock_irqsave(&host->lock, flags);
2713 __msdc_enable_sdio_irq(host, 1);
2714 spin_unlock_irqrestore(&host->lock, flags);
2715 }
2716
msdc_get_cd(struct mmc_host * mmc)2717 static int msdc_get_cd(struct mmc_host *mmc)
2718 {
2719 struct msdc_host *host = mmc_priv(mmc);
2720 int val;
2721
2722 if (mmc->caps & MMC_CAP_NONREMOVABLE)
2723 return 1;
2724
2725 if (!host->internal_cd)
2726 return mmc_gpio_get_cd(mmc);
2727
2728 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2729 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2730 return !!val;
2731 else
2732 return !val;
2733 }
2734
msdc_hs400_enhanced_strobe(struct mmc_host * mmc,struct mmc_ios * ios)2735 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2736 struct mmc_ios *ios)
2737 {
2738 struct msdc_host *host = mmc_priv(mmc);
2739
2740 if (ios->enhanced_strobe) {
2741 msdc_prepare_hs400_tuning(mmc, ios);
2742 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2743 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2744 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2745
2746 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2747 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2748 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2749 } else {
2750 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2751 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2752 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2753
2754 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2755 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2756 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2757 }
2758 }
2759
msdc_cqe_cit_cal(struct msdc_host * host,u64 timer_ns)2760 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2761 {
2762 struct mmc_host *mmc = mmc_from_priv(host);
2763 struct cqhci_host *cq_host = mmc->cqe_private;
2764 u8 itcfmul;
2765 u64 hclk_freq, value;
2766
2767 /*
2768 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2769 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2770 * Send Status Command Idle Timer (CIT) value.
2771 */
2772 hclk_freq = (u64)clk_get_rate(host->h_clk);
2773 itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2774 switch (itcfmul) {
2775 case 0x0:
2776 do_div(hclk_freq, 1000);
2777 break;
2778 case 0x1:
2779 do_div(hclk_freq, 100);
2780 break;
2781 case 0x2:
2782 do_div(hclk_freq, 10);
2783 break;
2784 case 0x3:
2785 break;
2786 case 0x4:
2787 hclk_freq = hclk_freq * 10;
2788 break;
2789 default:
2790 host->cq_ssc1_time = 0x40;
2791 return;
2792 }
2793
2794 value = hclk_freq * timer_ns;
2795 do_div(value, 1000000000);
2796 host->cq_ssc1_time = value;
2797 }
2798
msdc_cqe_enable(struct mmc_host * mmc)2799 static void msdc_cqe_enable(struct mmc_host *mmc)
2800 {
2801 struct msdc_host *host = mmc_priv(mmc);
2802 struct cqhci_host *cq_host = mmc->cqe_private;
2803
2804 /* enable cmdq irq */
2805 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2806 /* enable busy check */
2807 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2808 /* default write data / busy timeout 20s */
2809 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2810 /* default read data timeout 1s */
2811 msdc_set_timeout(host, 1000000000ULL, 0);
2812
2813 /* Set the send status command idle timer */
2814 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2815 }
2816
msdc_cqe_disable(struct mmc_host * mmc,bool recovery)2817 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2818 {
2819 struct msdc_host *host = mmc_priv(mmc);
2820 unsigned int val = 0;
2821
2822 /* disable cmdq irq */
2823 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2824 /* disable busy check */
2825 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2826
2827 val = readl(host->base + MSDC_INT);
2828 writel(val, host->base + MSDC_INT);
2829
2830 if (recovery) {
2831 sdr_set_field(host->base + MSDC_DMA_CTRL,
2832 MSDC_DMA_CTRL_STOP, 1);
2833 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2834 !(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2835 return;
2836 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2837 !(val & MSDC_DMA_CFG_STS), 1, 3000)))
2838 return;
2839 msdc_reset_hw(host);
2840 }
2841 }
2842
msdc_cqe_pre_enable(struct mmc_host * mmc)2843 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2844 {
2845 struct cqhci_host *cq_host = mmc->cqe_private;
2846 u32 reg;
2847
2848 reg = cqhci_readl(cq_host, CQHCI_CFG);
2849 reg |= CQHCI_ENABLE;
2850 cqhci_writel(cq_host, reg, CQHCI_CFG);
2851 }
2852
msdc_cqe_post_disable(struct mmc_host * mmc)2853 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2854 {
2855 struct cqhci_host *cq_host = mmc->cqe_private;
2856 u32 reg;
2857
2858 reg = cqhci_readl(cq_host, CQHCI_CFG);
2859 reg &= ~CQHCI_ENABLE;
2860 cqhci_writel(cq_host, reg, CQHCI_CFG);
2861 }
2862
2863 static const struct mmc_host_ops mt_msdc_ops = {
2864 .post_req = msdc_post_req,
2865 .pre_req = msdc_pre_req,
2866 .request = msdc_ops_request,
2867 .set_ios = msdc_ops_set_ios,
2868 .get_ro = mmc_gpio_get_ro,
2869 .get_cd = msdc_get_cd,
2870 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2871 .enable_sdio_irq = msdc_enable_sdio_irq,
2872 .ack_sdio_irq = msdc_ack_sdio_irq,
2873 .start_signal_voltage_switch = msdc_ops_switch_volt,
2874 .card_busy = msdc_card_busy,
2875 .execute_tuning = msdc_execute_tuning,
2876 .prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2877 .execute_hs400_tuning = msdc_execute_hs400_tuning,
2878 .card_hw_reset = msdc_hw_reset,
2879 };
2880
2881 static const struct cqhci_host_ops msdc_cmdq_ops = {
2882 .enable = msdc_cqe_enable,
2883 .disable = msdc_cqe_disable,
2884 .pre_enable = msdc_cqe_pre_enable,
2885 .post_disable = msdc_cqe_post_disable,
2886 };
2887
msdc_of_property_parse(struct platform_device * pdev,struct msdc_host * host)2888 static void msdc_of_property_parse(struct platform_device *pdev,
2889 struct msdc_host *host)
2890 {
2891 struct mmc_host *mmc = mmc_from_priv(host);
2892
2893 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2894 &host->latch_ck);
2895
2896 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2897 &host->hs400_ds_delay);
2898
2899 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2900 &host->hs400_ds_dly3);
2901
2902 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2903 &host->hs200_cmd_int_delay);
2904
2905 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2906 &host->hs400_cmd_int_delay);
2907
2908 if (of_property_read_bool(pdev->dev.of_node,
2909 "mediatek,hs400-cmd-resp-sel-rising"))
2910 host->hs400_cmd_resp_sel_rising = true;
2911 else
2912 host->hs400_cmd_resp_sel_rising = false;
2913
2914 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step",
2915 &host->tuning_step)) {
2916 if (mmc->caps2 & MMC_CAP2_NO_MMC)
2917 host->tuning_step = PAD_DELAY_FULL;
2918 else
2919 host->tuning_step = PAD_DELAY_HALF;
2920 }
2921
2922 if (of_property_read_bool(pdev->dev.of_node,
2923 "supports-cqe"))
2924 host->cqhci = true;
2925 else
2926 host->cqhci = false;
2927 }
2928
msdc_of_clock_parse(struct platform_device * pdev,struct msdc_host * host)2929 static int msdc_of_clock_parse(struct platform_device *pdev,
2930 struct msdc_host *host)
2931 {
2932 int ret;
2933
2934 host->src_clk = devm_clk_get(&pdev->dev, "source");
2935 if (IS_ERR(host->src_clk))
2936 return PTR_ERR(host->src_clk);
2937
2938 host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2939 if (IS_ERR(host->h_clk))
2940 return PTR_ERR(host->h_clk);
2941
2942 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2943 if (IS_ERR(host->bus_clk))
2944 host->bus_clk = NULL;
2945
2946 /*source clock control gate is optional clock*/
2947 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2948 if (IS_ERR(host->src_clk_cg))
2949 return PTR_ERR(host->src_clk_cg);
2950
2951 /*
2952 * Fallback for legacy device-trees: src_clk and HCLK use the same
2953 * bit to control gating but they are parented to a different mux,
2954 * hence if our intention is to gate only the source, required
2955 * during a clk mode switch to avoid hw hangs, we need to gate
2956 * its parent (specified as a different clock only on new DTs).
2957 */
2958 if (!host->src_clk_cg) {
2959 host->src_clk_cg = clk_get_parent(host->src_clk);
2960 if (IS_ERR(host->src_clk_cg))
2961 return PTR_ERR(host->src_clk_cg);
2962 }
2963
2964 /* If present, always enable for this clock gate */
2965 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2966 if (IS_ERR(host->sys_clk_cg))
2967 host->sys_clk_cg = NULL;
2968
2969 host->bulk_clks[0].id = "pclk_cg";
2970 host->bulk_clks[1].id = "axi_cg";
2971 host->bulk_clks[2].id = "ahb_cg";
2972 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2973 host->bulk_clks);
2974 if (ret) {
2975 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2976 return ret;
2977 }
2978
2979 return 0;
2980 }
2981
msdc_drv_probe(struct platform_device * pdev)2982 static int msdc_drv_probe(struct platform_device *pdev)
2983 {
2984 struct mmc_host *mmc;
2985 struct msdc_host *host;
2986 int ret;
2987
2988 if (!pdev->dev.of_node) {
2989 dev_err(&pdev->dev, "No DT found\n");
2990 return -EINVAL;
2991 }
2992
2993 /* Allocate MMC host for this device */
2994 mmc = devm_mmc_alloc_host(&pdev->dev, sizeof(struct msdc_host));
2995 if (!mmc)
2996 return -ENOMEM;
2997
2998 host = mmc_priv(mmc);
2999 ret = mmc_of_parse(mmc);
3000 if (ret)
3001 return ret;
3002
3003 host->base = devm_platform_ioremap_resource(pdev, 0);
3004 if (IS_ERR(host->base))
3005 return PTR_ERR(host->base);
3006
3007 host->dev_comp = of_device_get_match_data(&pdev->dev);
3008
3009 if (host->dev_comp->needs_top_base) {
3010 host->top_base = devm_platform_ioremap_resource(pdev, 1);
3011 if (IS_ERR(host->top_base))
3012 return PTR_ERR(host->top_base);
3013 }
3014
3015 ret = mmc_regulator_get_supply(mmc);
3016 if (ret)
3017 return ret;
3018
3019 ret = msdc_of_clock_parse(pdev, host);
3020 if (ret)
3021 return ret;
3022
3023 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
3024 "hrst");
3025 if (IS_ERR(host->reset))
3026 return PTR_ERR(host->reset);
3027
3028 /* only eMMC has crypto property */
3029 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
3030 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
3031 if (IS_ERR(host->crypto_clk))
3032 return PTR_ERR(host->crypto_clk);
3033 else if (host->crypto_clk)
3034 mmc->caps2 |= MMC_CAP2_CRYPTO;
3035 }
3036
3037 host->irq = platform_get_irq(pdev, 0);
3038 if (host->irq < 0)
3039 return host->irq;
3040
3041 host->pinctrl = devm_pinctrl_get(&pdev->dev);
3042 if (IS_ERR(host->pinctrl))
3043 return dev_err_probe(&pdev->dev, PTR_ERR(host->pinctrl),
3044 "Cannot find pinctrl");
3045
3046 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
3047 if (IS_ERR(host->pins_default)) {
3048 dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
3049 return PTR_ERR(host->pins_default);
3050 }
3051
3052 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
3053 if (IS_ERR(host->pins_uhs)) {
3054 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
3055 return PTR_ERR(host->pins_uhs);
3056 }
3057
3058 /* Support for SDIO eint irq ? */
3059 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
3060 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
3061 if (host->eint_irq > 0) {
3062 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
3063 if (IS_ERR(host->pins_eint)) {
3064 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
3065 host->pins_eint = NULL;
3066 } else {
3067 device_init_wakeup(&pdev->dev, true);
3068 }
3069 }
3070 }
3071
3072 msdc_of_property_parse(pdev, host);
3073
3074 host->dev = &pdev->dev;
3075 host->src_clk_freq = clk_get_rate(host->src_clk);
3076 /* Set host parameters to mmc */
3077 mmc->ops = &mt_msdc_ops;
3078 if (host->dev_comp->clk_div_bits == 8)
3079 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
3080 else
3081 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
3082
3083 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
3084 !mmc_host_can_gpio_cd(mmc) &&
3085 host->dev_comp->use_internal_cd) {
3086 /*
3087 * Is removable but no GPIO declared, so
3088 * use internal functionality.
3089 */
3090 host->internal_cd = true;
3091 }
3092
3093 if (mmc->caps & MMC_CAP_SDIO_IRQ)
3094 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
3095
3096 mmc->caps |= MMC_CAP_CMD23;
3097 if (host->cqhci)
3098 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
3099 /* MMC core transfer sizes tunable parameters */
3100 mmc->max_segs = MAX_BD_NUM;
3101 if (host->dev_comp->support_64g)
3102 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
3103 else
3104 mmc->max_seg_size = BDMA_DESC_BUFLEN;
3105 mmc->max_blk_size = 2048;
3106 mmc->max_req_size = 512 * 1024;
3107 mmc->max_blk_count = mmc->max_req_size / 512;
3108 if (host->dev_comp->support_64g)
3109 host->dma_mask = DMA_BIT_MASK(36);
3110 else
3111 host->dma_mask = DMA_BIT_MASK(32);
3112 mmc_dev(mmc)->dma_mask = &host->dma_mask;
3113
3114 host->timeout_clks = 3 * 1048576;
3115 host->dma.gpd = dma_alloc_coherent(&pdev->dev,
3116 2 * sizeof(struct mt_gpdma_desc),
3117 &host->dma.gpd_addr, GFP_KERNEL);
3118 host->dma.bd = dma_alloc_coherent(&pdev->dev,
3119 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3120 &host->dma.bd_addr, GFP_KERNEL);
3121 if (!host->dma.gpd || !host->dma.bd) {
3122 ret = -ENOMEM;
3123 goto release_mem;
3124 }
3125 msdc_init_gpd_bd(host, &host->dma);
3126 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
3127 spin_lock_init(&host->lock);
3128
3129 platform_set_drvdata(pdev, mmc);
3130 ret = msdc_ungate_clock(host);
3131 if (ret) {
3132 dev_err(&pdev->dev, "Cannot ungate clocks!\n");
3133 goto release_clk;
3134 }
3135 msdc_init_hw(host);
3136
3137 if (mmc->caps2 & MMC_CAP2_CQE) {
3138 host->cq_host = devm_kzalloc(mmc->parent,
3139 sizeof(*host->cq_host),
3140 GFP_KERNEL);
3141 if (!host->cq_host) {
3142 ret = -ENOMEM;
3143 goto release;
3144 }
3145 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
3146 host->cq_host->mmio = host->base + 0x800;
3147 host->cq_host->ops = &msdc_cmdq_ops;
3148 ret = cqhci_init(host->cq_host, mmc, true);
3149 if (ret)
3150 goto release;
3151 mmc->max_segs = 128;
3152 /* cqhci 16bit length */
3153 /* 0 size, means 65536 so we don't have to -1 here */
3154 mmc->max_seg_size = 64 * 1024;
3155 /* Reduce CIT to 0x40 that corresponds to 2.35us */
3156 msdc_cqe_cit_cal(host, 2350);
3157 } else if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
3158 /* Use HSQ on eMMC/SD (but not on SDIO) if HW CQE not supported */
3159 struct mmc_hsq *hsq = devm_kzalloc(&pdev->dev, sizeof(*hsq), GFP_KERNEL);
3160 if (!hsq) {
3161 ret = -ENOMEM;
3162 goto release;
3163 }
3164
3165 ret = mmc_hsq_init(hsq, mmc);
3166 if (ret)
3167 goto release;
3168
3169 host->hsq_en = true;
3170 }
3171
3172 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
3173 IRQF_TRIGGER_NONE, pdev->name, host);
3174 if (ret)
3175 goto release;
3176
3177 pm_runtime_set_active(host->dev);
3178 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
3179 pm_runtime_use_autosuspend(host->dev);
3180 pm_runtime_enable(host->dev);
3181 ret = mmc_add_host(mmc);
3182
3183 if (ret)
3184 goto end;
3185
3186 return 0;
3187 end:
3188 pm_runtime_disable(host->dev);
3189 release:
3190 msdc_deinit_hw(host);
3191 release_clk:
3192 msdc_gate_clock(host);
3193 platform_set_drvdata(pdev, NULL);
3194 release_mem:
3195 device_init_wakeup(&pdev->dev, false);
3196 if (host->dma.gpd)
3197 dma_free_coherent(&pdev->dev,
3198 2 * sizeof(struct mt_gpdma_desc),
3199 host->dma.gpd, host->dma.gpd_addr);
3200 if (host->dma.bd)
3201 dma_free_coherent(&pdev->dev,
3202 MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3203 host->dma.bd, host->dma.bd_addr);
3204 return ret;
3205 }
3206
msdc_drv_remove(struct platform_device * pdev)3207 static void msdc_drv_remove(struct platform_device *pdev)
3208 {
3209 struct mmc_host *mmc;
3210 struct msdc_host *host;
3211
3212 mmc = platform_get_drvdata(pdev);
3213 host = mmc_priv(mmc);
3214
3215 pm_runtime_get_sync(host->dev);
3216
3217 platform_set_drvdata(pdev, NULL);
3218 mmc_remove_host(mmc);
3219 cancel_delayed_work_sync(&host->req_timeout);
3220 msdc_deinit_hw(host);
3221 msdc_gate_clock(host);
3222
3223 pm_runtime_disable(host->dev);
3224 pm_runtime_put_noidle(host->dev);
3225 dma_free_coherent(&pdev->dev,
3226 2 * sizeof(struct mt_gpdma_desc),
3227 host->dma.gpd, host->dma.gpd_addr);
3228 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
3229 host->dma.bd, host->dma.bd_addr);
3230 device_init_wakeup(&pdev->dev, false);
3231 }
3232
msdc_save_reg(struct msdc_host * host)3233 static void msdc_save_reg(struct msdc_host *host)
3234 {
3235 u32 tune_reg = host->dev_comp->pad_tune_reg;
3236
3237 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
3238 host->save_para.iocon = readl(host->base + MSDC_IOCON);
3239 host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
3240 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
3241 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
3242 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
3243 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
3244 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
3245 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
3246 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
3247 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
3248 if (host->top_base) {
3249 host->save_para.emmc_top_control =
3250 readl(host->top_base + EMMC_TOP_CONTROL);
3251 host->save_para.emmc_top_cmd =
3252 readl(host->top_base + EMMC_TOP_CMD);
3253 host->save_para.emmc50_pad_ds_tune =
3254 readl(host->top_base + EMMC50_PAD_DS_TUNE);
3255 host->save_para.loop_test_control =
3256 readl(host->top_base + LOOP_TEST_CONTROL);
3257 } else {
3258 host->save_para.pad_tune = readl(host->base + tune_reg);
3259 }
3260 }
3261
msdc_restore_reg(struct msdc_host * host)3262 static void msdc_restore_reg(struct msdc_host *host)
3263 {
3264 struct mmc_host *mmc = mmc_from_priv(host);
3265 u32 tune_reg = host->dev_comp->pad_tune_reg;
3266
3267 if (host->dev_comp->support_new_tx) {
3268 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3269 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_NEW_TX_EN);
3270 }
3271 if (host->dev_comp->support_new_rx) {
3272 sdr_clr_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3273 sdr_set_bits(host->base + MSDC_NEW_RX_CFG, MSDC_NEW_RX_PATH_SEL);
3274 }
3275
3276 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3277 writel(host->save_para.iocon, host->base + MSDC_IOCON);
3278 writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3279 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3280 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3281 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3282 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3283 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3284 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3285 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3286 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3287 if (host->top_base) {
3288 writel(host->save_para.emmc_top_control,
3289 host->top_base + EMMC_TOP_CONTROL);
3290 writel(host->save_para.emmc_top_cmd,
3291 host->top_base + EMMC_TOP_CMD);
3292 writel(host->save_para.emmc50_pad_ds_tune,
3293 host->top_base + EMMC50_PAD_DS_TUNE);
3294 writel(host->save_para.loop_test_control,
3295 host->top_base + LOOP_TEST_CONTROL);
3296 } else {
3297 writel(host->save_para.pad_tune, host->base + tune_reg);
3298 }
3299
3300 if (sdio_irq_claimed(mmc))
3301 __msdc_enable_sdio_irq(host, 1);
3302 }
3303
msdc_runtime_suspend(struct device * dev)3304 static int msdc_runtime_suspend(struct device *dev)
3305 {
3306 struct mmc_host *mmc = dev_get_drvdata(dev);
3307 struct msdc_host *host = mmc_priv(mmc);
3308
3309 if (host->hsq_en)
3310 mmc_hsq_suspend(mmc);
3311
3312 msdc_save_reg(host);
3313
3314 if (sdio_irq_claimed(mmc)) {
3315 if (host->pins_eint) {
3316 disable_irq(host->irq);
3317 pinctrl_select_state(host->pinctrl, host->pins_eint);
3318 }
3319
3320 __msdc_enable_sdio_irq(host, 0);
3321 }
3322
3323 if (host->dev_comp->support_spm_res_release)
3324 sdr_set_bits(host->base + SDC_STS, SDC_STS_SPM_RESOURCE_RELEASE);
3325
3326 msdc_gate_clock(host);
3327 return 0;
3328 }
3329
msdc_runtime_resume(struct device * dev)3330 static int msdc_runtime_resume(struct device *dev)
3331 {
3332 struct mmc_host *mmc = dev_get_drvdata(dev);
3333 struct msdc_host *host = mmc_priv(mmc);
3334 int ret;
3335
3336 ret = msdc_ungate_clock(host);
3337 if (ret)
3338 return ret;
3339
3340 msdc_restore_reg(host);
3341
3342 if (sdio_irq_claimed(mmc) && host->pins_eint) {
3343 pinctrl_select_state(host->pinctrl, host->pins_uhs);
3344 enable_irq(host->irq);
3345 }
3346
3347 if (host->hsq_en)
3348 mmc_hsq_resume(mmc);
3349
3350 return 0;
3351 }
3352
msdc_suspend(struct device * dev)3353 static int msdc_suspend(struct device *dev)
3354 {
3355 struct mmc_host *mmc = dev_get_drvdata(dev);
3356 struct msdc_host *host = mmc_priv(mmc);
3357 int ret;
3358 u32 val;
3359
3360 if (mmc->caps2 & MMC_CAP2_CQE) {
3361 ret = cqhci_suspend(mmc);
3362 if (ret)
3363 return ret;
3364 val = readl(host->base + MSDC_INT);
3365 writel(val, host->base + MSDC_INT);
3366 }
3367
3368 /*
3369 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3370 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3371 */
3372 if (sdio_irq_claimed(mmc) && host->pins_eint)
3373 pm_runtime_get_noresume(dev);
3374
3375 return pm_runtime_force_suspend(dev);
3376 }
3377
msdc_resume(struct device * dev)3378 static int msdc_resume(struct device *dev)
3379 {
3380 struct mmc_host *mmc = dev_get_drvdata(dev);
3381 struct msdc_host *host = mmc_priv(mmc);
3382
3383 if (sdio_irq_claimed(mmc) && host->pins_eint)
3384 pm_runtime_put_noidle(dev);
3385
3386 return pm_runtime_force_resume(dev);
3387 }
3388
3389 static const struct dev_pm_ops msdc_dev_pm_ops = {
3390 SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3391 RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3392 };
3393
3394 static struct platform_driver mt_msdc_driver = {
3395 .probe = msdc_drv_probe,
3396 .remove = msdc_drv_remove,
3397 .driver = {
3398 .name = "mtk-msdc",
3399 .probe_type = PROBE_PREFER_ASYNCHRONOUS,
3400 .of_match_table = msdc_of_ids,
3401 .pm = pm_ptr(&msdc_dev_pm_ops),
3402 },
3403 };
3404
3405 module_platform_driver(mt_msdc_driver);
3406 MODULE_LICENSE("GPL v2");
3407 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3408