1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 4 * 5 * 6 * Name: mpi2_cnfg.h 7 * Title: MPI Configuration messages and pages 8 * Creation Date: November 10, 2006 9 * 10 * mpi2_cnfg.h Version: 02.00.47 11 * 12 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 13 * prefix are for use only on MPI v2.5 products, and must not be used 14 * with MPI v2.0 products. Unless otherwise noted, names beginning with 15 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 16 * 17 * Version History 18 * --------------- 19 * 20 * Date Version Description 21 * -------- -------- ------------------------------------------------------ 22 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 23 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 24 * Added Manufacturing Page 11. 25 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 26 * define. 27 * 06-26-07 02.00.02 Adding generic structure for product-specific 28 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 29 * Rework of BIOS Page 2 configuration page. 30 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 31 * forms. 32 * Added configuration pages IOC Page 8 and Driver 33 * Persistent Mapping Page 0. 34 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 35 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 36 * RAID Physical Disk Pages 0 and 1, RAID Configuration 37 * Page 0). 38 * Added new value for AccessStatus field of SAS Device 39 * Page 0 (_SATA_NEEDS_INITIALIZATION). 40 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 41 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 42 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 43 * NVDATA. 44 * Modified IOC Page 7 to use masks and added field for 45 * SASBroadcastPrimitiveMasks. 46 * Added MPI2_CONFIG_PAGE_BIOS_4. 47 * Added MPI2_CONFIG_PAGE_LOG_0. 48 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 49 * Added SAS Device IDs. 50 * Updated Integrated RAID configuration pages including 51 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 52 * Page 0. 53 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 54 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 55 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 56 * Added missing MaxNumRoutedSasAddresses field to 57 * MPI2_CONFIG_PAGE_EXPANDER_0. 58 * Added SAS Port Page 0. 59 * Modified structure layout for 60 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 61 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 62 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 63 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 64 * to 0x000000FF. 65 * Added two new values for the Physical Disk Coercion Size 66 * bits in the Flags field of Manufacturing Page 4. 67 * Added product-specific Manufacturing pages 16 to 31. 68 * Modified Flags bits for controlling write cache on SATA 69 * drives in IO Unit Page 1. 70 * Added new bit to AdditionalControlFlags of SAS IO Unit 71 * Page 1 to control Invalid Topology Correction. 72 * Added additional defines for RAID Volume Page 0 73 * VolumeStatusFlags field. 74 * Modified meaning of RAID Volume Page 0 VolumeSettings 75 * define for auto-configure of hot-swap drives. 76 * Added SupportedPhysDisks field to RAID Volume Page 1 and 77 * added related defines. 78 * Added PhysDiskAttributes field (and related defines) to 79 * RAID Physical Disk Page 0. 80 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 81 * Added three new DiscoveryStatus bits for SAS IO Unit 82 * Page 0 and SAS Expander Page 0. 83 * Removed multiplexing information from SAS IO Unit pages. 84 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 85 * Removed Zone Address Resolved bit from PhyInfo and from 86 * Expander Page 0 Flags field. 87 * Added two new AccessStatus values to SAS Device Page 0 88 * for indicating routing problems. Added 3 reserved words 89 * to this page. 90 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 91 * Inserted missing reserved field into structure for IOC 92 * Page 6. 93 * Added more pending task bits to RAID Volume Page 0 94 * VolumeStatusFlags defines. 95 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 96 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 97 * and SAS Expander Page 0 to flag a downstream initiator 98 * when in simplified routing mode. 99 * Removed SATA Init Failure defines for DiscoveryStatus 100 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 101 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 102 * Added PortGroups, DmaGroup, and ControlGroup fields to 103 * SAS Device Page 0. 104 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 105 * Unit Page 6. 106 * Added expander reduced functionality data to SAS 107 * Expander Page 0. 108 * Added SAS PHY Page 2 and SAS PHY Page 3. 109 * 07-30-09 02.00.12 Added IO Unit Page 7. 110 * Added new device ids. 111 * Added SAS IO Unit Page 5. 112 * Added partial and slumber power management capable flags 113 * to SAS Device Page 0 Flags field. 114 * Added PhyInfo defines for power condition. 115 * Added Ethernet configuration pages. 116 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 117 * Added SAS PHY Page 4 structure and defines. 118 * 02-10-10 02.00.14 Modified the comments for the configuration page 119 * structures that contain an array of data. The host 120 * should use the "count" field in the page data (e.g. the 121 * NumPhys field) to determine the number of valid elements 122 * in the array. 123 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 124 * Added PowerManagementCapabilities to IO Unit Page 7. 125 * Added PortWidthModGroup field to 126 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 127 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 128 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 129 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 130 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 131 * define. 132 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 133 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 134 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 135 * defines. 136 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 137 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 138 * the Pinout field. 139 * Added BoardTemperature and BoardTemperatureUnits fields 140 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 141 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 142 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 143 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 144 * Added IO Unit Page 8, IO Unit Page 9, 145 * and IO Unit Page 10. 146 * Added SASNotifyPrimitiveMasks field to 147 * MPI2_CONFIG_PAGE_IOC_7. 148 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 149 * 05-25-11 02.00.20 Cleaned up a few comments. 150 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 151 * for PCIe link as obsolete. 152 * Added SpinupFlags field containing a Disable Spin-up bit 153 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 154 * Unit Page 4. 155 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 156 * Added UEFIVersion field to BIOS Page 1 and defined new 157 * BiosOptions bits. 158 * Incorporating additions for MPI v2.5. 159 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 160 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 161 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 162 * obsolete for MPI v2.5 and later. 163 * Added some defines for 12G SAS speeds. 164 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 165 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 166 * match the specification. 167 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 168 * future use. 169 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 170 * MPI2_CONFIG_PAGE_MAN_7. 171 * Added EnclosureLevel and ConnectorName fields to 172 * MPI2_CONFIG_PAGE_SAS_DEV_0. 173 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 174 * MPI2_CONFIG_PAGE_SAS_DEV_0. 175 * Added EnclosureLevel field to 176 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 177 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 178 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 179 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 180 * MPI2_CONFIG_PAGE_BIOS_1. 181 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 182 * more defines for the BiosOptions field. 183 * 11-18-14 02.00.30 Updated copyright information. 184 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 185 * Added AdapterOrderAux fields to BIOS Page 3. 186 * 03-16-15 02.00.31 Updated for MPI v2.6. 187 * Added Flags field to IO Unit Page 7. 188 * Added new SAS Phy Event codes 189 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 190 * MPI2_CONFIG_PAGE_BIOS_1. 191 * 08-25-15 02.00.34 Bumped Header Version. 192 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 193 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 194 * Added Link field to PCIe Link Pages 195 * Added EnclosureLevel and ConnectorName to PCIe 196 * Device Page 0. 197 * Added define for PCIE IoUnit page 1 max rate shift. 198 * Added comment for reserved ExtPageTypes. 199 * Added SAS 4 22.5 gbs speed support. 200 * Added PCIe 4 16.0 GT/sec speec support. 201 * Removed AHCI support. 202 * Removed SOP support. 203 * Added NegotiatedLinkRate and NegotiatedPortWidth to 204 * PCIe device page 0. 205 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 206 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 207 * Changed declaration of ConnectorName in PCIe DevicePage0 208 * to match SAS DevicePage 0. 209 * Added SATADeviceWaitTime to IO Unit Page 11. 210 * Added MPI26_MFGPAGE_DEVID_SAS4008 211 * Added x16 PCIe width to IO Unit Page 7 212 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 213 * phy data. 214 * Added InitStatus to PCIe IO Unit Page 1 header. 215 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 216 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 217 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 218 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 219 * Added ChassisSlot field to SAS Enclosure Page 0. 220 * Added ChassisSlot Valid bit (bit 5) to the Flags field 221 * in SAS Enclosure Page 0. 222 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and 223 * MPI26_MFGPAGE_DEVID_SAS3916 defines. 224 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. 225 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. 226 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to 227 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. 228 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to 229 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. 230 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. 231 * Added NOIOB field to PCIe Device Page 2. 232 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to 233 * the Capabilities field of PCIe Device Page 2. 234 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816. 235 * Added WRiteCache defines to IO Unit Page 1. 236 * Added MaxEnclosureLevel to BIOS Page 1. 237 * Added OEMRD to SAS Enclosure Page 1. 238 * Added DMDReportPCIe to PCIe IO Unit Page 1. 239 * Added Flags field and flags for Retimers to 240 * PCIe Switch Page 1. 241 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. 242 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 243 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1 244 * Added DMDReport Delay Time defines to 245 * PCIeIOUnitPage1 246 * -------------------------------------------------------------------------- 247 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. 248 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 249 * 08-28-18 02.00.46 Added NVMs Write Cache flag to IOUnitPage1 250 * Added DMDReport Delay Time defines to PCIeIOUnitPage1 251 * 12-17-18 02.00.47 Swap locations of Slotx2 and Slotx4 in ManPage 7. 252 * 08-01-19 02.00.49 Add MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID 253 * Add MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT 254 * 09-13-24 02.00.50 Added PCIe 32 GT/s link rate 255 */ 256 257 #ifndef MPI2_CNFG_H 258 #define MPI2_CNFG_H 259 260 /***************************************************************************** 261 * Configuration Page Header and defines 262 *****************************************************************************/ 263 264 /*Config Page Header */ 265 typedef struct _MPI2_CONFIG_PAGE_HEADER { 266 U8 PageVersion; /*0x00 */ 267 U8 PageLength; /*0x01 */ 268 U8 PageNumber; /*0x02 */ 269 U8 PageType; /*0x03 */ 270 } MPI2_CONFIG_PAGE_HEADER, *PTR_MPI2_CONFIG_PAGE_HEADER, 271 Mpi2ConfigPageHeader_t, *pMpi2ConfigPageHeader_t; 272 273 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION { 274 MPI2_CONFIG_PAGE_HEADER Struct; 275 U8 Bytes[4]; 276 U16 Word16[2]; 277 U32 Word32; 278 } MPI2_CONFIG_PAGE_HEADER_UNION, *PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 279 Mpi2ConfigPageHeaderUnion, *pMpi2ConfigPageHeaderUnion; 280 281 /*Extended Config Page Header */ 282 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER { 283 U8 PageVersion; /*0x00 */ 284 U8 Reserved1; /*0x01 */ 285 U8 PageNumber; /*0x02 */ 286 U8 PageType; /*0x03 */ 287 U16 ExtPageLength; /*0x04 */ 288 U8 ExtPageType; /*0x06 */ 289 U8 Reserved2; /*0x07 */ 290 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 291 *PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 292 Mpi2ConfigExtendedPageHeader_t, 293 *pMpi2ConfigExtendedPageHeader_t; 294 295 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION { 296 MPI2_CONFIG_PAGE_HEADER Struct; 297 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 298 U8 Bytes[8]; 299 U16 Word16[4]; 300 U32 Word32[2]; 301 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 302 *PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 303 Mpi2ConfigPageExtendedHeaderUnion, 304 *pMpi2ConfigPageExtendedHeaderUnion; 305 306 307 /*PageType field values */ 308 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 309 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 310 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 311 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 312 313 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 314 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 315 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 316 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 317 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 318 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 319 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 320 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 321 322 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 323 324 325 /*ExtPageType field values */ 326 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 327 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 328 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 329 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 330 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 331 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 332 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 333 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 334 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 335 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 336 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 337 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) 338 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) 339 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) 340 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) 341 342 343 /***************************************************************************** 344 * PageAddress defines 345 *****************************************************************************/ 346 347 /*RAID Volume PageAddress format */ 348 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 349 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 350 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 351 352 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 353 354 355 /*RAID Physical Disk PageAddress format */ 356 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 357 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 358 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 359 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 360 361 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 362 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 363 364 365 /*SAS Expander PageAddress format */ 366 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 367 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 368 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 369 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 370 371 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 372 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 373 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 374 375 376 /*SAS Device PageAddress format */ 377 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 378 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 379 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 380 381 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 382 383 384 /*SAS PHY PageAddress format */ 385 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 386 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 387 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 388 389 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 390 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 391 392 393 /*SAS Port PageAddress format */ 394 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 395 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 396 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 397 398 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 399 400 401 /*SAS Enclosure PageAddress format */ 402 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 403 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 404 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 405 406 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 407 408 /*Enclosure PageAddress format */ 409 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 410 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 411 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 412 413 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 414 415 /*RAID Configuration PageAddress format */ 416 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 417 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 418 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 419 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 420 421 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 422 423 424 /*Driver Persistent Mapping PageAddress format */ 425 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 426 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 427 428 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 429 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 430 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 431 432 433 /*Ethernet PageAddress format */ 434 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 435 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 436 437 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 438 439 440 /*PCIe Switch PageAddress format */ 441 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 442 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 443 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 444 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 445 446 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 447 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 448 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 449 450 451 /*PCIe Device PageAddress format */ 452 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 453 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 454 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 455 456 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 457 458 /*PCIe Link PageAddress format */ 459 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 460 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 461 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 462 463 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 464 465 466 467 /**************************************************************************** 468 * Configuration messages 469 ****************************************************************************/ 470 471 /*Configuration Request Message */ 472 typedef struct _MPI2_CONFIG_REQUEST { 473 U8 Action; /*0x00 */ 474 U8 SGLFlags; /*0x01 */ 475 U8 ChainOffset; /*0x02 */ 476 U8 Function; /*0x03 */ 477 U16 ExtPageLength; /*0x04 */ 478 U8 ExtPageType; /*0x06 */ 479 U8 MsgFlags; /*0x07 */ 480 U8 VP_ID; /*0x08 */ 481 U8 VF_ID; /*0x09 */ 482 U16 Reserved1; /*0x0A */ 483 U8 Reserved2; /*0x0C */ 484 U8 ProxyVF_ID; /*0x0D */ 485 U16 Reserved4; /*0x0E */ 486 U32 Reserved3; /*0x10 */ 487 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 488 U32 PageAddress; /*0x18 */ 489 MPI2_SGE_IO_UNION PageBufferSGE; /*0x1C */ 490 } MPI2_CONFIG_REQUEST, *PTR_MPI2_CONFIG_REQUEST, 491 Mpi2ConfigRequest_t, *pMpi2ConfigRequest_t; 492 493 /*values for the Action field */ 494 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 495 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 496 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 497 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 498 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 499 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 500 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 501 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 502 503 /*use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 504 505 506 /*Config Reply Message */ 507 typedef struct _MPI2_CONFIG_REPLY { 508 U8 Action; /*0x00 */ 509 U8 SGLFlags; /*0x01 */ 510 U8 MsgLength; /*0x02 */ 511 U8 Function; /*0x03 */ 512 U16 ExtPageLength; /*0x04 */ 513 U8 ExtPageType; /*0x06 */ 514 U8 MsgFlags; /*0x07 */ 515 U8 VP_ID; /*0x08 */ 516 U8 VF_ID; /*0x09 */ 517 U16 Reserved1; /*0x0A */ 518 U16 Reserved2; /*0x0C */ 519 U16 IOCStatus; /*0x0E */ 520 U32 IOCLogInfo; /*0x10 */ 521 MPI2_CONFIG_PAGE_HEADER Header; /*0x14 */ 522 } MPI2_CONFIG_REPLY, *PTR_MPI2_CONFIG_REPLY, 523 Mpi2ConfigReply_t, *pMpi2ConfigReply_t; 524 525 526 527 /***************************************************************************** 528 * 529 * C o n f i g u r a t i o n P a g e s 530 * 531 *****************************************************************************/ 532 533 /**************************************************************************** 534 * Manufacturing Config pages 535 ****************************************************************************/ 536 537 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 538 #define MPI2_MFGPAGE_VENDORID_ATTO (0x117C) 539 540 /*MPI v2.0 SAS products */ 541 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 542 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 543 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 544 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 545 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 546 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 547 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 548 549 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 550 551 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 552 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 553 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 554 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 555 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 556 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 557 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 558 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 559 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 560 #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP (0x02B0) 561 #define MPI2_MFGPAGE_DEVID_SWITCH_MPI_EP_1 (0x02B1) 562 563 /*MPI v2.5 SAS products */ 564 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 565 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 566 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 567 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 568 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 569 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 570 571 /* MPI v2.6 SAS Products */ 572 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 573 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 574 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 575 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 576 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 577 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 578 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 579 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 580 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 581 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 582 583 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 584 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 585 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 586 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 587 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 588 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 589 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 590 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 591 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 592 593 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3916 (0x0003) 594 #define MPI26_MFGPAGE_DEVID_INVALID0_3916 (0x00E0) 595 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3916 (0x00E1) 596 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3916 (0x00E2) 597 #define MPI26_MFGPAGE_DEVID_INVALID1_3916 (0x00E3) 598 599 #define MPI26_MFGPAGE_DEVID_SEC_MASK_3816 (0x0003) 600 #define MPI26_MFGPAGE_DEVID_INVALID0_3816 (0x00E4) 601 #define MPI26_MFGPAGE_DEVID_CFG_SEC_3816 (0x00E5) 602 #define MPI26_MFGPAGE_DEVID_HARD_SEC_3816 (0x00E6) 603 #define MPI26_MFGPAGE_DEVID_INVALID1_3816 (0x00E7) 604 605 606 /*Manufacturing Page 0 */ 607 608 typedef struct _MPI2_CONFIG_PAGE_MAN_0 { 609 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 610 U8 ChipName[16] __nonstring; /*0x04 */ 611 U8 ChipRevision[8]; /*0x14 */ 612 U8 BoardName[16]; /*0x1C */ 613 U8 BoardAssembly[16]; /*0x2C */ 614 U8 BoardTracerNumber[16]; /*0x3C */ 615 } MPI2_CONFIG_PAGE_MAN_0, 616 *PTR_MPI2_CONFIG_PAGE_MAN_0, 617 Mpi2ManufacturingPage0_t, 618 *pMpi2ManufacturingPage0_t; 619 620 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 621 622 623 /*Manufacturing Page 1 */ 624 625 typedef struct _MPI2_CONFIG_PAGE_MAN_1 { 626 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 627 U8 VPD[256]; /*0x04 */ 628 } MPI2_CONFIG_PAGE_MAN_1, 629 *PTR_MPI2_CONFIG_PAGE_MAN_1, 630 Mpi2ManufacturingPage1_t, 631 *pMpi2ManufacturingPage1_t; 632 633 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 634 635 636 typedef struct _MPI2_CHIP_REVISION_ID { 637 U16 DeviceID; /*0x00 */ 638 U8 PCIRevisionID; /*0x02 */ 639 U8 Reserved; /*0x03 */ 640 } MPI2_CHIP_REVISION_ID, *PTR_MPI2_CHIP_REVISION_ID, 641 Mpi2ChipRevisionId_t, *pMpi2ChipRevisionId_t; 642 643 644 /*Manufacturing Page 2 */ 645 646 /* 647 *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at 648 *runtime before using HwSettings[]. 649 */ 650 651 typedef struct _MPI2_CONFIG_PAGE_MAN_2 { 652 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 653 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 654 U32 HwSettings[]; /*0x08 */ 655 } MPI2_CONFIG_PAGE_MAN_2, 656 *PTR_MPI2_CONFIG_PAGE_MAN_2, 657 Mpi2ManufacturingPage2_t, 658 *pMpi2ManufacturingPage2_t; 659 660 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 661 662 663 /*Manufacturing Page 3 */ 664 665 /* 666 *Host code (drivers, BIOS, utilities, etc.) should check Header.PageLength at 667 *runtime before using Info[]. 668 */ 669 670 typedef struct _MPI2_CONFIG_PAGE_MAN_3 { 671 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 672 MPI2_CHIP_REVISION_ID ChipId; /*0x04 */ 673 U32 Info[]; /*0x08 */ 674 } MPI2_CONFIG_PAGE_MAN_3, 675 *PTR_MPI2_CONFIG_PAGE_MAN_3, 676 Mpi2ManufacturingPage3_t, 677 *pMpi2ManufacturingPage3_t; 678 679 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 680 681 682 /*Manufacturing Page 4 */ 683 684 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS { 685 U8 PowerSaveFlags; /*0x00 */ 686 U8 InternalOperationsSleepTime; /*0x01 */ 687 U8 InternalOperationsRunTime; /*0x02 */ 688 U8 HostIdleTime; /*0x03 */ 689 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 690 *PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 691 Mpi2ManPage4PwrSaveSettings_t, 692 *pMpi2ManPage4PwrSaveSettings_t; 693 694 /*defines for the PowerSaveFlags field */ 695 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 696 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 697 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 698 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 699 700 typedef struct _MPI2_CONFIG_PAGE_MAN_4 { 701 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 702 U32 Reserved1; /*0x04 */ 703 U32 Flags; /*0x08 */ 704 U8 InquirySize; /*0x0C */ 705 U8 Reserved2; /*0x0D */ 706 U16 Reserved3; /*0x0E */ 707 U8 InquiryData[56]; /*0x10 */ 708 U32 RAID0VolumeSettings; /*0x48 */ 709 U32 RAID1EVolumeSettings; /*0x4C */ 710 U32 RAID1VolumeSettings; /*0x50 */ 711 U32 RAID10VolumeSettings; /*0x54 */ 712 U32 Reserved4; /*0x58 */ 713 U32 Reserved5; /*0x5C */ 714 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /*0x60 */ 715 U8 MaxOCEDisks; /*0x64 */ 716 U8 ResyncRate; /*0x65 */ 717 U16 DataScrubDuration; /*0x66 */ 718 U8 MaxHotSpares; /*0x68 */ 719 U8 MaxPhysDisksPerVol; /*0x69 */ 720 U8 MaxPhysDisks; /*0x6A */ 721 U8 MaxVolumes; /*0x6B */ 722 } MPI2_CONFIG_PAGE_MAN_4, 723 *PTR_MPI2_CONFIG_PAGE_MAN_4, 724 Mpi2ManufacturingPage4_t, 725 *pMpi2ManufacturingPage4_t; 726 727 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 728 729 /*Manufacturing Page 4 Flags field */ 730 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 731 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 732 733 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 734 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 735 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 736 737 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 738 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 739 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 740 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 741 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 742 743 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 744 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 745 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 746 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 747 748 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 749 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 750 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 751 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 752 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 753 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 754 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 755 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 756 757 758 /*Manufacturing Page 5 */ 759 760 /* 761 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 762 *for NumPhys at runtime before using Phy[]. 763 */ 764 765 typedef struct _MPI2_MANUFACTURING5_ENTRY { 766 U64 WWID; /*0x00 */ 767 U64 DeviceName; /*0x08 */ 768 } MPI2_MANUFACTURING5_ENTRY, 769 *PTR_MPI2_MANUFACTURING5_ENTRY, 770 Mpi2Manufacturing5Entry_t, 771 *pMpi2Manufacturing5Entry_t; 772 773 typedef struct _MPI2_CONFIG_PAGE_MAN_5 { 774 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 775 U8 NumPhys; /*0x04 */ 776 U8 Reserved1; /*0x05 */ 777 U16 Reserved2; /*0x06 */ 778 U32 Reserved3; /*0x08 */ 779 U32 Reserved4; /*0x0C */ 780 MPI2_MANUFACTURING5_ENTRY Phy[]; /*0x10 */ 781 } MPI2_CONFIG_PAGE_MAN_5, 782 *PTR_MPI2_CONFIG_PAGE_MAN_5, 783 Mpi2ManufacturingPage5_t, 784 *pMpi2ManufacturingPage5_t; 785 786 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 787 788 789 /*Manufacturing Page 6 */ 790 791 typedef struct _MPI2_CONFIG_PAGE_MAN_6 { 792 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 793 U32 ProductSpecificInfo;/*0x04 */ 794 } MPI2_CONFIG_PAGE_MAN_6, 795 *PTR_MPI2_CONFIG_PAGE_MAN_6, 796 Mpi2ManufacturingPage6_t, 797 *pMpi2ManufacturingPage6_t; 798 799 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 800 801 802 /*Manufacturing Page 7 */ 803 804 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO { 805 U32 Pinout; /*0x00 */ 806 U8 Connector[16]; /*0x04 */ 807 U8 Location; /*0x14 */ 808 U8 ReceptacleID; /*0x15 */ 809 U16 Slot; /*0x16 */ 810 U16 Slotx2; /*0x18 */ 811 U16 Slotx4; /*0x1A */ 812 } MPI2_MANPAGE7_CONNECTOR_INFO, 813 *PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 814 Mpi2ManPage7ConnectorInfo_t, 815 *pMpi2ManPage7ConnectorInfo_t; 816 817 /*defines for the Pinout field */ 818 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 819 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 820 821 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 822 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 823 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 824 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 825 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 826 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 827 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 828 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 829 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 830 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 831 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 832 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 833 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 834 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 835 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 836 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 837 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 838 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 839 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 840 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 841 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 842 843 /*defines for the Location field */ 844 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 845 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 846 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 847 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 848 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 849 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 850 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 851 852 /*defines for the Slot field */ 853 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 854 855 /* 856 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 857 *for NumPhys at runtime before using ConnectorInfo[]. 858 */ 859 860 typedef struct _MPI2_CONFIG_PAGE_MAN_7 { 861 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 862 U32 Reserved1; /*0x04 */ 863 U32 Reserved2; /*0x08 */ 864 U32 Flags; /*0x0C */ 865 U8 EnclosureName[16]; /*0x10 */ 866 U8 NumPhys; /*0x20 */ 867 U8 Reserved3; /*0x21 */ 868 U16 Reserved4; /*0x22 */ 869 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[]; /*0x24 */ 870 } MPI2_CONFIG_PAGE_MAN_7, 871 *PTR_MPI2_CONFIG_PAGE_MAN_7, 872 Mpi2ManufacturingPage7_t, 873 *pMpi2ManufacturingPage7_t; 874 875 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 876 877 /*defines for the Flags field */ 878 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 879 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 880 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 881 882 #define MPI26_MANPAGE7_FLAG_CONN_LANE_USE_PINOUT (0x00000020) 883 #define MPI26_MANPAGE7_FLAG_X2_X4_SLOT_INFO_VALID (0x00000010) 884 885 /* 886 *Generic structure to use for product-specific manufacturing pages 887 *(currently Manufacturing Page 8 through Manufacturing Page 31). 888 */ 889 890 typedef struct _MPI2_CONFIG_PAGE_MAN_PS { 891 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 892 U32 ProductSpecificInfo;/*0x04 */ 893 } MPI2_CONFIG_PAGE_MAN_PS, 894 *PTR_MPI2_CONFIG_PAGE_MAN_PS, 895 Mpi2ManufacturingPagePS_t, 896 *pMpi2ManufacturingPagePS_t; 897 898 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 899 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 900 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 901 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 902 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 903 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 904 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 905 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 906 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 907 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 908 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 909 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 910 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 911 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 912 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 913 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 914 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 915 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 916 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 917 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 918 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 919 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 920 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 921 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 922 923 924 /**************************************************************************** 925 * IO Unit Config Pages 926 ****************************************************************************/ 927 928 /*IO Unit Page 0 */ 929 930 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 { 931 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 932 U64 UniqueValue; /*0x04 */ 933 MPI2_VERSION_UNION NvdataVersionDefault; /*0x08 */ 934 MPI2_VERSION_UNION NvdataVersionPersistent; /*0x0A */ 935 } MPI2_CONFIG_PAGE_IO_UNIT_0, 936 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 937 Mpi2IOUnitPage0_t, *pMpi2IOUnitPage0_t; 938 939 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 940 941 942 /*IO Unit Page 1 */ 943 944 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 { 945 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 946 U32 Flags; /*0x04 */ 947 } MPI2_CONFIG_PAGE_IO_UNIT_1, 948 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 949 Mpi2IOUnitPage1_t, *pMpi2IOUnitPage1_t; 950 951 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 952 953 /* IO Unit Page 1 Flags defines */ 954 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_MASK (0x00030000) 955 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_SHIFT (16) 956 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_NO_CHANGE (0x00000000) 957 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_ENABLE (0x00010000) 958 #define MPI26_IOUNITPAGE1_NVME_WRCACHE_DISABLE (0x00020000) 959 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 960 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 961 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 962 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 963 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 964 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 965 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 966 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 967 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 968 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 969 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 970 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 971 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 972 973 974 /*IO Unit Page 3 */ 975 976 /* 977 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 978 *36 and check the value returned for GPIOCount at runtime. 979 */ 980 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 981 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (36) 982 #endif 983 984 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 { 985 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 986 U8 GPIOCount; /*0x04 */ 987 U8 Reserved1; /*0x05 */ 988 U16 Reserved2; /*0x06 */ 989 U16 990 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/*0x08 */ 991 } MPI2_CONFIG_PAGE_IO_UNIT_3, 992 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 993 Mpi2IOUnitPage3_t, *pMpi2IOUnitPage3_t; 994 995 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 996 997 /*defines for IO Unit Page 3 GPIOVal field */ 998 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 999 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1000 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 1001 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 1002 1003 1004 /*IO Unit Page 5 */ 1005 1006 /* 1007 *Upper layer code (drivers, utilities, etc.) should check the value returned 1008 *for NumDmaEngines at runtime before using DmaEngineCapabilities[]. 1009 */ 1010 1011 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 { 1012 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1013 U64 1014 RaidAcceleratorBufferBaseAddress; /*0x04 */ 1015 U64 1016 RaidAcceleratorBufferSize; /*0x0C */ 1017 U64 1018 RaidAcceleratorControlBaseAddress; /*0x14 */ 1019 U8 RAControlSize; /*0x1C */ 1020 U8 NumDmaEngines; /*0x1D */ 1021 U8 RAMinControlSize; /*0x1E */ 1022 U8 RAMaxControlSize; /*0x1F */ 1023 U32 Reserved1; /*0x20 */ 1024 U32 Reserved2; /*0x24 */ 1025 U32 Reserved3; /*0x28 */ 1026 U32 1027 DmaEngineCapabilities[]; /*0x2C */ 1028 } MPI2_CONFIG_PAGE_IO_UNIT_5, 1029 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1030 Mpi2IOUnitPage5_t, *pMpi2IOUnitPage5_t; 1031 1032 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1033 1034 /*defines for IO Unit Page 5 DmaEngineCapabilities field */ 1035 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1036 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1037 1038 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1039 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1040 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1041 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1042 1043 1044 /*IO Unit Page 6 */ 1045 1046 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 { 1047 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1048 U16 Flags; /*0x04 */ 1049 U8 RAHostControlSize; /*0x06 */ 1050 U8 Reserved0; /*0x07 */ 1051 U64 1052 RaidAcceleratorHostControlBaseAddress; /*0x08 */ 1053 U32 Reserved1; /*0x10 */ 1054 U32 Reserved2; /*0x14 */ 1055 U32 Reserved3; /*0x18 */ 1056 } MPI2_CONFIG_PAGE_IO_UNIT_6, 1057 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1058 Mpi2IOUnitPage6_t, *pMpi2IOUnitPage6_t; 1059 1060 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1061 1062 /*defines for IO Unit Page 6 Flags field */ 1063 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1064 1065 1066 /*IO Unit Page 7 */ 1067 1068 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 { 1069 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1070 U8 CurrentPowerMode; /*0x04 */ 1071 U8 PreviousPowerMode; /*0x05 */ 1072 U8 PCIeWidth; /*0x06 */ 1073 U8 PCIeSpeed; /*0x07 */ 1074 U32 ProcessorState; /*0x08 */ 1075 U32 1076 PowerManagementCapabilities; /*0x0C */ 1077 U16 IOCTemperature; /*0x10 */ 1078 U8 1079 IOCTemperatureUnits; /*0x12 */ 1080 U8 IOCSpeed; /*0x13 */ 1081 U16 BoardTemperature; /*0x14 */ 1082 U8 1083 BoardTemperatureUnits; /*0x16 */ 1084 U8 Reserved3; /*0x17 */ 1085 U32 BoardPowerRequirement; /*0x18 */ 1086 U32 PCISlotPowerAllocation; /*0x1C */ 1087 /* reserved prior to MPI v2.6 */ 1088 U8 Flags; /* 0x20 */ 1089 U8 Reserved6; /* 0x21 */ 1090 U16 Reserved7; /* 0x22 */ 1091 U32 Reserved8; /* 0x24 */ 1092 } MPI2_CONFIG_PAGE_IO_UNIT_7, 1093 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1094 Mpi2IOUnitPage7_t, *pMpi2IOUnitPage7_t; 1095 1096 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1097 1098 /*defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1099 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1100 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1101 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1102 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1103 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1104 1105 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1106 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1107 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1108 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1109 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1110 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1111 1112 1113 /*defines for IO Unit Page 7 PCIeWidth field */ 1114 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1115 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1116 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1117 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1118 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1119 1120 /*defines for IO Unit Page 7 PCIeSpeed field */ 1121 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1122 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1123 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1124 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1125 #define MPI2_IOUNITPAGE7_PCIE_SPEED_32_0_GBPS (0x04) 1126 1127 /*defines for IO Unit Page 7 ProcessorState field */ 1128 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1129 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1130 1131 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1132 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1133 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1134 1135 /*defines for IO Unit Page 7 PowerManagementCapabilities field */ 1136 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1137 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1138 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1139 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1140 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1141 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1142 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1143 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1144 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1145 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1146 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1147 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1148 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1149 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1150 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1151 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) 1152 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) 1153 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) 1154 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) 1155 1156 /*obsolete names for the PowerManagementCapabilities bits (above) */ 1157 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1158 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1159 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1160 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /*obsolete */ 1161 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /*obsolete */ 1162 1163 1164 /*defines for IO Unit Page 7 IOCTemperatureUnits field */ 1165 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1166 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1167 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1168 1169 /*defines for IO Unit Page 7 IOCSpeed field */ 1170 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1171 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1172 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1173 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1174 1175 /*defines for IO Unit Page 7 BoardTemperatureUnits field */ 1176 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1177 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1178 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1179 1180 /* defines for IO Unit Page 7 Flags field */ 1181 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1182 1183 /*IO Unit Page 8 */ 1184 1185 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1186 1187 typedef struct _MPI2_IOUNIT8_SENSOR { 1188 U16 Flags; /*0x00 */ 1189 U16 Reserved1; /*0x02 */ 1190 U16 1191 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /*0x04 */ 1192 U32 Reserved2; /*0x0C */ 1193 U32 Reserved3; /*0x10 */ 1194 U32 Reserved4; /*0x14 */ 1195 } MPI2_IOUNIT8_SENSOR, *PTR_MPI2_IOUNIT8_SENSOR, 1196 Mpi2IOUnit8Sensor_t, *pMpi2IOUnit8Sensor_t; 1197 1198 /*defines for IO Unit Page 8 Sensor Flags field */ 1199 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1200 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1201 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1202 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1203 1204 /* 1205 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 1206 *for NumSensors at runtime before using Sensor[]. 1207 */ 1208 1209 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 { 1210 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1211 U32 Reserved1; /*0x04 */ 1212 U32 Reserved2; /*0x08 */ 1213 U8 NumSensors; /*0x0C */ 1214 U8 PollingInterval; /*0x0D */ 1215 U16 Reserved3; /*0x0E */ 1216 MPI2_IOUNIT8_SENSOR Sensor[]; /*0x10 */ 1217 } MPI2_CONFIG_PAGE_IO_UNIT_8, 1218 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1219 Mpi2IOUnitPage8_t, *pMpi2IOUnitPage8_t; 1220 1221 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1222 1223 1224 /*IO Unit Page 9 */ 1225 1226 typedef struct _MPI2_IOUNIT9_SENSOR { 1227 U16 CurrentTemperature; /*0x00 */ 1228 U16 Reserved1; /*0x02 */ 1229 U8 Flags; /*0x04 */ 1230 U8 Reserved2; /*0x05 */ 1231 U16 Reserved3; /*0x06 */ 1232 U32 Reserved4; /*0x08 */ 1233 U32 Reserved5; /*0x0C */ 1234 } MPI2_IOUNIT9_SENSOR, *PTR_MPI2_IOUNIT9_SENSOR, 1235 Mpi2IOUnit9Sensor_t, *pMpi2IOUnit9Sensor_t; 1236 1237 /*defines for IO Unit Page 9 Sensor Flags field */ 1238 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1239 1240 /* 1241 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 1242 *for NumSensors at runtime before using Sensor[]. 1243 */ 1244 1245 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 { 1246 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1247 U32 Reserved1; /*0x04 */ 1248 U32 Reserved2; /*0x08 */ 1249 U8 NumSensors; /*0x0C */ 1250 U8 Reserved4; /*0x0D */ 1251 U16 Reserved3; /*0x0E */ 1252 MPI2_IOUNIT9_SENSOR Sensor[]; /*0x10 */ 1253 } MPI2_CONFIG_PAGE_IO_UNIT_9, 1254 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1255 Mpi2IOUnitPage9_t, *pMpi2IOUnitPage9_t; 1256 1257 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1258 1259 1260 /*IO Unit Page 10 */ 1261 1262 typedef struct _MPI2_IOUNIT10_FUNCTION { 1263 U8 CreditPercent; /*0x00 */ 1264 U8 Reserved1; /*0x01 */ 1265 U16 Reserved2; /*0x02 */ 1266 } MPI2_IOUNIT10_FUNCTION, 1267 *PTR_MPI2_IOUNIT10_FUNCTION, 1268 Mpi2IOUnit10Function_t, 1269 *pMpi2IOUnit10Function_t; 1270 1271 /* 1272 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 1273 *for NumFunctions at runtime before using Function[]. 1274 */ 1275 1276 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 { 1277 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1278 U8 NumFunctions; /*0x04 */ 1279 U8 Reserved1; /*0x05 */ 1280 U16 Reserved2; /*0x06 */ 1281 U32 Reserved3; /*0x08 */ 1282 U32 Reserved4; /*0x0C */ 1283 MPI2_IOUNIT10_FUNCTION Function[]; /*0x10 */ 1284 } MPI2_CONFIG_PAGE_IO_UNIT_10, 1285 *PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1286 Mpi2IOUnitPage10_t, *pMpi2IOUnitPage10_t; 1287 1288 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1289 1290 1291 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1292 1293 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP { 1294 U8 MaxTargetSpinup; /* 0x00 */ 1295 U8 SpinupDelay; /* 0x01 */ 1296 U8 SpinupFlags; /* 0x02 */ 1297 U8 Reserved1; /* 0x03 */ 1298 } MPI26_IOUNIT11_SPINUP_GROUP, 1299 *PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1300 Mpi26IOUnit11SpinupGroup_t, 1301 *pMpi26IOUnit11SpinupGroup_t; 1302 1303 /* defines for IO Unit Page 11 SpinupFlags */ 1304 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1305 1306 1307 /* 1308 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1309 * four and check the value returned for NumPhys at runtime. 1310 */ 1311 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1312 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1313 #endif 1314 1315 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 { 1316 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1317 U32 Reserved1; /*0x04 */ 1318 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /*0x08 */ 1319 U32 Reserved2; /*0x18 */ 1320 U32 Reserved3; /*0x1C */ 1321 U32 Reserved4; /*0x20 */ 1322 U8 BootDeviceWaitTime; /*0x24 */ 1323 U8 Reserved5; /*0x25 */ 1324 U16 Reserved6; /*0x26 */ 1325 U8 NumPhys; /*0x28 */ 1326 U8 PEInitialSpinupDelay; /*0x29 */ 1327 U8 PEReplyDelay; /*0x2A */ 1328 U8 Flags; /*0x2B */ 1329 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/*0x2C */ 1330 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1331 *PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1332 Mpi26IOUnitPage11_t, 1333 *pMpi26IOUnitPage11_t; 1334 1335 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1336 1337 /* defines for Flags field */ 1338 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1339 1340 /* defines for PHY field */ 1341 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1342 1343 1344 1345 1346 1347 1348 /**************************************************************************** 1349 * IOC Config Pages 1350 ****************************************************************************/ 1351 1352 /*IOC Page 0 */ 1353 1354 typedef struct _MPI2_CONFIG_PAGE_IOC_0 { 1355 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1356 U32 Reserved1; /*0x04 */ 1357 U32 Reserved2; /*0x08 */ 1358 U16 VendorID; /*0x0C */ 1359 U16 DeviceID; /*0x0E */ 1360 U8 RevisionID; /*0x10 */ 1361 U8 Reserved3; /*0x11 */ 1362 U16 Reserved4; /*0x12 */ 1363 U32 ClassCode; /*0x14 */ 1364 U16 SubsystemVendorID; /*0x18 */ 1365 U16 SubsystemID; /*0x1A */ 1366 } MPI2_CONFIG_PAGE_IOC_0, 1367 *PTR_MPI2_CONFIG_PAGE_IOC_0, 1368 Mpi2IOCPage0_t, *pMpi2IOCPage0_t; 1369 1370 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1371 1372 1373 /*IOC Page 1 */ 1374 1375 typedef struct _MPI2_CONFIG_PAGE_IOC_1 { 1376 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1377 U32 Flags; /*0x04 */ 1378 U32 CoalescingTimeout; /*0x08 */ 1379 U8 CoalescingDepth; /*0x0C */ 1380 U8 PCISlotNum; /*0x0D */ 1381 U8 PCIBusNum; /*0x0E */ 1382 U8 PCIDomainSegment; /*0x0F */ 1383 U32 Reserved1; /*0x10 */ 1384 U32 ProductSpecific; /* 0x14 */ 1385 } MPI2_CONFIG_PAGE_IOC_1, 1386 *PTR_MPI2_CONFIG_PAGE_IOC_1, 1387 Mpi2IOCPage1_t, *pMpi2IOCPage1_t; 1388 1389 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1390 1391 /*defines for IOC Page 1 Flags field */ 1392 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1393 1394 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1395 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1396 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1397 1398 /*IOC Page 6 */ 1399 1400 typedef struct _MPI2_CONFIG_PAGE_IOC_6 { 1401 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1402 U32 1403 CapabilitiesFlags; /*0x04 */ 1404 U8 MaxDrivesRAID0; /*0x08 */ 1405 U8 MaxDrivesRAID1; /*0x09 */ 1406 U8 1407 MaxDrivesRAID1E; /*0x0A */ 1408 U8 1409 MaxDrivesRAID10; /*0x0B */ 1410 U8 MinDrivesRAID0; /*0x0C */ 1411 U8 MinDrivesRAID1; /*0x0D */ 1412 U8 1413 MinDrivesRAID1E; /*0x0E */ 1414 U8 1415 MinDrivesRAID10; /*0x0F */ 1416 U32 Reserved1; /*0x10 */ 1417 U8 1418 MaxGlobalHotSpares; /*0x14 */ 1419 U8 MaxPhysDisks; /*0x15 */ 1420 U8 MaxVolumes; /*0x16 */ 1421 U8 MaxConfigs; /*0x17 */ 1422 U8 MaxOCEDisks; /*0x18 */ 1423 U8 Reserved2; /*0x19 */ 1424 U16 Reserved3; /*0x1A */ 1425 U32 1426 SupportedStripeSizeMapRAID0; /*0x1C */ 1427 U32 1428 SupportedStripeSizeMapRAID1E; /*0x20 */ 1429 U32 1430 SupportedStripeSizeMapRAID10; /*0x24 */ 1431 U32 Reserved4; /*0x28 */ 1432 U32 Reserved5; /*0x2C */ 1433 U16 1434 DefaultMetadataSize; /*0x30 */ 1435 U16 Reserved6; /*0x32 */ 1436 U16 1437 MaxBadBlockTableEntries; /*0x34 */ 1438 U16 Reserved7; /*0x36 */ 1439 U32 1440 IRNvsramVersion; /*0x38 */ 1441 } MPI2_CONFIG_PAGE_IOC_6, 1442 *PTR_MPI2_CONFIG_PAGE_IOC_6, 1443 Mpi2IOCPage6_t, *pMpi2IOCPage6_t; 1444 1445 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1446 1447 /*defines for IOC Page 6 CapabilitiesFlags */ 1448 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1449 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1450 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1451 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1452 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1453 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1454 1455 1456 /*IOC Page 7 */ 1457 1458 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1459 1460 typedef struct _MPI2_CONFIG_PAGE_IOC_7 { 1461 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1462 U32 Reserved1; /*0x04 */ 1463 U32 1464 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/*0x08 */ 1465 U16 SASBroadcastPrimitiveMasks; /*0x18 */ 1466 U16 SASNotifyPrimitiveMasks; /*0x1A */ 1467 U32 Reserved3; /*0x1C */ 1468 } MPI2_CONFIG_PAGE_IOC_7, 1469 *PTR_MPI2_CONFIG_PAGE_IOC_7, 1470 Mpi2IOCPage7_t, *pMpi2IOCPage7_t; 1471 1472 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1473 1474 1475 /*IOC Page 8 */ 1476 1477 typedef struct _MPI2_CONFIG_PAGE_IOC_8 { 1478 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1479 U8 NumDevsPerEnclosure; /*0x04 */ 1480 U8 Reserved1; /*0x05 */ 1481 U16 Reserved2; /*0x06 */ 1482 U16 MaxPersistentEntries; /*0x08 */ 1483 U16 MaxNumPhysicalMappedIDs; /*0x0A */ 1484 U16 Flags; /*0x0C */ 1485 U16 Reserved3; /*0x0E */ 1486 U16 IRVolumeMappingFlags; /*0x10 */ 1487 U16 Reserved4; /*0x12 */ 1488 U32 Reserved5; /*0x14 */ 1489 } MPI2_CONFIG_PAGE_IOC_8, 1490 *PTR_MPI2_CONFIG_PAGE_IOC_8, 1491 Mpi2IOCPage8_t, *pMpi2IOCPage8_t; 1492 1493 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1494 1495 /*defines for IOC Page 8 Flags field */ 1496 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1497 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1498 1499 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1500 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1501 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1502 1503 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1504 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1505 1506 /*defines for IOC Page 8 IRVolumeMappingFlags */ 1507 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1508 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1509 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1510 1511 1512 /**************************************************************************** 1513 * BIOS Config Pages 1514 ****************************************************************************/ 1515 1516 /*BIOS Page 1 */ 1517 1518 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 { 1519 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1520 U32 BiosOptions; /*0x04 */ 1521 U32 IOCSettings; /*0x08 */ 1522 U8 SSUTimeout; /*0x0C */ 1523 U8 MaxEnclosureLevel; /*0x0D */ 1524 U16 Reserved2; /*0x0E */ 1525 U32 DeviceSettings; /*0x10 */ 1526 U16 NumberOfDevices; /*0x14 */ 1527 U16 UEFIVersion; /*0x16 */ 1528 U16 IOTimeoutBlockDevicesNonRM; /*0x18 */ 1529 U16 IOTimeoutSequential; /*0x1A */ 1530 U16 IOTimeoutOther; /*0x1C */ 1531 U16 IOTimeoutBlockDevicesRM; /*0x1E */ 1532 } MPI2_CONFIG_PAGE_BIOS_1, 1533 *PTR_MPI2_CONFIG_PAGE_BIOS_1, 1534 Mpi2BiosPage1_t, *pMpi2BiosPage1_t; 1535 1536 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1537 1538 /*values for BIOS Page 1 BiosOptions field */ 1539 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1540 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1541 1542 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1543 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1544 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1545 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1546 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1547 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1548 1549 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1550 1551 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1552 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1553 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1554 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1555 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1556 1557 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1558 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1559 1560 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1561 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1562 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1563 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1564 1565 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1566 1567 /*values for BIOS Page 1 IOCSettings field */ 1568 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1569 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1570 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1571 1572 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1573 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1574 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1575 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1576 1577 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1578 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1579 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1580 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1581 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1582 1583 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1584 1585 /*values for BIOS Page 1 DeviceSettings field */ 1586 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1587 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1588 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1589 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1590 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1591 1592 /*defines for BIOS Page 1 UEFIVersion field */ 1593 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1594 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1595 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1596 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1597 1598 1599 1600 /*BIOS Page 2 */ 1601 1602 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER { 1603 U32 Reserved1; /*0x00 */ 1604 U32 Reserved2; /*0x04 */ 1605 U32 Reserved3; /*0x08 */ 1606 U32 Reserved4; /*0x0C */ 1607 U32 Reserved5; /*0x10 */ 1608 U32 Reserved6; /*0x14 */ 1609 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1610 *PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1611 Mpi2BootDeviceAdapterOrder_t, 1612 *pMpi2BootDeviceAdapterOrder_t; 1613 1614 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID { 1615 U64 SASAddress; /*0x00 */ 1616 U8 LUN[8]; /*0x08 */ 1617 U32 Reserved1; /*0x10 */ 1618 U32 Reserved2; /*0x14 */ 1619 } MPI2_BOOT_DEVICE_SAS_WWID, 1620 *PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1621 Mpi2BootDeviceSasWwid_t, 1622 *pMpi2BootDeviceSasWwid_t; 1623 1624 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT { 1625 U64 EnclosureLogicalID; /*0x00 */ 1626 U32 Reserved1; /*0x08 */ 1627 U32 Reserved2; /*0x0C */ 1628 U16 SlotNumber; /*0x10 */ 1629 U16 Reserved3; /*0x12 */ 1630 U32 Reserved4; /*0x14 */ 1631 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1632 *PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1633 Mpi2BootDeviceEnclosureSlot_t, 1634 *pMpi2BootDeviceEnclosureSlot_t; 1635 1636 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME { 1637 U64 DeviceName; /*0x00 */ 1638 U8 LUN[8]; /*0x08 */ 1639 U32 Reserved1; /*0x10 */ 1640 U32 Reserved2; /*0x14 */ 1641 } MPI2_BOOT_DEVICE_DEVICE_NAME, 1642 *PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1643 Mpi2BootDeviceDeviceName_t, 1644 *pMpi2BootDeviceDeviceName_t; 1645 1646 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE { 1647 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1648 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1649 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1650 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1651 } MPI2_BIOSPAGE2_BOOT_DEVICE, 1652 *PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1653 Mpi2BiosPage2BootDevice_t, 1654 *pMpi2BiosPage2BootDevice_t; 1655 1656 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 { 1657 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1658 U32 Reserved1; /*0x04 */ 1659 U32 Reserved2; /*0x08 */ 1660 U32 Reserved3; /*0x0C */ 1661 U32 Reserved4; /*0x10 */ 1662 U32 Reserved5; /*0x14 */ 1663 U32 Reserved6; /*0x18 */ 1664 U8 ReqBootDeviceForm; /*0x1C */ 1665 U8 Reserved7; /*0x1D */ 1666 U16 Reserved8; /*0x1E */ 1667 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /*0x20 */ 1668 U8 ReqAltBootDeviceForm; /*0x38 */ 1669 U8 Reserved9; /*0x39 */ 1670 U16 Reserved10; /*0x3A */ 1671 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /*0x3C */ 1672 U8 CurrentBootDeviceForm; /*0x58 */ 1673 U8 Reserved11; /*0x59 */ 1674 U16 Reserved12; /*0x5A */ 1675 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /*0x58 */ 1676 } MPI2_CONFIG_PAGE_BIOS_2, *PTR_MPI2_CONFIG_PAGE_BIOS_2, 1677 Mpi2BiosPage2_t, *pMpi2BiosPage2_t; 1678 1679 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1680 1681 /*values for BIOS Page 2 BootDeviceForm fields */ 1682 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1683 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1684 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1685 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1686 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1687 1688 1689 /*BIOS Page 3 */ 1690 1691 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1692 1693 typedef struct _MPI2_ADAPTER_INFO { 1694 U8 PciBusNumber; /*0x00 */ 1695 U8 PciDeviceAndFunctionNumber; /*0x01 */ 1696 U16 AdapterFlags; /*0x02 */ 1697 } MPI2_ADAPTER_INFO, *PTR_MPI2_ADAPTER_INFO, 1698 Mpi2AdapterInfo_t, *pMpi2AdapterInfo_t; 1699 1700 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1701 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1702 1703 typedef struct _MPI2_ADAPTER_ORDER_AUX { 1704 U64 WWID; /* 0x00 */ 1705 U32 Reserved1; /* 0x08 */ 1706 U32 Reserved2; /* 0x0C */ 1707 } MPI2_ADAPTER_ORDER_AUX, *PTR_MPI2_ADAPTER_ORDER_AUX, 1708 Mpi2AdapterOrderAux_t, *pMpi2AdapterOrderAux_t; 1709 1710 1711 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 { 1712 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1713 U32 GlobalFlags; /*0x04 */ 1714 U32 BiosVersion; /*0x08 */ 1715 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1716 U32 Reserved1; /*0x1C */ 1717 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; 1718 } MPI2_CONFIG_PAGE_BIOS_3, 1719 *PTR_MPI2_CONFIG_PAGE_BIOS_3, 1720 Mpi2BiosPage3_t, *pMpi2BiosPage3_t; 1721 1722 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1723 1724 /*values for BIOS Page 3 GlobalFlags */ 1725 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1726 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1727 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1728 1729 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1730 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1731 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1732 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1733 1734 1735 /*BIOS Page 4 */ 1736 1737 /* 1738 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 1739 *for NumPhys at runtime before using Phy[]. 1740 */ 1741 1742 typedef struct _MPI2_BIOS4_ENTRY { 1743 U64 ReassignmentWWID; /*0x00 */ 1744 U64 ReassignmentDeviceName; /*0x08 */ 1745 } MPI2_BIOS4_ENTRY, *PTR_MPI2_BIOS4_ENTRY, 1746 Mpi2MBios4Entry_t, *pMpi2Bios4Entry_t; 1747 1748 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 { 1749 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1750 U8 NumPhys; /*0x04 */ 1751 U8 Reserved1; /*0x05 */ 1752 U16 Reserved2; /*0x06 */ 1753 MPI2_BIOS4_ENTRY Phy[]; /*0x08 */ 1754 } MPI2_CONFIG_PAGE_BIOS_4, *PTR_MPI2_CONFIG_PAGE_BIOS_4, 1755 Mpi2BiosPage4_t, *pMpi2BiosPage4_t; 1756 1757 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1758 1759 1760 /**************************************************************************** 1761 * RAID Volume Config Pages 1762 ****************************************************************************/ 1763 1764 /*RAID Volume Page 0 */ 1765 1766 typedef struct _MPI2_RAIDVOL0_PHYS_DISK { 1767 U8 RAIDSetNum; /*0x00 */ 1768 U8 PhysDiskMap; /*0x01 */ 1769 U8 PhysDiskNum; /*0x02 */ 1770 U8 Reserved; /*0x03 */ 1771 } MPI2_RAIDVOL0_PHYS_DISK, *PTR_MPI2_RAIDVOL0_PHYS_DISK, 1772 Mpi2RaidVol0PhysDisk_t, *pMpi2RaidVol0PhysDisk_t; 1773 1774 /*defines for the PhysDiskMap field */ 1775 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1776 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1777 1778 typedef struct _MPI2_RAIDVOL0_SETTINGS { 1779 U16 Settings; /*0x00 */ 1780 U8 HotSparePool; /*0x01 */ 1781 U8 Reserved; /*0x02 */ 1782 } MPI2_RAIDVOL0_SETTINGS, *PTR_MPI2_RAIDVOL0_SETTINGS, 1783 Mpi2RaidVol0Settings_t, 1784 *pMpi2RaidVol0Settings_t; 1785 1786 /*RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1787 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1788 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1789 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1790 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1791 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1792 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1793 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1794 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1795 1796 /*RAID Volume Page 0 VolumeSettings defines */ 1797 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1798 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1799 1800 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1801 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1802 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1803 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1804 1805 /* 1806 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 1807 *for NumPhysDisks at runtime before using PhysDisk[]. 1808 */ 1809 1810 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 { 1811 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1812 U16 DevHandle; /*0x04 */ 1813 U8 VolumeState; /*0x06 */ 1814 U8 VolumeType; /*0x07 */ 1815 U32 VolumeStatusFlags; /*0x08 */ 1816 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /*0x0C */ 1817 U64 MaxLBA; /*0x10 */ 1818 U32 StripeSize; /*0x18 */ 1819 U16 BlockSize; /*0x1C */ 1820 U16 Reserved1; /*0x1E */ 1821 U8 SupportedPhysDisks;/*0x20 */ 1822 U8 ResyncRate; /*0x21 */ 1823 U16 DataScrubDuration; /*0x22 */ 1824 U8 NumPhysDisks; /*0x24 */ 1825 U8 Reserved2; /*0x25 */ 1826 U8 Reserved3; /*0x26 */ 1827 U8 InactiveStatus; /*0x27 */ 1828 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[]; /*0x28 */ 1829 } MPI2_CONFIG_PAGE_RAID_VOL_0, 1830 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1831 Mpi2RaidVolPage0_t, *pMpi2RaidVolPage0_t; 1832 1833 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1834 1835 /*values for RAID VolumeState */ 1836 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1837 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1838 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1839 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1840 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1841 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1842 1843 /*values for RAID VolumeType */ 1844 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1845 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1846 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1847 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1848 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1849 1850 /*values for RAID Volume Page 0 VolumeStatusFlags field */ 1851 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1852 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1853 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1854 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1855 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1856 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1857 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1858 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1859 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1860 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1861 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1862 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1863 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1864 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1865 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1866 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1867 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1868 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1869 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1870 1871 /*values for RAID Volume Page 0 SupportedPhysDisks field */ 1872 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1873 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1874 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1875 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1876 1877 /*values for RAID Volume Page 0 InactiveStatus field */ 1878 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1879 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1880 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1881 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1882 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1883 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1884 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1885 1886 1887 /*RAID Volume Page 1 */ 1888 1889 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 { 1890 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1891 U16 DevHandle; /*0x04 */ 1892 U16 Reserved0; /*0x06 */ 1893 U8 GUID[24]; /*0x08 */ 1894 U8 Name[16]; /*0x20 */ 1895 U64 WWID; /*0x30 */ 1896 U32 Reserved1; /*0x38 */ 1897 U32 Reserved2; /*0x3C */ 1898 } MPI2_CONFIG_PAGE_RAID_VOL_1, 1899 *PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1900 Mpi2RaidVolPage1_t, *pMpi2RaidVolPage1_t; 1901 1902 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1903 1904 1905 /**************************************************************************** 1906 * RAID Physical Disk Config Pages 1907 ****************************************************************************/ 1908 1909 /*RAID Physical Disk Page 0 */ 1910 1911 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS { 1912 U16 Reserved1; /*0x00 */ 1913 U8 HotSparePool; /*0x02 */ 1914 U8 Reserved2; /*0x03 */ 1915 } MPI2_RAIDPHYSDISK0_SETTINGS, 1916 *PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1917 Mpi2RaidPhysDisk0Settings_t, 1918 *pMpi2RaidPhysDisk0Settings_t; 1919 1920 /*use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1921 1922 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA { 1923 U8 VendorID[8]; /*0x00 */ 1924 U8 ProductID[16]; /*0x08 */ 1925 U8 ProductRevLevel[4]; /*0x18 */ 1926 U8 SerialNum[32]; /*0x1C */ 1927 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1928 *PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1929 Mpi2RaidPhysDisk0InquiryData_t, 1930 *pMpi2RaidPhysDisk0InquiryData_t; 1931 1932 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 { 1933 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 1934 U16 DevHandle; /*0x04 */ 1935 U8 Reserved1; /*0x06 */ 1936 U8 PhysDiskNum; /*0x07 */ 1937 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /*0x08 */ 1938 U32 Reserved2; /*0x0C */ 1939 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /*0x10 */ 1940 U32 Reserved3; /*0x4C */ 1941 U8 PhysDiskState; /*0x50 */ 1942 U8 OfflineReason; /*0x51 */ 1943 U8 IncompatibleReason; /*0x52 */ 1944 U8 PhysDiskAttributes; /*0x53 */ 1945 U32 PhysDiskStatusFlags;/*0x54 */ 1946 U64 DeviceMaxLBA; /*0x58 */ 1947 U64 HostMaxLBA; /*0x60 */ 1948 U64 CoercedMaxLBA; /*0x68 */ 1949 U16 BlockSize; /*0x70 */ 1950 U16 Reserved5; /*0x72 */ 1951 U32 Reserved6; /*0x74 */ 1952 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1953 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1954 Mpi2RaidPhysDiskPage0_t, 1955 *pMpi2RaidPhysDiskPage0_t; 1956 1957 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1958 1959 /*PhysDiskState defines */ 1960 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1961 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1962 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1963 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1964 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1965 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1966 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1967 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1968 1969 /*OfflineReason defines */ 1970 #define MPI2_PHYSDISK0_ONLINE (0x00) 1971 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1972 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1973 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1974 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1975 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1976 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1977 1978 /*IncompatibleReason defines */ 1979 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1980 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1981 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1982 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1983 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1984 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1985 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1986 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1987 1988 /*PhysDiskAttributes defines */ 1989 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1990 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1991 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1992 1993 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1994 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1995 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1996 1997 /*PhysDiskStatusFlags defines */ 1998 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1999 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 2000 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 2001 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 2002 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 2003 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 2004 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 2005 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 2006 2007 2008 /*RAID Physical Disk Page 1 */ 2009 2010 /* 2011 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 2012 *for NumPhysDiskPaths at runtime before using PhysicalDiskPath[]. 2013 */ 2014 2015 typedef struct _MPI2_RAIDPHYSDISK1_PATH { 2016 U16 DevHandle; /*0x00 */ 2017 U16 Reserved1; /*0x02 */ 2018 U64 WWID; /*0x04 */ 2019 U64 OwnerWWID; /*0x0C */ 2020 U8 OwnerIdentifier; /*0x14 */ 2021 U8 Reserved2; /*0x15 */ 2022 U16 Flags; /*0x16 */ 2023 } MPI2_RAIDPHYSDISK1_PATH, *PTR_MPI2_RAIDPHYSDISK1_PATH, 2024 Mpi2RaidPhysDisk1Path_t, 2025 *pMpi2RaidPhysDisk1Path_t; 2026 2027 /*RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2028 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2029 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2030 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2031 2032 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 { 2033 MPI2_CONFIG_PAGE_HEADER Header; /*0x00 */ 2034 U8 NumPhysDiskPaths; /*0x04 */ 2035 U8 PhysDiskNum; /*0x05 */ 2036 U16 Reserved1; /*0x06 */ 2037 U32 Reserved2; /*0x08 */ 2038 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[]; /*0x0C */ 2039 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2040 *PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2041 Mpi2RaidPhysDiskPage1_t, 2042 *pMpi2RaidPhysDiskPage1_t; 2043 2044 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2045 2046 2047 /**************************************************************************** 2048 * values for fields used by several types of SAS Config Pages 2049 ****************************************************************************/ 2050 2051 /*values for NegotiatedLinkRates fields */ 2052 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2053 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2054 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2055 /*link rates used for Negotiated Physical and Logical Link Rate */ 2056 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2057 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2058 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2059 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2060 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2061 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2062 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2063 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2064 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2065 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2066 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2067 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2068 2069 2070 /*values for AttachedPhyInfo fields */ 2071 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2072 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2073 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2074 2075 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2076 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2077 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2078 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2079 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2080 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2081 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2082 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2083 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2084 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2085 2086 2087 /*values for PhyInfo fields */ 2088 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2089 2090 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2091 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2092 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2093 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2094 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2095 2096 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2097 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2098 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2099 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2100 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2101 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2102 2103 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2104 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2105 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2106 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2107 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2108 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2109 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2110 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2111 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2112 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2113 2114 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2115 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2116 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2117 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2118 2119 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2120 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2121 2122 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2123 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2124 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2125 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2126 2127 2128 /*values for SAS ProgrammedLinkRate fields */ 2129 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2130 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2131 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2132 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2133 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2134 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2135 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2136 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2137 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2138 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2139 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2140 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2141 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2142 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2143 2144 2145 /*values for SAS HwLinkRate fields */ 2146 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2147 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2148 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2149 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2150 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2151 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2152 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2153 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2154 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2155 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2156 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2157 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2158 2159 2160 2161 /**************************************************************************** 2162 * SAS IO Unit Config Pages 2163 ****************************************************************************/ 2164 2165 /*SAS IO Unit Page 0 */ 2166 2167 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA { 2168 U8 Port; /*0x00 */ 2169 U8 PortFlags; /*0x01 */ 2170 U8 PhyFlags; /*0x02 */ 2171 U8 NegotiatedLinkRate; /*0x03 */ 2172 U32 ControllerPhyDeviceInfo;/*0x04 */ 2173 U16 AttachedDevHandle; /*0x08 */ 2174 U16 ControllerDevHandle; /*0x0A */ 2175 U32 DiscoveryStatus; /*0x0C */ 2176 U32 Reserved; /*0x10 */ 2177 } MPI2_SAS_IO_UNIT0_PHY_DATA, 2178 *PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2179 Mpi2SasIOUnit0PhyData_t, 2180 *pMpi2SasIOUnit0PhyData_t; 2181 2182 /* 2183 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 2184 *for NumPhys at runtime before using PhyData[]. 2185 */ 2186 2187 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 { 2188 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2189 U32 Reserved1;/*0x08 */ 2190 U8 NumPhys; /*0x0C */ 2191 U8 Reserved2;/*0x0D */ 2192 U16 Reserved3;/*0x0E */ 2193 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[];/*0x10 */ 2194 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2195 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2196 Mpi2SasIOUnitPage0_t, *pMpi2SasIOUnitPage0_t; 2197 2198 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2199 2200 /*values for SAS IO Unit Page 0 PortFlags */ 2201 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2202 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2203 2204 /*values for SAS IO Unit Page 0 PhyFlags */ 2205 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2206 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2207 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2208 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2209 2210 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2211 2212 /*see mpi2_sas.h for values for 2213 *SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2214 2215 /*values for SAS IO Unit Page 0 DiscoveryStatus */ 2216 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2217 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2218 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2219 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2220 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2221 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2222 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2223 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2224 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2225 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2226 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2227 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2228 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2229 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2230 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2231 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2232 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2233 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2234 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2235 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2236 2237 2238 /*SAS IO Unit Page 1 */ 2239 2240 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA { 2241 U8 Port; /*0x00 */ 2242 U8 PortFlags; /*0x01 */ 2243 U8 PhyFlags; /*0x02 */ 2244 U8 MaxMinLinkRate; /*0x03 */ 2245 U32 ControllerPhyDeviceInfo; /*0x04 */ 2246 U16 MaxTargetPortConnectTime; /*0x08 */ 2247 U16 Reserved1; /*0x0A */ 2248 } MPI2_SAS_IO_UNIT1_PHY_DATA, 2249 *PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2250 Mpi2SasIOUnit1PhyData_t, 2251 *pMpi2SasIOUnit1PhyData_t; 2252 2253 /* 2254 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 2255 *for NumPhys at runtime before using PhyData[]. 2256 */ 2257 2258 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 { 2259 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2260 U16 2261 ControlFlags; /*0x08 */ 2262 U16 2263 SASNarrowMaxQueueDepth; /*0x0A */ 2264 U16 2265 AdditionalControlFlags; /*0x0C */ 2266 U16 2267 SASWideMaxQueueDepth; /*0x0E */ 2268 U8 2269 NumPhys; /*0x10 */ 2270 U8 2271 SATAMaxQDepth; /*0x11 */ 2272 U8 2273 ReportDeviceMissingDelay; /*0x12 */ 2274 U8 2275 IODeviceMissingDelay; /*0x13 */ 2276 MPI2_SAS_IO_UNIT1_PHY_DATA 2277 PhyData[]; /*0x14 */ 2278 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2279 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2280 Mpi2SasIOUnitPage1_t, *pMpi2SasIOUnitPage1_t; 2281 2282 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2283 2284 /*values for SAS IO Unit Page 1 ControlFlags */ 2285 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2286 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2287 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2288 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2289 2290 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2291 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2292 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2293 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2294 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2295 2296 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2297 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2298 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2299 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2300 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2301 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2302 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2303 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2304 2305 /*values for SAS IO Unit Page 1 AdditionalControlFlags */ 2306 #define MPI2_SASIOUNIT1_ACONTROL_PROD_SPECIFIC_1 (0x8000) 2307 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2308 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2309 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2310 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2311 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2312 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2313 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2314 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2315 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2316 2317 /*defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2318 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2319 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2320 2321 /*values for SAS IO Unit Page 1 PortFlags */ 2322 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2323 2324 /*values for SAS IO Unit Page 1 PhyFlags */ 2325 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2326 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2327 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2328 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2329 2330 /*values for SAS IO Unit Page 1 MaxMinLinkRate */ 2331 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2332 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2333 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2334 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2335 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2336 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2337 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2338 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2339 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2340 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2341 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2342 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2343 2344 /*see mpi2_sas.h for values for 2345 *SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2346 2347 2348 /*SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2349 2350 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP { 2351 U8 MaxTargetSpinup; /*0x00 */ 2352 U8 SpinupDelay; /*0x01 */ 2353 U8 SpinupFlags; /*0x02 */ 2354 U8 Reserved1; /*0x03 */ 2355 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2356 *PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2357 Mpi2SasIOUnit4SpinupGroup_t, 2358 *pMpi2SasIOUnit4SpinupGroup_t; 2359 /*defines for SAS IO Unit Page 4 SpinupFlags */ 2360 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2361 2362 2363 /* 2364 *Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2365 *one and check the value returned for NumPhys at runtime. 2366 */ 2367 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2368 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2369 #endif 2370 2371 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 { 2372 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header;/*0x00 */ 2373 MPI2_SAS_IOUNIT4_SPINUP_GROUP 2374 SpinupGroupParameters[4]; /*0x08 */ 2375 U32 2376 Reserved1; /*0x18 */ 2377 U32 2378 Reserved2; /*0x1C */ 2379 U32 2380 Reserved3; /*0x20 */ 2381 U8 2382 BootDeviceWaitTime; /*0x24 */ 2383 U8 2384 SATADeviceWaitTime; /*0x25 */ 2385 U16 2386 Reserved5; /*0x26 */ 2387 U8 2388 NumPhys; /*0x28 */ 2389 U8 2390 PEInitialSpinupDelay; /*0x29 */ 2391 U8 2392 PEReplyDelay; /*0x2A */ 2393 U8 2394 Flags; /*0x2B */ 2395 U8 2396 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /*0x2C */ 2397 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2398 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2399 Mpi2SasIOUnitPage4_t, *pMpi2SasIOUnitPage4_t; 2400 2401 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2402 2403 /*defines for Flags field */ 2404 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2405 2406 /*defines for PHY field */ 2407 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2408 2409 2410 /*SAS IO Unit Page 5 */ 2411 2412 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS { 2413 U8 ControlFlags; /*0x00 */ 2414 U8 PortWidthModGroup; /*0x01 */ 2415 U16 InactivityTimerExponent; /*0x02 */ 2416 U8 SATAPartialTimeout; /*0x04 */ 2417 U8 Reserved2; /*0x05 */ 2418 U8 SATASlumberTimeout; /*0x06 */ 2419 U8 Reserved3; /*0x07 */ 2420 U8 SASPartialTimeout; /*0x08 */ 2421 U8 Reserved4; /*0x09 */ 2422 U8 SASSlumberTimeout; /*0x0A */ 2423 U8 Reserved5; /*0x0B */ 2424 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2425 *PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2426 Mpi2SasIOUnit5PhyPmSettings_t, 2427 *pMpi2SasIOUnit5PhyPmSettings_t; 2428 2429 /*defines for ControlFlags field */ 2430 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2431 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2432 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2433 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2434 2435 /*defines for PortWidthModeGroup field */ 2436 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2437 2438 /*defines for InactivityTimerExponent field */ 2439 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2440 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2441 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2442 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2443 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2444 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2445 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2446 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2447 2448 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2449 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2450 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2451 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2452 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2453 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2454 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2455 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2456 2457 /* 2458 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 2459 *for NumPhys at runtime before using SASPhyPowerManagementSettings[]. 2460 */ 2461 2462 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 { 2463 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2464 U8 NumPhys; /*0x08 */ 2465 U8 Reserved1;/*0x09 */ 2466 U16 Reserved2;/*0x0A */ 2467 U32 Reserved3;/*0x0C */ 2468 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2469 SASPhyPowerManagementSettings[]; /*0x10 */ 2470 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2471 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2472 Mpi2SasIOUnitPage5_t, *pMpi2SasIOUnitPage5_t; 2473 2474 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2475 2476 2477 /*SAS IO Unit Page 6 */ 2478 2479 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS { 2480 U8 CurrentStatus; /*0x00 */ 2481 U8 CurrentModulation; /*0x01 */ 2482 U8 CurrentUtilization; /*0x02 */ 2483 U8 Reserved1; /*0x03 */ 2484 U32 Reserved2; /*0x04 */ 2485 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2486 *PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2487 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2488 *pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2489 2490 /*defines for CurrentStatus field */ 2491 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2492 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2493 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2494 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2495 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2496 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2497 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2498 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2499 2500 /*defines for CurrentModulation field */ 2501 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2502 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2503 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2504 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2505 2506 /* 2507 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 2508 *for NumGroups at runtime before using PortWidthModulationGroupStatus[]. 2509 */ 2510 2511 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 { 2512 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2513 U32 Reserved1; /*0x08 */ 2514 U32 Reserved2; /*0x0C */ 2515 U8 NumGroups; /*0x10 */ 2516 U8 Reserved3; /*0x11 */ 2517 U16 Reserved4; /*0x12 */ 2518 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2519 PortWidthModulationGroupStatus[]; /*0x14 */ 2520 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2521 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2522 Mpi2SasIOUnitPage6_t, *pMpi2SasIOUnitPage6_t; 2523 2524 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2525 2526 2527 /*SAS IO Unit Page 7 */ 2528 2529 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS { 2530 U8 Flags; /*0x00 */ 2531 U8 Reserved1; /*0x01 */ 2532 U16 Reserved2; /*0x02 */ 2533 U8 Threshold75Pct; /*0x04 */ 2534 U8 Threshold50Pct; /*0x05 */ 2535 U8 Threshold25Pct; /*0x06 */ 2536 U8 Reserved3; /*0x07 */ 2537 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2538 *PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2539 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2540 *pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2541 2542 /*defines for Flags field */ 2543 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2544 2545 2546 /* 2547 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 2548 *for NumGroups at runtime before using PortWidthModulationGroupSettings[]. 2549 */ 2550 2551 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 { 2552 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 2553 U8 SamplingInterval; /*0x08 */ 2554 U8 WindowLength; /*0x09 */ 2555 U16 Reserved1; /*0x0A */ 2556 U32 Reserved2; /*0x0C */ 2557 U32 Reserved3; /*0x10 */ 2558 U8 NumGroups; /*0x14 */ 2559 U8 Reserved4; /*0x15 */ 2560 U16 Reserved5; /*0x16 */ 2561 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2562 PortWidthModulationGroupSettings[]; /*0x18 */ 2563 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2564 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2565 Mpi2SasIOUnitPage7_t, *pMpi2SasIOUnitPage7_t; 2566 2567 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2568 2569 2570 /*SAS IO Unit Page 8 */ 2571 2572 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 { 2573 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2574 Header; /*0x00 */ 2575 U32 2576 Reserved1; /*0x08 */ 2577 U32 2578 PowerManagementCapabilities; /*0x0C */ 2579 U8 2580 TxRxSleepStatus; /*0x10 */ 2581 U8 2582 Reserved2; /*0x11 */ 2583 U16 2584 Reserved3; /*0x12 */ 2585 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2586 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2587 Mpi2SasIOUnitPage8_t, *pMpi2SasIOUnitPage8_t; 2588 2589 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2590 2591 /*defines for PowerManagementCapabilities field */ 2592 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2593 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2594 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2595 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2596 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2597 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2598 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2599 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2600 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2601 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2602 2603 /*defines for TxRxSleepStatus field */ 2604 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2605 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2606 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2607 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2608 2609 2610 2611 /*SAS IO Unit Page 16 */ 2612 2613 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 { 2614 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2615 Header; /*0x00 */ 2616 U64 2617 TimeStamp; /*0x08 */ 2618 U32 2619 Reserved1; /*0x10 */ 2620 U32 2621 Reserved2; /*0x14 */ 2622 U32 2623 FastPathPendedRequests; /*0x18 */ 2624 U32 2625 FastPathUnPendedRequests; /*0x1C */ 2626 U32 2627 FastPathHostRequestStarts; /*0x20 */ 2628 U32 2629 FastPathFirmwareRequestStarts; /*0x24 */ 2630 U32 2631 FastPathHostCompletions; /*0x28 */ 2632 U32 2633 FastPathFirmwareCompletions; /*0x2C */ 2634 U32 2635 NonFastPathRequestStarts; /*0x30 */ 2636 U32 2637 NonFastPathHostCompletions; /*0x30 */ 2638 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2639 *PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2640 Mpi2SasIOUnitPage16_t, *pMpi2SasIOUnitPage16_t; 2641 2642 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2643 2644 2645 /**************************************************************************** 2646 * SAS Expander Config Pages 2647 ****************************************************************************/ 2648 2649 /*SAS Expander Page 0 */ 2650 2651 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 { 2652 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2653 Header; /*0x00 */ 2654 U8 2655 PhysicalPort; /*0x08 */ 2656 U8 2657 ReportGenLength; /*0x09 */ 2658 U16 2659 EnclosureHandle; /*0x0A */ 2660 U64 2661 SASAddress; /*0x0C */ 2662 U32 2663 DiscoveryStatus; /*0x14 */ 2664 U16 2665 DevHandle; /*0x18 */ 2666 U16 2667 ParentDevHandle; /*0x1A */ 2668 U16 2669 ExpanderChangeCount; /*0x1C */ 2670 U16 2671 ExpanderRouteIndexes; /*0x1E */ 2672 U8 2673 NumPhys; /*0x20 */ 2674 U8 2675 SASLevel; /*0x21 */ 2676 U16 2677 Flags; /*0x22 */ 2678 U16 2679 STPBusInactivityTimeLimit; /*0x24 */ 2680 U16 2681 STPMaxConnectTimeLimit; /*0x26 */ 2682 U16 2683 STP_SMP_NexusLossTime; /*0x28 */ 2684 U16 2685 MaxNumRoutedSasAddresses; /*0x2A */ 2686 U64 2687 ActiveZoneManagerSASAddress;/*0x2C */ 2688 U16 2689 ZoneLockInactivityLimit; /*0x34 */ 2690 U16 2691 Reserved1; /*0x36 */ 2692 U8 2693 TimeToReducedFunc; /*0x38 */ 2694 U8 2695 InitialTimeToReducedFunc; /*0x39 */ 2696 U8 2697 MaxReducedFuncTime; /*0x3A */ 2698 U8 2699 Reserved2; /*0x3B */ 2700 } MPI2_CONFIG_PAGE_EXPANDER_0, 2701 *PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2702 Mpi2ExpanderPage0_t, *pMpi2ExpanderPage0_t; 2703 2704 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2705 2706 /*values for SAS Expander Page 0 DiscoveryStatus field */ 2707 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2708 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2709 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2710 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2711 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2712 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2713 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2714 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2715 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2716 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2717 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2718 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2719 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2720 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2721 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2722 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2723 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2724 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2725 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2726 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2727 2728 /*values for SAS Expander Page 0 Flags field */ 2729 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2730 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2731 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2732 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2733 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2734 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2735 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2736 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2737 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2738 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2739 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2740 2741 2742 /*SAS Expander Page 1 */ 2743 2744 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 { 2745 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2746 Header; /*0x00 */ 2747 U8 2748 PhysicalPort; /*0x08 */ 2749 U8 2750 Reserved1; /*0x09 */ 2751 U16 2752 Reserved2; /*0x0A */ 2753 U8 2754 NumPhys; /*0x0C */ 2755 U8 2756 Phy; /*0x0D */ 2757 U16 2758 NumTableEntriesProgrammed; /*0x0E */ 2759 U8 2760 ProgrammedLinkRate; /*0x10 */ 2761 U8 2762 HwLinkRate; /*0x11 */ 2763 U16 2764 AttachedDevHandle; /*0x12 */ 2765 U32 2766 PhyInfo; /*0x14 */ 2767 U32 2768 AttachedDeviceInfo; /*0x18 */ 2769 U16 2770 ExpanderDevHandle; /*0x1C */ 2771 U8 2772 ChangeCount; /*0x1E */ 2773 U8 2774 NegotiatedLinkRate; /*0x1F */ 2775 U8 2776 PhyIdentifier; /*0x20 */ 2777 U8 2778 AttachedPhyIdentifier; /*0x21 */ 2779 U8 2780 Reserved3; /*0x22 */ 2781 U8 2782 DiscoveryInfo; /*0x23 */ 2783 U32 2784 AttachedPhyInfo; /*0x24 */ 2785 U8 2786 ZoneGroup; /*0x28 */ 2787 U8 2788 SelfConfigStatus; /*0x29 */ 2789 U16 2790 Reserved4; /*0x2A */ 2791 } MPI2_CONFIG_PAGE_EXPANDER_1, 2792 *PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2793 Mpi2ExpanderPage1_t, *pMpi2ExpanderPage1_t; 2794 2795 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2796 2797 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2798 2799 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2800 2801 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2802 2803 /*see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines 2804 *used for the AttachedDeviceInfo field */ 2805 2806 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2807 2808 /*values for SAS Expander Page 1 DiscoveryInfo field */ 2809 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2810 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2811 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2812 2813 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2814 2815 2816 /**************************************************************************** 2817 * SAS Device Config Pages 2818 ****************************************************************************/ 2819 2820 /*SAS Device Page 0 */ 2821 2822 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 { 2823 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2824 Header; /*0x00 */ 2825 U16 2826 Slot; /*0x08 */ 2827 U16 2828 EnclosureHandle; /*0x0A */ 2829 U64 2830 SASAddress; /*0x0C */ 2831 U16 2832 ParentDevHandle; /*0x14 */ 2833 U8 2834 PhyNum; /*0x16 */ 2835 U8 2836 AccessStatus; /*0x17 */ 2837 U16 2838 DevHandle; /*0x18 */ 2839 U8 2840 AttachedPhyIdentifier; /*0x1A */ 2841 U8 2842 ZoneGroup; /*0x1B */ 2843 U32 2844 DeviceInfo; /*0x1C */ 2845 U16 2846 Flags; /*0x20 */ 2847 U8 2848 PhysicalPort; /*0x22 */ 2849 U8 2850 MaxPortConnections; /*0x23 */ 2851 U64 2852 DeviceName; /*0x24 */ 2853 U8 2854 PortGroups; /*0x2C */ 2855 U8 2856 DmaGroup; /*0x2D */ 2857 U8 2858 ControlGroup; /*0x2E */ 2859 U8 2860 EnclosureLevel; /*0x2F */ 2861 U32 2862 ConnectorName[4]; /*0x30 */ 2863 U32 2864 Reserved3; /*0x34 */ 2865 } MPI2_CONFIG_PAGE_SAS_DEV_0, 2866 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2867 Mpi2SasDevicePage0_t, 2868 *pMpi2SasDevicePage0_t; 2869 2870 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2871 2872 /*values for SAS Device Page 0 AccessStatus field */ 2873 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2874 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2875 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2876 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2877 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2878 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2879 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2880 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2881 /*specific values for SATA Init failures */ 2882 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2883 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2884 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2885 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2886 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2887 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2888 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2889 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2890 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2891 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2892 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2893 2894 /*see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2895 2896 /*values for SAS Device Page 0 Flags field */ 2897 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2898 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2899 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2900 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2901 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2902 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2903 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2904 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2905 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2906 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2907 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2908 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2909 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2910 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2911 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2912 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2913 2914 2915 /*SAS Device Page 1 */ 2916 2917 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 { 2918 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2919 Header; /*0x00 */ 2920 U32 2921 Reserved1; /*0x08 */ 2922 U64 2923 SASAddress; /*0x0C */ 2924 U32 2925 Reserved2; /*0x14 */ 2926 U16 2927 DevHandle; /*0x18 */ 2928 U16 2929 Reserved3; /*0x1A */ 2930 U8 2931 InitialRegDeviceFIS[20];/*0x1C */ 2932 } MPI2_CONFIG_PAGE_SAS_DEV_1, 2933 *PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2934 Mpi2SasDevicePage1_t, 2935 *pMpi2SasDevicePage1_t; 2936 2937 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2938 2939 2940 /**************************************************************************** 2941 * SAS PHY Config Pages 2942 ****************************************************************************/ 2943 2944 /*SAS PHY Page 0 */ 2945 2946 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 { 2947 MPI2_CONFIG_EXTENDED_PAGE_HEADER 2948 Header; /*0x00 */ 2949 U16 2950 OwnerDevHandle; /*0x08 */ 2951 U16 2952 Reserved1; /*0x0A */ 2953 U16 2954 AttachedDevHandle; /*0x0C */ 2955 U8 2956 AttachedPhyIdentifier; /*0x0E */ 2957 U8 2958 Reserved2; /*0x0F */ 2959 U32 2960 AttachedPhyInfo; /*0x10 */ 2961 U8 2962 ProgrammedLinkRate; /*0x14 */ 2963 U8 2964 HwLinkRate; /*0x15 */ 2965 U8 2966 ChangeCount; /*0x16 */ 2967 U8 2968 Flags; /*0x17 */ 2969 U32 2970 PhyInfo; /*0x18 */ 2971 U8 2972 NegotiatedLinkRate; /*0x1C */ 2973 U8 2974 Reserved3; /*0x1D */ 2975 U16 2976 Reserved4; /*0x1E */ 2977 } MPI2_CONFIG_PAGE_SAS_PHY_0, 2978 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2979 Mpi2SasPhyPage0_t, *pMpi2SasPhyPage0_t; 2980 2981 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2982 2983 /*use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2984 2985 /*use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2986 2987 /*use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2988 2989 /*values for SAS PHY Page 0 Flags field */ 2990 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2991 2992 /*use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2993 2994 /*use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2995 2996 2997 /*SAS PHY Page 1 */ 2998 2999 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 { 3000 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3001 Header; /*0x00 */ 3002 U32 3003 Reserved1; /*0x08 */ 3004 U32 3005 InvalidDwordCount; /*0x0C */ 3006 U32 3007 RunningDisparityErrorCount; /*0x10 */ 3008 U32 3009 LossDwordSynchCount; /*0x14 */ 3010 U32 3011 PhyResetProblemCount; /*0x18 */ 3012 } MPI2_CONFIG_PAGE_SAS_PHY_1, 3013 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 3014 Mpi2SasPhyPage1_t, *pMpi2SasPhyPage1_t; 3015 3016 #define MPI2_SASPHY1_PAGEVERSION (0x01) 3017 3018 3019 /*SAS PHY Page 2 */ 3020 3021 typedef struct _MPI2_SASPHY2_PHY_EVENT { 3022 U8 PhyEventCode; /*0x00 */ 3023 U8 Reserved1; /*0x01 */ 3024 U16 Reserved2; /*0x02 */ 3025 U32 PhyEventInfo; /*0x04 */ 3026 } MPI2_SASPHY2_PHY_EVENT, *PTR_MPI2_SASPHY2_PHY_EVENT, 3027 Mpi2SasPhy2PhyEvent_t, *pMpi2SasPhy2PhyEvent_t; 3028 3029 /*use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 3030 3031 3032 /* 3033 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3034 *for NumPhyEvents at runtime before using PhyEvent[]. 3035 */ 3036 3037 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 { 3038 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3039 Header; /*0x00 */ 3040 U32 3041 Reserved1; /*0x08 */ 3042 U8 3043 NumPhyEvents; /*0x0C */ 3044 U8 3045 Reserved2; /*0x0D */ 3046 U16 3047 Reserved3; /*0x0E */ 3048 MPI2_SASPHY2_PHY_EVENT 3049 PhyEvent[]; /*0x10 */ 3050 } MPI2_CONFIG_PAGE_SAS_PHY_2, 3051 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 3052 Mpi2SasPhyPage2_t, 3053 *pMpi2SasPhyPage2_t; 3054 3055 #define MPI2_SASPHY2_PAGEVERSION (0x00) 3056 3057 3058 /*SAS PHY Page 3 */ 3059 3060 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG { 3061 U8 PhyEventCode; /*0x00 */ 3062 U8 Reserved1; /*0x01 */ 3063 U16 Reserved2; /*0x02 */ 3064 U8 CounterType; /*0x04 */ 3065 U8 ThresholdWindow; /*0x05 */ 3066 U8 TimeUnits; /*0x06 */ 3067 U8 Reserved3; /*0x07 */ 3068 U32 EventThreshold; /*0x08 */ 3069 U16 ThresholdFlags; /*0x0C */ 3070 U16 Reserved4; /*0x0E */ 3071 } MPI2_SASPHY3_PHY_EVENT_CONFIG, 3072 *PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 3073 Mpi2SasPhy3PhyEventConfig_t, 3074 *pMpi2SasPhy3PhyEventConfig_t; 3075 3076 /*values for PhyEventCode field */ 3077 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 3078 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 3079 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 3080 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 3081 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 3082 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3083 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3084 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3085 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3086 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3087 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3088 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3089 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3090 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3091 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3092 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3093 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3094 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3095 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3096 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3097 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3098 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3099 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3100 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3101 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3102 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3103 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3104 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3105 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3106 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3107 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3108 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3109 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3110 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3111 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3112 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3113 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3114 3115 /*Following codes are product specific and in MPI v2.6 and later */ 3116 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3117 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3118 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3119 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3120 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3121 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3122 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3123 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3124 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3125 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3126 3127 3128 /*values for the CounterType field */ 3129 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3130 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3131 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3132 3133 /*values for the TimeUnits field */ 3134 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3135 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3136 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3137 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3138 3139 /*values for the ThresholdFlags field */ 3140 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3141 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3142 3143 /* 3144 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3145 *for NumPhyEvents at runtime before using PhyEventConfig[]. 3146 */ 3147 3148 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 { 3149 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3150 Header; /*0x00 */ 3151 U32 3152 Reserved1; /*0x08 */ 3153 U8 3154 NumPhyEvents; /*0x0C */ 3155 U8 3156 Reserved2; /*0x0D */ 3157 U16 3158 Reserved3; /*0x0E */ 3159 MPI2_SASPHY3_PHY_EVENT_CONFIG 3160 PhyEventConfig[]; /*0x10 */ 3161 } MPI2_CONFIG_PAGE_SAS_PHY_3, 3162 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3163 Mpi2SasPhyPage3_t, *pMpi2SasPhyPage3_t; 3164 3165 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3166 3167 3168 /*SAS PHY Page 4 */ 3169 3170 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 { 3171 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3172 Header; /*0x00 */ 3173 U16 3174 Reserved1; /*0x08 */ 3175 U8 3176 Reserved2; /*0x0A */ 3177 U8 3178 Flags; /*0x0B */ 3179 U8 3180 InitialFrame[28]; /*0x0C */ 3181 } MPI2_CONFIG_PAGE_SAS_PHY_4, 3182 *PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3183 Mpi2SasPhyPage4_t, *pMpi2SasPhyPage4_t; 3184 3185 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3186 3187 /*values for the Flags field */ 3188 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3189 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3190 3191 3192 3193 3194 /**************************************************************************** 3195 * SAS Port Config Pages 3196 ****************************************************************************/ 3197 3198 /*SAS Port Page 0 */ 3199 3200 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 { 3201 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3202 Header; /*0x00 */ 3203 U8 3204 PortNumber; /*0x08 */ 3205 U8 3206 PhysicalPort; /*0x09 */ 3207 U8 3208 PortWidth; /*0x0A */ 3209 U8 3210 PhysicalPortWidth; /*0x0B */ 3211 U8 3212 ZoneGroup; /*0x0C */ 3213 U8 3214 Reserved1; /*0x0D */ 3215 U16 3216 Reserved2; /*0x0E */ 3217 U64 3218 SASAddress; /*0x10 */ 3219 U32 3220 DeviceInfo; /*0x18 */ 3221 U32 3222 Reserved3; /*0x1C */ 3223 U32 3224 Reserved4; /*0x20 */ 3225 } MPI2_CONFIG_PAGE_SAS_PORT_0, 3226 *PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3227 Mpi2SasPortPage0_t, *pMpi2SasPortPage0_t; 3228 3229 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3230 3231 /*see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3232 3233 3234 /**************************************************************************** 3235 * SAS Enclosure Config Pages 3236 ****************************************************************************/ 3237 3238 /*SAS Enclosure Page 0 */ 3239 3240 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 { 3241 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3242 U32 Reserved1; /*0x08 */ 3243 U64 EnclosureLogicalID; /*0x0C */ 3244 U16 Flags; /*0x14 */ 3245 U16 EnclosureHandle; /*0x16 */ 3246 U16 NumSlots; /*0x18 */ 3247 U16 StartSlot; /*0x1A */ 3248 U8 ChassisSlot; /*0x1C */ 3249 U8 EnclosureLevel; /*0x1D */ 3250 U16 SEPDevHandle; /*0x1E */ 3251 U8 OEMRD; /*0x20 */ 3252 U8 Reserved1a; /*0x21 */ 3253 U16 Reserved2; /*0x22 */ 3254 U32 Reserved3; /*0x24 */ 3255 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3256 *PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3257 Mpi2SasEnclosurePage0_t, *pMpi2SasEnclosurePage0_t, 3258 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3259 *PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3260 Mpi26EnclosurePage0_t, *pMpi26EnclosurePage0_t; 3261 3262 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3263 3264 /*values for SAS Enclosure Page 0 Flags field */ 3265 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3266 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3267 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3268 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3269 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3270 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3271 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3272 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3273 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3274 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3275 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3276 3277 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3278 3279 /*Values for Enclosure Page 0 Flags field */ 3280 #define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3281 #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3282 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3283 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3284 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3285 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3286 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3287 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3288 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3289 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3290 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3291 3292 /**************************************************************************** 3293 * Log Config Page 3294 ****************************************************************************/ 3295 3296 /*Log Page 0 */ 3297 3298 /* 3299 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3300 *for NumLogEntries at runtime before using LogEntry[]. 3301 */ 3302 3303 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3304 3305 typedef struct _MPI2_LOG_0_ENTRY { 3306 U64 TimeStamp; /*0x00 */ 3307 U32 Reserved1; /*0x08 */ 3308 U16 LogSequence; /*0x0C */ 3309 U16 LogEntryQualifier; /*0x0E */ 3310 U8 VP_ID; /*0x10 */ 3311 U8 VF_ID; /*0x11 */ 3312 U16 Reserved2; /*0x12 */ 3313 U8 3314 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/*0x14 */ 3315 } MPI2_LOG_0_ENTRY, *PTR_MPI2_LOG_0_ENTRY, 3316 Mpi2Log0Entry_t, *pMpi2Log0Entry_t; 3317 3318 /*values for Log Page 0 LogEntry LogEntryQualifier field */ 3319 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3320 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3321 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3322 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3323 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3324 3325 typedef struct _MPI2_CONFIG_PAGE_LOG_0 { 3326 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3327 U32 Reserved1; /*0x08 */ 3328 U32 Reserved2; /*0x0C */ 3329 U16 NumLogEntries;/*0x10 */ 3330 U16 Reserved3; /*0x12 */ 3331 MPI2_LOG_0_ENTRY LogEntry[]; /*0x14 */ 3332 } MPI2_CONFIG_PAGE_LOG_0, *PTR_MPI2_CONFIG_PAGE_LOG_0, 3333 Mpi2LogPage0_t, *pMpi2LogPage0_t; 3334 3335 #define MPI2_LOG_0_PAGEVERSION (0x02) 3336 3337 3338 /**************************************************************************** 3339 * RAID Config Page 3340 ****************************************************************************/ 3341 3342 /*RAID Page 0 */ 3343 3344 /* 3345 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3346 *for NumElements at runtime before using ConfigElement[]. 3347 */ 3348 3349 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT { 3350 U16 ElementFlags; /*0x00 */ 3351 U16 VolDevHandle; /*0x02 */ 3352 U8 HotSparePool; /*0x04 */ 3353 U8 PhysDiskNum; /*0x05 */ 3354 U16 PhysDiskDevHandle; /*0x06 */ 3355 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3356 *PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3357 Mpi2RaidConfig0ConfigElement_t, 3358 *pMpi2RaidConfig0ConfigElement_t; 3359 3360 /*values for the ElementFlags field */ 3361 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3362 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3363 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3364 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3365 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3366 3367 3368 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 { 3369 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3370 U8 NumHotSpares; /*0x08 */ 3371 U8 NumPhysDisks; /*0x09 */ 3372 U8 NumVolumes; /*0x0A */ 3373 U8 ConfigNum; /*0x0B */ 3374 U32 Flags; /*0x0C */ 3375 U8 ConfigGUID[24]; /*0x10 */ 3376 U32 Reserved1; /*0x28 */ 3377 U8 NumElements; /*0x2C */ 3378 U8 Reserved2; /*0x2D */ 3379 U16 Reserved3; /*0x2E */ 3380 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[];/*0x30 */ 3381 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3382 *PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3383 Mpi2RaidConfigurationPage0_t, 3384 *pMpi2RaidConfigurationPage0_t; 3385 3386 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3387 3388 /*values for RAID Configuration Page 0 Flags field */ 3389 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3390 3391 3392 /**************************************************************************** 3393 * Driver Persistent Mapping Config Pages 3394 ****************************************************************************/ 3395 3396 /*Driver Persistent Mapping Page 0 */ 3397 3398 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY { 3399 U64 PhysicalIdentifier; /*0x00 */ 3400 U16 MappingInformation; /*0x08 */ 3401 U16 DeviceIndex; /*0x0A */ 3402 U32 PhysicalBitsMapping; /*0x0C */ 3403 U32 Reserved1; /*0x10 */ 3404 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3405 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3406 Mpi2DriverMap0Entry_t, *pMpi2DriverMap0Entry_t; 3407 3408 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 { 3409 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3410 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /*0x08 */ 3411 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3412 *PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3413 Mpi2DriverMappingPage0_t, *pMpi2DriverMappingPage0_t; 3414 3415 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3416 3417 /*values for Driver Persistent Mapping Page 0 MappingInformation field */ 3418 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3419 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3420 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3421 3422 3423 /**************************************************************************** 3424 * Ethernet Config Pages 3425 ****************************************************************************/ 3426 3427 /*Ethernet Page 0 */ 3428 3429 /*IP address (union of IPv4 and IPv6) */ 3430 typedef union _MPI2_ETHERNET_IP_ADDR { 3431 U32 IPv4Addr; 3432 U32 IPv6Addr[4]; 3433 } MPI2_ETHERNET_IP_ADDR, *PTR_MPI2_ETHERNET_IP_ADDR, 3434 Mpi2EthernetIpAddr_t, *pMpi2EthernetIpAddr_t; 3435 3436 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3437 3438 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 { 3439 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3440 U8 NumInterfaces; /*0x08 */ 3441 U8 Reserved0; /*0x09 */ 3442 U16 Reserved1; /*0x0A */ 3443 U32 Status; /*0x0C */ 3444 U8 MediaState; /*0x10 */ 3445 U8 Reserved2; /*0x11 */ 3446 U16 Reserved3; /*0x12 */ 3447 U8 MacAddress[6]; /*0x14 */ 3448 U8 Reserved4; /*0x1A */ 3449 U8 Reserved5; /*0x1B */ 3450 MPI2_ETHERNET_IP_ADDR IpAddress; /*0x1C */ 3451 MPI2_ETHERNET_IP_ADDR SubnetMask; /*0x2C */ 3452 MPI2_ETHERNET_IP_ADDR GatewayIpAddress;/*0x3C */ 3453 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /*0x4C */ 3454 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /*0x5C */ 3455 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /*0x6C */ 3456 U8 3457 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3458 } MPI2_CONFIG_PAGE_ETHERNET_0, 3459 *PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3460 Mpi2EthernetPage0_t, *pMpi2EthernetPage0_t; 3461 3462 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3463 3464 /*values for Ethernet Page 0 Status field */ 3465 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3466 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3467 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3468 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3469 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3470 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3471 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3472 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3473 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3474 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3475 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3476 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3477 3478 /*values for Ethernet Page 0 MediaState field */ 3479 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3480 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3481 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3482 3483 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3484 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3485 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3486 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3487 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3488 3489 3490 /*Ethernet Page 1 */ 3491 3492 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 { 3493 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3494 Header; /*0x00 */ 3495 U32 3496 Reserved0; /*0x08 */ 3497 U32 3498 Flags; /*0x0C */ 3499 U8 3500 MediaState; /*0x10 */ 3501 U8 3502 Reserved1; /*0x11 */ 3503 U16 3504 Reserved2; /*0x12 */ 3505 U8 3506 MacAddress[6]; /*0x14 */ 3507 U8 3508 Reserved3; /*0x1A */ 3509 U8 3510 Reserved4; /*0x1B */ 3511 MPI2_ETHERNET_IP_ADDR 3512 StaticIpAddress; /*0x1C */ 3513 MPI2_ETHERNET_IP_ADDR 3514 StaticSubnetMask; /*0x2C */ 3515 MPI2_ETHERNET_IP_ADDR 3516 StaticGatewayIpAddress; /*0x3C */ 3517 MPI2_ETHERNET_IP_ADDR 3518 StaticDNS1IpAddress; /*0x4C */ 3519 MPI2_ETHERNET_IP_ADDR 3520 StaticDNS2IpAddress; /*0x5C */ 3521 U32 3522 Reserved5; /*0x6C */ 3523 U32 3524 Reserved6; /*0x70 */ 3525 U32 3526 Reserved7; /*0x74 */ 3527 U32 3528 Reserved8; /*0x78 */ 3529 U8 3530 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/*0x7C */ 3531 } MPI2_CONFIG_PAGE_ETHERNET_1, 3532 *PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3533 Mpi2EthernetPage1_t, *pMpi2EthernetPage1_t; 3534 3535 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3536 3537 /*values for Ethernet Page 1 Flags field */ 3538 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3539 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3540 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3541 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3542 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3543 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3544 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3545 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3546 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3547 3548 /*values for Ethernet Page 1 MediaState field */ 3549 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3550 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3551 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3552 3553 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3554 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3555 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3556 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3557 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3558 3559 3560 /**************************************************************************** 3561 * Extended Manufacturing Config Pages 3562 ****************************************************************************/ 3563 3564 /* 3565 *Generic structure to use for product-specific extended manufacturing pages 3566 *(currently Extended Manufacturing Page 40 through Extended Manufacturing 3567 *Page 60). 3568 */ 3569 3570 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS { 3571 MPI2_CONFIG_EXTENDED_PAGE_HEADER 3572 Header; /*0x00 */ 3573 U32 3574 ProductSpecificInfo; /*0x08 */ 3575 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3576 *PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3577 Mpi2ExtManufacturingPagePS_t, 3578 *pMpi2ExtManufacturingPagePS_t; 3579 3580 /*PageVersion should be provided by product-specific code */ 3581 3582 3583 3584 /**************************************************************************** 3585 * values for fields used by several types of PCIe Config Pages 3586 ****************************************************************************/ 3587 3588 /*values for NegotiatedLinkRates fields */ 3589 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3590 /*link rates used for Negotiated Physical Link Rate */ 3591 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3592 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3593 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3594 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3595 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3596 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3597 #define MPI26_PCIE_NEG_LINK_RATE_32_0 (0x06) 3598 3599 3600 /**************************************************************************** 3601 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3602 ****************************************************************************/ 3603 3604 /*PCIe IO Unit Page 0 */ 3605 3606 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA { 3607 U8 Link; /*0x00 */ 3608 U8 LinkFlags; /*0x01 */ 3609 U8 PhyFlags; /*0x02 */ 3610 U8 NegotiatedLinkRate; /*0x03 */ 3611 U32 ControllerPhyDeviceInfo;/*0x04 */ 3612 U16 AttachedDevHandle; /*0x08 */ 3613 U16 ControllerDevHandle; /*0x0A */ 3614 U32 EnumerationStatus; /*0x0C */ 3615 U32 Reserved1; /*0x10 */ 3616 } MPI26_PCIE_IO_UNIT0_PHY_DATA, 3617 *PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3618 Mpi26PCIeIOUnit0PhyData_t, *pMpi26PCIeIOUnit0PhyData_t; 3619 3620 /* 3621 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3622 *for NumPhys at runtime before using PhyData[]. 3623 */ 3624 3625 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 { 3626 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3627 U32 Reserved1; /*0x08 */ 3628 U8 NumPhys; /*0x0C */ 3629 U8 InitStatus; /*0x0D */ 3630 U16 Reserved3; /*0x0E */ 3631 MPI26_PCIE_IO_UNIT0_PHY_DATA 3632 PhyData[]; /*0x10 */ 3633 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3634 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3635 Mpi26PCIeIOUnitPage0_t, *pMpi26PCIeIOUnitPage0_t; 3636 3637 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3638 3639 /*values for PCIe IO Unit Page 0 LinkFlags */ 3640 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3641 3642 /*values for PCIe IO Unit Page 0 PhyFlags */ 3643 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3644 3645 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3646 3647 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3648 *values 3649 */ 3650 3651 /*values for PCIe IO Unit Page 0 EnumerationStatus */ 3652 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3653 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3654 3655 3656 /*PCIe IO Unit Page 1 */ 3657 3658 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA { 3659 U8 Link; /*0x00 */ 3660 U8 LinkFlags; /*0x01 */ 3661 U8 PhyFlags; /*0x02 */ 3662 U8 MaxMinLinkRate; /*0x03 */ 3663 U32 ControllerPhyDeviceInfo; /*0x04 */ 3664 U32 Reserved1; /*0x08 */ 3665 } MPI26_PCIE_IO_UNIT1_PHY_DATA, 3666 *PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3667 Mpi26PCIeIOUnit1PhyData_t, *pMpi26PCIeIOUnit1PhyData_t; 3668 3669 /*values for LinkFlags */ 3670 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00) 3671 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01) 3672 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02) 3673 3674 /* 3675 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3676 *for NumPhys at runtime before using PhyData[]. 3677 */ 3678 3679 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 { 3680 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3681 U16 ControlFlags; /*0x08 */ 3682 U16 Reserved; /*0x0A */ 3683 U16 AdditionalControlFlags; /*0x0C */ 3684 U16 NVMeMaxQueueDepth; /*0x0E */ 3685 U8 NumPhys; /*0x10 */ 3686 U8 DMDReportPCIe; /*0x11 */ 3687 U16 Reserved2; /*0x12 */ 3688 MPI26_PCIE_IO_UNIT1_PHY_DATA 3689 PhyData[]; /*0x14 */ 3690 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3691 *PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3692 Mpi26PCIeIOUnitPage1_t, *pMpi26PCIeIOUnitPage1_t; 3693 3694 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3695 3696 /*values for PCIe IO Unit Page 1 PhyFlags */ 3697 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3698 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3699 3700 /*values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3701 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3702 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3703 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3704 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3705 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3706 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3707 #define MPI26_PCIEIOUNIT1_MAX_RATE_32_0 (0x60) 3708 3709 /*values for PCIe IO Unit Page 1 DMDReportPCIe */ 3710 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_MASK (0x80) 3711 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_1_SEC (0x00) 3712 #define MPI26_PCIEIOUNIT1_DMDRPT_UNIT_16_SEC (0x80) 3713 #define MPI26_PCIEIOUNIT1_DMDRPT_DELAY_TIME_MASK (0x7F) 3714 3715 /*see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo 3716 *values 3717 */ 3718 3719 3720 /**************************************************************************** 3721 * PCIe Switch Config Pages (MPI v2.6 and later) 3722 ****************************************************************************/ 3723 3724 /*PCIe Switch Page 0 */ 3725 3726 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 { 3727 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3728 U8 PhysicalPort; /*0x08 */ 3729 U8 Reserved1; /*0x09 */ 3730 U16 Reserved2; /*0x0A */ 3731 U16 DevHandle; /*0x0C */ 3732 U16 ParentDevHandle; /*0x0E */ 3733 U8 NumPorts; /*0x10 */ 3734 U8 PCIeLevel; /*0x11 */ 3735 U16 Reserved3; /*0x12 */ 3736 U32 Reserved4; /*0x14 */ 3737 U32 Reserved5; /*0x18 */ 3738 U32 Reserved6; /*0x1C */ 3739 } MPI26_CONFIG_PAGE_PSWITCH_0, *PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3740 Mpi26PCIeSwitchPage0_t, *pMpi26PCIeSwitchPage0_t; 3741 3742 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3743 3744 3745 /*PCIe Switch Page 1 */ 3746 3747 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 { 3748 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3749 U8 PhysicalPort; /*0x08 */ 3750 U8 Reserved1; /*0x09 */ 3751 U16 Reserved2; /*0x0A */ 3752 U8 NumPorts; /*0x0C */ 3753 U8 PortNum; /*0x0D */ 3754 U16 AttachedDevHandle; /*0x0E */ 3755 U16 SwitchDevHandle; /*0x10 */ 3756 U8 NegotiatedPortWidth; /*0x12 */ 3757 U8 NegotiatedLinkRate; /*0x13 */ 3758 U32 Reserved4; /*0x14 */ 3759 U32 Reserved5; /*0x18 */ 3760 } MPI26_CONFIG_PAGE_PSWITCH_1, *PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3761 Mpi26PCIeSwitchPage1_t, *pMpi26PCIeSwitchPage1_t; 3762 3763 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3764 3765 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3766 3767 /* defines for the Flags field */ 3768 #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002) 3769 #define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001) 3770 3771 /**************************************************************************** 3772 * PCIe Device Config Pages (MPI v2.6 and later) 3773 ****************************************************************************/ 3774 3775 /*PCIe Device Page 0 */ 3776 3777 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 { 3778 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3779 U16 Slot; /*0x08 */ 3780 U16 EnclosureHandle; /*0x0A */ 3781 U64 WWID; /*0x0C */ 3782 U16 ParentDevHandle; /*0x14 */ 3783 U8 PortNum; /*0x16 */ 3784 U8 AccessStatus; /*0x17 */ 3785 U16 DevHandle; /*0x18 */ 3786 U8 PhysicalPort; /*0x1A */ 3787 U8 Reserved1; /*0x1B */ 3788 U32 DeviceInfo; /*0x1C */ 3789 U32 Flags; /*0x20 */ 3790 U8 SupportedLinkRates; /*0x24 */ 3791 U8 MaxPortWidth; /*0x25 */ 3792 U8 NegotiatedPortWidth; /*0x26 */ 3793 U8 NegotiatedLinkRate; /*0x27 */ 3794 U8 EnclosureLevel; /*0x28 */ 3795 U8 Reserved2; /*0x29 */ 3796 U16 Reserved3; /*0x2A */ 3797 U8 ConnectorName[4]; /*0x2C */ 3798 U32 Reserved4; /*0x30 */ 3799 U32 Reserved5; /*0x34 */ 3800 } MPI26_CONFIG_PAGE_PCIEDEV_0, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3801 Mpi26PCIeDevicePage0_t, *pMpi26PCIeDevicePage0_t; 3802 3803 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3804 3805 /*values for PCIe Device Page 0 AccessStatus field */ 3806 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3807 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3808 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3809 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3810 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3811 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3812 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3813 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3814 3815 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3816 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3817 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3818 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3819 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3820 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3821 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3822 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3823 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3824 3825 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3826 3827 /*see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo 3828 *field 3829 */ 3830 3831 /*values for PCIe Device Page 0 Flags field*/ 3832 #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000) 3833 #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000) 3834 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000) 3835 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000) 3836 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000) 3837 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400) 3838 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200) 3839 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100) 3840 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080) 3841 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040) 3842 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020) 3843 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010) 3844 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002) 3845 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001) 3846 3847 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3848 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3849 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3850 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3851 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3852 3853 /*use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3854 3855 3856 /*PCIe Device Page 2 */ 3857 3858 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 { 3859 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3860 U16 DevHandle; /*0x08 */ 3861 U8 ControllerResetTO; /* 0x0A */ 3862 U8 Reserved1; /* 0x0B */ 3863 U32 MaximumDataTransferSize; /*0x0C */ 3864 U32 Capabilities; /*0x10 */ 3865 U16 NOIOB; /* 0x14 */ 3866 U16 ShutdownLatency; /* 0x16 */ 3867 U16 VendorID; /* 0x18 */ 3868 U16 DeviceID; /* 0x1A */ 3869 U16 SubsystemVendorID; /* 0x1C */ 3870 U16 SubsystemID; /* 0x1E */ 3871 U8 RevisionID; /* 0x20 */ 3872 U8 Reserved21[3]; /* 0x21 */ 3873 } MPI26_CONFIG_PAGE_PCIEDEV_2, *PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3874 Mpi26PCIeDevicePage2_t, *pMpi26PCIeDevicePage2_t; 3875 3876 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) 3877 3878 /*defines for PCIe Device Page 2 Capabilities field */ 3879 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) 3880 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3881 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3882 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3883 3884 /* Defines for the NOIOB field */ 3885 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) 3886 3887 /**************************************************************************** 3888 * PCIe Link Config Pages (MPI v2.6 and later) 3889 ****************************************************************************/ 3890 3891 /*PCIe Link Page 1 */ 3892 3893 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 { 3894 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3895 U8 Link; /*0x08 */ 3896 U8 Reserved1; /*0x09 */ 3897 U16 Reserved2; /*0x0A */ 3898 U32 CorrectableErrorCount; /*0x0C */ 3899 U16 NonFatalErrorCount; /*0x10 */ 3900 U16 Reserved3; /*0x12 */ 3901 U16 FatalErrorCount; /*0x14 */ 3902 U16 Reserved4; /*0x16 */ 3903 } MPI26_CONFIG_PAGE_PCIELINK_1, *PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3904 Mpi26PcieLinkPage1_t, *pMpi26PcieLinkPage1_t; 3905 3906 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3907 3908 /*PCIe Link Page 2 */ 3909 3910 typedef struct _MPI26_PCIELINK2_LINK_EVENT { 3911 U8 LinkEventCode; /*0x00 */ 3912 U8 Reserved1; /*0x01 */ 3913 U16 Reserved2; /*0x02 */ 3914 U32 LinkEventInfo; /*0x04 */ 3915 } MPI26_PCIELINK2_LINK_EVENT, *PTR_MPI26_PCIELINK2_LINK_EVENT, 3916 Mpi26PcieLink2LinkEvent_t, *pMpi26PcieLink2LinkEvent_t; 3917 3918 /*use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3919 3920 3921 /* 3922 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3923 *for NumLinkEvents at runtime before using LinkEvent[]. 3924 */ 3925 3926 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 { 3927 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3928 U8 Link; /*0x08 */ 3929 U8 Reserved1; /*0x09 */ 3930 U16 Reserved2; /*0x0A */ 3931 U8 NumLinkEvents; /*0x0C */ 3932 U8 Reserved3; /*0x0D */ 3933 U16 Reserved4; /*0x0E */ 3934 MPI26_PCIELINK2_LINK_EVENT 3935 LinkEvent[]; /*0x10 */ 3936 } MPI26_CONFIG_PAGE_PCIELINK_2, *PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3937 Mpi26PcieLinkPage2_t, *pMpi26PcieLinkPage2_t; 3938 3939 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3940 3941 /*PCIe Link Page 3 */ 3942 3943 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG { 3944 U8 LinkEventCode; /*0x00 */ 3945 U8 Reserved1; /*0x01 */ 3946 U16 Reserved2; /*0x02 */ 3947 U8 CounterType; /*0x04 */ 3948 U8 ThresholdWindow; /*0x05 */ 3949 U8 TimeUnits; /*0x06 */ 3950 U8 Reserved3; /*0x07 */ 3951 U32 EventThreshold; /*0x08 */ 3952 U16 ThresholdFlags; /*0x0C */ 3953 U16 Reserved4; /*0x0E */ 3954 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, *PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3955 Mpi26PcieLink3LinkEventConfig_t, *pMpi26PcieLink3LinkEventConfig_t; 3956 3957 /*values for LinkEventCode field */ 3958 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3959 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3960 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3961 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3962 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3963 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3964 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3965 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3966 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3967 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3968 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3969 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3970 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3971 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3972 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3973 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3974 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3975 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3976 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3977 3978 /*values for the CounterType field */ 3979 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3980 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3981 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3982 3983 /*values for the TimeUnits field */ 3984 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 3985 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 3986 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 3987 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 3988 3989 /*values for the ThresholdFlags field */ 3990 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 3991 3992 /* 3993 *Host code (drivers, BIOS, utilities, etc.) should check the value returned 3994 *for NumLinkEvents at runtime before using LinkEventConfig[]. 3995 */ 3996 3997 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 { 3998 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /*0x00 */ 3999 U8 Link; /*0x08 */ 4000 U8 Reserved1; /*0x09 */ 4001 U16 Reserved2; /*0x0A */ 4002 U8 NumLinkEvents; /*0x0C */ 4003 U8 Reserved3; /*0x0D */ 4004 U16 Reserved4; /*0x0E */ 4005 MPI26_PCIELINK3_LINK_EVENT_CONFIG 4006 LinkEventConfig[]; /*0x10 */ 4007 } MPI26_CONFIG_PAGE_PCIELINK_3, *PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 4008 Mpi26PcieLinkPage3_t, *pMpi26PcieLinkPage3_t; 4009 4010 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 4011 4012 4013 #endif 4014