1 // SPDX-License-Identifier: BSD-3-Clause
2 /*
3 * Copyright (c) 2020, MIPI Alliance, Inc.
4 *
5 * Author: Nicolas Pitre <npitre@baylibre.com>
6 *
7 * I3C HCI v1.0/v1.1 Command Descriptor Handling
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/i3c/master.h>
12
13 #include "hci.h"
14 #include "cmd.h"
15 #include "dat.h"
16 #include "dct.h"
17
18 /*
19 * Address Assignment Command
20 */
21
22 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2)
23
24 #define CMD_A0_TOC W0_BIT_(31)
25 #define CMD_A0_ROC W0_BIT_(30)
26 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v)
27 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
28 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
29 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
30
31 /*
32 * Immediate Data Transfer Command
33 */
34
35 #define CMD_0_ATTR_I FIELD_PREP(CMD_0_ATTR, 0x1)
36
37 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v)
38 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v)
39 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v)
40 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MASK(39, 32), v)
41 #define CMD_I1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v)
42 #define CMD_I0_TOC W0_BIT_(31)
43 #define CMD_I0_ROC W0_BIT_(30)
44 #define CMD_I0_RNW W0_BIT_(29)
45 #define CMD_I0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
46 #define CMD_I0_DTT(v) FIELD_PREP(W0_MASK(25, 23), v)
47 #define CMD_I0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
48 #define CMD_I0_CP W0_BIT_(15)
49 #define CMD_I0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
50 #define CMD_I0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
51
52 /*
53 * Regular Data Transfer Command
54 */
55
56 #define CMD_0_ATTR_R FIELD_PREP(CMD_0_ATTR, 0x0)
57
58 #define CMD_R1_DATA_LENGTH(v) FIELD_PREP(W1_MASK(63, 48), v)
59 #define CMD_R1_DEF_BYTE(v) FIELD_PREP(W1_MASK(39, 32), v)
60 #define CMD_R0_TOC W0_BIT_(31)
61 #define CMD_R0_ROC W0_BIT_(30)
62 #define CMD_R0_RNW W0_BIT_(29)
63 #define CMD_R0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
64 #define CMD_R0_DBP W0_BIT_(25)
65 #define CMD_R0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
66 #define CMD_R0_CP W0_BIT_(15)
67 #define CMD_R0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
68 #define CMD_R0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
69
70 /*
71 * Combo Transfer (Write + Write/Read) Command
72 */
73
74 #define CMD_0_ATTR_C FIELD_PREP(CMD_0_ATTR, 0x3)
75
76 #define CMD_C1_DATA_LENGTH(v) FIELD_PREP(W1_MASK(63, 48), v)
77 #define CMD_C1_OFFSET(v) FIELD_PREP(W1_MASK(47, 32), v)
78 #define CMD_C0_TOC W0_BIT_(31)
79 #define CMD_C0_ROC W0_BIT_(30)
80 #define CMD_C0_RNW W0_BIT_(29)
81 #define CMD_C0_MODE(v) FIELD_PREP(W0_MASK(28, 26), v)
82 #define CMD_C0_16_BIT_SUBOFFSET W0_BIT_(25)
83 #define CMD_C0_FIRST_PHASE_MODE W0_BIT_(24)
84 #define CMD_C0_DATA_LENGTH_POSITION(v) FIELD_PREP(W0_MASK(23, 22), v)
85 #define CMD_C0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v)
86 #define CMD_C0_CP W0_BIT_(15)
87 #define CMD_C0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v)
88 #define CMD_C0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
89
90 /*
91 * Internal Control Command
92 */
93
94 #define CMD_0_ATTR_M FIELD_PREP(CMD_0_ATTR, 0x7)
95
96 #define CMD_M1_VENDOR_SPECIFIC W1_MASK(63, 32)
97 #define CMD_M0_MIPI_RESERVED W0_MASK(31, 12)
98 #define CMD_M0_MIPI_CMD W0_MASK(11, 8)
99 #define CMD_M0_VENDOR_INFO_PRESENT W0_BIT_( 7)
100 #define CMD_M0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v)
101
102 /* Data Transfer Speed and Mode */
103 enum hci_cmd_mode {
104 MODE_I3C_SDR0 = 0x0,
105 MODE_I3C_SDR1 = 0x1,
106 MODE_I3C_SDR2 = 0x2,
107 MODE_I3C_SDR3 = 0x3,
108 MODE_I3C_SDR4 = 0x4,
109 MODE_I3C_HDR_TSx = 0x5,
110 MODE_I3C_HDR_DDR = 0x6,
111 MODE_I3C_HDR_BT = 0x7,
112 MODE_I3C_Fm_FmP = 0x8,
113 MODE_I2C_Fm = 0x0,
114 MODE_I2C_FmP = 0x1,
115 MODE_I2C_UD1 = 0x2,
116 MODE_I2C_UD2 = 0x3,
117 MODE_I2C_UD3 = 0x4,
118 };
119
get_i3c_mode(struct i3c_hci * hci)120 static enum hci_cmd_mode get_i3c_mode(struct i3c_hci *hci)
121 {
122 struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
123
124 if (bus->scl_rate.i3c > 8000000)
125 return MODE_I3C_SDR0;
126 if (bus->scl_rate.i3c > 6000000)
127 return MODE_I3C_SDR1;
128 if (bus->scl_rate.i3c > 4000000)
129 return MODE_I3C_SDR2;
130 if (bus->scl_rate.i3c > 2000000)
131 return MODE_I3C_SDR3;
132 return MODE_I3C_SDR4;
133 }
134
get_i2c_mode(struct i3c_hci * hci)135 static enum hci_cmd_mode get_i2c_mode(struct i3c_hci *hci)
136 {
137 struct i3c_bus *bus = i3c_master_get_bus(&hci->master);
138
139 if (bus->scl_rate.i2c >= 1000000)
140 return MODE_I2C_FmP;
141 return MODE_I2C_Fm;
142 }
143
fill_data_bytes(struct hci_xfer * xfer,u8 * data,unsigned int data_len)144 static void fill_data_bytes(struct hci_xfer *xfer, u8 *data,
145 unsigned int data_len)
146 {
147 xfer->cmd_desc[1] = 0;
148 switch (data_len) {
149 case 4:
150 xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_4(data[3]);
151 fallthrough;
152 case 3:
153 xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_3(data[2]);
154 fallthrough;
155 case 2:
156 xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_2(data[1]);
157 fallthrough;
158 case 1:
159 xfer->cmd_desc[1] |= CMD_I1_DATA_BYTE_1(data[0]);
160 fallthrough;
161 case 0:
162 break;
163 }
164 /* we consumed all the data with the cmd descriptor */
165 xfer->data = NULL;
166 }
167
hci_cmd_v1_prep_ccc(struct i3c_hci * hci,struct hci_xfer * xfer,u8 ccc_addr,u8 ccc_cmd,bool raw)168 static int hci_cmd_v1_prep_ccc(struct i3c_hci *hci,
169 struct hci_xfer *xfer,
170 u8 ccc_addr, u8 ccc_cmd, bool raw)
171 {
172 unsigned int dat_idx = 0;
173 enum hci_cmd_mode mode = get_i3c_mode(hci);
174 u8 *data = xfer->data;
175 unsigned int data_len = xfer->data_len;
176 bool rnw = xfer->rnw;
177 int ret;
178
179 /* this should never happen */
180 if (WARN_ON(raw))
181 return -EINVAL;
182
183 if (ccc_addr != I3C_BROADCAST_ADDR) {
184 ret = mipi_i3c_hci_dat_v1.get_index(hci, ccc_addr);
185 if (ret < 0)
186 return ret;
187 dat_idx = ret;
188 }
189
190 xfer->cmd_tid = hci_get_tid();
191
192 if (!rnw && data_len <= 4) {
193 /* we use an Immediate Data Transfer Command */
194 xfer->cmd_desc[0] =
195 CMD_0_ATTR_I |
196 CMD_I0_TID(xfer->cmd_tid) |
197 CMD_I0_CMD(ccc_cmd) | CMD_I0_CP |
198 CMD_I0_DEV_INDEX(dat_idx) |
199 CMD_I0_DTT(data_len) |
200 CMD_I0_MODE(mode);
201 fill_data_bytes(xfer, data, data_len);
202 } else {
203 /* we use a Regular Data Transfer Command */
204 xfer->cmd_desc[0] =
205 CMD_0_ATTR_R |
206 CMD_R0_TID(xfer->cmd_tid) |
207 CMD_R0_CMD(ccc_cmd) | CMD_R0_CP |
208 CMD_R0_DEV_INDEX(dat_idx) |
209 CMD_R0_MODE(mode) |
210 (rnw ? CMD_R0_RNW : 0);
211 xfer->cmd_desc[1] =
212 CMD_R1_DATA_LENGTH(data_len);
213 }
214
215 return 0;
216 }
217
hci_cmd_v1_prep_i3c_xfer(struct i3c_hci * hci,struct i3c_dev_desc * dev,struct hci_xfer * xfer)218 static void hci_cmd_v1_prep_i3c_xfer(struct i3c_hci *hci,
219 struct i3c_dev_desc *dev,
220 struct hci_xfer *xfer)
221 {
222 struct i3c_hci_dev_data *dev_data = i3c_dev_get_master_data(dev);
223 unsigned int dat_idx = dev_data->dat_idx;
224 enum hci_cmd_mode mode = get_i3c_mode(hci);
225 u8 *data = xfer->data;
226 unsigned int data_len = xfer->data_len;
227 bool rnw = xfer->rnw;
228
229 xfer->cmd_tid = hci_get_tid();
230
231 if (!rnw && data_len <= 4) {
232 /* we use an Immediate Data Transfer Command */
233 xfer->cmd_desc[0] =
234 CMD_0_ATTR_I |
235 CMD_I0_TID(xfer->cmd_tid) |
236 CMD_I0_DEV_INDEX(dat_idx) |
237 CMD_I0_DTT(data_len) |
238 CMD_I0_MODE(mode);
239 fill_data_bytes(xfer, data, data_len);
240 } else {
241 /* we use a Regular Data Transfer Command */
242 xfer->cmd_desc[0] =
243 CMD_0_ATTR_R |
244 CMD_R0_TID(xfer->cmd_tid) |
245 CMD_R0_DEV_INDEX(dat_idx) |
246 CMD_R0_MODE(mode) |
247 (rnw ? CMD_R0_RNW : 0);
248 xfer->cmd_desc[1] =
249 CMD_R1_DATA_LENGTH(data_len);
250 }
251 }
252
hci_cmd_v1_prep_i2c_xfer(struct i3c_hci * hci,struct i2c_dev_desc * dev,struct hci_xfer * xfer)253 static void hci_cmd_v1_prep_i2c_xfer(struct i3c_hci *hci,
254 struct i2c_dev_desc *dev,
255 struct hci_xfer *xfer)
256 {
257 struct i3c_hci_dev_data *dev_data = i2c_dev_get_master_data(dev);
258 unsigned int dat_idx = dev_data->dat_idx;
259 enum hci_cmd_mode mode = get_i2c_mode(hci);
260 u8 *data = xfer->data;
261 unsigned int data_len = xfer->data_len;
262 bool rnw = xfer->rnw;
263
264 xfer->cmd_tid = hci_get_tid();
265
266 if (!rnw && data_len <= 4) {
267 /* we use an Immediate Data Transfer Command */
268 xfer->cmd_desc[0] =
269 CMD_0_ATTR_I |
270 CMD_I0_TID(xfer->cmd_tid) |
271 CMD_I0_DEV_INDEX(dat_idx) |
272 CMD_I0_DTT(data_len) |
273 CMD_I0_MODE(mode);
274 fill_data_bytes(xfer, data, data_len);
275 } else {
276 /* we use a Regular Data Transfer Command */
277 xfer->cmd_desc[0] =
278 CMD_0_ATTR_R |
279 CMD_R0_TID(xfer->cmd_tid) |
280 CMD_R0_DEV_INDEX(dat_idx) |
281 CMD_R0_MODE(mode) |
282 (rnw ? CMD_R0_RNW : 0);
283 xfer->cmd_desc[1] =
284 CMD_R1_DATA_LENGTH(data_len);
285 }
286 }
287
hci_cmd_v1_daa(struct i3c_hci * hci)288 static int hci_cmd_v1_daa(struct i3c_hci *hci)
289 {
290 struct hci_xfer *xfer;
291 int ret, dat_idx = -1;
292 u8 next_addr = 0;
293 u64 pid;
294 unsigned int dcr, bcr;
295 DECLARE_COMPLETION_ONSTACK(done);
296
297 xfer = hci_alloc_xfer(1);
298 if (!xfer)
299 return -ENOMEM;
300
301 /*
302 * Simple for now: we allocate a temporary DAT entry, do a single
303 * DAA, register the device which will allocate its own DAT entry
304 * via the core callback, then free the temporary DAT entry.
305 * Loop until there is no more devices to assign an address to.
306 * Yes, there is room for improvements.
307 */
308 for (;;) {
309 ret = mipi_i3c_hci_dat_v1.alloc_entry(hci);
310 if (ret < 0)
311 break;
312 dat_idx = ret;
313 ret = i3c_master_get_free_addr(&hci->master, next_addr);
314 if (ret < 0)
315 break;
316 next_addr = ret;
317
318 dev_dbg(&hci->master.dev,
319 "next_addr = 0x%02x, DAA using DAT %d",
320 next_addr, dat_idx);
321 mipi_i3c_hci_dat_v1.set_dynamic_addr(hci, dat_idx, next_addr);
322 mipi_i3c_hci_dct_index_reset(hci);
323
324 xfer->cmd_tid = hci_get_tid();
325 xfer->cmd_desc[0] =
326 CMD_0_ATTR_A |
327 CMD_A0_TID(xfer->cmd_tid) |
328 CMD_A0_CMD(I3C_CCC_ENTDAA) |
329 CMD_A0_DEV_INDEX(dat_idx) |
330 CMD_A0_DEV_COUNT(1) |
331 CMD_A0_ROC | CMD_A0_TOC;
332 xfer->cmd_desc[1] = 0;
333 xfer->completion = &done;
334 xfer->timeout = HZ;
335 ret = i3c_hci_process_xfer(hci, xfer, 1);
336 if (ret)
337 break;
338 if ((RESP_STATUS(xfer->response) == RESP_ERR_ADDR_HEADER ||
339 RESP_STATUS(xfer->response) == RESP_ERR_NACK) &&
340 RESP_DATA_LENGTH(xfer->response) == 1) {
341 ret = 0; /* no more devices to be assigned */
342 break;
343 }
344 if (RESP_STATUS(xfer->response) != RESP_SUCCESS) {
345 ret = -EIO;
346 break;
347 }
348
349 i3c_hci_dct_get_val(hci, 0, &pid, &dcr, &bcr);
350 dev_dbg(&hci->master.dev,
351 "assigned address %#x to device PID=0x%llx DCR=%#x BCR=%#x",
352 next_addr, pid, dcr, bcr);
353
354 mipi_i3c_hci_dat_v1.free_entry(hci, dat_idx);
355 dat_idx = -1;
356
357 /*
358 * TODO: Extend the subsystem layer to allow for registering
359 * new device and provide BCR/DCR/PID at the same time.
360 */
361 ret = i3c_master_add_i3c_dev_locked(&hci->master, next_addr);
362 if (ret)
363 break;
364 }
365
366 if (dat_idx >= 0)
367 mipi_i3c_hci_dat_v1.free_entry(hci, dat_idx);
368 hci_free_xfer(xfer, 1);
369 return ret;
370 }
371
372 const struct hci_cmd_ops mipi_i3c_hci_cmd_v1 = {
373 .prep_ccc = hci_cmd_v1_prep_ccc,
374 .prep_i3c_xfer = hci_cmd_v1_prep_i3c_xfer,
375 .prep_i2c_xfer = hci_cmd_v1_prep_i2c_xfer,
376 .perform_daa = hci_cmd_v1_daa,
377 };
378