1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /* Copyright (C) 2020 MediaTek Inc. */
3
4 #ifndef __MT76_CONNAC_MCU_H
5 #define __MT76_CONNAC_MCU_H
6
7 #include "mt76_connac.h"
8
9 #define FW_FEATURE_SET_ENCRYPT BIT(0)
10 #define FW_FEATURE_SET_KEY_IDX GENMASK(2, 1)
11 #define FW_FEATURE_ENCRY_MODE BIT(4)
12 #define FW_FEATURE_OVERRIDE_ADDR BIT(5)
13 #define FW_FEATURE_NON_DL BIT(6)
14
15 #define DL_MODE_ENCRYPT BIT(0)
16 #define DL_MODE_KEY_IDX GENMASK(2, 1)
17 #define DL_MODE_RESET_SEC_IV BIT(3)
18 #define DL_MODE_WORKING_PDA_CR4 BIT(4)
19 #define DL_MODE_VALID_RAM_ENTRY BIT(5)
20 #define DL_CONFIG_ENCRY_MODE_SEL BIT(6)
21 #define DL_MODE_NEED_RSP BIT(31)
22
23 #define FW_START_OVERRIDE BIT(0)
24 #define FW_START_WORKING_PDA_CR4 BIT(2)
25 #define FW_START_WORKING_PDA_DSP BIT(3)
26
27 #define PATCH_SEC_NOT_SUPPORT GENMASK(31, 0)
28 #define PATCH_SEC_TYPE_MASK GENMASK(15, 0)
29 #define PATCH_SEC_TYPE_INFO 0x2
30
31 #define PATCH_SEC_ENC_TYPE_MASK GENMASK(31, 24)
32 #define PATCH_SEC_ENC_TYPE_PLAIN 0x00
33 #define PATCH_SEC_ENC_TYPE_AES 0x01
34 #define PATCH_SEC_ENC_TYPE_SCRAMBLE 0x02
35 #define PATCH_SEC_ENC_SCRAMBLE_INFO_MASK GENMASK(15, 0)
36 #define PATCH_SEC_ENC_AES_KEY_MASK GENMASK(7, 0)
37
38 #define SEC_TYPE_SUBSYS_MASK GENMASK(23, 16)
39 #define SEC_TYPE_SUBSYS_CBMCU BIT(16)
40
41 #define SEC_TYPE_SUBSYS_SEC_MASK GENMASK(15, 0)
42 #define SEC_TYPE_SUBSYS_SEC_IMG_SIGN 0x05
43
44 enum {
45 FW_TYPE_DEFAULT = 0,
46 FW_TYPE_CLC = 2,
47 FW_TYPE_MAX_NUM = 255
48 };
49
50 #define MCU_PQ_ID(p, q) (((p) << 15) | ((q) << 10))
51 #define MCU_PKT_ID 0xa0
52
53 struct mt76_connac2_mcu_txd {
54 __le32 txd[8];
55
56 __le16 len;
57 __le16 pq_id;
58
59 u8 cid;
60 u8 pkt_type;
61 u8 set_query; /* FW don't care */
62 u8 seq;
63
64 u8 uc_d2b0_rev;
65 u8 ext_cid;
66 u8 s2d_index;
67 u8 ext_cid_ack;
68
69 u32 rsv[5];
70 } __packed __aligned(4);
71
72 /**
73 * struct mt76_connac2_mcu_uni_txd - mcu command descriptor for connac2 and connac3
74 * @txd: hardware descriptor
75 * @len: total length not including txd
76 * @cid: command identifier
77 * @pkt_type: must be 0xa0 (cmd packet by long format)
78 * @frag_n: fragment number
79 * @seq: sequence number
80 * @checksum: 0 mean there is no checksum
81 * @s2d_index: index for command source and destination
82 * Definition | value | note
83 * CMD_S2D_IDX_H2N | 0x00 | command from HOST to WM
84 * CMD_S2D_IDX_C2N | 0x01 | command from WA to WM
85 * CMD_S2D_IDX_H2C | 0x02 | command from HOST to WA
86 * CMD_S2D_IDX_H2N_AND_H2C | 0x03 | command from HOST to WA and WM
87 *
88 * @option: command option
89 * BIT[0]: UNI_CMD_OPT_BIT_ACK
90 * set to 1 to request a fw reply
91 * if UNI_CMD_OPT_BIT_0_ACK is set and UNI_CMD_OPT_BIT_2_SET_QUERY
92 * is set, mcu firmware will send response event EID = 0x01
93 * (UNI_EVENT_ID_CMD_RESULT) to the host.
94 * BIT[1]: UNI_CMD_OPT_BIT_UNI_CMD
95 * 0: original command
96 * 1: unified command
97 * BIT[2]: UNI_CMD_OPT_BIT_SET_QUERY
98 * 0: QUERY command
99 * 1: SET command
100 */
101 struct mt76_connac2_mcu_uni_txd {
102 __le32 txd[8];
103
104 /* DW1 */
105 __le16 len;
106 __le16 cid;
107
108 /* DW2 */
109 u8 rsv;
110 u8 pkt_type;
111 u8 frag_n;
112 u8 seq;
113
114 /* DW3 */
115 __le16 checksum;
116 u8 s2d_index;
117 u8 option;
118
119 /* DW4 */
120 u8 rsv1[4];
121 } __packed __aligned(4);
122
123 struct mt76_connac2_mcu_rxd {
124 /* New members MUST be added within the struct_group() macro below. */
125 struct_group_tagged(mt76_connac2_mcu_rxd_hdr, hdr,
126 __le32 rxd[6];
127
128 __le16 len;
129 __le16 pkt_type_id;
130
131 u8 eid;
132 u8 seq;
133 u8 option;
134 u8 rsv;
135 u8 ext_eid;
136 u8 rsv1[2];
137 u8 s2d_index;
138 );
139
140 u8 tlv[];
141 };
142 static_assert(offsetof(struct mt76_connac2_mcu_rxd, tlv) == sizeof(struct mt76_connac2_mcu_rxd_hdr),
143 "struct member likely outside of struct_group_tagged()");
144
145 struct mt76_connac2_patch_hdr {
146 char build_date[16];
147 char platform[4];
148 __be32 hw_sw_ver;
149 __be32 patch_ver;
150 __be16 checksum;
151 u16 rsv;
152 struct {
153 __be32 patch_ver;
154 __be32 subsys;
155 __be32 feature;
156 __be32 n_region;
157 __be32 crc;
158 u32 rsv[11];
159 } desc;
160 } __packed;
161
162 struct mt76_connac2_patch_sec {
163 __be32 type;
164 __be32 offs;
165 __be32 size;
166 union {
167 __be32 spec[13];
168 struct {
169 __be32 addr;
170 __be32 len;
171 __be32 sec_key_idx;
172 __be32 align_len;
173 u32 rsv[9];
174 } info;
175 };
176 } __packed;
177
178 struct mt76_connac2_fw_trailer {
179 u8 chip_id;
180 u8 eco_code;
181 u8 n_region;
182 u8 format_ver;
183 u8 format_flag;
184 u8 rsv[2];
185 char fw_ver[10];
186 char build_date[15];
187 __le32 crc;
188 } __packed;
189
190 struct mt76_connac2_fw_region {
191 __le32 decomp_crc;
192 __le32 decomp_len;
193 __le32 decomp_blk_sz;
194 u8 rsv[4];
195 __le32 addr;
196 __le32 len;
197 u8 feature_set;
198 u8 type;
199 u8 rsv1[14];
200 } __packed;
201
202 struct mt76_connac3_multi_header_v2_sec_raw_format {
203 __le32 type;
204 __le32 offset;
205 __le32 size;
206 u8 spec[52];
207 } __packed;
208
209 struct mt76_connac3_multi_header_v2_raw_format {
210 u8 pack_time[20];
211 u8 chip_id_eco_ver[8];
212 __le32 patch_ver;
213 u8 global_desc_head[4];
214 __le32 global_subsys;
215 u8 rsv2[4];
216 __le32 sec_num;
217 u8 rsv3[48];
218 struct mt76_connac3_multi_header_v2_sec_raw_format sects[];
219 } __packed;
220
221 struct tlv {
222 __le16 tag;
223 __le16 len;
224 u8 data[];
225 } __packed;
226
227 struct bss_info_omac {
228 __le16 tag;
229 __le16 len;
230 u8 hw_bss_idx;
231 u8 omac_idx;
232 u8 band_idx;
233 u8 rsv0;
234 __le32 conn_type;
235 u32 rsv1;
236 } __packed;
237
238 struct bss_info_basic {
239 __le16 tag;
240 __le16 len;
241 __le32 network_type;
242 u8 active;
243 u8 rsv0;
244 __le16 bcn_interval;
245 u8 bssid[ETH_ALEN];
246 u8 wmm_idx;
247 u8 dtim_period;
248 u8 bmc_wcid_lo;
249 u8 cipher;
250 u8 phy_mode;
251 u8 max_bssid; /* max BSSID. range: 1 ~ 8, 0: MBSSID disabled */
252 u8 non_tx_bssid;/* non-transmitted BSSID, 0: transmitted BSSID */
253 u8 bmc_wcid_hi; /* high Byte and version */
254 u8 rsv[2];
255 } __packed;
256
257 struct bss_info_rf_ch {
258 __le16 tag;
259 __le16 len;
260 u8 pri_ch;
261 u8 center_ch0;
262 u8 center_ch1;
263 u8 bw;
264 u8 he_ru26_block; /* 1: don't send HETB in RU26, 0: allow */
265 u8 he_all_disable; /* 1: disallow all HETB, 0: allow */
266 u8 rsv[2];
267 } __packed;
268
269 struct bss_info_ext_bss {
270 __le16 tag;
271 __le16 len;
272 __le32 mbss_tsf_offset; /* in unit of us */
273 u8 rsv[8];
274 } __packed;
275
276 enum {
277 BSS_INFO_OMAC,
278 BSS_INFO_BASIC,
279 BSS_INFO_RF_CH, /* optional, for BT/LTE coex */
280 BSS_INFO_PM, /* sta only */
281 BSS_INFO_UAPSD, /* sta only */
282 BSS_INFO_ROAM_DETECT, /* obsoleted */
283 BSS_INFO_LQ_RM, /* obsoleted */
284 BSS_INFO_EXT_BSS,
285 BSS_INFO_BMC_RATE, /* for bmc rate control in CR4 */
286 BSS_INFO_SYNC_MODE, /* obsoleted */
287 BSS_INFO_RA,
288 BSS_INFO_HW_AMSDU,
289 BSS_INFO_BSS_COLOR,
290 BSS_INFO_HE_BASIC,
291 BSS_INFO_PROTECT_INFO,
292 BSS_INFO_OFFLOAD,
293 BSS_INFO_11V_MBSSID,
294 BSS_INFO_MAX_NUM
295 };
296
297 /* sta_rec */
298
299 struct sta_ntlv_hdr {
300 u8 rsv[2];
301 __le16 tlv_num;
302 } __packed;
303
304 struct sta_req_hdr {
305 u8 bss_idx;
306 u8 wlan_idx_lo;
307 __le16 tlv_num;
308 u8 is_tlv_append;
309 u8 muar_idx;
310 u8 wlan_idx_hi;
311 u8 rsv;
312 } __packed;
313
314 struct sta_rec_basic {
315 __le16 tag;
316 __le16 len;
317 __le32 conn_type;
318 u8 conn_state;
319 u8 qos;
320 __le16 aid;
321 u8 peer_addr[ETH_ALEN];
322 #define EXTRA_INFO_VER BIT(0)
323 #define EXTRA_INFO_NEW BIT(1)
324 __le16 extra_info;
325 } __packed;
326
327 struct sta_rec_ht {
328 __le16 tag;
329 __le16 len;
330 __le16 ht_cap;
331 u16 rsv;
332 } __packed;
333
334 struct sta_rec_vht {
335 __le16 tag;
336 __le16 len;
337 __le32 vht_cap;
338 __le16 vht_rx_mcs_map;
339 __le16 vht_tx_mcs_map;
340 /* mt7915 - mt7921 */
341 u8 rts_bw_sig;
342 u8 rsv[3];
343 } __packed;
344
345 struct sta_rec_uapsd {
346 __le16 tag;
347 __le16 len;
348 u8 dac_map;
349 u8 tac_map;
350 u8 max_sp;
351 u8 rsv0;
352 __le16 listen_interval;
353 u8 rsv1[2];
354 } __packed;
355
356 struct sta_rec_ba {
357 __le16 tag;
358 __le16 len;
359 u8 tid;
360 u8 ba_type;
361 u8 amsdu;
362 u8 ba_en;
363 __le16 ssn;
364 __le16 winsize;
365 } __packed;
366
367 struct sta_rec_he {
368 __le16 tag;
369 __le16 len;
370
371 __le32 he_cap;
372
373 u8 t_frame_dur;
374 u8 max_ampdu_exp;
375 u8 bw_set;
376 u8 device_class;
377 u8 dcm_tx_mode;
378 u8 dcm_tx_max_nss;
379 u8 dcm_rx_mode;
380 u8 dcm_rx_max_nss;
381 u8 dcm_max_ru;
382 u8 punc_pream_rx;
383 u8 pkt_ext;
384 u8 rsv1;
385
386 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
387
388 u8 rsv2[2];
389 } __packed;
390
391 struct sta_rec_he_v2 {
392 __le16 tag;
393 __le16 len;
394 u8 he_mac_cap[6];
395 u8 he_phy_cap[11];
396 u8 pkt_ext;
397 /* 0: BW80, 1: BW160, 2: BW8080 */
398 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
399 } __packed;
400
401 struct sta_rec_amsdu {
402 __le16 tag;
403 __le16 len;
404 u8 max_amsdu_num;
405 u8 max_mpdu_size;
406 u8 amsdu_en;
407 u8 rsv;
408 } __packed;
409
410 struct sta_rec_state {
411 __le16 tag;
412 __le16 len;
413 __le32 flags;
414 u8 state;
415 u8 vht_opmode;
416 u8 action;
417 u8 rsv[1];
418 } __packed;
419
420 #define RA_LEGACY_OFDM GENMASK(13, 6)
421 #define RA_LEGACY_CCK GENMASK(3, 0)
422 #define HT_MCS_MASK_NUM 10
423 struct sta_rec_ra_info {
424 __le16 tag;
425 __le16 len;
426 __le16 legacy;
427 u8 rx_mcs_bitmask[HT_MCS_MASK_NUM];
428 } __packed;
429
430 struct sta_rec_phy {
431 __le16 tag;
432 __le16 len;
433 __le16 basic_rate;
434 u8 phy_type;
435 u8 ampdu;
436 u8 rts_policy;
437 u8 rcpi;
438 u8 max_ampdu_len; /* connac3 */
439 u8 rsv[1];
440 } __packed;
441
442 struct sta_rec_he_6g_capa {
443 __le16 tag;
444 __le16 len;
445 __le16 capa;
446 u8 rsv[2];
447 } __packed;
448
449 struct sta_rec_pn_info {
450 __le16 tag;
451 __le16 len;
452 u8 pn[6];
453 u8 tsc_type;
454 u8 rsv;
455 } __packed;
456
457 struct sec_key {
458 u8 cipher_id;
459 u8 cipher_len;
460 u8 key_id;
461 u8 key_len;
462 u8 key[32];
463 } __packed;
464
465 struct sta_rec_sec {
466 __le16 tag;
467 __le16 len;
468 u8 add;
469 u8 n_cipher;
470 u8 rsv[2];
471
472 struct sec_key key[2];
473 } __packed;
474
475 struct sta_rec_bf {
476 __le16 tag;
477 __le16 len;
478
479 __le16 pfmu; /* 0xffff: no access right for PFMU */
480 bool su_mu; /* 0: SU, 1: MU */
481 u8 bf_cap; /* 0: iBF, 1: eBF */
482 u8 sounding_phy; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT */
483 u8 ndpa_rate;
484 u8 ndp_rate;
485 u8 rept_poll_rate;
486 u8 tx_mode; /* 0: legacy, 1: OFDM, 2: HT, 4: VHT ... */
487 u8 ncol;
488 u8 nrow;
489 u8 bw; /* 0: 20M, 1: 40M, 2: 80M, 3: 160M */
490
491 u8 mem_total;
492 u8 mem_20m;
493 struct {
494 u8 row;
495 u8 col: 6, row_msb: 2;
496 } mem[4];
497
498 __le16 smart_ant;
499 u8 se_idx;
500 u8 auto_sounding; /* b7: low traffic indicator
501 * b6: Stop sounding for this entry
502 * b5 ~ b0: postpone sounding
503 */
504 u8 ibf_timeout;
505 u8 ibf_dbw;
506 u8 ibf_ncol;
507 u8 ibf_nrow;
508 u8 nrow_gt_bw80;
509 u8 ncol_gt_bw80;
510 u8 ru_start_idx;
511 u8 ru_end_idx;
512
513 bool trigger_su;
514 bool trigger_mu;
515 bool ng16_su;
516 bool ng16_mu;
517 bool codebook42_su;
518 bool codebook75_mu;
519
520 u8 he_ltf;
521 u8 rsv[3];
522 } __packed;
523
524 struct sta_rec_bfee {
525 __le16 tag;
526 __le16 len;
527 bool fb_identity_matrix; /* 1: feedback identity matrix */
528 bool ignore_feedback; /* 1: ignore */
529 u8 rsv[2];
530 } __packed;
531
532 struct sta_rec_muru {
533 __le16 tag;
534 __le16 len;
535
536 struct {
537 bool ofdma_dl_en;
538 bool ofdma_ul_en;
539 bool mimo_dl_en;
540 bool mimo_ul_en;
541 u8 rsv[4];
542 } cfg;
543
544 struct {
545 u8 punc_pream_rx;
546 bool he_20m_in_40m_2g;
547 bool he_20m_in_160m;
548 bool he_80m_in_160m;
549 bool lt16_sigb;
550 bool rx_su_comp_sigb;
551 bool rx_su_non_comp_sigb;
552 u8 rsv;
553 } ofdma_dl;
554
555 struct {
556 u8 t_frame_dur;
557 u8 mu_cascading;
558 u8 uo_ra;
559 u8 he_2x996_tone;
560 u8 rx_t_frame_11ac;
561 u8 rx_ctrl_frame_to_mbss;
562 u8 rsv[2];
563 } ofdma_ul;
564
565 struct {
566 bool vht_mu_bfee;
567 bool partial_bw_dl_mimo;
568 u8 rsv[2];
569 } mimo_dl;
570
571 struct {
572 bool full_ul_mimo;
573 bool partial_ul_mimo;
574 u8 rsv[2];
575 } mimo_ul;
576 } __packed;
577
578 struct sta_rec_remove {
579 __le16 tag;
580 __le16 len;
581 u8 action;
582 u8 pad[3];
583 } __packed;
584
585 struct sta_phy {
586 u8 type;
587 u8 flag;
588 u8 stbc;
589 u8 sgi;
590 u8 bw;
591 u8 ldpc;
592 u8 mcs;
593 u8 nss;
594 u8 he_ltf;
595 };
596
597 struct sta_rec_ra {
598 __le16 tag;
599 __le16 len;
600
601 u8 valid;
602 u8 auto_rate;
603 u8 phy_mode;
604 u8 channel;
605 u8 bw;
606 u8 disable_cck;
607 u8 ht_mcs32;
608 u8 ht_gf;
609 u8 ht_mcs[4];
610 u8 mmps_mode;
611 u8 gband_256;
612 u8 af;
613 u8 auth_wapi_mode;
614 u8 rate_len;
615
616 u8 supp_mode;
617 u8 supp_cck_rate;
618 u8 supp_ofdm_rate;
619 __le32 supp_ht_mcs;
620 __le16 supp_vht_mcs[4];
621
622 u8 op_mode;
623 u8 op_vht_chan_width;
624 u8 op_vht_rx_nss;
625 u8 op_vht_rx_nss_type;
626
627 __le32 sta_cap;
628
629 struct sta_phy phy;
630 } __packed;
631
632 struct sta_rec_ra_fixed {
633 __le16 tag;
634 __le16 len;
635
636 __le32 field;
637 u8 op_mode;
638 u8 op_vht_chan_width;
639 u8 op_vht_rx_nss;
640 u8 op_vht_rx_nss_type;
641
642 struct sta_phy phy;
643
644 u8 spe_idx;
645 u8 short_preamble;
646 u8 is_5g;
647 u8 mmps_mode;
648 } __packed;
649
650 struct sta_rec_tx_proc {
651 __le16 tag;
652 __le16 len;
653 __le32 flag;
654 } __packed;
655
656 struct sta_rec_eml_op {
657 __le16 tag;
658 __le16 len;
659 u8 link_bitmap;
660 u8 link_ant_num[3];
661 } __packed;
662
663 /* wtbl_rec */
664
665 struct wtbl_req_hdr {
666 u8 wlan_idx_lo;
667 u8 operation;
668 __le16 tlv_num;
669 u8 wlan_idx_hi;
670 u8 rsv[3];
671 } __packed;
672
673 struct wtbl_generic {
674 __le16 tag;
675 __le16 len;
676 u8 peer_addr[ETH_ALEN];
677 u8 muar_idx;
678 u8 skip_tx;
679 u8 cf_ack;
680 u8 qos;
681 u8 mesh;
682 u8 adm;
683 __le16 partial_aid;
684 u8 baf_en;
685 u8 aad_om;
686 } __packed;
687
688 struct wtbl_rx {
689 __le16 tag;
690 __le16 len;
691 u8 rcid;
692 u8 rca1;
693 u8 rca2;
694 u8 rv;
695 u8 rsv[4];
696 } __packed;
697
698 struct wtbl_ht {
699 __le16 tag;
700 __le16 len;
701 u8 ht;
702 u8 ldpc;
703 u8 af;
704 u8 mm;
705 u8 rsv[4];
706 } __packed;
707
708 struct wtbl_vht {
709 __le16 tag;
710 __le16 len;
711 u8 ldpc;
712 u8 dyn_bw;
713 u8 vht;
714 u8 txop_ps;
715 u8 rsv[4];
716 } __packed;
717
718 struct wtbl_tx_ps {
719 __le16 tag;
720 __le16 len;
721 u8 txps;
722 u8 rsv[3];
723 } __packed;
724
725 struct wtbl_hdr_trans {
726 __le16 tag;
727 __le16 len;
728 u8 to_ds;
729 u8 from_ds;
730 u8 no_rx_trans;
731 u8 rsv;
732 } __packed;
733
734 struct wtbl_ba {
735 __le16 tag;
736 __le16 len;
737 /* common */
738 u8 tid;
739 u8 ba_type;
740 u8 rsv0[2];
741 /* originator only */
742 __le16 sn;
743 u8 ba_en;
744 u8 ba_winsize_idx;
745 /* originator & recipient */
746 __le16 ba_winsize;
747 /* recipient only */
748 u8 peer_addr[ETH_ALEN];
749 u8 rst_ba_tid;
750 u8 rst_ba_sel;
751 u8 rst_ba_sb;
752 u8 band_idx;
753 u8 rsv1[4];
754 } __packed;
755
756 struct wtbl_smps {
757 __le16 tag;
758 __le16 len;
759 u8 smps;
760 u8 rsv[3];
761 } __packed;
762
763 /* mt7615 only */
764
765 struct wtbl_bf {
766 __le16 tag;
767 __le16 len;
768 u8 ibf;
769 u8 ebf;
770 u8 ibf_vht;
771 u8 ebf_vht;
772 u8 gid;
773 u8 pfmu_idx;
774 u8 rsv[2];
775 } __packed;
776
777 struct wtbl_pn {
778 __le16 tag;
779 __le16 len;
780 u8 pn[6];
781 u8 rsv[2];
782 } __packed;
783
784 struct wtbl_spe {
785 __le16 tag;
786 __le16 len;
787 u8 spe_idx;
788 u8 rsv[3];
789 } __packed;
790
791 struct wtbl_raw {
792 __le16 tag;
793 __le16 len;
794 u8 wtbl_idx;
795 u8 dw;
796 u8 rsv[2];
797 __le32 msk;
798 __le32 val;
799 } __packed;
800
801 #define MT76_CONNAC_WTBL_UPDATE_MAX_SIZE (sizeof(struct wtbl_req_hdr) + \
802 sizeof(struct wtbl_generic) + \
803 sizeof(struct wtbl_rx) + \
804 sizeof(struct wtbl_ht) + \
805 sizeof(struct wtbl_vht) + \
806 sizeof(struct wtbl_tx_ps) + \
807 sizeof(struct wtbl_hdr_trans) +\
808 sizeof(struct wtbl_ba) + \
809 sizeof(struct wtbl_bf) + \
810 sizeof(struct wtbl_smps) + \
811 sizeof(struct wtbl_pn) + \
812 sizeof(struct wtbl_spe))
813
814 #define MT76_CONNAC_STA_UPDATE_MAX_SIZE (sizeof(struct sta_req_hdr) + \
815 sizeof(struct sta_rec_basic) + \
816 sizeof(struct sta_rec_bf) + \
817 sizeof(struct sta_rec_ht) + \
818 sizeof(struct sta_rec_he) + \
819 sizeof(struct sta_rec_ba) + \
820 sizeof(struct sta_rec_vht) + \
821 sizeof(struct sta_rec_uapsd) + \
822 sizeof(struct sta_rec_amsdu) + \
823 sizeof(struct sta_rec_muru) + \
824 sizeof(struct sta_rec_bfee) + \
825 sizeof(struct sta_rec_ra) + \
826 sizeof(struct sta_rec_sec) + \
827 sizeof(struct sta_rec_ra_fixed) + \
828 sizeof(struct sta_rec_he_6g_capa) + \
829 sizeof(struct sta_rec_pn_info) + \
830 sizeof(struct sta_rec_tx_proc) + \
831 sizeof(struct sta_rec_eml_op) + \
832 sizeof(struct tlv) + \
833 MT76_CONNAC_WTBL_UPDATE_MAX_SIZE)
834
835 enum {
836 STA_REC_BASIC,
837 STA_REC_RA,
838 STA_REC_RA_CMM_INFO,
839 STA_REC_RA_UPDATE,
840 STA_REC_BF,
841 STA_REC_AMSDU,
842 STA_REC_BA,
843 STA_REC_STATE,
844 STA_REC_TX_PROC, /* for hdr trans and CSO in CR4 */
845 STA_REC_HT,
846 STA_REC_VHT,
847 STA_REC_APPS,
848 STA_REC_KEY,
849 STA_REC_WTBL,
850 STA_REC_HE,
851 STA_REC_HW_AMSDU,
852 STA_REC_WTBL_AADOM,
853 STA_REC_KEY_V2,
854 STA_REC_MURU,
855 STA_REC_MUEDCA,
856 STA_REC_BFEE,
857 STA_REC_PHY = 0x15,
858 STA_REC_HE_6G = 0x17,
859 STA_REC_HE_V2 = 0x19,
860 STA_REC_MLD = 0x20,
861 STA_REC_EHT_MLD = 0x21,
862 STA_REC_EHT = 0x22,
863 STA_REC_MLD_OFF = 0x23,
864 STA_REC_REMOVE = 0x25,
865 STA_REC_PN_INFO = 0x26,
866 STA_REC_KEY_V3 = 0x27,
867 STA_REC_HDRT = 0x28,
868 STA_REC_EML_OP = 0x29,
869 STA_REC_HDR_TRANS = 0x2B,
870 STA_REC_PS_LEAVE = 0x45,
871 STA_REC_MAX_NUM
872 };
873
874 enum {
875 WTBL_GENERIC,
876 WTBL_RX,
877 WTBL_HT,
878 WTBL_VHT,
879 WTBL_PEER_PS, /* not used */
880 WTBL_TX_PS,
881 WTBL_HDR_TRANS,
882 WTBL_SEC_KEY,
883 WTBL_BA,
884 WTBL_RDG, /* obsoleted */
885 WTBL_PROTECT, /* not used */
886 WTBL_CLEAR, /* not used */
887 WTBL_BF,
888 WTBL_SMPS,
889 WTBL_RAW_DATA, /* debug only */
890 WTBL_PN,
891 WTBL_SPE,
892 WTBL_MAX_NUM
893 };
894
895 #define STA_TYPE_STA BIT(0)
896 #define STA_TYPE_AP BIT(1)
897 #define STA_TYPE_ADHOC BIT(2)
898 #define STA_TYPE_WDS BIT(4)
899 #define STA_TYPE_BC BIT(5)
900
901 #define NETWORK_INFRA BIT(16)
902 #define NETWORK_P2P BIT(17)
903 #define NETWORK_IBSS BIT(18)
904 #define NETWORK_WDS BIT(21)
905 #define NETWORK_NAN BIT(22)
906
907 #define SCAN_FUNC_RANDOM_MAC BIT(0)
908 #define SCAN_FUNC_RNR_SCAN BIT(3)
909 #define SCAN_FUNC_SPLIT_SCAN BIT(5)
910
911 #define CONNECTION_INFRA_STA (STA_TYPE_STA | NETWORK_INFRA)
912 #define CONNECTION_INFRA_AP (STA_TYPE_AP | NETWORK_INFRA)
913 #define CONNECTION_P2P_GC (STA_TYPE_STA | NETWORK_P2P)
914 #define CONNECTION_P2P_GO (STA_TYPE_AP | NETWORK_P2P)
915 #define CONNECTION_IBSS_ADHOC (STA_TYPE_ADHOC | NETWORK_IBSS)
916 #define CONNECTION_WDS (STA_TYPE_WDS | NETWORK_WDS)
917 #define CONNECTION_INFRA_BC (STA_TYPE_BC | NETWORK_INFRA)
918 #define CONNECTION_NAN (NETWORK_NAN)
919
920 #define CONN_STATE_DISCONNECT 0
921 #define CONN_STATE_CONNECT 1
922 #define CONN_STATE_PORT_SECURE 2
923
924 /* HE MAC */
925 #define STA_REC_HE_CAP_HTC BIT(0)
926 #define STA_REC_HE_CAP_BQR BIT(1)
927 #define STA_REC_HE_CAP_BSR BIT(2)
928 #define STA_REC_HE_CAP_OM BIT(3)
929 #define STA_REC_HE_CAP_AMSDU_IN_AMPDU BIT(4)
930 /* HE PHY */
931 #define STA_REC_HE_CAP_DUAL_BAND BIT(5)
932 #define STA_REC_HE_CAP_LDPC BIT(6)
933 #define STA_REC_HE_CAP_TRIG_CQI_FK BIT(7)
934 #define STA_REC_HE_CAP_PARTIAL_BW_EXT_RANGE BIT(8)
935 /* STBC */
936 #define STA_REC_HE_CAP_LE_EQ_80M_TX_STBC BIT(9)
937 #define STA_REC_HE_CAP_LE_EQ_80M_RX_STBC BIT(10)
938 #define STA_REC_HE_CAP_GT_80M_TX_STBC BIT(11)
939 #define STA_REC_HE_CAP_GT_80M_RX_STBC BIT(12)
940 /* GI */
941 #define STA_REC_HE_CAP_SU_PPDU_1LTF_8US_GI BIT(13)
942 #define STA_REC_HE_CAP_SU_MU_PPDU_4LTF_8US_GI BIT(14)
943 #define STA_REC_HE_CAP_ER_SU_PPDU_1LTF_8US_GI BIT(15)
944 #define STA_REC_HE_CAP_ER_SU_PPDU_4LTF_8US_GI BIT(16)
945 #define STA_REC_HE_CAP_NDP_4LTF_3DOT2MS_GI BIT(17)
946 /* 242 TONE */
947 #define STA_REC_HE_CAP_BW20_RU242_SUPPORT BIT(18)
948 #define STA_REC_HE_CAP_TX_1024QAM_UNDER_RU242 BIT(19)
949 #define STA_REC_HE_CAP_RX_1024QAM_UNDER_RU242 BIT(20)
950
951 #define PHY_MODE_A BIT(0)
952 #define PHY_MODE_B BIT(1)
953 #define PHY_MODE_G BIT(2)
954 #define PHY_MODE_GN BIT(3)
955 #define PHY_MODE_AN BIT(4)
956 #define PHY_MODE_AC BIT(5)
957 #define PHY_MODE_AX_24G BIT(6)
958 #define PHY_MODE_AX_5G BIT(7)
959
960 #define PHY_MODE_AX_6G BIT(0) /* phymode_ext */
961 #define PHY_MODE_BE_24G BIT(1)
962 #define PHY_MODE_BE_5G BIT(2)
963 #define PHY_MODE_BE_6G BIT(3)
964
965 #define MODE_CCK BIT(0)
966 #define MODE_OFDM BIT(1)
967 #define MODE_HT BIT(2)
968 #define MODE_VHT BIT(3)
969 #define MODE_HE BIT(4)
970 #define MODE_EHT BIT(5)
971
972 #define STA_CAP_WMM BIT(0)
973 #define STA_CAP_SGI_20 BIT(4)
974 #define STA_CAP_SGI_40 BIT(5)
975 #define STA_CAP_TX_STBC BIT(6)
976 #define STA_CAP_RX_STBC BIT(7)
977 #define STA_CAP_VHT_SGI_80 BIT(16)
978 #define STA_CAP_VHT_SGI_160 BIT(17)
979 #define STA_CAP_VHT_TX_STBC BIT(18)
980 #define STA_CAP_VHT_RX_STBC BIT(19)
981 #define STA_CAP_VHT_LDPC BIT(23)
982 #define STA_CAP_LDPC BIT(24)
983 #define STA_CAP_HT BIT(26)
984 #define STA_CAP_VHT BIT(27)
985 #define STA_CAP_HE BIT(28)
986
987 enum {
988 PHY_TYPE_HR_DSSS_INDEX = 0,
989 PHY_TYPE_ERP_INDEX,
990 PHY_TYPE_ERP_P2P_INDEX,
991 PHY_TYPE_OFDM_INDEX,
992 PHY_TYPE_HT_INDEX,
993 PHY_TYPE_VHT_INDEX,
994 PHY_TYPE_HE_INDEX,
995 PHY_TYPE_BE_INDEX,
996 PHY_TYPE_INDEX_NUM
997 };
998
999 #define HR_DSSS_ERP_BASIC_RATE GENMASK(3, 0)
1000 #define OFDM_BASIC_RATE (BIT(6) | BIT(8) | BIT(10))
1001
1002 #define PHY_TYPE_BIT_HR_DSSS BIT(PHY_TYPE_HR_DSSS_INDEX)
1003 #define PHY_TYPE_BIT_ERP BIT(PHY_TYPE_ERP_INDEX)
1004 #define PHY_TYPE_BIT_OFDM BIT(PHY_TYPE_OFDM_INDEX)
1005 #define PHY_TYPE_BIT_HT BIT(PHY_TYPE_HT_INDEX)
1006 #define PHY_TYPE_BIT_VHT BIT(PHY_TYPE_VHT_INDEX)
1007 #define PHY_TYPE_BIT_HE BIT(PHY_TYPE_HE_INDEX)
1008 #define PHY_TYPE_BIT_BE BIT(PHY_TYPE_BE_INDEX)
1009
1010 #define MT_WTBL_RATE_TX_MODE GENMASK(9, 6)
1011 #define MT_WTBL_RATE_MCS GENMASK(5, 0)
1012 #define MT_WTBL_RATE_NSS GENMASK(12, 10)
1013 #define MT_WTBL_RATE_HE_GI GENMASK(7, 4)
1014 #define MT_WTBL_RATE_GI GENMASK(3, 0)
1015
1016 #define MT_WTBL_W5_CHANGE_BW_RATE GENMASK(7, 5)
1017 #define MT_WTBL_W5_SHORT_GI_20 BIT(8)
1018 #define MT_WTBL_W5_SHORT_GI_40 BIT(9)
1019 #define MT_WTBL_W5_SHORT_GI_80 BIT(10)
1020 #define MT_WTBL_W5_SHORT_GI_160 BIT(11)
1021 #define MT_WTBL_W5_BW_CAP GENMASK(13, 12)
1022 #define MT_WTBL_W5_MPDU_FAIL_COUNT GENMASK(25, 23)
1023 #define MT_WTBL_W5_MPDU_OK_COUNT GENMASK(28, 26)
1024 #define MT_WTBL_W5_RATE_IDX GENMASK(31, 29)
1025
1026 enum {
1027 WTBL_RESET_AND_SET = 1,
1028 WTBL_SET,
1029 WTBL_QUERY,
1030 WTBL_RESET_ALL
1031 };
1032
1033 enum {
1034 MT_BA_TYPE_INVALID,
1035 MT_BA_TYPE_ORIGINATOR,
1036 MT_BA_TYPE_RECIPIENT
1037 };
1038
1039 enum {
1040 RST_BA_MAC_TID_MATCH,
1041 RST_BA_MAC_MATCH,
1042 RST_BA_NO_MATCH
1043 };
1044
1045 enum {
1046 DEV_INFO_ACTIVE,
1047 DEV_INFO_MAX_NUM
1048 };
1049
1050 /* event table */
1051 enum {
1052 MCU_EVENT_TARGET_ADDRESS_LEN = 0x01,
1053 MCU_EVENT_FW_START = 0x01,
1054 MCU_EVENT_GENERIC = 0x01,
1055 MCU_EVENT_ACCESS_REG = 0x02,
1056 MCU_EVENT_MT_PATCH_SEM = 0x04,
1057 MCU_EVENT_REG_ACCESS = 0x05,
1058 MCU_EVENT_LP_INFO = 0x07,
1059 MCU_EVENT_SCAN_DONE = 0x0d,
1060 MCU_EVENT_TX_DONE = 0x0f,
1061 MCU_EVENT_ROC = 0x10,
1062 MCU_EVENT_BSS_ABSENCE = 0x11,
1063 MCU_EVENT_BSS_BEACON_LOSS = 0x13,
1064 MCU_EVENT_CH_PRIVILEGE = 0x18,
1065 MCU_EVENT_SCHED_SCAN_DONE = 0x23,
1066 MCU_EVENT_DBG_MSG = 0x27,
1067 MCU_EVENT_RSSI_NOTIFY = 0x96,
1068 MCU_EVENT_TXPWR = 0xd0,
1069 MCU_EVENT_EXT = 0xed,
1070 MCU_EVENT_RESTART_DL = 0xef,
1071 MCU_EVENT_COREDUMP = 0xf0,
1072 };
1073
1074 /* ext event table */
1075 enum {
1076 MCU_EXT_EVENT_PS_SYNC = 0x5,
1077 MCU_EXT_EVENT_FW_LOG_2_HOST = 0x13,
1078 MCU_EXT_EVENT_THERMAL_PROTECT = 0x22,
1079 MCU_EXT_EVENT_ASSERT_DUMP = 0x23,
1080 MCU_EXT_EVENT_RDD_REPORT = 0x3a,
1081 MCU_EXT_EVENT_CSA_NOTIFY = 0x4f,
1082 MCU_EXT_EVENT_WA_TX_STAT = 0x74,
1083 MCU_EXT_EVENT_BCC_NOTIFY = 0x75,
1084 MCU_EXT_EVENT_WF_RF_PIN_CTRL = 0x9a,
1085 MCU_EXT_EVENT_MURU_CTRL = 0x9f,
1086 };
1087
1088 /* unified event table */
1089 enum {
1090 MCU_UNI_EVENT_RESULT = 0x01,
1091 MCU_UNI_EVENT_HIF_CTRL = 0x03,
1092 MCU_UNI_EVENT_FW_LOG_2_HOST = 0x04,
1093 MCU_UNI_EVENT_ACCESS_REG = 0x6,
1094 MCU_UNI_EVENT_IE_COUNTDOWN = 0x09,
1095 MCU_UNI_EVENT_COREDUMP = 0x0a,
1096 MCU_UNI_EVENT_BSS_BEACON_LOSS = 0x0c,
1097 MCU_UNI_EVENT_PS_SYNC = 0x0d,
1098 MCU_UNI_EVENT_SCAN_DONE = 0x0e,
1099 MCU_UNI_EVENT_RDD_REPORT = 0x11,
1100 MCU_UNI_EVENT_ROC = 0x27,
1101 MCU_UNI_EVENT_MBMC = 0x28,
1102 MCU_UNI_EVENT_TX_DONE = 0x2d,
1103 MCU_UNI_EVENT_THERMAL = 0x35,
1104 MCU_UNI_EVENT_RSSI_MONITOR = 0x41,
1105 MCU_UNI_EVENT_NIC_CAPAB = 0x43,
1106 MCU_UNI_EVENT_NAN = 0x56,
1107 MCU_UNI_EVENT_WED_RRO = 0x57,
1108 MCU_UNI_EVENT_PER_STA_INFO = 0x6d,
1109 MCU_UNI_EVENT_ALL_STA_INFO = 0x6e,
1110 MCU_UNI_EVENT_SDO = 0x83,
1111 };
1112
1113 #define MCU_UNI_CMD_EVENT BIT(1)
1114 #define MCU_UNI_CMD_UNSOLICITED_EVENT BIT(2)
1115
1116 enum {
1117 MCU_Q_QUERY,
1118 MCU_Q_SET,
1119 MCU_Q_RESERVED,
1120 MCU_Q_NA
1121 };
1122
1123 enum {
1124 MCU_S2D_H2N,
1125 MCU_S2D_C2N,
1126 MCU_S2D_H2C,
1127 MCU_S2D_H2CN
1128 };
1129
1130 enum {
1131 PATCH_NOT_DL_SEM_FAIL,
1132 PATCH_IS_DL,
1133 PATCH_NOT_DL_SEM_SUCCESS,
1134 PATCH_REL_SEM_SUCCESS
1135 };
1136
1137 enum {
1138 CB_PATCH_GET_SEM_NEED_PATCH,
1139 CB_PATCH_IS_DL,
1140 CB_PATCH_NO_SEM_NEED_PATCH,
1141 CB_PATCH_REL_SEM_SUCCESS
1142 };
1143
1144 enum {
1145 FW_STATE_INITIAL,
1146 FW_STATE_FW_DOWNLOAD,
1147 FW_STATE_NORMAL_OPERATION,
1148 FW_STATE_NORMAL_TRX,
1149 FW_STATE_RDY = 7
1150 };
1151
1152 enum {
1153 CH_SWITCH_NORMAL = 0,
1154 CH_SWITCH_SCAN = 3,
1155 CH_SWITCH_MCC = 4,
1156 CH_SWITCH_DFS = 5,
1157 CH_SWITCH_BACKGROUND_SCAN_START = 6,
1158 CH_SWITCH_BACKGROUND_SCAN_RUNNING = 7,
1159 CH_SWITCH_BACKGROUND_SCAN_STOP = 8,
1160 CH_SWITCH_SCAN_BYPASS_DPD = 9
1161 };
1162
1163 enum {
1164 THERMAL_SENSOR_TEMP_QUERY,
1165 THERMAL_SENSOR_MANUAL_CTRL,
1166 THERMAL_SENSOR_INFO_QUERY,
1167 THERMAL_SENSOR_TASK_CTRL,
1168 };
1169
1170 enum mcu_cipher_type {
1171 MCU_CIPHER_NONE = 0,
1172 MCU_CIPHER_WEP40,
1173 MCU_CIPHER_WEP104,
1174 MCU_CIPHER_WEP128,
1175 MCU_CIPHER_TKIP,
1176 MCU_CIPHER_AES_CCMP,
1177 MCU_CIPHER_CCMP_256,
1178 MCU_CIPHER_GCMP,
1179 MCU_CIPHER_GCMP_256,
1180 MCU_CIPHER_WAPI,
1181 MCU_CIPHER_BIP_CMAC_128,
1182 MCU_CIPHER_BIP_CMAC_256,
1183 MCU_CIPHER_BCN_PROT_CMAC_128,
1184 MCU_CIPHER_BCN_PROT_CMAC_256,
1185 MCU_CIPHER_BCN_PROT_GMAC_128,
1186 MCU_CIPHER_BCN_PROT_GMAC_256,
1187 MCU_CIPHER_BIP_GMAC_128,
1188 MCU_CIPHER_BIP_GMAC_256,
1189 };
1190
1191 enum {
1192 EE_MODE_EFUSE,
1193 EE_MODE_BUFFER,
1194 };
1195
1196 enum {
1197 EE_FORMAT_BIN,
1198 EE_FORMAT_WHOLE,
1199 EE_FORMAT_MULTIPLE,
1200 };
1201
1202 enum {
1203 MCU_PHY_STATE_TX_RATE,
1204 MCU_PHY_STATE_RX_RATE,
1205 MCU_PHY_STATE_RSSI,
1206 MCU_PHY_STATE_CONTENTION_RX_RATE,
1207 MCU_PHY_STATE_OFDMLQ_CNINFO,
1208 };
1209
1210 #define MCU_CMD_ACK BIT(0)
1211 #define MCU_CMD_UNI BIT(1)
1212 #define MCU_CMD_SET BIT(2)
1213
1214 #define MCU_CMD_UNI_EXT_ACK (MCU_CMD_ACK | MCU_CMD_UNI | \
1215 MCU_CMD_SET)
1216 #define MCU_CMD_UNI_QUERY_ACK (MCU_CMD_ACK | MCU_CMD_UNI)
1217
1218 #define __MCU_CMD_FIELD_ID GENMASK(7, 0)
1219 #define __MCU_CMD_FIELD_EXT_ID GENMASK(15, 8)
1220 #define __MCU_CMD_FIELD_QUERY BIT(16)
1221 #define __MCU_CMD_FIELD_UNI BIT(17)
1222 #define __MCU_CMD_FIELD_CE BIT(18)
1223 #define __MCU_CMD_FIELD_WA BIT(19)
1224 #define __MCU_CMD_FIELD_WM BIT(20)
1225
1226 #define MCU_CMD(_t) FIELD_PREP(__MCU_CMD_FIELD_ID, \
1227 MCU_CMD_##_t)
1228 #define MCU_EXT_CMD(_t) (MCU_CMD(EXT_CID) | \
1229 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1230 MCU_EXT_CMD_##_t))
1231 #define MCU_EXT_QUERY(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1232 #define MCU_UNI_CMD(_t) (__MCU_CMD_FIELD_UNI | \
1233 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1234 MCU_UNI_CMD_##_t))
1235
1236 #define MCU_UNI_QUERY(_t) (__MCU_CMD_FIELD_UNI | __MCU_CMD_FIELD_QUERY | \
1237 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1238 MCU_UNI_CMD_##_t))
1239
1240 #define MCU_CE_CMD(_t) (__MCU_CMD_FIELD_CE | \
1241 FIELD_PREP(__MCU_CMD_FIELD_ID, \
1242 MCU_CE_CMD_##_t))
1243 #define MCU_CE_QUERY(_t) (MCU_CE_CMD(_t) | __MCU_CMD_FIELD_QUERY)
1244
1245 #define MCU_WA_CMD(_t) (MCU_CMD(_t) | __MCU_CMD_FIELD_WA)
1246 #define MCU_WA_EXT_CMD(_t) (MCU_EXT_CMD(_t) | __MCU_CMD_FIELD_WA)
1247 #define MCU_WA_PARAM_CMD(_t) (MCU_WA_CMD(WA_PARAM) | \
1248 FIELD_PREP(__MCU_CMD_FIELD_EXT_ID, \
1249 MCU_WA_PARAM_CMD_##_t))
1250
1251 #define MCU_WM_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1252 __MCU_CMD_FIELD_WM)
1253 #define MCU_WM_UNI_CMD_QUERY(_t) (MCU_UNI_CMD(_t) | \
1254 __MCU_CMD_FIELD_QUERY | \
1255 __MCU_CMD_FIELD_WM)
1256 #define MCU_WA_UNI_CMD(_t) (MCU_UNI_CMD(_t) | \
1257 __MCU_CMD_FIELD_WA)
1258 #define MCU_WMWA_UNI_CMD(_t) (MCU_WM_UNI_CMD(_t) | \
1259 __MCU_CMD_FIELD_WA)
1260
1261 enum {
1262 MCU_EXT_CMD_EFUSE_ACCESS = 0x01,
1263 MCU_EXT_CMD_RF_REG_ACCESS = 0x02,
1264 MCU_EXT_CMD_RF_TEST = 0x04,
1265 MCU_EXT_CMD_ID_RADIO_ON_OFF_CTRL = 0x05,
1266 MCU_EXT_CMD_PM_STATE_CTRL = 0x07,
1267 MCU_EXT_CMD_CHANNEL_SWITCH = 0x08,
1268 MCU_EXT_CMD_SET_TX_POWER_CTRL = 0x11,
1269 MCU_EXT_CMD_FW_LOG_2_HOST = 0x13,
1270 MCU_EXT_CMD_TXBF_ACTION = 0x1e,
1271 MCU_EXT_CMD_EFUSE_BUFFER_MODE = 0x21,
1272 MCU_EXT_CMD_THERMAL_PROT = 0x23,
1273 MCU_EXT_CMD_STA_REC_UPDATE = 0x25,
1274 MCU_EXT_CMD_BSS_INFO_UPDATE = 0x26,
1275 MCU_EXT_CMD_EDCA_UPDATE = 0x27,
1276 MCU_EXT_CMD_DEV_INFO_UPDATE = 0x2A,
1277 MCU_EXT_CMD_THERMAL_CTRL = 0x2c,
1278 MCU_EXT_CMD_WTBL_UPDATE = 0x32,
1279 MCU_EXT_CMD_SET_DRR_CTRL = 0x36,
1280 MCU_EXT_CMD_SET_RDD_CTRL = 0x3a,
1281 MCU_EXT_CMD_ATE_CTRL = 0x3d,
1282 MCU_EXT_CMD_PROTECT_CTRL = 0x3e,
1283 MCU_EXT_CMD_DBDC_CTRL = 0x45,
1284 MCU_EXT_CMD_MAC_INIT_CTRL = 0x46,
1285 MCU_EXT_CMD_RX_HDR_TRANS = 0x47,
1286 MCU_EXT_CMD_MUAR_UPDATE = 0x48,
1287 MCU_EXT_CMD_BCN_OFFLOAD = 0x49,
1288 MCU_EXT_CMD_RX_AIRTIME_CTRL = 0x4a,
1289 MCU_EXT_CMD_SET_RX_PATH = 0x4e,
1290 MCU_EXT_CMD_EFUSE_FREE_BLOCK = 0x4f,
1291 MCU_EXT_CMD_TX_POWER_FEATURE_CTRL = 0x58,
1292 MCU_EXT_CMD_RXDCOC_CAL = 0x59,
1293 MCU_EXT_CMD_GET_MIB_INFO = 0x5a,
1294 MCU_EXT_CMD_TXDPD_CAL = 0x60,
1295 MCU_EXT_CMD_CAL_CACHE = 0x67,
1296 MCU_EXT_CMD_RED_ENABLE = 0x68,
1297 MCU_EXT_CMD_CP_SUPPORT = 0x75,
1298 MCU_EXT_CMD_SET_RADAR_TH = 0x7c,
1299 MCU_EXT_CMD_SET_RDD_PATTERN = 0x7d,
1300 MCU_EXT_CMD_MWDS_SUPPORT = 0x80,
1301 MCU_EXT_CMD_SET_SER_TRIGGER = 0x81,
1302 MCU_EXT_CMD_TWT_AGRT_UPDATE = 0x94,
1303 MCU_EXT_CMD_FW_DBG_CTRL = 0x95,
1304 MCU_EXT_CMD_OFFCH_SCAN_CTRL = 0x9a,
1305 MCU_EXT_CMD_SET_RDD_TH = 0x9d,
1306 MCU_EXT_CMD_MURU_CTRL = 0x9f,
1307 MCU_EXT_CMD_SET_SPR = 0xa8,
1308 MCU_EXT_CMD_GROUP_PRE_CAL_INFO = 0xab,
1309 MCU_EXT_CMD_DPD_PRE_CAL_INFO = 0xac,
1310 MCU_EXT_CMD_PHY_STAT_INFO = 0xad,
1311 MCU_EXT_CMD_WF_RF_PIN_CTRL = 0xbd,
1312 };
1313
1314 enum {
1315 MCU_UNI_CMD_DEV_INFO_UPDATE = 0x01,
1316 MCU_UNI_CMD_BSS_INFO_UPDATE = 0x02,
1317 MCU_UNI_CMD_STA_REC_UPDATE = 0x03,
1318 MCU_UNI_CMD_EDCA_UPDATE = 0x04,
1319 MCU_UNI_CMD_SUSPEND = 0x05,
1320 MCU_UNI_CMD_OFFLOAD = 0x06,
1321 MCU_UNI_CMD_HIF_CTRL = 0x07,
1322 MCU_UNI_CMD_BAND_CONFIG = 0x08,
1323 MCU_UNI_CMD_REPT_MUAR = 0x09,
1324 MCU_UNI_CMD_WSYS_CONFIG = 0x0b,
1325 MCU_UNI_CMD_REG_ACCESS = 0x0d,
1326 MCU_UNI_CMD_CHIP_CONFIG = 0x0e,
1327 MCU_UNI_CMD_POWER_CTRL = 0x0f,
1328 MCU_UNI_CMD_RX_HDR_TRANS = 0x12,
1329 MCU_UNI_CMD_SER = 0x13,
1330 MCU_UNI_CMD_TWT = 0x14,
1331 MCU_UNI_CMD_SET_DOMAIN_INFO = 0x15,
1332 MCU_UNI_CMD_SCAN_REQ = 0x16,
1333 MCU_UNI_CMD_RDD_CTRL = 0x19,
1334 MCU_UNI_CMD_GET_MIB_INFO = 0x22,
1335 MCU_UNI_CMD_GET_STAT_INFO = 0x23,
1336 MCU_UNI_CMD_SNIFFER = 0x24,
1337 MCU_UNI_CMD_SR = 0x25,
1338 MCU_UNI_CMD_ROC = 0x27,
1339 MCU_UNI_CMD_SET_DBDC_PARMS = 0x28,
1340 MCU_UNI_CMD_TXPOWER = 0x2b,
1341 MCU_UNI_CMD_SET_POWER_LIMIT = 0x2c,
1342 MCU_UNI_CMD_EFUSE_CTRL = 0x2d,
1343 MCU_UNI_CMD_RA = 0x2f,
1344 MCU_UNI_CMD_MURU = 0x31,
1345 MCU_UNI_CMD_TESTMODE_RX_STAT = 0x32,
1346 MCU_UNI_CMD_BF = 0x33,
1347 MCU_UNI_CMD_CHANNEL_SWITCH = 0x34,
1348 MCU_UNI_CMD_THERMAL = 0x35,
1349 MCU_UNI_CMD_VOW = 0x37,
1350 MCU_UNI_CMD_FIXED_RATE_TABLE = 0x40,
1351 MCU_UNI_CMD_RSSI_MONITOR = 0x41,
1352 MCU_UNI_CMD_TESTMODE_CTRL = 0x46,
1353 MCU_UNI_CMD_NAN = 0x56,
1354 MCU_UNI_CMD_RRO = 0x57,
1355 MCU_UNI_CMD_OFFCH_SCAN_CTRL = 0x58,
1356 MCU_UNI_CMD_PER_STA_INFO = 0x6d,
1357 MCU_UNI_CMD_ALL_STA_INFO = 0x6e,
1358 MCU_UNI_CMD_ASSERT_DUMP = 0x6f,
1359 MCU_UNI_CMD_EXT_EEPROM_CTRL = 0x74,
1360 MCU_UNI_CMD_RADIO_STATUS = 0x80,
1361 MCU_UNI_CMD_MLD = 0x82,
1362 MCU_UNI_CMD_SDO = 0x88,
1363 };
1364
1365 enum {
1366 MCU_CMD_TARGET_ADDRESS_LEN_REQ = 0x01,
1367 MCU_CMD_FW_START_REQ = 0x02,
1368 MCU_CMD_INIT_ACCESS_REG = 0x3,
1369 MCU_CMD_NIC_POWER_CTRL = 0x4,
1370 MCU_CMD_PATCH_START_REQ = 0x05,
1371 MCU_CMD_PATCH_FINISH_REQ = 0x07,
1372 MCU_CMD_PATCH_SEM_CONTROL = 0x10,
1373 MCU_CMD_CB_PATCH_SEM_CONTROL = 0x30,
1374 MCU_CMD_CB_PATCH_START_REQ = 0x31,
1375 MCU_CMD_CB_PATCH_FINISH_REQ = 0x32,
1376 MCU_CMD_WA_PARAM = 0xc4,
1377 MCU_CMD_EXT_CID = 0xed,
1378 MCU_CMD_FW_SCATTER = 0xee,
1379 MCU_CMD_RESTART_DL_REQ = 0xef,
1380 };
1381
1382 /* offload mcu commands */
1383 enum {
1384 MCU_CE_CMD_TEST_CTRL = 0x01,
1385 MCU_CE_CMD_START_HW_SCAN = 0x03,
1386 MCU_CE_CMD_SET_PS_PROFILE = 0x05,
1387 MCU_CE_CMD_SET_RX_FILTER = 0x0a,
1388 MCU_CE_CMD_SET_CHAN_DOMAIN = 0x0f,
1389 MCU_CE_CMD_SET_BSS_CONNECTED = 0x16,
1390 MCU_CE_CMD_SET_BSS_ABORT = 0x17,
1391 MCU_CE_CMD_CANCEL_HW_SCAN = 0x1b,
1392 MCU_CE_CMD_SET_ROC = 0x1c,
1393 MCU_CE_CMD_SET_EDCA_PARMS = 0x1d,
1394 MCU_CE_CMD_SET_P2P_OPPPS = 0x33,
1395 MCU_CE_CMD_SET_CLC = 0x5c,
1396 MCU_CE_CMD_SET_RATE_TX_POWER = 0x5d,
1397 MCU_CE_CMD_SCHED_SCAN_ENABLE = 0x61,
1398 MCU_CE_CMD_SCHED_SCAN_REQ = 0x62,
1399 MCU_CE_CMD_GET_NIC_CAPAB = 0x8a,
1400 MCU_CE_CMD_RSSI_MONITOR = 0xa1,
1401 MCU_CE_CMD_SET_MU_EDCA_PARMS = 0xb0,
1402 MCU_CE_CMD_REG_WRITE = 0xc0,
1403 MCU_CE_CMD_REG_READ = 0xc0,
1404 MCU_CE_CMD_CHIP_CONFIG = 0xca,
1405 MCU_CE_CMD_FWLOG_2_HOST = 0xc5,
1406 MCU_CE_CMD_GET_WTBL = 0xcd,
1407 MCU_CE_CMD_GET_TXPWR = 0xd0,
1408 MCU_CE_CMD_SET_REGD_CH = 0xd1,
1409 };
1410
1411 enum {
1412 PATCH_SEM_RELEASE,
1413 PATCH_SEM_GET
1414 };
1415
1416 enum {
1417 UNI_BSS_INFO_BASIC = 0,
1418 UNI_BSS_INFO_RA = 1,
1419 UNI_BSS_INFO_RLM = 2,
1420 UNI_BSS_INFO_PROTECT_INFO = 3,
1421 UNI_BSS_INFO_BSS_COLOR = 4,
1422 UNI_BSS_INFO_HE_BASIC = 5,
1423 UNI_BSS_INFO_11V_MBSSID = 6,
1424 UNI_BSS_INFO_BCN_CONTENT = 7,
1425 UNI_BSS_INFO_BCN_CSA = 8,
1426 UNI_BSS_INFO_BCN_BCC = 9,
1427 UNI_BSS_INFO_BCN_MBSSID = 10,
1428 UNI_BSS_INFO_RATE = 11,
1429 UNI_BSS_INFO_QBSS = 15,
1430 UNI_BSS_INFO_SEC = 16,
1431 UNI_BSS_INFO_BCN_PROT = 17,
1432 UNI_BSS_INFO_TXCMD = 18,
1433 UNI_BSS_INFO_UAPSD = 19,
1434 UNI_BSS_INFO_PS = 21,
1435 UNI_BSS_INFO_BCNFT = 22,
1436 UNI_BSS_INFO_IFS_TIME = 23,
1437 UNI_BSS_INFO_OFFLOAD = 25,
1438 UNI_BSS_INFO_MLD = 26,
1439 UNI_BSS_INFO_PM_DISABLE = 27,
1440 UNI_BSS_INFO_EHT = 30,
1441 UNI_BSS_INFO_MLD_LINK_OP = 36,
1442 };
1443
1444 enum {
1445 UNI_OFFLOAD_OFFLOAD_ARP,
1446 UNI_OFFLOAD_OFFLOAD_ND,
1447 UNI_OFFLOAD_OFFLOAD_GTK_REKEY,
1448 UNI_OFFLOAD_OFFLOAD_BMC_RPY_DETECT,
1449 };
1450
1451 enum UNI_ALL_STA_INFO_TAG {
1452 UNI_ALL_STA_TXRX_RATE,
1453 UNI_ALL_STA_TX_STAT,
1454 UNI_ALL_STA_TXRX_ADM_STAT,
1455 UNI_ALL_STA_TXRX_AIR_TIME,
1456 UNI_ALL_STA_DATA_TX_RETRY_COUNT,
1457 UNI_ALL_STA_GI_MODE,
1458 UNI_ALL_STA_TXRX_MSDU_COUNT,
1459 UNI_ALL_STA_MAX_NUM
1460 };
1461
1462 enum {
1463 MT_NIC_CAP_TX_RESOURCE,
1464 MT_NIC_CAP_TX_EFUSE_ADDR,
1465 MT_NIC_CAP_COEX,
1466 MT_NIC_CAP_SINGLE_SKU,
1467 MT_NIC_CAP_CSUM_OFFLOAD,
1468 MT_NIC_CAP_HW_VER,
1469 MT_NIC_CAP_SW_VER,
1470 MT_NIC_CAP_MAC_ADDR,
1471 MT_NIC_CAP_PHY,
1472 MT_NIC_CAP_MAC,
1473 MT_NIC_CAP_FRAME_BUF,
1474 MT_NIC_CAP_BEAM_FORM,
1475 MT_NIC_CAP_LOCATION,
1476 MT_NIC_CAP_MUMIMO,
1477 MT_NIC_CAP_BUFFER_MODE_INFO,
1478 MT_NIC_CAP_HW_ADIE_VERSION = 0x14,
1479 MT_NIC_CAP_ANTSWP = 0x16,
1480 MT_NIC_CAP_WFDMA_REALLOC,
1481 MT_NIC_CAP_6G,
1482 MT_NIC_CAP_CHIP_CAP = 0x20,
1483 MT_NIC_CAP_EML_CAP = 0x22,
1484 };
1485
1486 #define UNI_WOW_DETECT_TYPE_MAGIC BIT(0)
1487 #define UNI_WOW_DETECT_TYPE_ANY BIT(1)
1488 #define UNI_WOW_DETECT_TYPE_DISCONNECT BIT(2)
1489 #define UNI_WOW_DETECT_TYPE_GTK_REKEY_FAIL BIT(3)
1490 #define UNI_WOW_DETECT_TYPE_BCN_LOST BIT(4)
1491 #define UNI_WOW_DETECT_TYPE_SCH_SCAN_HIT BIT(5)
1492 #define UNI_WOW_DETECT_TYPE_BITMAP BIT(6)
1493
1494 enum {
1495 UNI_SUSPEND_MODE_SETTING,
1496 UNI_SUSPEND_WOW_CTRL,
1497 UNI_SUSPEND_WOW_GPIO_PARAM,
1498 UNI_SUSPEND_WOW_WAKEUP_PORT,
1499 UNI_SUSPEND_WOW_PATTERN,
1500 };
1501
1502 enum {
1503 WOW_USB = 1,
1504 WOW_PCIE = 2,
1505 WOW_GPIO = 3,
1506 };
1507
1508 struct mt76_connac_bss_basic_tlv {
1509 __le16 tag;
1510 __le16 len;
1511 u8 active;
1512 u8 omac_idx;
1513 u8 hw_bss_idx;
1514 u8 band_idx;
1515 __le32 conn_type;
1516 u8 conn_state;
1517 u8 wmm_idx;
1518 u8 bssid[ETH_ALEN];
1519 __le16 bmc_tx_wlan_idx;
1520 __le16 bcn_interval;
1521 u8 dtim_period;
1522 u8 phymode; /* bit(0): A
1523 * bit(1): B
1524 * bit(2): G
1525 * bit(3): GN
1526 * bit(4): AN
1527 * bit(5): AC
1528 * bit(6): AX2
1529 * bit(7): AX5
1530 * bit(8): AX6
1531 */
1532 __le16 sta_idx;
1533 __le16 nonht_basic_phy;
1534 u8 phymode_ext; /* bit(0) AX_6G */
1535 u8 link_idx;
1536 } __packed;
1537
1538 struct mt76_connac_bss_qos_tlv {
1539 __le16 tag;
1540 __le16 len;
1541 u8 qos;
1542 u8 pad[3];
1543 } __packed;
1544
1545 struct mt76_connac_beacon_loss_event {
1546 u8 bss_idx;
1547 u8 reason;
1548 u8 pad[2];
1549 } __packed;
1550
1551 struct mt76_connac_rssi_notify_event {
1552 __le32 rssi[4];
1553 } __packed;
1554
1555 struct mt76_connac_mcu_bss_event {
1556 u8 bss_idx;
1557 u8 is_absent;
1558 u8 free_quota;
1559 u8 pad;
1560 } __packed;
1561
1562 struct mt76_connac_mcu_scan_ssid {
1563 __le32 ssid_len;
1564 u8 ssid[IEEE80211_MAX_SSID_LEN];
1565 } __packed;
1566
1567 struct mt76_connac_mcu_scan_channel {
1568 u8 band; /* 1: 2.4GHz
1569 * 2: 5.0GHz
1570 * Others: Reserved
1571 */
1572 u8 channel_num;
1573 } __packed;
1574
1575 struct mt76_connac_mcu_scan_match {
1576 __le32 rssi_th;
1577 u8 ssid[IEEE80211_MAX_SSID_LEN];
1578 u8 ssid_len;
1579 u8 rsv[3];
1580 } __packed;
1581
1582 struct mt76_connac_hw_scan_req {
1583 u8 seq_num;
1584 u8 bss_idx;
1585 u8 scan_type; /* 0: PASSIVE SCAN
1586 * 1: ACTIVE SCAN
1587 */
1588 u8 ssid_type; /* BIT(0) wildcard SSID
1589 * BIT(1) P2P wildcard SSID
1590 * BIT(2) specified SSID + wildcard SSID
1591 * BIT(2) + ssid_type_ext BIT(0) specified SSID only
1592 */
1593 u8 ssids_num;
1594 u8 probe_req_num; /* Number of probe request for each SSID */
1595 u8 scan_func; /* BIT(0) Enable random MAC scan
1596 * BIT(1) Disable DBDC scan type 1~3.
1597 * BIT(2) Use DBDC scan type 3 (dedicated one RF to scan).
1598 */
1599 u8 version; /* 0: Not support fields after ies.
1600 * 1: Support fields after ies.
1601 */
1602 struct mt76_connac_mcu_scan_ssid ssids[4];
1603 __le16 probe_delay_time;
1604 __le16 channel_dwell_time; /* channel Dwell interval */
1605 __le16 timeout_value;
1606 u8 channel_type; /* 0: Full channels
1607 * 1: Only 2.4GHz channels
1608 * 2: Only 5GHz channels
1609 * 3: P2P social channel only (channel #1, #6 and #11)
1610 * 4: Specified channels
1611 * Others: Reserved
1612 */
1613 u8 channels_num; /* valid when channel_type is 4 */
1614 /* valid when channels_num is set */
1615 struct mt76_connac_mcu_scan_channel channels[32];
1616 __le16 ies_len;
1617 u8 ies[MT76_CONNAC_SCAN_IE_LEN];
1618 /* following fields are valid if version > 0 */
1619 u8 ext_channels_num;
1620 u8 ext_ssids_num;
1621 __le16 channel_min_dwell_time;
1622 struct mt76_connac_mcu_scan_channel ext_channels[32];
1623 struct mt76_connac_mcu_scan_ssid ext_ssids[6];
1624 u8 bssid[ETH_ALEN];
1625 u8 random_mac[ETH_ALEN]; /* valid when BIT(1) in scan_func is set. */
1626 u8 pad[63];
1627 u8 ssid_type_ext;
1628 } __packed;
1629
1630 #define MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM 64
1631
1632 struct mt76_connac_hw_scan_done {
1633 u8 seq_num;
1634 u8 sparse_channel_num;
1635 struct mt76_connac_mcu_scan_channel sparse_channel;
1636 u8 complete_channel_num;
1637 u8 current_state;
1638 u8 version;
1639 u8 pad;
1640 __le32 beacon_scan_num;
1641 u8 pno_enabled;
1642 u8 pad2[3];
1643 u8 sparse_channel_valid_num;
1644 u8 alpha2[3];
1645 u8 channel_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1646 /* idle format for channel_idle_time
1647 * 0: first bytes: idle time(ms) 2nd byte: dwell time(ms)
1648 * 1: first bytes: idle time(8ms) 2nd byte: dwell time(8ms)
1649 * 2: dwell time (16us)
1650 */
1651 __le16 channel_idle_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1652 /* beacon and probe response count */
1653 u8 beacon_probe_num[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1654 u8 mdrdy_count[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1655 __le32 beacon_2g_num;
1656 __le32 beacon_5g_num;
1657 __le16 channel_scan_time[MT76_CONNAC_SCAN_DONE_EVENT_MAX_CHANNEL_NUM];
1658 } __packed;
1659
1660 struct mt76_connac_sched_scan_req {
1661 u8 version;
1662 u8 seq_num;
1663 u8 stop_on_match;
1664 u8 ssids_num;
1665 u8 match_num;
1666 u8 pad;
1667 __le16 ie_len;
1668 struct mt76_connac_mcu_scan_ssid ssids[MT76_CONNAC_MAX_SCHED_SCAN_SSID];
1669 struct mt76_connac_mcu_scan_match match[MT76_CONNAC_MAX_SCAN_MATCH];
1670 u8 channel_type;
1671 u8 channels_num;
1672 u8 intervals_num;
1673 u8 scan_func; /* MT7663: BIT(0) eable random mac address */
1674 struct mt76_connac_mcu_scan_channel channels[64];
1675 __le16 intervals[MT76_CONNAC_MAX_NUM_SCHED_SCAN_INTERVAL];
1676 union {
1677 struct {
1678 u8 random_mac[ETH_ALEN];
1679 u8 pad2[58];
1680 } mt7663;
1681 struct {
1682 u8 bss_idx;
1683 u8 pad1[3];
1684 __le32 delay;
1685 u8 pad2[12];
1686 u8 random_mac[ETH_ALEN];
1687 u8 pad3[38];
1688 } mt7921;
1689 };
1690 } __packed;
1691
1692 struct mt76_connac_sched_scan_done {
1693 u8 seq_num;
1694 u8 status; /* 0: ssid found */
1695 __le16 pad;
1696 } __packed;
1697
1698 struct bss_info_uni_bss_color {
1699 __le16 tag;
1700 __le16 len;
1701 u8 enable;
1702 u8 bss_color;
1703 u8 rsv[2];
1704 } __packed;
1705
1706 struct bss_info_uni_he {
1707 __le16 tag;
1708 __le16 len;
1709 __le16 he_rts_thres;
1710 u8 he_pe_duration;
1711 u8 su_disable;
1712 __le16 max_nss_mcs[CMD_HE_MCS_BW_NUM];
1713 u8 rsv[2];
1714 } __packed;
1715
1716 struct bss_info_uni_mbssid {
1717 __le16 tag;
1718 __le16 len;
1719 u8 max_indicator;
1720 u8 mbss_idx;
1721 u8 tx_bss_omac_idx;
1722 u8 rsv;
1723 } __packed;
1724
1725 struct mt76_connac_gtk_rekey_tlv {
1726 __le16 tag;
1727 __le16 len;
1728 u8 kek[NL80211_KEK_LEN];
1729 u8 kck[NL80211_KCK_LEN];
1730 u8 replay_ctr[NL80211_REPLAY_CTR_LEN];
1731 u8 rekey_mode; /* 0: rekey offload enable
1732 * 1: rekey offload disable
1733 * 2: rekey update
1734 */
1735 u8 keyid;
1736 u8 option; /* 1: rekey data update without enabling offload */
1737 u8 pad[1];
1738 __le32 proto; /* WPA-RSN-WAPI-OPSN */
1739 __le32 pairwise_cipher;
1740 __le32 group_cipher;
1741 __le32 key_mgmt; /* NONE-PSK-IEEE802.1X */
1742 __le32 mgmt_group_cipher;
1743 u8 reserverd[4];
1744 } __packed;
1745
1746 #define MT76_CONNAC_WOW_MASK_MAX_LEN 16
1747 #define MT76_CONNAC_WOW_PATTEN_MAX_LEN 128
1748
1749 struct mt76_connac_wow_pattern_tlv {
1750 __le16 tag;
1751 __le16 len;
1752 u8 index; /* pattern index */
1753 u8 enable; /* 0: disable
1754 * 1: enable
1755 */
1756 u8 data_len; /* pattern length */
1757 u8 pad;
1758 u8 mask[MT76_CONNAC_WOW_MASK_MAX_LEN];
1759 u8 pattern[MT76_CONNAC_WOW_PATTEN_MAX_LEN];
1760 u8 rsv[4];
1761 } __packed;
1762
1763 struct mt76_connac_wow_ctrl_tlv {
1764 __le16 tag;
1765 __le16 len;
1766 u8 cmd; /* 0x1: PM_WOWLAN_REQ_START
1767 * 0x2: PM_WOWLAN_REQ_STOP
1768 * 0x3: PM_WOWLAN_PARAM_CLEAR
1769 */
1770 u8 trigger; /* 0: NONE
1771 * BIT(0): NL80211_WOWLAN_TRIG_MAGIC_PKT
1772 * BIT(1): NL80211_WOWLAN_TRIG_ANY
1773 * BIT(2): NL80211_WOWLAN_TRIG_DISCONNECT
1774 * BIT(3): NL80211_WOWLAN_TRIG_GTK_REKEY_FAILURE
1775 * BIT(4): BEACON_LOST
1776 * BIT(5): NL80211_WOWLAN_TRIG_NET_DETECT
1777 */
1778 u8 wakeup_hif; /* 0x0: HIF_SDIO
1779 * 0x1: HIF_USB
1780 * 0x2: HIF_PCIE
1781 * 0x3: HIF_GPIO
1782 */
1783 u8 pad;
1784 u8 rsv[4];
1785 } __packed;
1786
1787 struct mt76_connac_wow_gpio_param_tlv {
1788 __le16 tag;
1789 __le16 len;
1790 u8 gpio_pin;
1791 u8 trigger_lvl;
1792 u8 pad[2];
1793 __le32 gpio_interval;
1794 u8 rsv[4];
1795 } __packed;
1796
1797 struct mt76_connac_arpns_tlv {
1798 __le16 tag;
1799 __le16 len;
1800 u8 mode;
1801 u8 ips_num;
1802 u8 option;
1803 u8 pad[1];
1804 } __packed;
1805
1806 struct mt76_connac_suspend_tlv {
1807 __le16 tag;
1808 __le16 len;
1809 u8 enable; /* 0: suspend mode disabled
1810 * 1: suspend mode enabled
1811 */
1812 u8 mdtim; /* LP parameter */
1813 u8 wow_suspend; /* 0: update by origin policy
1814 * 1: update by wow dtim
1815 */
1816 u8 pad[5];
1817 } __packed;
1818
1819 enum mt76_sta_info_state {
1820 MT76_STA_INFO_STATE_NONE,
1821 MT76_STA_INFO_STATE_AUTH,
1822 MT76_STA_INFO_STATE_ASSOC
1823 };
1824
1825 struct mt76_sta_cmd_info {
1826 union {
1827 struct ieee80211_sta *sta;
1828 struct ieee80211_link_sta *link_sta;
1829 };
1830 struct mt76_wcid *wcid;
1831
1832 struct ieee80211_vif *vif;
1833 struct ieee80211_bss_conf *link_conf;
1834
1835 bool offload_fw;
1836 bool enable;
1837 bool newly;
1838 int cmd;
1839 u8 rcpi;
1840 u8 state;
1841 };
1842
1843 #define MT_SKU_POWER_LIMIT 161
1844
1845 struct mt76_connac_sku_tlv {
1846 u8 channel;
1847 s8 pwr_limit[MT_SKU_POWER_LIMIT];
1848 } __packed;
1849
1850 struct mt76_connac_tx_power_limit_tlv {
1851 /* DW0 - common info*/
1852 u8 ver;
1853 u8 pad0;
1854 __le16 len;
1855 /* DW1 - cmd hint */
1856 u8 n_chan; /* # channel */
1857 u8 band; /* 2.4GHz - 5GHz - 6GHz */
1858 u8 last_msg;
1859 u8 pad1;
1860 /* DW3 */
1861 u8 alpha2[4]; /* regulatory_request.alpha2 */
1862 u8 pad2[32];
1863 } __packed;
1864
1865 struct mt76_connac_config {
1866 __le16 id;
1867 u8 type;
1868 u8 resp_type;
1869 __le16 data_size;
1870 __le16 resv;
1871 u8 data[320];
1872 } __packed;
1873
1874 struct mt76_connac_mcu_uni_event {
1875 u8 cid;
1876 u8 pad[3];
1877 __le32 status; /* 0: success, others: fail */
1878 } __packed;
1879
1880 struct mt76_connac_mcu_reg_event {
1881 __le32 reg;
1882 __le32 val;
1883 } __packed;
1884
1885 static inline enum mcu_cipher_type
mt76_connac_mcu_get_cipher(int cipher)1886 mt76_connac_mcu_get_cipher(int cipher)
1887 {
1888 switch (cipher) {
1889 case WLAN_CIPHER_SUITE_WEP40:
1890 return MCU_CIPHER_WEP40;
1891 case WLAN_CIPHER_SUITE_WEP104:
1892 return MCU_CIPHER_WEP104;
1893 case WLAN_CIPHER_SUITE_TKIP:
1894 return MCU_CIPHER_TKIP;
1895 case WLAN_CIPHER_SUITE_AES_CMAC:
1896 return MCU_CIPHER_BIP_CMAC_128;
1897 case WLAN_CIPHER_SUITE_CCMP:
1898 return MCU_CIPHER_AES_CCMP;
1899 case WLAN_CIPHER_SUITE_CCMP_256:
1900 return MCU_CIPHER_CCMP_256;
1901 case WLAN_CIPHER_SUITE_GCMP:
1902 return MCU_CIPHER_GCMP;
1903 case WLAN_CIPHER_SUITE_GCMP_256:
1904 return MCU_CIPHER_GCMP_256;
1905 case WLAN_CIPHER_SUITE_BIP_GMAC_128:
1906 return MCU_CIPHER_BIP_GMAC_128;
1907 case WLAN_CIPHER_SUITE_BIP_GMAC_256:
1908 return MCU_CIPHER_BIP_GMAC_256;
1909 case WLAN_CIPHER_SUITE_BIP_CMAC_256:
1910 return MCU_CIPHER_BIP_CMAC_256;
1911 case WLAN_CIPHER_SUITE_SMS4:
1912 return MCU_CIPHER_WAPI;
1913 default:
1914 return MCU_CIPHER_NONE;
1915 }
1916 }
1917
1918 static inline u32
mt76_connac_mcu_gen_dl_mode(struct mt76_dev * dev,u8 feature_set,bool is_wa)1919 mt76_connac_mcu_gen_dl_mode(struct mt76_dev *dev, u8 feature_set, bool is_wa)
1920 {
1921 u32 ret = 0;
1922
1923 ret |= feature_set & FW_FEATURE_SET_ENCRYPT ?
1924 DL_MODE_ENCRYPT | DL_MODE_RESET_SEC_IV : 0;
1925 if (is_connac2(dev) || is_connac3(dev))
1926 ret |= feature_set & FW_FEATURE_ENCRY_MODE ?
1927 DL_CONFIG_ENCRY_MODE_SEL : 0;
1928 ret |= FIELD_PREP(DL_MODE_KEY_IDX,
1929 FIELD_GET(FW_FEATURE_SET_KEY_IDX, feature_set));
1930 ret |= DL_MODE_NEED_RSP;
1931 ret |= is_wa ? DL_MODE_WORKING_PDA_CR4 : 0;
1932
1933 return ret;
1934 }
1935
1936 #define to_wcid_lo(id) FIELD_GET(GENMASK(7, 0), (u16)id)
1937 #define to_wcid_hi(id) FIELD_GET(GENMASK(10, 8), (u16)id)
1938
1939 static inline void
mt76_connac_mcu_get_wlan_idx(struct mt76_dev * dev,struct mt76_wcid * wcid,u8 * wlan_idx_lo,u8 * wlan_idx_hi)1940 mt76_connac_mcu_get_wlan_idx(struct mt76_dev *dev, struct mt76_wcid *wcid,
1941 u8 *wlan_idx_lo, u8 *wlan_idx_hi)
1942 {
1943 *wlan_idx_hi = 0;
1944
1945 if (!is_connac_v1(dev)) {
1946 *wlan_idx_lo = wcid ? to_wcid_lo(wcid->idx) : 0;
1947 *wlan_idx_hi = wcid ? to_wcid_hi(wcid->idx) : 0;
1948 } else {
1949 *wlan_idx_lo = wcid ? wcid->idx : 0;
1950 }
1951 }
1952
1953 #define MT76_CONNAC_MCU_STATUS_WLAN_FAILURE 0xc0000001
1954
1955 static inline int
mt76_connac_mcu_bss_deact_err(struct mt76_dev * mdev,int err,bool enable)1956 mt76_connac_mcu_bss_deact_err(struct mt76_dev *mdev, int err, bool enable)
1957 {
1958 if (err != (int)MT76_CONNAC_MCU_STATUS_WLAN_FAILURE)
1959 return err;
1960
1961 /* Ignore wlan_failure state false alarm when deactivating an
1962 * inactive network. It does not harm the firmware state.
1963 */
1964 if (!enable) {
1965 dev_dbg(mdev->dev,
1966 "ignore wlan_failure when bss is deactivated\n");
1967 return 0;
1968 }
1969
1970 dev_warn(mdev->dev,
1971 "wlan_failure when bss is activated\n");
1972
1973 return err;
1974 }
1975
1976 struct sk_buff *
1977 __mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif_link *mvif,
1978 struct mt76_wcid *wcid, int len);
1979 static inline struct sk_buff *
mt76_connac_mcu_alloc_sta_req(struct mt76_dev * dev,struct mt76_vif_link * mvif,struct mt76_wcid * wcid)1980 mt76_connac_mcu_alloc_sta_req(struct mt76_dev *dev, struct mt76_vif_link *mvif,
1981 struct mt76_wcid *wcid)
1982 {
1983 return __mt76_connac_mcu_alloc_sta_req(dev, mvif, wcid,
1984 MT76_CONNAC_STA_UPDATE_MAX_SIZE);
1985 }
1986
1987 struct wtbl_req_hdr *
1988 mt76_connac_mcu_alloc_wtbl_req(struct mt76_dev *dev, struct mt76_wcid *wcid,
1989 int cmd, void *sta_wtbl, struct sk_buff **skb);
1990 struct tlv *mt76_connac_mcu_add_nested_tlv(struct sk_buff *skb, int tag,
1991 int len, void *sta_ntlv,
1992 void *sta_wtbl);
1993 static inline struct tlv *
mt76_connac_mcu_add_tlv(struct sk_buff * skb,int tag,int len)1994 mt76_connac_mcu_add_tlv(struct sk_buff *skb, int tag, int len)
1995 {
1996 return mt76_connac_mcu_add_nested_tlv(skb, tag, len, skb->data, NULL);
1997 }
1998
1999 int mt76_connac_mcu_set_channel_domain(struct mt76_phy *phy);
2000 int mt76_connac_mcu_set_vif_ps(struct mt76_dev *dev, struct ieee80211_vif *vif);
2001 void mt76_connac_mcu_sta_basic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
2002 struct ieee80211_bss_conf *link_conf,
2003 struct ieee80211_link_sta *link_sta,
2004 int state, bool newly);
2005 void mt76_connac_mcu_wtbl_generic_tlv(struct mt76_dev *dev, struct sk_buff *skb,
2006 struct ieee80211_vif *vif,
2007 struct ieee80211_sta *sta, void *sta_wtbl,
2008 void *wtbl_tlv);
2009 void mt76_connac_mcu_wtbl_hdr_trans_tlv(struct sk_buff *skb,
2010 struct ieee80211_vif *vif,
2011 struct mt76_wcid *wcid,
2012 void *sta_wtbl, void *wtbl_tlv);
2013 int mt76_connac_mcu_sta_update_hdr_trans(struct mt76_dev *dev,
2014 struct ieee80211_vif *vif,
2015 struct mt76_wcid *wcid, int cmd);
2016 void mt76_connac_mcu_sta_he_tlv_v2(struct sk_buff *skb, struct ieee80211_sta *sta);
2017 u8 mt76_connac_get_phy_mode_v2(struct mt76_phy *mphy, struct ieee80211_vif *vif,
2018 enum nl80211_band band,
2019 struct ieee80211_link_sta *link_sta);
2020 int mt76_connac_mcu_wtbl_update_hdr_trans(struct mt76_dev *dev,
2021 struct ieee80211_vif *vif,
2022 struct ieee80211_sta *sta);
2023 void mt76_connac_mcu_sta_tlv(struct mt76_phy *mphy, struct sk_buff *skb,
2024 struct ieee80211_sta *sta,
2025 struct ieee80211_vif *vif,
2026 u8 rcpi, u8 state);
2027 void mt76_connac_mcu_wtbl_ht_tlv(struct mt76_dev *dev, struct sk_buff *skb,
2028 struct ieee80211_sta *sta, void *sta_wtbl,
2029 void *wtbl_tlv, bool ht_ldpc, bool vht_ldpc);
2030 void mt76_connac_mcu_wtbl_ba_tlv(struct mt76_dev *dev, struct sk_buff *skb,
2031 struct ieee80211_ampdu_params *params,
2032 bool enable, bool tx, void *sta_wtbl,
2033 void *wtbl_tlv);
2034 void mt76_connac_mcu_sta_ba_tlv(struct sk_buff *skb,
2035 struct ieee80211_ampdu_params *params,
2036 bool enable, bool tx);
2037 int mt76_connac_mcu_uni_add_dev(struct mt76_phy *phy,
2038 struct ieee80211_bss_conf *bss_conf,
2039 struct mt76_vif_link *mvif,
2040 struct mt76_wcid *wcid,
2041 bool enable);
2042 int mt76_connac_mcu_sta_ba(struct mt76_dev *dev, struct mt76_vif_link *mvif,
2043 struct ieee80211_ampdu_params *params,
2044 int cmd, bool enable, bool tx);
2045 int mt76_connac_mcu_uni_set_chctx(struct mt76_phy *phy,
2046 struct mt76_vif_link *vif,
2047 struct ieee80211_chanctx_conf *ctx);
2048 int mt76_connac_mcu_uni_add_bss(struct mt76_phy *phy,
2049 struct ieee80211_vif *vif,
2050 struct mt76_wcid *wcid,
2051 bool enable,
2052 struct ieee80211_chanctx_conf *ctx);
2053 int mt76_connac_mcu_sta_cmd(struct mt76_phy *phy,
2054 struct mt76_sta_cmd_info *info);
2055 void mt76_connac_mcu_beacon_loss_iter(void *priv, u8 *mac,
2056 struct ieee80211_vif *vif);
2057 int mt76_connac_mcu_set_rts_thresh(struct mt76_dev *dev, u32 val, u8 band);
2058 int mt76_connac_mcu_set_mac_enable(struct mt76_dev *dev, int band, bool enable,
2059 bool hdr_trans);
2060 int mt76_connac_mcu_init_download(struct mt76_dev *dev, u32 addr, u32 len,
2061 u32 mode);
2062 int mt76_connac_mcu_start_patch(struct mt76_dev *dev);
2063 int mt76_connac_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
2064 int mt76_connac_cb_mcu_init_download(struct mt76_dev *dev, u32 len);
2065 int mt76_connac_cb_mcu_start_patch(struct mt76_dev *dev);
2066 int mt76_connac_cb_mcu_patch_sem_ctrl(struct mt76_dev *dev, bool get);
2067 int mt76_connac_mcu_start_firmware(struct mt76_dev *dev, u32 addr, u32 option);
2068
2069 void mt76_connac_mcu_build_rnr_scan_param(struct mt76_dev *mdev,
2070 struct cfg80211_scan_request *sreq);
2071 int mt76_connac_mcu_hw_scan(struct mt76_phy *phy, struct ieee80211_vif *vif,
2072 struct ieee80211_scan_request *scan_req);
2073 int mt76_connac_mcu_cancel_hw_scan(struct mt76_phy *phy,
2074 struct ieee80211_vif *vif);
2075 int mt76_connac_mcu_sched_scan_req(struct mt76_phy *phy,
2076 struct ieee80211_vif *vif,
2077 struct cfg80211_sched_scan_request *sreq);
2078 int mt76_connac_mcu_sched_scan_enable(struct mt76_phy *phy,
2079 struct ieee80211_vif *vif,
2080 bool enable);
2081 int mt76_connac_mcu_update_arp_filter(struct mt76_dev *dev,
2082 struct mt76_vif_link *vif,
2083 struct ieee80211_bss_conf *info);
2084 int mt76_connac_mcu_set_gtk_rekey(struct mt76_dev *dev, struct ieee80211_vif *vif,
2085 bool suspend);
2086 int mt76_connac_mcu_set_wow_ctrl(struct mt76_phy *phy, struct ieee80211_vif *vif,
2087 bool suspend, struct cfg80211_wowlan *wowlan);
2088 int mt76_connac_mcu_update_gtk_rekey(struct ieee80211_hw *hw,
2089 struct ieee80211_vif *vif,
2090 struct cfg80211_gtk_rekey_data *key);
2091 int mt76_connac_mcu_set_suspend_mode(struct mt76_dev *dev,
2092 struct ieee80211_vif *vif,
2093 bool enable, u8 mdtim,
2094 bool wow_suspend);
2095 int mt76_connac_mcu_set_hif_suspend(struct mt76_dev *dev, bool suspend, bool wait_resp);
2096 void mt76_connac_mcu_set_suspend_iter(void *priv, u8 *mac,
2097 struct ieee80211_vif *vif);
2098 int mt76_connac_sta_state_dp(struct mt76_dev *dev,
2099 enum ieee80211_sta_state old_state,
2100 enum ieee80211_sta_state new_state);
2101 int mt76_connac_mcu_chip_config(struct mt76_dev *dev);
2102 int mt76_connac_mcu_set_deep_sleep(struct mt76_dev *dev, bool enable);
2103 void mt76_connac_mcu_coredump_event(struct mt76_dev *dev, struct sk_buff *skb,
2104 struct mt76_connac_coredump *coredump);
2105 s8 mt76_connac_get_ch_power(struct mt76_phy *phy,
2106 struct ieee80211_channel *chan,
2107 s8 target_power);
2108 int mt76_connac_mcu_set_rate_txpower(struct mt76_phy *phy);
2109 int mt76_connac_mcu_set_p2p_oppps(struct ieee80211_hw *hw,
2110 struct ieee80211_vif *vif);
2111 u32 mt76_connac_mcu_reg_rr(struct mt76_dev *dev, u32 offset);
2112 void mt76_connac_mcu_reg_wr(struct mt76_dev *dev, u32 offset, u32 val);
2113
2114 const struct ieee80211_sta_he_cap *
2115 mt76_connac_get_he_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
2116 const struct ieee80211_sta_eht_cap *
2117 mt76_connac_get_eht_phy_cap(struct mt76_phy *phy, struct ieee80211_vif *vif);
2118 u8 mt76_connac_get_phy_mode(struct mt76_phy *phy, struct ieee80211_vif *vif,
2119 enum nl80211_band band,
2120 struct ieee80211_link_sta *sta);
2121 u8 mt76_connac_get_phy_mode_ext(struct mt76_phy *phy, struct ieee80211_bss_conf *conf,
2122 enum nl80211_band band);
2123
2124 int mt76_connac_mcu_add_key(struct mt76_dev *dev, struct ieee80211_vif *vif,
2125 struct mt76_connac_sta_key_conf *sta_key_conf,
2126 struct ieee80211_key_conf *key, int mcu_cmd,
2127 struct mt76_wcid *wcid, enum set_key_cmd cmd);
2128
2129 void mt76_connac_mcu_bss_ext_tlv(struct sk_buff *skb, struct mt76_vif_link *mvif);
2130 void mt76_connac_mcu_bss_omac_tlv(struct sk_buff *skb,
2131 struct ieee80211_vif *vif);
2132 int mt76_connac_mcu_bss_basic_tlv(struct sk_buff *skb,
2133 struct ieee80211_vif *vif,
2134 struct ieee80211_sta *sta,
2135 struct mt76_phy *phy, u16 wlan_idx,
2136 bool enable);
2137 void mt76_connac_mcu_sta_uapsd(struct sk_buff *skb, struct ieee80211_vif *vif,
2138 struct ieee80211_sta *sta);
2139 void mt76_connac_mcu_wtbl_smps_tlv(struct sk_buff *skb,
2140 struct ieee80211_sta *sta,
2141 void *sta_wtbl, void *wtbl_tlv);
2142 int mt76_connac_mcu_set_pm(struct mt76_dev *dev, int band, int enter);
2143 int mt76_connac_mcu_restart(struct mt76_dev *dev);
2144 int mt76_connac_mcu_del_wtbl_all(struct mt76_dev *dev);
2145 int mt76_connac_mcu_rdd_cmd(struct mt76_dev *dev, int cmd, u8 index,
2146 u8 rx_sel, u8 val);
2147 int mt76_connac_mcu_sta_wed_update(struct mt76_dev *dev, struct sk_buff *skb);
2148 int mt76_connac2_load_ram(struct mt76_dev *dev, const char *fw_wm,
2149 const char *fw_wa);
2150 int mt76_connac3_load_phy_ram(struct mt76_dev *dev, const char *fw_name);
2151 int mt76_connac2_load_patch(struct mt76_dev *dev, const char *fw_name);
2152 int mt76_connac3_load_cb_patch(struct mt76_dev *dev, const char *fw_name);
2153 int mt76_connac2_mcu_fill_message(struct mt76_dev *mdev, struct sk_buff *skb,
2154 int cmd, int *wait_seq);
2155 #endif /* __MT76_CONNAC_MCU_H */
2156