| /linux/Documentation/translations/zh_CN/userspace-api/accelerators/ |
| H A D | ocxl.rst | 72 存上下文、内存映射IO（MMIO）区域的大小等。
76 MMIO chapter
79 OpenCAPI为每个AFU定义了两个MMIO区域：
81 * 全局MMIO区域，保存和整个AFU相关的寄存器。
82 * 每个进程的MMIO区域，对于每个上下文固定大小。
168 一个进程可以mmap每个进程的MMIO区域来和AFU交互。
|
| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | processor_mmio_stale_data.rst | 2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
6 (MMIO) vulnerabilities that can expose data. The sequences of operations for
8 vulnerabilities require the attacker to have access to MMIO, many environments
9 are not affected. System environments using virtualization where MMIO access is
22 one microarchitectural buffer or register to another. Processor MMIO Stale Data
49 processors, MMIO primary reads will return 64 bytes of data to the core fill
57 Some endpoint MMIO registers incorrectly handle writes that are smaller than
117 specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
145 is more critical, or the untrusted software has no MMIO access). Note that
[all …]
|
| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | pvpanic-mmio.txt | 1 * QEMU PVPANIC MMIO Configuration bindings
4 MMIO Configuration interface on the "virt" machine.
14 - reg: the MMIO region used by the device.
|
| /linux/Documentation/driver-api/pci/ |
| H A D | p2pdma.rst | 29 its MMIO to the consuming driver. To meet the driver model lifecycle rules the
30 MMIO must have all DMA mapping removed, all CPU accesses prevented, all page
34 guarantee that the consuming driver has stopped using the MMIO during a removal
40 drivers using this option will wrap their MMIO memory in DMABUF and use DMABUF
41 to provide an invalidation shutdown. These MMIO addresess have no struct page, and
46 Building on this, the subsystem offers a layer to wrap the MMIO in a ZONE_DEVICE
49 using the MMIO. This option works with O_DIRECT flows, in some cases, if the
147 KVA is still MMIO and must still be accessed through the normal
149 like any other MMIO mapping. While this will actually work on some
161 some of its MMIO in a DMABUF and give the DMABUF FD to userspace.
[all …]
|
| /linux/arch/x86/kernel/cpu/ |
| H A D | common.c | 1249 #define MMIO BIT(1) macro
1279 VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO | VMSCAPE),
1280 VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO | VMSCAPE),
1281 VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO | VMSCAPE),
1284 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, 0x5, MMIO | RETBLEED | GDS | VMSCAPE),
1285 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | GDS | ITS | VMSCAPE),
1286 VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE),
1287 VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE),
1288 VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, 0xb, MMIO | RETBLEED | GDS | SRBDS | VMSCAPE),
1289 …VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | GDS | SRBDS | ITS | VMSC…
[all …]
|
| /linux/Documentation/PCI/ |
| H A D | pci.rst | 46 - Request MMIO/IOP resources
62 - Release MMIO/IOP resources
183 - Request MMIO/IOP resources
236 Request MMIO/IOP resources
238 Memory (MMIO), and I/O port addresses should NOT be read directly
254 determine MMIO and IO Port resource availability _after_ calling
258 (for MMIO ranges) and request_region() (for IO Port ranges).
354 This guarantee allows the driver to omit MMIO reads to flush
372 - Disable device from responding to MMIO/IO Port addresses
373 - Release MMIO/IO Port resource(s)
[all …]
|
| /linux/drivers/misc/pvpanic/ |
| H A D | Kconfig | 16 tristate "pvpanic MMIO device support"
19 This driver provides support for the MMIO pvpanic device.
|
| /linux/Documentation/mhi/ |
| H A D | mhi.rst | 25 MMIO section in MHI Internals
28 MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
30 Following are the major components of MMIO register space:
160 to access device MMIO register space.
165 programming MMIO registers.
192 the device's MMIO register space. To initialize the MHI in a device,
198 * Programs MHI MMIO registers and sets device into MHI_M0 state.
|
| /linux/Documentation/devicetree/bindings/regmap/ |
| H A D | regmap.txt | 10 Regmap defaults to little-endian register access on MMIO based
18 of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
|
| /linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| H A D | overview.rst | 121 A DPRC has a mappable MMIO region (an MC portal) that can be used
172 supports and a summary of key resources of the object (MMIO regions
180 - MMIO regions: none
191 - MMIO regions: none
201 from the queues themselves. The DPIO provides an MMIO interface to
203 to the DPIO MMIO region, which includes the target queue number.
208 - MMIO regions: queue operations, buffer management
217 - MMIO regions: none
227 - MMIO regions: MC command portal
|
| /linux/Documentation/trace/ |
| H A D | mmiotrace.rst | 10 MMIO tracing was originally developed by Intel around 2003 for their Fault
12 Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
67 Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
126 MMIO accesses are recorded via page faults. Just before __ioremap() returns,
166 zero if it is not recorded. PID is always zero as tracing MMIO accesses
182 - replaying MMIO logs, i.e., re-executing the recorded writes
|
| /linux/drivers/soc/aspeed/ |
| H A D | Kconfig | 38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The
|
| /linux/drivers/net/ethernet/dlink/ |
| H A D | Kconfig | 46 bool "Use MMIO instead of PIO"
50 Do NOT enable this by default, PIO (enabled when MMIO is disabled)
|
| /linux/drivers/mux/ |
| H A D | Kconfig | 49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
53 MMIO/Regmap register bitfield-controlled Multiplexer controller.
|
| /linux/Documentation/arch/powerpc/ |
| H A D | pci_iov_resource_on_powernv.rst | 13 This document describes the requirement from hardware for PCI MMIO resource
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
96 maps each segment to a PE#. That allows portions of the MMIO space
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
222 The IODA2 platform has 16 M64 windows, which are used to map MMIO
223 range to PE#. Each M64 window defines one MMIO range and this range is
232 device's MMIO range.
236 segments [total_VFs, 255] of the M64 window may map to some MMIO range on
287 In IODA2, the MMIO address determines the PE#. If the address is in an M32
|
| /linux/drivers/net/ethernet/via/ |
| H A D | Kconfig | 37 bool "Use MMIO instead of PIO"
40 This instructs the driver to use PCI shared memory (MMIO) instead of
|
| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi.txt | 5 write to an MMIO address.
14 - The doorbell (the MMIO address written to).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
|
| /linux/Documentation/virt/kvm/x86/ |
| H A D | mmu.rst | 338 accessing MMIO and cached MMIO information is available.
342 MMIO sptes" below)
465 Fast invalidation of MMIO sptes
468 As mentioned in "Reaction to events" above, kvm will cache MMIO
474 MMIO sptes have a few spare bits, which are used to store a
479 When KVM finds an MMIO spte, it checks the generation number of the spte.
481 number, it will ignore the cached MMIO information and handle the page
489 stored into the MMIO spte. Thus, the MMIO spte might be created based on
495 want to use an MMIO sptes created with an odd generation number, and we can do
496 this without losing a bit in the MMIO spte. The "update in-progress" bit of the
[all …]
|
| /linux/Documentation/security/tpm/ |
| H A D | tpm_tis.rst | 13 memory mapped (aka MMIO) interface but it was later on extended to cover other
16 For historical reasons above the original MMIO driver is called tpm_tis and the
|
| /linux/drivers/net/ethernet/chelsio/cxgb3/ |
| H A D | adapter.h | 274 CH_DBG(adapter, MMIO, "read register 0x%x value 0x%x\n", reg_addr, val); in t3_read_reg()
280 CH_DBG(adapter, MMIO, "setting register 0x%x to 0x%x\n", reg_addr, val); in t3_write_reg()
|
| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-amd-iommu | 6 MMIO register offset for iommu<x>, and the file outputs the corresponding
7 MMIO register value of iommu<x>
|
| /linux/Documentation/devicetree/bindings/sound/ |
| H A D | marvell,pxa2xx-ac97.txt | 10 - reg: device MMIO address space
|
| /linux/Documentation/networking/device_drivers/ethernet/google/ |
| H A D | gve.rst | 39 - A block of MMIO registers
66 All registers are MMIO.
149 - TX and RX buffers queues, which send descriptors to the device, use MMIO
|
| /linux/drivers/platform/x86/intel/speed_select_if/ |
| H A D | Kconfig | 16 via MMIO and Mail boxes to enumerate and control all the speed select
|
| /linux/lib/ |
| H A D | Kconfig | 102 bool "Access I/O in non-MMIO mode"
107 hosts which can not be accessed in MMIO mode. Using the logical PIO
109 logic PIO space shared with MMIO hosts, such as PCI/PCIe, then the
136 Create tracepoints for MMIO read/write operations. These trace events
137 can be used for logging all MMIO read/write operations.
|