| /linux/Documentation/translations/zh_CN/userspace-api/accelerators/ |
| H A D | ocxl.rst | 72 存上下文、内存映射IO（MMIO）区域的大小等。
76 MMIO chapter
79 OpenCAPI为每个AFU定义了两个MMIO区域：
81 * 全局MMIO区域，保存和整个AFU相关的寄存器。
82 * 每个进程的MMIO区域，对于每个上下文固定大小。
168 一个进程可以mmap每个进程的MMIO区域来和AFU交互。
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| /linux/Documentation/admin-guide/hw-vuln/ |
| H A D | processor_mmio_stale_data.rst | 2 Processor MMIO Stale Data Vulnerabilities
5 Processor MMIO Stale Data Vulnerabilities are a class of memory-mapped I/O
6 (MMIO) vulnerabilities that can expose data. The sequences of operations for
8 vulnerabilities require the attacker to have access to MMIO, many environments
9 are not affected. System environments using virtualization where MMIO access is
22 one microarchitectural buffer or register to another. Processor MMIO Stale Data
49 processors, MMIO primary reads will return 64 bytes of data to the core fill
57 Some endpoint MMIO registers incorrectly handle writes that are smaller than
117 specific variants of Processor MMIO Stale Data vulnerabilities and mitigation
145 is more critical, or the untrusted software has no MMIO access). Note that
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| /linux/Documentation/devicetree/bindings/misc/ |
| H A D | pvpanic-mmio.txt | 1 * QEMU PVPANIC MMIO Configuration bindings
4 MMIO Configuration interface on the "virt" machine.
14 - reg: the MMIO region used by the device.
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| /linux/Documentation/userspace-api/accelerators/ |
| H A D | ocxl.rst | 66 work with, the size of its MMIO areas, ...
70 MMIO chapter
73 OpenCAPI defines two MMIO areas for each AFU:
75 * the global MMIO area, with registers pertinent to the whole AFU.
76 * a per-process MMIO area, which has a fixed size for each context.
158 MMIO areas, the AFU version, and the PASID for the current context.
175 A process can mmap the per-process MMIO area for interactions with the
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| /linux/arch/x86/kernel/cpu/ |
| H A D | common.c | 1218 #define MMIO BIT(1) macro
1237 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO),
1238 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO),
1240 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO),
1242 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1243 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1244 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1245 VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1246 VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1248 VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
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| /linux/drivers/gpio/ |
| H A D | TODO | 55 driver infrastructure for doing simpler MMIO GPIO devices and there was
83 - Get rid of struct of_mm_gpio_chip altogether: use the generic MMIO
112 Generic MMIO GPIO
114 The GPIO drivers can utilize the generic MMIO helper library in many
115 cases, and the helper library should be as helpful as possible for MMIO
121 dry-code conversions to MMIO GPIO for maintainers to test
123 - Expand the MMIO GPIO or write a new library for regmap-based I/O
127 - Expand the MMIO GPIO or write a new library for port-mapped I/O
134 In the very similar way to Generic MMIO GPIO convert the users which can
136 MMIO case the regmap MMIO with gpio-regmap.c is preferable over gpio-mmio.c.
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| /linux/Documentation/arch/powerpc/ |
| H A D | cxl.rst | 99 MMIO space
102 A portion of the accelerator MMIO space can be directly mapped
141 context. Master contexts have access to the full MMIO space an
143 MMIO space an AFU provides.
147 /dev/cxl/afu0.0d. This will have access to the entire MMIO space
251 An AFU may have an MMIO space to facilitate communication with the
252 AFU. If it does, the MMIO space can be accessed via mmap. The size
257 the MMIO space and slave contexts are allowed to only map the per
258 process MMIO space associated with the context. In dedicated
259 process mode the entire MMIO space can always be mapped.
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| H A D | pci_iov_resource_on_powernv.rst | 13 This document describes the requirement from hardware for PCI MMIO resource
29 state bits (one for MMIO and one for DMA, they get set together but can be
37 The interesting part is how the various PCIe transactions (MMIO, DMA, ...)
96 maps each segment to a PE#. That allows portions of the MMIO space
101 SR-IOV). We basically use the trick of forcing the bridge MMIO windows
222 The IODA2 platform has 16 M64 windows, which are used to map MMIO
223 range to PE#. Each M64 window defines one MMIO range and this range is
232 device's MMIO range.
236 segments [total_VFs, 255] of the M64 window may map to some MMIO range on
287 In IODA2, the MMIO address determines the PE#. If the address is in an M32
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| /linux/Documentation/PCI/ |
| H A D | pci.rst | 46 - Request MMIO/IOP resources
62 - Release MMIO/IOP resources
183 - Request MMIO/IOP resources
236 Request MMIO/IOP resources
238 Memory (MMIO), and I/O port addresses should NOT be read directly
254 determine MMIO and IO Port resource availability _after_ calling
258 (for MMIO ranges) and request_region() (for IO Port ranges).
354 This guarantee allows the driver to omit MMIO reads to flush
372 - Disable device from responding to MMIO/IO Port addresses
373 - Release MMIO/IO Port resource(s)
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| /linux/drivers/misc/pvpanic/ |
| H A D | Kconfig | 16 tristate "pvpanic MMIO device support"
19 This driver provides support for the MMIO pvpanic device.
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| /linux/Documentation/mhi/ |
| H A D | mhi.rst | 25 MMIO section in MHI Internals
28 MMIO (Memory mapped IO) consists of a set of registers in the device hardware,
30 Following are the major components of MMIO register space:
160 to access device MMIO register space.
165 programming MMIO registers.
192 the device's MMIO register space. To initialize the MHI in a device,
198 * Programs MHI MMIO registers and sets device into MHI_M0 state.
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| /linux/Documentation/devicetree/bindings/regmap/ |
| H A D | regmap.txt | 10 Regmap defaults to little-endian register access on MMIO based
18 of the CPU and a byteswap for MMIO registers (e.g. many Broadcom MIPS
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| /linux/Documentation/translations/ko_KR/ |
| H A D | memory-barriers.txt | 121 - 캐시 일관성 vs MMIO.
1833 합니다. 하지만, 느슨한 순서 규칙의 메모리 I/O 윈도우를 통한 MMIO 의 효과를
1910 사용하면 캐시 일관성이 있는 메모리 (cache coherent memory) 쓰기가 MMIO
2515 readX() 와 writeX() MMIO 액세스 함수는 접근되는 주변장치로의 포인터를
2520 순서지어집니다. 이는 같은 CPU 쓰레드에 의한 특정 디바이스로의 MMIO
2526 호출된 MMIO 레지스터 쓰기는 해당 락의 획득에 일관적인 순서로 도달할
2533 전송을 시작시키기 위해 MMIO 컨트롤 레지스터에 쓰기를 할 때 DMA
2539 읽기는 이 DMA 수신의 완료를 표시하는 DMA 엔진의 MMIO 상태 레지스터
2544 주변장치로의 두개의 MMIO 레지스터 쓰기가 행해지는데 첫번째 쓰기가
2568 readsX() 와 writesX() MMIO 액세스 함수는 DMA 를 수행하는데 적절치 않은,
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| /linux/Documentation/networking/device_drivers/ethernet/freescale/dpaa2/ |
| H A D | overview.rst | 121 A DPRC has a mappable MMIO region (an MC portal) that can be used
172 supports and a summary of key resources of the object (MMIO regions
180 - MMIO regions: none
191 - MMIO regions: none
201 from the queues themselves. The DPIO provides an MMIO interface to
203 to the DPIO MMIO region, which includes the target queue number.
208 - MMIO regions: queue operations, buffer management
217 - MMIO regions: none
227 - MMIO regions: MC command portal
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| /linux/Documentation/trace/ |
| H A D | mmiotrace.rst | 10 MMIO tracing was originally developed by Intel around 2003 for their Fault
12 Jeff Muizelaar created a tool for tracing MMIO accesses with the Nouveau
67 Load the driver you want to trace and use it. Mmiotrace will only catch MMIO
126 MMIO accesses are recorded via page faults. Just before __ioremap() returns,
166 zero if it is not recorded. PID is always zero as tracing MMIO accesses
182 - replaying MMIO logs, i.e., re-executing the recorded writes
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| /linux/drivers/soc/aspeed/ |
| H A D | Kconfig | 38 tristate "ASPEED P2A (VGA MMIO to BMC) bridge control"
43 Control ASPEED P2A VGA MMIO to BMC mappings through ioctl()s. The
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| /linux/drivers/mux/ |
| H A D | Kconfig | 49 tristate "MMIO/Regmap register bitfield-controlled Multiplexer"
52 MMIO/Regmap register bitfield-controlled Multiplexer controller.
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| /linux/drivers/net/ethernet/dlink/ |
| H A D | Kconfig | 46 bool "Use MMIO instead of PIO"
50 Do NOT enable this by default, PIO (enabled when MMIO is disabled)
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| /linux/drivers/net/ethernet/via/ |
| H A D | Kconfig | 37 bool "Use MMIO instead of PIO"
40 This instructs the driver to use PCI shared memory (MMIO) instead of
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| /linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | msi.txt | 5 write to an MMIO address.
14 - The doorbell (the MMIO address written to).
34 An MSI controller signals interrupts to a CPU when a write is made to an MMIO
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| /linux/Documentation/virt/kvm/x86/ |
| H A D | mmu.rst | 338 accessing MMIO and cached MMIO information is available.
342 MMIO sptes" below)
465 Fast invalidation of MMIO sptes
468 As mentioned in "Reaction to events" above, kvm will cache MMIO
474 MMIO sptes have a few spare bits, which are used to store a
479 When KVM finds an MMIO spte, it checks the generation number of the spte.
481 number, it will ignore the cached MMIO information and handle the page
489 stored into the MMIO spte. Thus, the MMIO spte might be created based on
495 want to use an MMIO sptes created with an odd generation number, and we can do
496 this without losing a bit in the MMIO spte. The "update in-progress" bit of the
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| /linux/Documentation/driver-api/ |
| H A D | device-io.rst | 152 The data type for an MMIO address is an ``__iomem`` qualified pointer, such as
161 uncached virtual address pointing to the physical MMIO address, some
162 architectures require special instructions for MMIO, and the ``__iomem`` pointer
172 MMIO accesses and DMA accesses as well as fixed endianness for accessing
183 DMA, these "relaxed" versions of the MMIO accessors only serialize against
206 reversed byte order, for accessing devices with big-endian MMIO registers.
235 These are low-level MMIO accessors without barriers or byteorder changes and
239 is only safe to use these to access memory behind a device bus but not MMIO
240 registers, as there are no ordering guarantees with regard to other MMIO
283 MMIO accessors, these do not perform a byteswap on big-endian kernels, so the
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| /linux/Documentation/devicetree/bindings/pci/ |
| H A D | mvebu-pci.txt | 15 - ranges: ranges describing the MMIO registers to control the PCIe
21 The ranges describing the MMIO registers have the following layout:
27 * r is a 32-bits value that gives the offset of the MMIO
31 * s is a 32-bits value that give the size of this MMIO
62 - assigned-addresses: reference to the MMIO registers used to control
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| /linux/Documentation/security/tpm/ |
| H A D | tpm_tis.rst | 13 memory mapped (aka MMIO) interface but it was later on extended to cover other
16 For historical reasons above the original MMIO driver is called tpm_tis and the
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| /linux/Documentation/gpu/amdgpu/ |
| H A D | amdgpu-glossary.rst | 36 (memory or MMIO space) into the GPU's address space so the GPU can access
57 which provides access to system resources (memory or MMIO space) for
|