| /linux/drivers/gpu/drm/amd/amdgpu/ |
| H A D | mmhub_v2_0.c | 154 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_print_l2_protection_fault_status()
571 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
604 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_clock_gating()
628 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_update_medium_grain_light_sleep()
654 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_set_clockgating()
679 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_0_get_clockgating()
|
| H A D | cyan_skillfish_reg_init.c | 40 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in cyan_skillfish_reg_base_init()
|
| H A D | dimgrey_cavefish_reg_init.c | 37 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in dimgrey_cavefish_reg_base_init()
|
| H A D | aldebaran_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in aldebaran_reg_base_init()
|
| H A D | arct_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in arct_reg_base_init()
|
| H A D | vega10_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega10_reg_base_init()
|
| H A D | vega20_reg_init.c | 36 adev->reg_offset[MMHUB_HWIP][i] = (uint32_t *)(&(MMHUB_BASE.instance[i])); in vega20_reg_base_init()
|
| H A D | umsch_mm_v4_0.c | 295 memcpy(set_hw_resources.mmhub_base, adev->reg_offset[MMHUB_HWIP][0], in umsch_mm_v4_0_set_hw_resources()
298 IP_VERSION_MAJ_MIN_REV(amdgpu_ip_version(adev, MMHUB_HWIP, 0)); in umsch_mm_v4_0_set_hw_resources()
|
| H A D | amdgpu_discovery.c | 222 [MMHUB_HWIP] = MMHUB_HWID,
2637 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0); in amdgpu_discovery_set_ip_blocks()
2666 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0); in amdgpu_discovery_set_ip_blocks()
2697 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0); in amdgpu_discovery_set_ip_blocks()
2714 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 1, 0); in amdgpu_discovery_set_ip_blocks()
2743 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0); in amdgpu_discovery_set_ip_blocks()
2774 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1); in amdgpu_discovery_set_ip_blocks()
2809 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2); in amdgpu_discovery_set_ip_blocks()
2845 adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(2, 0, 3); in amdgpu_discovery_set_ip_blocks()
|
| H A D | gmc_v12_0.c | 240 GC_HWIP : MMHUB_HWIP; in gmc_v12_0_flush_vm_hub()
622 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v12_0_set_mmhub_funcs()
|
| H A D | gmc_v11_0.c | 271 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v11_0_flush_gpu_tlb()
594 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v11_0_set_mmhub_funcs()
|
| H A D | gmc_v9_0.c | 694 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_process_interrupt()
1464 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_set_mmhub_funcs()
1483 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_set_mmhub_ras_funcs()
2094 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v9_0_init_golden_registers()
|
| H A D | gmc_v10_0.c | 283 hub_ip = (vmhub == AMDGPU_GFXHUB(0)) ? GC_HWIP : MMHUB_HWIP; in gmc_v10_0_flush_gpu_tlb()
598 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in gmc_v10_0_set_mmhub_funcs()
|
| H A D | amdgpu_dev_coredump.c | 49 [MMHUB_HWIP] = "MMHUB",
|
| H A D | mmhub_v3_0_1.c | 118 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v3_0_1_print_l2_protection_fault_status()
|
| H A D | mmhub_v3_0.c | 110 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v3_0_print_l2_protection_fault_status()
|
| H A D | mmhub_v2_3.c | 93 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v2_3_print_l2_protection_fault_status()
|
| H A D | mmhub_v4_1_0.c | 103 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v4_1_0_print_l2_protection_fault_status()
|
| H A D | mmhub_v3_3.c | 202 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) { in mmhub_v3_3_print_l2_protection_fault_status()
|
| H A D | amdgpu.h | 775 MMHUB_HWIP, enumerator
|
| H A D | amdgpu_virt.c | 1327 case MMHUB_HWIP: in amdgpu_virt_get_rlcg_reg_access_flag()
|
| H A D | mes_v11_0.c | 710 adev->reg_offset[MMHUB_HWIP][0][i]; in mes_v11_0_set_hw_resources()
|
| H A D | mes_v12_0.c | 772 adev->reg_offset[MMHUB_HWIP][0][i]; in mes_v12_0_set_hw_resources()
|