1 /* 2 * Copyright 2020 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #ifndef _mmhub_1_7_SH_MASK_HEADER 24 #define _mmhub_1_7_SH_MASK_HEADER 25 26 27 // addressBlock: mmhub_dagb_dagbdec0 28 //DAGB0_RDCLI0 29 #define DAGB0_RDCLI0__VIRT_CHAN__SHIFT 0x0 30 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 31 #define DAGB0_RDCLI0__URG_HIGH__SHIFT 0x4 32 #define DAGB0_RDCLI0__URG_LOW__SHIFT 0x8 33 #define DAGB0_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 34 #define DAGB0_RDCLI0__MAX_BW__SHIFT 0xd 35 #define DAGB0_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 36 #define DAGB0_RDCLI0__MIN_BW__SHIFT 0x16 37 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 38 #define DAGB0_RDCLI0__MAX_OSD__SHIFT 0x1a 39 #define DAGB0_RDCLI0__VIRT_CHAN_MASK 0x00000007L 40 #define DAGB0_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 41 #define DAGB0_RDCLI0__URG_HIGH_MASK 0x000000F0L 42 #define DAGB0_RDCLI0__URG_LOW_MASK 0x00000F00L 43 #define DAGB0_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 44 #define DAGB0_RDCLI0__MAX_BW_MASK 0x001FE000L 45 #define DAGB0_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 46 #define DAGB0_RDCLI0__MIN_BW_MASK 0x01C00000L 47 #define DAGB0_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 48 #define DAGB0_RDCLI0__MAX_OSD_MASK 0xFC000000L 49 //DAGB0_RDCLI1 50 #define DAGB0_RDCLI1__VIRT_CHAN__SHIFT 0x0 51 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 52 #define DAGB0_RDCLI1__URG_HIGH__SHIFT 0x4 53 #define DAGB0_RDCLI1__URG_LOW__SHIFT 0x8 54 #define DAGB0_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 55 #define DAGB0_RDCLI1__MAX_BW__SHIFT 0xd 56 #define DAGB0_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 57 #define DAGB0_RDCLI1__MIN_BW__SHIFT 0x16 58 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 59 #define DAGB0_RDCLI1__MAX_OSD__SHIFT 0x1a 60 #define DAGB0_RDCLI1__VIRT_CHAN_MASK 0x00000007L 61 #define DAGB0_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 62 #define DAGB0_RDCLI1__URG_HIGH_MASK 0x000000F0L 63 #define DAGB0_RDCLI1__URG_LOW_MASK 0x00000F00L 64 #define DAGB0_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 65 #define DAGB0_RDCLI1__MAX_BW_MASK 0x001FE000L 66 #define DAGB0_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 67 #define DAGB0_RDCLI1__MIN_BW_MASK 0x01C00000L 68 #define DAGB0_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 69 #define DAGB0_RDCLI1__MAX_OSD_MASK 0xFC000000L 70 //DAGB0_RDCLI2 71 #define DAGB0_RDCLI2__VIRT_CHAN__SHIFT 0x0 72 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 73 #define DAGB0_RDCLI2__URG_HIGH__SHIFT 0x4 74 #define DAGB0_RDCLI2__URG_LOW__SHIFT 0x8 75 #define DAGB0_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 76 #define DAGB0_RDCLI2__MAX_BW__SHIFT 0xd 77 #define DAGB0_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 78 #define DAGB0_RDCLI2__MIN_BW__SHIFT 0x16 79 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 80 #define DAGB0_RDCLI2__MAX_OSD__SHIFT 0x1a 81 #define DAGB0_RDCLI2__VIRT_CHAN_MASK 0x00000007L 82 #define DAGB0_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 83 #define DAGB0_RDCLI2__URG_HIGH_MASK 0x000000F0L 84 #define DAGB0_RDCLI2__URG_LOW_MASK 0x00000F00L 85 #define DAGB0_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 86 #define DAGB0_RDCLI2__MAX_BW_MASK 0x001FE000L 87 #define DAGB0_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 88 #define DAGB0_RDCLI2__MIN_BW_MASK 0x01C00000L 89 #define DAGB0_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 90 #define DAGB0_RDCLI2__MAX_OSD_MASK 0xFC000000L 91 //DAGB0_RDCLI3 92 #define DAGB0_RDCLI3__VIRT_CHAN__SHIFT 0x0 93 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 94 #define DAGB0_RDCLI3__URG_HIGH__SHIFT 0x4 95 #define DAGB0_RDCLI3__URG_LOW__SHIFT 0x8 96 #define DAGB0_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 97 #define DAGB0_RDCLI3__MAX_BW__SHIFT 0xd 98 #define DAGB0_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 99 #define DAGB0_RDCLI3__MIN_BW__SHIFT 0x16 100 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 101 #define DAGB0_RDCLI3__MAX_OSD__SHIFT 0x1a 102 #define DAGB0_RDCLI3__VIRT_CHAN_MASK 0x00000007L 103 #define DAGB0_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 104 #define DAGB0_RDCLI3__URG_HIGH_MASK 0x000000F0L 105 #define DAGB0_RDCLI3__URG_LOW_MASK 0x00000F00L 106 #define DAGB0_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 107 #define DAGB0_RDCLI3__MAX_BW_MASK 0x001FE000L 108 #define DAGB0_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 109 #define DAGB0_RDCLI3__MIN_BW_MASK 0x01C00000L 110 #define DAGB0_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 111 #define DAGB0_RDCLI3__MAX_OSD_MASK 0xFC000000L 112 //DAGB0_RDCLI4 113 #define DAGB0_RDCLI4__VIRT_CHAN__SHIFT 0x0 114 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 115 #define DAGB0_RDCLI4__URG_HIGH__SHIFT 0x4 116 #define DAGB0_RDCLI4__URG_LOW__SHIFT 0x8 117 #define DAGB0_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 118 #define DAGB0_RDCLI4__MAX_BW__SHIFT 0xd 119 #define DAGB0_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 120 #define DAGB0_RDCLI4__MIN_BW__SHIFT 0x16 121 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 122 #define DAGB0_RDCLI4__MAX_OSD__SHIFT 0x1a 123 #define DAGB0_RDCLI4__VIRT_CHAN_MASK 0x00000007L 124 #define DAGB0_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 125 #define DAGB0_RDCLI4__URG_HIGH_MASK 0x000000F0L 126 #define DAGB0_RDCLI4__URG_LOW_MASK 0x00000F00L 127 #define DAGB0_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 128 #define DAGB0_RDCLI4__MAX_BW_MASK 0x001FE000L 129 #define DAGB0_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 130 #define DAGB0_RDCLI4__MIN_BW_MASK 0x01C00000L 131 #define DAGB0_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 132 #define DAGB0_RDCLI4__MAX_OSD_MASK 0xFC000000L 133 //DAGB0_RDCLI5 134 #define DAGB0_RDCLI5__VIRT_CHAN__SHIFT 0x0 135 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 136 #define DAGB0_RDCLI5__URG_HIGH__SHIFT 0x4 137 #define DAGB0_RDCLI5__URG_LOW__SHIFT 0x8 138 #define DAGB0_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 139 #define DAGB0_RDCLI5__MAX_BW__SHIFT 0xd 140 #define DAGB0_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 141 #define DAGB0_RDCLI5__MIN_BW__SHIFT 0x16 142 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 143 #define DAGB0_RDCLI5__MAX_OSD__SHIFT 0x1a 144 #define DAGB0_RDCLI5__VIRT_CHAN_MASK 0x00000007L 145 #define DAGB0_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 146 #define DAGB0_RDCLI5__URG_HIGH_MASK 0x000000F0L 147 #define DAGB0_RDCLI5__URG_LOW_MASK 0x00000F00L 148 #define DAGB0_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 149 #define DAGB0_RDCLI5__MAX_BW_MASK 0x001FE000L 150 #define DAGB0_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 151 #define DAGB0_RDCLI5__MIN_BW_MASK 0x01C00000L 152 #define DAGB0_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 153 #define DAGB0_RDCLI5__MAX_OSD_MASK 0xFC000000L 154 //DAGB0_RDCLI6 155 #define DAGB0_RDCLI6__VIRT_CHAN__SHIFT 0x0 156 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 157 #define DAGB0_RDCLI6__URG_HIGH__SHIFT 0x4 158 #define DAGB0_RDCLI6__URG_LOW__SHIFT 0x8 159 #define DAGB0_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 160 #define DAGB0_RDCLI6__MAX_BW__SHIFT 0xd 161 #define DAGB0_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 162 #define DAGB0_RDCLI6__MIN_BW__SHIFT 0x16 163 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 164 #define DAGB0_RDCLI6__MAX_OSD__SHIFT 0x1a 165 #define DAGB0_RDCLI6__VIRT_CHAN_MASK 0x00000007L 166 #define DAGB0_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 167 #define DAGB0_RDCLI6__URG_HIGH_MASK 0x000000F0L 168 #define DAGB0_RDCLI6__URG_LOW_MASK 0x00000F00L 169 #define DAGB0_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 170 #define DAGB0_RDCLI6__MAX_BW_MASK 0x001FE000L 171 #define DAGB0_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 172 #define DAGB0_RDCLI6__MIN_BW_MASK 0x01C00000L 173 #define DAGB0_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 174 #define DAGB0_RDCLI6__MAX_OSD_MASK 0xFC000000L 175 //DAGB0_RDCLI7 176 #define DAGB0_RDCLI7__VIRT_CHAN__SHIFT 0x0 177 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 178 #define DAGB0_RDCLI7__URG_HIGH__SHIFT 0x4 179 #define DAGB0_RDCLI7__URG_LOW__SHIFT 0x8 180 #define DAGB0_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 181 #define DAGB0_RDCLI7__MAX_BW__SHIFT 0xd 182 #define DAGB0_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 183 #define DAGB0_RDCLI7__MIN_BW__SHIFT 0x16 184 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 185 #define DAGB0_RDCLI7__MAX_OSD__SHIFT 0x1a 186 #define DAGB0_RDCLI7__VIRT_CHAN_MASK 0x00000007L 187 #define DAGB0_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 188 #define DAGB0_RDCLI7__URG_HIGH_MASK 0x000000F0L 189 #define DAGB0_RDCLI7__URG_LOW_MASK 0x00000F00L 190 #define DAGB0_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 191 #define DAGB0_RDCLI7__MAX_BW_MASK 0x001FE000L 192 #define DAGB0_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 193 #define DAGB0_RDCLI7__MIN_BW_MASK 0x01C00000L 194 #define DAGB0_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 195 #define DAGB0_RDCLI7__MAX_OSD_MASK 0xFC000000L 196 //DAGB0_RDCLI8 197 #define DAGB0_RDCLI8__VIRT_CHAN__SHIFT 0x0 198 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 199 #define DAGB0_RDCLI8__URG_HIGH__SHIFT 0x4 200 #define DAGB0_RDCLI8__URG_LOW__SHIFT 0x8 201 #define DAGB0_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 202 #define DAGB0_RDCLI8__MAX_BW__SHIFT 0xd 203 #define DAGB0_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 204 #define DAGB0_RDCLI8__MIN_BW__SHIFT 0x16 205 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 206 #define DAGB0_RDCLI8__MAX_OSD__SHIFT 0x1a 207 #define DAGB0_RDCLI8__VIRT_CHAN_MASK 0x00000007L 208 #define DAGB0_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 209 #define DAGB0_RDCLI8__URG_HIGH_MASK 0x000000F0L 210 #define DAGB0_RDCLI8__URG_LOW_MASK 0x00000F00L 211 #define DAGB0_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 212 #define DAGB0_RDCLI8__MAX_BW_MASK 0x001FE000L 213 #define DAGB0_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 214 #define DAGB0_RDCLI8__MIN_BW_MASK 0x01C00000L 215 #define DAGB0_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 216 #define DAGB0_RDCLI8__MAX_OSD_MASK 0xFC000000L 217 //DAGB0_RDCLI9 218 #define DAGB0_RDCLI9__VIRT_CHAN__SHIFT 0x0 219 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 220 #define DAGB0_RDCLI9__URG_HIGH__SHIFT 0x4 221 #define DAGB0_RDCLI9__URG_LOW__SHIFT 0x8 222 #define DAGB0_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 223 #define DAGB0_RDCLI9__MAX_BW__SHIFT 0xd 224 #define DAGB0_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 225 #define DAGB0_RDCLI9__MIN_BW__SHIFT 0x16 226 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 227 #define DAGB0_RDCLI9__MAX_OSD__SHIFT 0x1a 228 #define DAGB0_RDCLI9__VIRT_CHAN_MASK 0x00000007L 229 #define DAGB0_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 230 #define DAGB0_RDCLI9__URG_HIGH_MASK 0x000000F0L 231 #define DAGB0_RDCLI9__URG_LOW_MASK 0x00000F00L 232 #define DAGB0_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 233 #define DAGB0_RDCLI9__MAX_BW_MASK 0x001FE000L 234 #define DAGB0_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 235 #define DAGB0_RDCLI9__MIN_BW_MASK 0x01C00000L 236 #define DAGB0_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 237 #define DAGB0_RDCLI9__MAX_OSD_MASK 0xFC000000L 238 //DAGB0_RDCLI10 239 #define DAGB0_RDCLI10__VIRT_CHAN__SHIFT 0x0 240 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 241 #define DAGB0_RDCLI10__URG_HIGH__SHIFT 0x4 242 #define DAGB0_RDCLI10__URG_LOW__SHIFT 0x8 243 #define DAGB0_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 244 #define DAGB0_RDCLI10__MAX_BW__SHIFT 0xd 245 #define DAGB0_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 246 #define DAGB0_RDCLI10__MIN_BW__SHIFT 0x16 247 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 248 #define DAGB0_RDCLI10__MAX_OSD__SHIFT 0x1a 249 #define DAGB0_RDCLI10__VIRT_CHAN_MASK 0x00000007L 250 #define DAGB0_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 251 #define DAGB0_RDCLI10__URG_HIGH_MASK 0x000000F0L 252 #define DAGB0_RDCLI10__URG_LOW_MASK 0x00000F00L 253 #define DAGB0_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 254 #define DAGB0_RDCLI10__MAX_BW_MASK 0x001FE000L 255 #define DAGB0_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 256 #define DAGB0_RDCLI10__MIN_BW_MASK 0x01C00000L 257 #define DAGB0_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 258 #define DAGB0_RDCLI10__MAX_OSD_MASK 0xFC000000L 259 //DAGB0_RDCLI11 260 #define DAGB0_RDCLI11__VIRT_CHAN__SHIFT 0x0 261 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 262 #define DAGB0_RDCLI11__URG_HIGH__SHIFT 0x4 263 #define DAGB0_RDCLI11__URG_LOW__SHIFT 0x8 264 #define DAGB0_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 265 #define DAGB0_RDCLI11__MAX_BW__SHIFT 0xd 266 #define DAGB0_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 267 #define DAGB0_RDCLI11__MIN_BW__SHIFT 0x16 268 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 269 #define DAGB0_RDCLI11__MAX_OSD__SHIFT 0x1a 270 #define DAGB0_RDCLI11__VIRT_CHAN_MASK 0x00000007L 271 #define DAGB0_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 272 #define DAGB0_RDCLI11__URG_HIGH_MASK 0x000000F0L 273 #define DAGB0_RDCLI11__URG_LOW_MASK 0x00000F00L 274 #define DAGB0_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 275 #define DAGB0_RDCLI11__MAX_BW_MASK 0x001FE000L 276 #define DAGB0_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 277 #define DAGB0_RDCLI11__MIN_BW_MASK 0x01C00000L 278 #define DAGB0_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 279 #define DAGB0_RDCLI11__MAX_OSD_MASK 0xFC000000L 280 //DAGB0_RDCLI12 281 #define DAGB0_RDCLI12__VIRT_CHAN__SHIFT 0x0 282 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 283 #define DAGB0_RDCLI12__URG_HIGH__SHIFT 0x4 284 #define DAGB0_RDCLI12__URG_LOW__SHIFT 0x8 285 #define DAGB0_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 286 #define DAGB0_RDCLI12__MAX_BW__SHIFT 0xd 287 #define DAGB0_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 288 #define DAGB0_RDCLI12__MIN_BW__SHIFT 0x16 289 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 290 #define DAGB0_RDCLI12__MAX_OSD__SHIFT 0x1a 291 #define DAGB0_RDCLI12__VIRT_CHAN_MASK 0x00000007L 292 #define DAGB0_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 293 #define DAGB0_RDCLI12__URG_HIGH_MASK 0x000000F0L 294 #define DAGB0_RDCLI12__URG_LOW_MASK 0x00000F00L 295 #define DAGB0_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 296 #define DAGB0_RDCLI12__MAX_BW_MASK 0x001FE000L 297 #define DAGB0_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 298 #define DAGB0_RDCLI12__MIN_BW_MASK 0x01C00000L 299 #define DAGB0_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 300 #define DAGB0_RDCLI12__MAX_OSD_MASK 0xFC000000L 301 //DAGB0_RDCLI13 302 #define DAGB0_RDCLI13__VIRT_CHAN__SHIFT 0x0 303 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 304 #define DAGB0_RDCLI13__URG_HIGH__SHIFT 0x4 305 #define DAGB0_RDCLI13__URG_LOW__SHIFT 0x8 306 #define DAGB0_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 307 #define DAGB0_RDCLI13__MAX_BW__SHIFT 0xd 308 #define DAGB0_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 309 #define DAGB0_RDCLI13__MIN_BW__SHIFT 0x16 310 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 311 #define DAGB0_RDCLI13__MAX_OSD__SHIFT 0x1a 312 #define DAGB0_RDCLI13__VIRT_CHAN_MASK 0x00000007L 313 #define DAGB0_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 314 #define DAGB0_RDCLI13__URG_HIGH_MASK 0x000000F0L 315 #define DAGB0_RDCLI13__URG_LOW_MASK 0x00000F00L 316 #define DAGB0_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 317 #define DAGB0_RDCLI13__MAX_BW_MASK 0x001FE000L 318 #define DAGB0_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 319 #define DAGB0_RDCLI13__MIN_BW_MASK 0x01C00000L 320 #define DAGB0_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 321 #define DAGB0_RDCLI13__MAX_OSD_MASK 0xFC000000L 322 //DAGB0_RDCLI14 323 #define DAGB0_RDCLI14__VIRT_CHAN__SHIFT 0x0 324 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 325 #define DAGB0_RDCLI14__URG_HIGH__SHIFT 0x4 326 #define DAGB0_RDCLI14__URG_LOW__SHIFT 0x8 327 #define DAGB0_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 328 #define DAGB0_RDCLI14__MAX_BW__SHIFT 0xd 329 #define DAGB0_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 330 #define DAGB0_RDCLI14__MIN_BW__SHIFT 0x16 331 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 332 #define DAGB0_RDCLI14__MAX_OSD__SHIFT 0x1a 333 #define DAGB0_RDCLI14__VIRT_CHAN_MASK 0x00000007L 334 #define DAGB0_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 335 #define DAGB0_RDCLI14__URG_HIGH_MASK 0x000000F0L 336 #define DAGB0_RDCLI14__URG_LOW_MASK 0x00000F00L 337 #define DAGB0_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 338 #define DAGB0_RDCLI14__MAX_BW_MASK 0x001FE000L 339 #define DAGB0_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 340 #define DAGB0_RDCLI14__MIN_BW_MASK 0x01C00000L 341 #define DAGB0_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 342 #define DAGB0_RDCLI14__MAX_OSD_MASK 0xFC000000L 343 //DAGB0_RDCLI15 344 #define DAGB0_RDCLI15__VIRT_CHAN__SHIFT 0x0 345 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 346 #define DAGB0_RDCLI15__URG_HIGH__SHIFT 0x4 347 #define DAGB0_RDCLI15__URG_LOW__SHIFT 0x8 348 #define DAGB0_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 349 #define DAGB0_RDCLI15__MAX_BW__SHIFT 0xd 350 #define DAGB0_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 351 #define DAGB0_RDCLI15__MIN_BW__SHIFT 0x16 352 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 353 #define DAGB0_RDCLI15__MAX_OSD__SHIFT 0x1a 354 #define DAGB0_RDCLI15__VIRT_CHAN_MASK 0x00000007L 355 #define DAGB0_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 356 #define DAGB0_RDCLI15__URG_HIGH_MASK 0x000000F0L 357 #define DAGB0_RDCLI15__URG_LOW_MASK 0x00000F00L 358 #define DAGB0_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 359 #define DAGB0_RDCLI15__MAX_BW_MASK 0x001FE000L 360 #define DAGB0_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 361 #define DAGB0_RDCLI15__MIN_BW_MASK 0x01C00000L 362 #define DAGB0_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 363 #define DAGB0_RDCLI15__MAX_OSD_MASK 0xFC000000L 364 //DAGB0_RD_CNTL 365 #define DAGB0_RD_CNTL__SCLK_FREQ__SHIFT 0x0 366 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 367 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 368 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 369 #define DAGB0_RD_CNTL__IO_LEVEL__SHIFT 0x11 370 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 371 #define DAGB0_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 372 #define DAGB0_RD_CNTL__FIX_JUMP__SHIFT 0x1a 373 #define DAGB0_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 374 #define DAGB0_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 375 #define DAGB0_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 376 #define DAGB0_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 377 #define DAGB0_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 378 #define DAGB0_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 379 #define DAGB0_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 380 #define DAGB0_RD_CNTL__FIX_JUMP_MASK 0x04000000L 381 //DAGB0_RD_GMI_CNTL 382 #define DAGB0_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 383 #define DAGB0_RD_GMI_CNTL__LEVEL__SHIFT 0x6 384 #define DAGB0_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 385 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 386 #define DAGB0_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 387 #define DAGB0_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 388 #define DAGB0_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 389 #define DAGB0_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 390 //DAGB0_RD_ADDR_DAGB 391 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 392 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 393 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 394 #define DAGB0_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 395 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 396 #define DAGB0_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 397 #define DAGB0_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 398 #define DAGB0_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 399 #define DAGB0_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 400 #define DAGB0_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 401 //DAGB0_RD_OUTPUT_DAGB_MAX_BURST 402 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 403 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 404 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 405 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 406 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 407 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 408 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 409 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 410 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 411 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 412 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 413 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 414 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 415 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 416 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 417 #define DAGB0_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 418 //DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER 419 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 420 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 421 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 422 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 423 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 424 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 425 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 426 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 427 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 428 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 429 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 430 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 431 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 432 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 433 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 434 #define DAGB0_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 435 //DAGB0_RD_CGTT_CLK_CTRL 436 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 437 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 438 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 439 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 440 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 441 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 442 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 443 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 444 #define DAGB0_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 445 #define DAGB0_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 446 #define DAGB0_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 447 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 448 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 449 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 450 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 451 #define DAGB0_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 452 //DAGB0_L1TLB_RD_CGTT_CLK_CTRL 453 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 454 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 455 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 456 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 457 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 458 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 459 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 460 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 461 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 462 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 463 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 464 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 465 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 466 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 467 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 468 #define DAGB0_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 469 //DAGB0_ATCVM_RD_CGTT_CLK_CTRL 470 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 471 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 472 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 473 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 474 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 475 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 476 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 477 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 478 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 479 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 480 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 481 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 482 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 483 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 484 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 485 #define DAGB0_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 486 //DAGB0_RD_ADDR_DAGB_MAX_BURST0 487 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 488 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 489 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 490 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 491 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 492 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 493 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 494 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 495 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 496 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 497 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 498 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 499 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 500 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 501 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 502 #define DAGB0_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 503 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER0 504 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 505 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 506 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 507 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 508 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 509 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 510 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 511 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 512 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 513 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 514 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 515 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 516 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 517 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 518 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 519 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 520 //DAGB0_RD_ADDR_DAGB_MAX_BURST1 521 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 522 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 523 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 524 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 525 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 526 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 527 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 528 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 529 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 530 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 531 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 532 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 533 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 534 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 535 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 536 #define DAGB0_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 537 //DAGB0_RD_ADDR_DAGB_LAZY_TIMER1 538 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 539 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 540 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 541 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 542 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 543 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 544 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 545 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 546 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 547 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 548 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 549 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 550 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 551 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 552 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 553 #define DAGB0_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 554 //DAGB0_RD_VC0_CNTL 555 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 556 #define DAGB0_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 557 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 558 #define DAGB0_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 559 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 560 #define DAGB0_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 561 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 562 #define DAGB0_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 563 #define DAGB0_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 564 #define DAGB0_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 565 #define DAGB0_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 566 #define DAGB0_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 567 #define DAGB0_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 568 #define DAGB0_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 569 #define DAGB0_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 570 #define DAGB0_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 571 //DAGB0_RD_VC1_CNTL 572 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 573 #define DAGB0_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 574 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 575 #define DAGB0_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 576 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 577 #define DAGB0_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 578 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 579 #define DAGB0_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 580 #define DAGB0_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 581 #define DAGB0_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 582 #define DAGB0_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 583 #define DAGB0_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 584 #define DAGB0_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 585 #define DAGB0_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 586 #define DAGB0_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 587 #define DAGB0_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 588 //DAGB0_RD_VC2_CNTL 589 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 590 #define DAGB0_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 591 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 592 #define DAGB0_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 593 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 594 #define DAGB0_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 595 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 596 #define DAGB0_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 597 #define DAGB0_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 598 #define DAGB0_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 599 #define DAGB0_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 600 #define DAGB0_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 601 #define DAGB0_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 602 #define DAGB0_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 603 #define DAGB0_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 604 #define DAGB0_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 605 //DAGB0_RD_VC3_CNTL 606 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 607 #define DAGB0_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 608 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 609 #define DAGB0_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 610 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 611 #define DAGB0_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 612 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 613 #define DAGB0_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 614 #define DAGB0_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 615 #define DAGB0_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 616 #define DAGB0_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 617 #define DAGB0_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 618 #define DAGB0_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 619 #define DAGB0_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 620 #define DAGB0_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 621 #define DAGB0_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 622 //DAGB0_RD_VC4_CNTL 623 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 624 #define DAGB0_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 625 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 626 #define DAGB0_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 627 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 628 #define DAGB0_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 629 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 630 #define DAGB0_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 631 #define DAGB0_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 632 #define DAGB0_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 633 #define DAGB0_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 634 #define DAGB0_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 635 #define DAGB0_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 636 #define DAGB0_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 637 #define DAGB0_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 638 #define DAGB0_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 639 //DAGB0_RD_VC5_CNTL 640 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 641 #define DAGB0_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 642 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 643 #define DAGB0_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 644 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 645 #define DAGB0_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 646 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 647 #define DAGB0_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 648 #define DAGB0_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 649 #define DAGB0_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 650 #define DAGB0_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 651 #define DAGB0_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 652 #define DAGB0_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 653 #define DAGB0_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 654 #define DAGB0_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 655 #define DAGB0_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 656 //DAGB0_RD_VC6_CNTL 657 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 658 #define DAGB0_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 659 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 660 #define DAGB0_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 661 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 662 #define DAGB0_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 663 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 664 #define DAGB0_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 665 #define DAGB0_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 666 #define DAGB0_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 667 #define DAGB0_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 668 #define DAGB0_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 669 #define DAGB0_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 670 #define DAGB0_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 671 #define DAGB0_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 672 #define DAGB0_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 673 //DAGB0_RD_VC7_CNTL 674 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 675 #define DAGB0_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 676 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 677 #define DAGB0_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 678 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 679 #define DAGB0_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 680 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 681 #define DAGB0_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 682 #define DAGB0_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 683 #define DAGB0_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 684 #define DAGB0_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 685 #define DAGB0_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 686 #define DAGB0_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 687 #define DAGB0_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 688 #define DAGB0_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 689 #define DAGB0_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 690 //DAGB0_RD_CNTL_MISC 691 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 692 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 693 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 694 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 695 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 696 #define DAGB0_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 697 #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 698 #define DAGB0_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 699 #define DAGB0_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 700 #define DAGB0_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 701 #define DAGB0_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 702 #define DAGB0_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 703 #define DAGB0_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 704 #define DAGB0_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 705 //DAGB0_RD_TLB_CREDIT 706 #define DAGB0_RD_TLB_CREDIT__TLB0__SHIFT 0x0 707 #define DAGB0_RD_TLB_CREDIT__TLB1__SHIFT 0x5 708 #define DAGB0_RD_TLB_CREDIT__TLB2__SHIFT 0xa 709 #define DAGB0_RD_TLB_CREDIT__TLB3__SHIFT 0xf 710 #define DAGB0_RD_TLB_CREDIT__TLB4__SHIFT 0x14 711 #define DAGB0_RD_TLB_CREDIT__TLB5__SHIFT 0x19 712 #define DAGB0_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 713 #define DAGB0_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 714 #define DAGB0_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 715 #define DAGB0_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 716 #define DAGB0_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 717 #define DAGB0_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 718 //DAGB0_RD_RDRET_CREDIT_CNTL 719 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 720 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 721 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc 722 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 723 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 724 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 725 #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 726 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL 727 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L 728 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L 729 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L 730 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L 731 #define DAGB0_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 732 #define DAGB0_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 733 //DAGB0_RD_RDRET_CREDIT_CNTL2 734 #define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 735 #define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 736 #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc 737 #define DAGB0_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL 738 #define DAGB0_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L 739 #define DAGB0_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L 740 //DAGB0_RDCLI_ASK_PENDING 741 #define DAGB0_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 742 #define DAGB0_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 743 //DAGB0_RDCLI_GO_PENDING 744 #define DAGB0_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 745 #define DAGB0_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 746 //DAGB0_RDCLI_GBLSEND_PENDING 747 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 748 #define DAGB0_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 749 //DAGB0_RDCLI_TLB_PENDING 750 #define DAGB0_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 751 #define DAGB0_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 752 //DAGB0_RDCLI_OARB_PENDING 753 #define DAGB0_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 754 #define DAGB0_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 755 //DAGB0_RDCLI_OSD_PENDING 756 #define DAGB0_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 757 #define DAGB0_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 758 //DAGB0_WRCLI0 759 #define DAGB0_WRCLI0__VIRT_CHAN__SHIFT 0x0 760 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 761 #define DAGB0_WRCLI0__URG_HIGH__SHIFT 0x4 762 #define DAGB0_WRCLI0__URG_LOW__SHIFT 0x8 763 #define DAGB0_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 764 #define DAGB0_WRCLI0__MAX_BW__SHIFT 0xd 765 #define DAGB0_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 766 #define DAGB0_WRCLI0__MIN_BW__SHIFT 0x16 767 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 768 #define DAGB0_WRCLI0__MAX_OSD__SHIFT 0x1a 769 #define DAGB0_WRCLI0__VIRT_CHAN_MASK 0x00000007L 770 #define DAGB0_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 771 #define DAGB0_WRCLI0__URG_HIGH_MASK 0x000000F0L 772 #define DAGB0_WRCLI0__URG_LOW_MASK 0x00000F00L 773 #define DAGB0_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 774 #define DAGB0_WRCLI0__MAX_BW_MASK 0x001FE000L 775 #define DAGB0_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 776 #define DAGB0_WRCLI0__MIN_BW_MASK 0x01C00000L 777 #define DAGB0_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 778 #define DAGB0_WRCLI0__MAX_OSD_MASK 0xFC000000L 779 //DAGB0_WRCLI1 780 #define DAGB0_WRCLI1__VIRT_CHAN__SHIFT 0x0 781 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 782 #define DAGB0_WRCLI1__URG_HIGH__SHIFT 0x4 783 #define DAGB0_WRCLI1__URG_LOW__SHIFT 0x8 784 #define DAGB0_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 785 #define DAGB0_WRCLI1__MAX_BW__SHIFT 0xd 786 #define DAGB0_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 787 #define DAGB0_WRCLI1__MIN_BW__SHIFT 0x16 788 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 789 #define DAGB0_WRCLI1__MAX_OSD__SHIFT 0x1a 790 #define DAGB0_WRCLI1__VIRT_CHAN_MASK 0x00000007L 791 #define DAGB0_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 792 #define DAGB0_WRCLI1__URG_HIGH_MASK 0x000000F0L 793 #define DAGB0_WRCLI1__URG_LOW_MASK 0x00000F00L 794 #define DAGB0_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 795 #define DAGB0_WRCLI1__MAX_BW_MASK 0x001FE000L 796 #define DAGB0_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 797 #define DAGB0_WRCLI1__MIN_BW_MASK 0x01C00000L 798 #define DAGB0_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 799 #define DAGB0_WRCLI1__MAX_OSD_MASK 0xFC000000L 800 //DAGB0_WRCLI2 801 #define DAGB0_WRCLI2__VIRT_CHAN__SHIFT 0x0 802 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 803 #define DAGB0_WRCLI2__URG_HIGH__SHIFT 0x4 804 #define DAGB0_WRCLI2__URG_LOW__SHIFT 0x8 805 #define DAGB0_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 806 #define DAGB0_WRCLI2__MAX_BW__SHIFT 0xd 807 #define DAGB0_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 808 #define DAGB0_WRCLI2__MIN_BW__SHIFT 0x16 809 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 810 #define DAGB0_WRCLI2__MAX_OSD__SHIFT 0x1a 811 #define DAGB0_WRCLI2__VIRT_CHAN_MASK 0x00000007L 812 #define DAGB0_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 813 #define DAGB0_WRCLI2__URG_HIGH_MASK 0x000000F0L 814 #define DAGB0_WRCLI2__URG_LOW_MASK 0x00000F00L 815 #define DAGB0_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 816 #define DAGB0_WRCLI2__MAX_BW_MASK 0x001FE000L 817 #define DAGB0_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 818 #define DAGB0_WRCLI2__MIN_BW_MASK 0x01C00000L 819 #define DAGB0_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 820 #define DAGB0_WRCLI2__MAX_OSD_MASK 0xFC000000L 821 //DAGB0_WRCLI3 822 #define DAGB0_WRCLI3__VIRT_CHAN__SHIFT 0x0 823 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 824 #define DAGB0_WRCLI3__URG_HIGH__SHIFT 0x4 825 #define DAGB0_WRCLI3__URG_LOW__SHIFT 0x8 826 #define DAGB0_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 827 #define DAGB0_WRCLI3__MAX_BW__SHIFT 0xd 828 #define DAGB0_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 829 #define DAGB0_WRCLI3__MIN_BW__SHIFT 0x16 830 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 831 #define DAGB0_WRCLI3__MAX_OSD__SHIFT 0x1a 832 #define DAGB0_WRCLI3__VIRT_CHAN_MASK 0x00000007L 833 #define DAGB0_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 834 #define DAGB0_WRCLI3__URG_HIGH_MASK 0x000000F0L 835 #define DAGB0_WRCLI3__URG_LOW_MASK 0x00000F00L 836 #define DAGB0_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 837 #define DAGB0_WRCLI3__MAX_BW_MASK 0x001FE000L 838 #define DAGB0_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 839 #define DAGB0_WRCLI3__MIN_BW_MASK 0x01C00000L 840 #define DAGB0_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 841 #define DAGB0_WRCLI3__MAX_OSD_MASK 0xFC000000L 842 //DAGB0_WRCLI4 843 #define DAGB0_WRCLI4__VIRT_CHAN__SHIFT 0x0 844 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 845 #define DAGB0_WRCLI4__URG_HIGH__SHIFT 0x4 846 #define DAGB0_WRCLI4__URG_LOW__SHIFT 0x8 847 #define DAGB0_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 848 #define DAGB0_WRCLI4__MAX_BW__SHIFT 0xd 849 #define DAGB0_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 850 #define DAGB0_WRCLI4__MIN_BW__SHIFT 0x16 851 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 852 #define DAGB0_WRCLI4__MAX_OSD__SHIFT 0x1a 853 #define DAGB0_WRCLI4__VIRT_CHAN_MASK 0x00000007L 854 #define DAGB0_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 855 #define DAGB0_WRCLI4__URG_HIGH_MASK 0x000000F0L 856 #define DAGB0_WRCLI4__URG_LOW_MASK 0x00000F00L 857 #define DAGB0_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 858 #define DAGB0_WRCLI4__MAX_BW_MASK 0x001FE000L 859 #define DAGB0_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 860 #define DAGB0_WRCLI4__MIN_BW_MASK 0x01C00000L 861 #define DAGB0_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 862 #define DAGB0_WRCLI4__MAX_OSD_MASK 0xFC000000L 863 //DAGB0_WRCLI5 864 #define DAGB0_WRCLI5__VIRT_CHAN__SHIFT 0x0 865 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 866 #define DAGB0_WRCLI5__URG_HIGH__SHIFT 0x4 867 #define DAGB0_WRCLI5__URG_LOW__SHIFT 0x8 868 #define DAGB0_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 869 #define DAGB0_WRCLI5__MAX_BW__SHIFT 0xd 870 #define DAGB0_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 871 #define DAGB0_WRCLI5__MIN_BW__SHIFT 0x16 872 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 873 #define DAGB0_WRCLI5__MAX_OSD__SHIFT 0x1a 874 #define DAGB0_WRCLI5__VIRT_CHAN_MASK 0x00000007L 875 #define DAGB0_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 876 #define DAGB0_WRCLI5__URG_HIGH_MASK 0x000000F0L 877 #define DAGB0_WRCLI5__URG_LOW_MASK 0x00000F00L 878 #define DAGB0_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 879 #define DAGB0_WRCLI5__MAX_BW_MASK 0x001FE000L 880 #define DAGB0_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 881 #define DAGB0_WRCLI5__MIN_BW_MASK 0x01C00000L 882 #define DAGB0_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 883 #define DAGB0_WRCLI5__MAX_OSD_MASK 0xFC000000L 884 //DAGB0_WRCLI6 885 #define DAGB0_WRCLI6__VIRT_CHAN__SHIFT 0x0 886 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 887 #define DAGB0_WRCLI6__URG_HIGH__SHIFT 0x4 888 #define DAGB0_WRCLI6__URG_LOW__SHIFT 0x8 889 #define DAGB0_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 890 #define DAGB0_WRCLI6__MAX_BW__SHIFT 0xd 891 #define DAGB0_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 892 #define DAGB0_WRCLI6__MIN_BW__SHIFT 0x16 893 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 894 #define DAGB0_WRCLI6__MAX_OSD__SHIFT 0x1a 895 #define DAGB0_WRCLI6__VIRT_CHAN_MASK 0x00000007L 896 #define DAGB0_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 897 #define DAGB0_WRCLI6__URG_HIGH_MASK 0x000000F0L 898 #define DAGB0_WRCLI6__URG_LOW_MASK 0x00000F00L 899 #define DAGB0_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 900 #define DAGB0_WRCLI6__MAX_BW_MASK 0x001FE000L 901 #define DAGB0_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 902 #define DAGB0_WRCLI6__MIN_BW_MASK 0x01C00000L 903 #define DAGB0_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 904 #define DAGB0_WRCLI6__MAX_OSD_MASK 0xFC000000L 905 //DAGB0_WRCLI7 906 #define DAGB0_WRCLI7__VIRT_CHAN__SHIFT 0x0 907 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 908 #define DAGB0_WRCLI7__URG_HIGH__SHIFT 0x4 909 #define DAGB0_WRCLI7__URG_LOW__SHIFT 0x8 910 #define DAGB0_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 911 #define DAGB0_WRCLI7__MAX_BW__SHIFT 0xd 912 #define DAGB0_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 913 #define DAGB0_WRCLI7__MIN_BW__SHIFT 0x16 914 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 915 #define DAGB0_WRCLI7__MAX_OSD__SHIFT 0x1a 916 #define DAGB0_WRCLI7__VIRT_CHAN_MASK 0x00000007L 917 #define DAGB0_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 918 #define DAGB0_WRCLI7__URG_HIGH_MASK 0x000000F0L 919 #define DAGB0_WRCLI7__URG_LOW_MASK 0x00000F00L 920 #define DAGB0_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 921 #define DAGB0_WRCLI7__MAX_BW_MASK 0x001FE000L 922 #define DAGB0_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 923 #define DAGB0_WRCLI7__MIN_BW_MASK 0x01C00000L 924 #define DAGB0_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 925 #define DAGB0_WRCLI7__MAX_OSD_MASK 0xFC000000L 926 //DAGB0_WRCLI8 927 #define DAGB0_WRCLI8__VIRT_CHAN__SHIFT 0x0 928 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 929 #define DAGB0_WRCLI8__URG_HIGH__SHIFT 0x4 930 #define DAGB0_WRCLI8__URG_LOW__SHIFT 0x8 931 #define DAGB0_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 932 #define DAGB0_WRCLI8__MAX_BW__SHIFT 0xd 933 #define DAGB0_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 934 #define DAGB0_WRCLI8__MIN_BW__SHIFT 0x16 935 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 936 #define DAGB0_WRCLI8__MAX_OSD__SHIFT 0x1a 937 #define DAGB0_WRCLI8__VIRT_CHAN_MASK 0x00000007L 938 #define DAGB0_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 939 #define DAGB0_WRCLI8__URG_HIGH_MASK 0x000000F0L 940 #define DAGB0_WRCLI8__URG_LOW_MASK 0x00000F00L 941 #define DAGB0_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 942 #define DAGB0_WRCLI8__MAX_BW_MASK 0x001FE000L 943 #define DAGB0_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 944 #define DAGB0_WRCLI8__MIN_BW_MASK 0x01C00000L 945 #define DAGB0_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 946 #define DAGB0_WRCLI8__MAX_OSD_MASK 0xFC000000L 947 //DAGB0_WRCLI9 948 #define DAGB0_WRCLI9__VIRT_CHAN__SHIFT 0x0 949 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 950 #define DAGB0_WRCLI9__URG_HIGH__SHIFT 0x4 951 #define DAGB0_WRCLI9__URG_LOW__SHIFT 0x8 952 #define DAGB0_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 953 #define DAGB0_WRCLI9__MAX_BW__SHIFT 0xd 954 #define DAGB0_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 955 #define DAGB0_WRCLI9__MIN_BW__SHIFT 0x16 956 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 957 #define DAGB0_WRCLI9__MAX_OSD__SHIFT 0x1a 958 #define DAGB0_WRCLI9__VIRT_CHAN_MASK 0x00000007L 959 #define DAGB0_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 960 #define DAGB0_WRCLI9__URG_HIGH_MASK 0x000000F0L 961 #define DAGB0_WRCLI9__URG_LOW_MASK 0x00000F00L 962 #define DAGB0_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 963 #define DAGB0_WRCLI9__MAX_BW_MASK 0x001FE000L 964 #define DAGB0_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 965 #define DAGB0_WRCLI9__MIN_BW_MASK 0x01C00000L 966 #define DAGB0_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 967 #define DAGB0_WRCLI9__MAX_OSD_MASK 0xFC000000L 968 //DAGB0_WRCLI10 969 #define DAGB0_WRCLI10__VIRT_CHAN__SHIFT 0x0 970 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 971 #define DAGB0_WRCLI10__URG_HIGH__SHIFT 0x4 972 #define DAGB0_WRCLI10__URG_LOW__SHIFT 0x8 973 #define DAGB0_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 974 #define DAGB0_WRCLI10__MAX_BW__SHIFT 0xd 975 #define DAGB0_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 976 #define DAGB0_WRCLI10__MIN_BW__SHIFT 0x16 977 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 978 #define DAGB0_WRCLI10__MAX_OSD__SHIFT 0x1a 979 #define DAGB0_WRCLI10__VIRT_CHAN_MASK 0x00000007L 980 #define DAGB0_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 981 #define DAGB0_WRCLI10__URG_HIGH_MASK 0x000000F0L 982 #define DAGB0_WRCLI10__URG_LOW_MASK 0x00000F00L 983 #define DAGB0_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 984 #define DAGB0_WRCLI10__MAX_BW_MASK 0x001FE000L 985 #define DAGB0_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 986 #define DAGB0_WRCLI10__MIN_BW_MASK 0x01C00000L 987 #define DAGB0_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 988 #define DAGB0_WRCLI10__MAX_OSD_MASK 0xFC000000L 989 //DAGB0_WRCLI11 990 #define DAGB0_WRCLI11__VIRT_CHAN__SHIFT 0x0 991 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 992 #define DAGB0_WRCLI11__URG_HIGH__SHIFT 0x4 993 #define DAGB0_WRCLI11__URG_LOW__SHIFT 0x8 994 #define DAGB0_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 995 #define DAGB0_WRCLI11__MAX_BW__SHIFT 0xd 996 #define DAGB0_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 997 #define DAGB0_WRCLI11__MIN_BW__SHIFT 0x16 998 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 999 #define DAGB0_WRCLI11__MAX_OSD__SHIFT 0x1a 1000 #define DAGB0_WRCLI11__VIRT_CHAN_MASK 0x00000007L 1001 #define DAGB0_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 1002 #define DAGB0_WRCLI11__URG_HIGH_MASK 0x000000F0L 1003 #define DAGB0_WRCLI11__URG_LOW_MASK 0x00000F00L 1004 #define DAGB0_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 1005 #define DAGB0_WRCLI11__MAX_BW_MASK 0x001FE000L 1006 #define DAGB0_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 1007 #define DAGB0_WRCLI11__MIN_BW_MASK 0x01C00000L 1008 #define DAGB0_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 1009 #define DAGB0_WRCLI11__MAX_OSD_MASK 0xFC000000L 1010 //DAGB0_WRCLI12 1011 #define DAGB0_WRCLI12__VIRT_CHAN__SHIFT 0x0 1012 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 1013 #define DAGB0_WRCLI12__URG_HIGH__SHIFT 0x4 1014 #define DAGB0_WRCLI12__URG_LOW__SHIFT 0x8 1015 #define DAGB0_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 1016 #define DAGB0_WRCLI12__MAX_BW__SHIFT 0xd 1017 #define DAGB0_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 1018 #define DAGB0_WRCLI12__MIN_BW__SHIFT 0x16 1019 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 1020 #define DAGB0_WRCLI12__MAX_OSD__SHIFT 0x1a 1021 #define DAGB0_WRCLI12__VIRT_CHAN_MASK 0x00000007L 1022 #define DAGB0_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 1023 #define DAGB0_WRCLI12__URG_HIGH_MASK 0x000000F0L 1024 #define DAGB0_WRCLI12__URG_LOW_MASK 0x00000F00L 1025 #define DAGB0_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 1026 #define DAGB0_WRCLI12__MAX_BW_MASK 0x001FE000L 1027 #define DAGB0_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 1028 #define DAGB0_WRCLI12__MIN_BW_MASK 0x01C00000L 1029 #define DAGB0_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 1030 #define DAGB0_WRCLI12__MAX_OSD_MASK 0xFC000000L 1031 //DAGB0_WRCLI13 1032 #define DAGB0_WRCLI13__VIRT_CHAN__SHIFT 0x0 1033 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 1034 #define DAGB0_WRCLI13__URG_HIGH__SHIFT 0x4 1035 #define DAGB0_WRCLI13__URG_LOW__SHIFT 0x8 1036 #define DAGB0_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 1037 #define DAGB0_WRCLI13__MAX_BW__SHIFT 0xd 1038 #define DAGB0_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 1039 #define DAGB0_WRCLI13__MIN_BW__SHIFT 0x16 1040 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 1041 #define DAGB0_WRCLI13__MAX_OSD__SHIFT 0x1a 1042 #define DAGB0_WRCLI13__VIRT_CHAN_MASK 0x00000007L 1043 #define DAGB0_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 1044 #define DAGB0_WRCLI13__URG_HIGH_MASK 0x000000F0L 1045 #define DAGB0_WRCLI13__URG_LOW_MASK 0x00000F00L 1046 #define DAGB0_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 1047 #define DAGB0_WRCLI13__MAX_BW_MASK 0x001FE000L 1048 #define DAGB0_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 1049 #define DAGB0_WRCLI13__MIN_BW_MASK 0x01C00000L 1050 #define DAGB0_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 1051 #define DAGB0_WRCLI13__MAX_OSD_MASK 0xFC000000L 1052 //DAGB0_WRCLI14 1053 #define DAGB0_WRCLI14__VIRT_CHAN__SHIFT 0x0 1054 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 1055 #define DAGB0_WRCLI14__URG_HIGH__SHIFT 0x4 1056 #define DAGB0_WRCLI14__URG_LOW__SHIFT 0x8 1057 #define DAGB0_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 1058 #define DAGB0_WRCLI14__MAX_BW__SHIFT 0xd 1059 #define DAGB0_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 1060 #define DAGB0_WRCLI14__MIN_BW__SHIFT 0x16 1061 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 1062 #define DAGB0_WRCLI14__MAX_OSD__SHIFT 0x1a 1063 #define DAGB0_WRCLI14__VIRT_CHAN_MASK 0x00000007L 1064 #define DAGB0_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 1065 #define DAGB0_WRCLI14__URG_HIGH_MASK 0x000000F0L 1066 #define DAGB0_WRCLI14__URG_LOW_MASK 0x00000F00L 1067 #define DAGB0_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 1068 #define DAGB0_WRCLI14__MAX_BW_MASK 0x001FE000L 1069 #define DAGB0_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 1070 #define DAGB0_WRCLI14__MIN_BW_MASK 0x01C00000L 1071 #define DAGB0_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 1072 #define DAGB0_WRCLI14__MAX_OSD_MASK 0xFC000000L 1073 //DAGB0_WRCLI15 1074 #define DAGB0_WRCLI15__VIRT_CHAN__SHIFT 0x0 1075 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 1076 #define DAGB0_WRCLI15__URG_HIGH__SHIFT 0x4 1077 #define DAGB0_WRCLI15__URG_LOW__SHIFT 0x8 1078 #define DAGB0_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 1079 #define DAGB0_WRCLI15__MAX_BW__SHIFT 0xd 1080 #define DAGB0_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 1081 #define DAGB0_WRCLI15__MIN_BW__SHIFT 0x16 1082 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 1083 #define DAGB0_WRCLI15__MAX_OSD__SHIFT 0x1a 1084 #define DAGB0_WRCLI15__VIRT_CHAN_MASK 0x00000007L 1085 #define DAGB0_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 1086 #define DAGB0_WRCLI15__URG_HIGH_MASK 0x000000F0L 1087 #define DAGB0_WRCLI15__URG_LOW_MASK 0x00000F00L 1088 #define DAGB0_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 1089 #define DAGB0_WRCLI15__MAX_BW_MASK 0x001FE000L 1090 #define DAGB0_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 1091 #define DAGB0_WRCLI15__MIN_BW_MASK 0x01C00000L 1092 #define DAGB0_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 1093 #define DAGB0_WRCLI15__MAX_OSD_MASK 0xFC000000L 1094 //DAGB0_WR_CNTL 1095 #define DAGB0_WR_CNTL__SCLK_FREQ__SHIFT 0x0 1096 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 1097 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 1098 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 1099 #define DAGB0_WR_CNTL__IO_LEVEL__SHIFT 0x11 1100 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 1101 #define DAGB0_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 1102 #define DAGB0_WR_CNTL__FIX_JUMP__SHIFT 0x1a 1103 #define DAGB0_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 1104 #define DAGB0_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 1105 #define DAGB0_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 1106 #define DAGB0_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 1107 #define DAGB0_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 1108 #define DAGB0_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 1109 #define DAGB0_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 1110 #define DAGB0_WR_CNTL__FIX_JUMP_MASK 0x04000000L 1111 //DAGB0_WR_GMI_CNTL 1112 #define DAGB0_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 1113 #define DAGB0_WR_GMI_CNTL__LEVEL__SHIFT 0x6 1114 #define DAGB0_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 1115 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 1116 #define DAGB0_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 1117 #define DAGB0_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 1118 #define DAGB0_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 1119 #define DAGB0_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 1120 //DAGB0_WR_ADDR_DAGB 1121 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 1122 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1123 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1124 #define DAGB0_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 1125 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 1126 #define DAGB0_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 1127 #define DAGB0_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1128 #define DAGB0_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1129 #define DAGB0_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 1130 #define DAGB0_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 1131 //DAGB0_WR_OUTPUT_DAGB_MAX_BURST 1132 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 1133 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 1134 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 1135 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 1136 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 1137 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 1138 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 1139 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 1140 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 1141 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 1142 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 1143 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 1144 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 1145 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 1146 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 1147 #define DAGB0_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 1148 //DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER 1149 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 1150 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 1151 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 1152 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 1153 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 1154 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 1155 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 1156 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 1157 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 1158 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 1159 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 1160 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 1161 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 1162 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 1163 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 1164 #define DAGB0_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 1165 //DAGB0_WR_CGTT_CLK_CTRL 1166 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1167 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1168 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1169 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1170 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1171 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1172 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1173 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1174 #define DAGB0_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1175 #define DAGB0_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1176 #define DAGB0_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1177 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1178 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1179 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1180 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1181 #define DAGB0_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1182 //DAGB0_L1TLB_WR_CGTT_CLK_CTRL 1183 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1184 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1185 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1186 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1187 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1188 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1189 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1190 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1191 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1192 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1193 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1194 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1195 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1196 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1197 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1198 #define DAGB0_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1199 //DAGB0_ATCVM_WR_CGTT_CLK_CTRL 1200 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 1201 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 1202 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 1203 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 1204 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 1205 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 1206 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 1207 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 1208 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 1209 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 1210 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 1211 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 1212 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 1213 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 1214 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 1215 #define DAGB0_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 1216 //DAGB0_WR_ADDR_DAGB_MAX_BURST0 1217 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1218 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1219 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1220 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1221 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1222 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1223 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1224 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1225 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1226 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1227 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1228 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1229 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1230 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1231 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1232 #define DAGB0_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1233 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER0 1234 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1235 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1236 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1237 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1238 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1239 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1240 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1241 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1242 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1243 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1244 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1245 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1246 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1247 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1248 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1249 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1250 //DAGB0_WR_ADDR_DAGB_MAX_BURST1 1251 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1252 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1253 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1254 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1255 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1256 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1257 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1258 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1259 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1260 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1261 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1262 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1263 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1264 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1265 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1266 #define DAGB0_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1267 //DAGB0_WR_ADDR_DAGB_LAZY_TIMER1 1268 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1269 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1270 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1271 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1272 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1273 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1274 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1275 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1276 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1277 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1278 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1279 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1280 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1281 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1282 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1283 #define DAGB0_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1284 //DAGB0_WR_DATA_DAGB 1285 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 1286 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 1287 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 1288 #define DAGB0_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 1289 #define DAGB0_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 1290 #define DAGB0_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 1291 #define DAGB0_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 1292 #define DAGB0_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 1293 //DAGB0_WR_DATA_DAGB_MAX_BURST0 1294 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 1295 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 1296 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 1297 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 1298 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 1299 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 1300 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 1301 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 1302 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 1303 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 1304 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 1305 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 1306 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 1307 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 1308 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 1309 #define DAGB0_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 1310 //DAGB0_WR_DATA_DAGB_LAZY_TIMER0 1311 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 1312 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 1313 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 1314 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 1315 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 1316 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 1317 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 1318 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 1319 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 1320 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 1321 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 1322 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 1323 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 1324 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 1325 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 1326 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 1327 //DAGB0_WR_DATA_DAGB_MAX_BURST1 1328 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 1329 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 1330 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 1331 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 1332 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 1333 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 1334 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 1335 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 1336 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 1337 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 1338 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 1339 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 1340 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 1341 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 1342 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 1343 #define DAGB0_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 1344 //DAGB0_WR_DATA_DAGB_LAZY_TIMER1 1345 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 1346 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 1347 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 1348 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 1349 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 1350 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 1351 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 1352 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 1353 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 1354 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 1355 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 1356 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 1357 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 1358 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 1359 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 1360 #define DAGB0_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 1361 //DAGB0_WR_VC0_CNTL 1362 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 1363 #define DAGB0_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 1364 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1365 #define DAGB0_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 1366 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1367 #define DAGB0_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 1368 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1369 #define DAGB0_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 1370 #define DAGB0_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 1371 #define DAGB0_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 1372 #define DAGB0_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1373 #define DAGB0_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 1374 #define DAGB0_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1375 #define DAGB0_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 1376 #define DAGB0_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1377 #define DAGB0_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 1378 //DAGB0_WR_VC1_CNTL 1379 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 1380 #define DAGB0_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 1381 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1382 #define DAGB0_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 1383 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1384 #define DAGB0_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 1385 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1386 #define DAGB0_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 1387 #define DAGB0_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 1388 #define DAGB0_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 1389 #define DAGB0_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1390 #define DAGB0_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 1391 #define DAGB0_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1392 #define DAGB0_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 1393 #define DAGB0_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1394 #define DAGB0_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 1395 //DAGB0_WR_VC2_CNTL 1396 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 1397 #define DAGB0_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 1398 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1399 #define DAGB0_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 1400 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1401 #define DAGB0_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 1402 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1403 #define DAGB0_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 1404 #define DAGB0_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 1405 #define DAGB0_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 1406 #define DAGB0_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1407 #define DAGB0_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 1408 #define DAGB0_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1409 #define DAGB0_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 1410 #define DAGB0_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1411 #define DAGB0_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 1412 //DAGB0_WR_VC3_CNTL 1413 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 1414 #define DAGB0_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 1415 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1416 #define DAGB0_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 1417 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1418 #define DAGB0_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 1419 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1420 #define DAGB0_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 1421 #define DAGB0_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 1422 #define DAGB0_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 1423 #define DAGB0_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1424 #define DAGB0_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 1425 #define DAGB0_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1426 #define DAGB0_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 1427 #define DAGB0_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1428 #define DAGB0_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 1429 //DAGB0_WR_VC4_CNTL 1430 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 1431 #define DAGB0_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 1432 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1433 #define DAGB0_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 1434 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1435 #define DAGB0_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 1436 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1437 #define DAGB0_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 1438 #define DAGB0_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 1439 #define DAGB0_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 1440 #define DAGB0_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1441 #define DAGB0_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 1442 #define DAGB0_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1443 #define DAGB0_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 1444 #define DAGB0_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1445 #define DAGB0_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 1446 //DAGB0_WR_VC5_CNTL 1447 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 1448 #define DAGB0_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 1449 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1450 #define DAGB0_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 1451 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1452 #define DAGB0_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 1453 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1454 #define DAGB0_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 1455 #define DAGB0_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 1456 #define DAGB0_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 1457 #define DAGB0_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1458 #define DAGB0_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 1459 #define DAGB0_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1460 #define DAGB0_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 1461 #define DAGB0_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1462 #define DAGB0_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 1463 //DAGB0_WR_VC6_CNTL 1464 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 1465 #define DAGB0_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 1466 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1467 #define DAGB0_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 1468 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1469 #define DAGB0_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 1470 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1471 #define DAGB0_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 1472 #define DAGB0_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 1473 #define DAGB0_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 1474 #define DAGB0_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1475 #define DAGB0_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 1476 #define DAGB0_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1477 #define DAGB0_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 1478 #define DAGB0_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1479 #define DAGB0_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 1480 //DAGB0_WR_VC7_CNTL 1481 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 1482 #define DAGB0_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 1483 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 1484 #define DAGB0_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 1485 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 1486 #define DAGB0_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 1487 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 1488 #define DAGB0_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 1489 #define DAGB0_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 1490 #define DAGB0_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 1491 #define DAGB0_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 1492 #define DAGB0_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 1493 #define DAGB0_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 1494 #define DAGB0_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 1495 #define DAGB0_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 1496 #define DAGB0_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 1497 //DAGB0_WR_CNTL_MISC 1498 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 1499 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 1500 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 1501 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 1502 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 1503 #define DAGB0_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 1504 #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 1505 #define DAGB0_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 1506 #define DAGB0_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 1507 #define DAGB0_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 1508 #define DAGB0_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 1509 #define DAGB0_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 1510 #define DAGB0_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 1511 #define DAGB0_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 1512 //DAGB0_WR_TLB_CREDIT 1513 #define DAGB0_WR_TLB_CREDIT__TLB0__SHIFT 0x0 1514 #define DAGB0_WR_TLB_CREDIT__TLB1__SHIFT 0x5 1515 #define DAGB0_WR_TLB_CREDIT__TLB2__SHIFT 0xa 1516 #define DAGB0_WR_TLB_CREDIT__TLB3__SHIFT 0xf 1517 #define DAGB0_WR_TLB_CREDIT__TLB4__SHIFT 0x14 1518 #define DAGB0_WR_TLB_CREDIT__TLB5__SHIFT 0x19 1519 #define DAGB0_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 1520 #define DAGB0_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 1521 #define DAGB0_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 1522 #define DAGB0_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 1523 #define DAGB0_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 1524 #define DAGB0_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 1525 //DAGB0_WR_DATA_CREDIT 1526 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 1527 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 1528 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 1529 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 1530 #define DAGB0_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 1531 #define DAGB0_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 1532 #define DAGB0_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 1533 #define DAGB0_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 1534 //DAGB0_WR_MISC_CREDIT 1535 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 1536 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 1537 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 1538 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 1539 #define DAGB0_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 1540 #define DAGB0_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 1541 #define DAGB0_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 1542 #define DAGB0_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 1543 //DAGB0_WR_OSD_CREDIT_CNTL1 1544 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1545 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 1546 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 1547 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc 1548 #define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 1549 #define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 1550 #define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 1551 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL 1552 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L 1553 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L 1554 #define DAGB0_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L 1555 #define DAGB0_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L 1556 #define DAGB0_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L 1557 #define DAGB0_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L 1558 //DAGB0_WR_OSD_CREDIT_CNTL2 1559 #define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 1560 #define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 1561 #define DAGB0_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL 1562 #define DAGB0_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L 1563 //DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1 1564 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 1565 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 1566 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 1567 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 1568 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 1569 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 1570 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 1571 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 1572 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 1573 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 1574 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 1575 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 1576 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 1577 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 1578 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 1579 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 1580 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 1581 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 1582 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 1583 #define DAGB0_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 1584 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE 1585 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 1586 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 1587 //DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 1588 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 1589 #define DAGB0_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 1590 //DAGB0_WRCLI_ASK_PENDING 1591 #define DAGB0_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 1592 #define DAGB0_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1593 //DAGB0_WRCLI_GO_PENDING 1594 #define DAGB0_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 1595 #define DAGB0_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1596 //DAGB0_WRCLI_GBLSEND_PENDING 1597 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 1598 #define DAGB0_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 1599 //DAGB0_WRCLI_TLB_PENDING 1600 #define DAGB0_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 1601 #define DAGB0_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 1602 //DAGB0_WRCLI_OARB_PENDING 1603 #define DAGB0_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 1604 #define DAGB0_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 1605 //DAGB0_WRCLI_OSD_PENDING 1606 #define DAGB0_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 1607 #define DAGB0_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 1608 //DAGB0_WRCLI_DBUS_ASK_PENDING 1609 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 1610 #define DAGB0_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 1611 //DAGB0_WRCLI_DBUS_GO_PENDING 1612 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 1613 #define DAGB0_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 1614 //DAGB0_DAGB_DLY 1615 #define DAGB0_DAGB_DLY__DLY__SHIFT 0x0 1616 #define DAGB0_DAGB_DLY__CLI__SHIFT 0x8 1617 #define DAGB0_DAGB_DLY__POS__SHIFT 0x10 1618 #define DAGB0_DAGB_DLY__DLY_MASK 0x000000FFL 1619 #define DAGB0_DAGB_DLY__CLI_MASK 0x0000FF00L 1620 #define DAGB0_DAGB_DLY__POS_MASK 0x000F0000L 1621 //DAGB0_CNTL_MISC 1622 #define DAGB0_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 1623 #define DAGB0_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 1624 #define DAGB0_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 1625 #define DAGB0_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 1626 #define DAGB0_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 1627 #define DAGB0_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 1628 #define DAGB0_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 1629 #define DAGB0_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 1630 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 1631 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 1632 #define DAGB0_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 1633 #define DAGB0_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 1634 #define DAGB0_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 1635 #define DAGB0_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 1636 #define DAGB0_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 1637 #define DAGB0_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 1638 #define DAGB0_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 1639 #define DAGB0_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 1640 #define DAGB0_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 1641 #define DAGB0_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 1642 //DAGB0_CNTL_MISC2 1643 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 1644 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 1645 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 1646 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 1647 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 1648 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 1649 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 1650 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 1651 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 1652 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 1653 #define DAGB0_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 1654 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 1655 #define DAGB0_CNTL_MISC2__HDP_CID__SHIFT 0xc 1656 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 1657 #define DAGB0_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 1658 #define DAGB0_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 1659 #define DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 1660 #define DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 1661 #define DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 1662 #define DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 1663 #define DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 1664 #define DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 1665 #define DAGB0_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 1666 #define DAGB0_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 1667 #define DAGB0_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 1668 #define DAGB0_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 1669 #define DAGB0_CNTL_MISC2__HDP_CID_MASK 0x0001F000L 1670 #define DAGB0_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 1671 //DAGB0_FATAL_ERROR_CNTL 1672 #define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 1673 #define DAGB0_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 1674 //DAGB0_FATAL_ERROR_CLEAR 1675 #define DAGB0_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 1676 #define DAGB0_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 1677 //DAGB0_FATAL_ERROR_STATUS0 1678 #define DAGB0_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 1679 #define DAGB0_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 1680 #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 1681 #define DAGB0_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 1682 #define DAGB0_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 1683 #define DAGB0_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 1684 //DAGB0_FATAL_ERROR_STATUS1 1685 #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 1686 #define DAGB0_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 1687 //DAGB0_FATAL_ERROR_STATUS2 1688 #define DAGB0_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 1689 #define DAGB0_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 1690 #define DAGB0_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 1691 #define DAGB0_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 1692 #define DAGB0_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 1693 #define DAGB0_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 1694 #define DAGB0_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 1695 #define DAGB0_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL 1696 #define DAGB0_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L 1697 #define DAGB0_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L 1698 #define DAGB0_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L 1699 #define DAGB0_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L 1700 #define DAGB0_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L 1701 #define DAGB0_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L 1702 //DAGB0_FATAL_ERROR_STATUS3 1703 #define DAGB0_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 1704 #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 1705 #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 1706 #define DAGB0_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 1707 #define DAGB0_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 1708 #define DAGB0_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 1709 #define DAGB0_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 1710 #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 1711 #define DAGB0_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 1712 #define DAGB0_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 1713 #define DAGB0_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 1714 #define DAGB0_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 1715 #define DAGB0_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 1716 #define DAGB0_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 1717 #define DAGB0_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 1718 #define DAGB0_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 1719 #define DAGB0_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 1720 #define DAGB0_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L 1721 //DAGB0_FIFO_EMPTY 1722 #define DAGB0_FIFO_EMPTY__EMPTY__SHIFT 0x0 1723 #define DAGB0_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 1724 //DAGB0_FIFO_FULL 1725 #define DAGB0_FIFO_FULL__FULL__SHIFT 0x0 1726 #define DAGB0_FIFO_FULL__FULL_MASK 0x007FFFFFL 1727 //DAGB0_WR_CREDITS_FULL 1728 #define DAGB0_WR_CREDITS_FULL__FULL__SHIFT 0x0 1729 #define DAGB0_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 1730 //DAGB0_RD_CREDITS_FULL 1731 #define DAGB0_RD_CREDITS_FULL__FULL__SHIFT 0x0 1732 #define DAGB0_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 1733 //DAGB0_PERFCOUNTER_LO 1734 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 1735 #define DAGB0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 1736 //DAGB0_PERFCOUNTER_HI 1737 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 1738 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 1739 #define DAGB0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 1740 #define DAGB0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 1741 //DAGB0_PERFCOUNTER0_CFG 1742 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 1743 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 1744 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 1745 #define DAGB0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 1746 #define DAGB0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 1747 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 1748 #define DAGB0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 1749 #define DAGB0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 1750 #define DAGB0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 1751 #define DAGB0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 1752 //DAGB0_PERFCOUNTER1_CFG 1753 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 1754 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 1755 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 1756 #define DAGB0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 1757 #define DAGB0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 1758 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 1759 #define DAGB0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 1760 #define DAGB0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 1761 #define DAGB0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 1762 #define DAGB0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 1763 //DAGB0_PERFCOUNTER2_CFG 1764 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 1765 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 1766 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 1767 #define DAGB0_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 1768 #define DAGB0_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 1769 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 1770 #define DAGB0_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 1771 #define DAGB0_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 1772 #define DAGB0_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 1773 #define DAGB0_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 1774 //DAGB0_PERFCOUNTER_RSLT_CNTL 1775 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 1776 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 1777 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 1778 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 1779 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 1780 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 1781 #define DAGB0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 1782 #define DAGB0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 1783 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 1784 #define DAGB0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 1785 #define DAGB0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 1786 #define DAGB0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 1787 //DAGB0_L1TLB_REG_RW 1788 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 1789 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 1790 #define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 1791 #define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 1792 #define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 1793 #define DAGB0_L1TLB_REG_RW__RESERVE__SHIFT 0x6 1794 #define DAGB0_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 1795 #define DAGB0_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 1796 #define DAGB0_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L 1797 #define DAGB0_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L 1798 #define DAGB0_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L 1799 #define DAGB0_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L 1800 //DAGB0_RESERVE1 1801 #define DAGB0_RESERVE1__RESERVE__SHIFT 0x0 1802 #define DAGB0_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 1803 //DAGB0_RESERVE2 1804 #define DAGB0_RESERVE2__RESERVE__SHIFT 0x0 1805 #define DAGB0_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 1806 //DAGB0_RESERVE3 1807 #define DAGB0_RESERVE3__RESERVE__SHIFT 0x0 1808 #define DAGB0_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 1809 //DAGB0_RESERVE4 1810 #define DAGB0_RESERVE4__RESERVE__SHIFT 0x0 1811 #define DAGB0_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 1812 1813 1814 // addressBlock: mmhub_dagb_dagbdec1 1815 //DAGB1_RDCLI0 1816 #define DAGB1_RDCLI0__VIRT_CHAN__SHIFT 0x0 1817 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 1818 #define DAGB1_RDCLI0__URG_HIGH__SHIFT 0x4 1819 #define DAGB1_RDCLI0__URG_LOW__SHIFT 0x8 1820 #define DAGB1_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 1821 #define DAGB1_RDCLI0__MAX_BW__SHIFT 0xd 1822 #define DAGB1_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 1823 #define DAGB1_RDCLI0__MIN_BW__SHIFT 0x16 1824 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 1825 #define DAGB1_RDCLI0__MAX_OSD__SHIFT 0x1a 1826 #define DAGB1_RDCLI0__VIRT_CHAN_MASK 0x00000007L 1827 #define DAGB1_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 1828 #define DAGB1_RDCLI0__URG_HIGH_MASK 0x000000F0L 1829 #define DAGB1_RDCLI0__URG_LOW_MASK 0x00000F00L 1830 #define DAGB1_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 1831 #define DAGB1_RDCLI0__MAX_BW_MASK 0x001FE000L 1832 #define DAGB1_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 1833 #define DAGB1_RDCLI0__MIN_BW_MASK 0x01C00000L 1834 #define DAGB1_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 1835 #define DAGB1_RDCLI0__MAX_OSD_MASK 0xFC000000L 1836 //DAGB1_RDCLI1 1837 #define DAGB1_RDCLI1__VIRT_CHAN__SHIFT 0x0 1838 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 1839 #define DAGB1_RDCLI1__URG_HIGH__SHIFT 0x4 1840 #define DAGB1_RDCLI1__URG_LOW__SHIFT 0x8 1841 #define DAGB1_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 1842 #define DAGB1_RDCLI1__MAX_BW__SHIFT 0xd 1843 #define DAGB1_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 1844 #define DAGB1_RDCLI1__MIN_BW__SHIFT 0x16 1845 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 1846 #define DAGB1_RDCLI1__MAX_OSD__SHIFT 0x1a 1847 #define DAGB1_RDCLI1__VIRT_CHAN_MASK 0x00000007L 1848 #define DAGB1_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 1849 #define DAGB1_RDCLI1__URG_HIGH_MASK 0x000000F0L 1850 #define DAGB1_RDCLI1__URG_LOW_MASK 0x00000F00L 1851 #define DAGB1_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 1852 #define DAGB1_RDCLI1__MAX_BW_MASK 0x001FE000L 1853 #define DAGB1_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 1854 #define DAGB1_RDCLI1__MIN_BW_MASK 0x01C00000L 1855 #define DAGB1_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 1856 #define DAGB1_RDCLI1__MAX_OSD_MASK 0xFC000000L 1857 //DAGB1_RDCLI2 1858 #define DAGB1_RDCLI2__VIRT_CHAN__SHIFT 0x0 1859 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 1860 #define DAGB1_RDCLI2__URG_HIGH__SHIFT 0x4 1861 #define DAGB1_RDCLI2__URG_LOW__SHIFT 0x8 1862 #define DAGB1_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 1863 #define DAGB1_RDCLI2__MAX_BW__SHIFT 0xd 1864 #define DAGB1_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 1865 #define DAGB1_RDCLI2__MIN_BW__SHIFT 0x16 1866 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 1867 #define DAGB1_RDCLI2__MAX_OSD__SHIFT 0x1a 1868 #define DAGB1_RDCLI2__VIRT_CHAN_MASK 0x00000007L 1869 #define DAGB1_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 1870 #define DAGB1_RDCLI2__URG_HIGH_MASK 0x000000F0L 1871 #define DAGB1_RDCLI2__URG_LOW_MASK 0x00000F00L 1872 #define DAGB1_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 1873 #define DAGB1_RDCLI2__MAX_BW_MASK 0x001FE000L 1874 #define DAGB1_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 1875 #define DAGB1_RDCLI2__MIN_BW_MASK 0x01C00000L 1876 #define DAGB1_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 1877 #define DAGB1_RDCLI2__MAX_OSD_MASK 0xFC000000L 1878 //DAGB1_RDCLI3 1879 #define DAGB1_RDCLI3__VIRT_CHAN__SHIFT 0x0 1880 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 1881 #define DAGB1_RDCLI3__URG_HIGH__SHIFT 0x4 1882 #define DAGB1_RDCLI3__URG_LOW__SHIFT 0x8 1883 #define DAGB1_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 1884 #define DAGB1_RDCLI3__MAX_BW__SHIFT 0xd 1885 #define DAGB1_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 1886 #define DAGB1_RDCLI3__MIN_BW__SHIFT 0x16 1887 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 1888 #define DAGB1_RDCLI3__MAX_OSD__SHIFT 0x1a 1889 #define DAGB1_RDCLI3__VIRT_CHAN_MASK 0x00000007L 1890 #define DAGB1_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 1891 #define DAGB1_RDCLI3__URG_HIGH_MASK 0x000000F0L 1892 #define DAGB1_RDCLI3__URG_LOW_MASK 0x00000F00L 1893 #define DAGB1_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 1894 #define DAGB1_RDCLI3__MAX_BW_MASK 0x001FE000L 1895 #define DAGB1_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 1896 #define DAGB1_RDCLI3__MIN_BW_MASK 0x01C00000L 1897 #define DAGB1_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 1898 #define DAGB1_RDCLI3__MAX_OSD_MASK 0xFC000000L 1899 //DAGB1_RDCLI4 1900 #define DAGB1_RDCLI4__VIRT_CHAN__SHIFT 0x0 1901 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 1902 #define DAGB1_RDCLI4__URG_HIGH__SHIFT 0x4 1903 #define DAGB1_RDCLI4__URG_LOW__SHIFT 0x8 1904 #define DAGB1_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 1905 #define DAGB1_RDCLI4__MAX_BW__SHIFT 0xd 1906 #define DAGB1_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 1907 #define DAGB1_RDCLI4__MIN_BW__SHIFT 0x16 1908 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 1909 #define DAGB1_RDCLI4__MAX_OSD__SHIFT 0x1a 1910 #define DAGB1_RDCLI4__VIRT_CHAN_MASK 0x00000007L 1911 #define DAGB1_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 1912 #define DAGB1_RDCLI4__URG_HIGH_MASK 0x000000F0L 1913 #define DAGB1_RDCLI4__URG_LOW_MASK 0x00000F00L 1914 #define DAGB1_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 1915 #define DAGB1_RDCLI4__MAX_BW_MASK 0x001FE000L 1916 #define DAGB1_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 1917 #define DAGB1_RDCLI4__MIN_BW_MASK 0x01C00000L 1918 #define DAGB1_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 1919 #define DAGB1_RDCLI4__MAX_OSD_MASK 0xFC000000L 1920 //DAGB1_RDCLI5 1921 #define DAGB1_RDCLI5__VIRT_CHAN__SHIFT 0x0 1922 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 1923 #define DAGB1_RDCLI5__URG_HIGH__SHIFT 0x4 1924 #define DAGB1_RDCLI5__URG_LOW__SHIFT 0x8 1925 #define DAGB1_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 1926 #define DAGB1_RDCLI5__MAX_BW__SHIFT 0xd 1927 #define DAGB1_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 1928 #define DAGB1_RDCLI5__MIN_BW__SHIFT 0x16 1929 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 1930 #define DAGB1_RDCLI5__MAX_OSD__SHIFT 0x1a 1931 #define DAGB1_RDCLI5__VIRT_CHAN_MASK 0x00000007L 1932 #define DAGB1_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 1933 #define DAGB1_RDCLI5__URG_HIGH_MASK 0x000000F0L 1934 #define DAGB1_RDCLI5__URG_LOW_MASK 0x00000F00L 1935 #define DAGB1_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 1936 #define DAGB1_RDCLI5__MAX_BW_MASK 0x001FE000L 1937 #define DAGB1_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 1938 #define DAGB1_RDCLI5__MIN_BW_MASK 0x01C00000L 1939 #define DAGB1_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 1940 #define DAGB1_RDCLI5__MAX_OSD_MASK 0xFC000000L 1941 //DAGB1_RDCLI6 1942 #define DAGB1_RDCLI6__VIRT_CHAN__SHIFT 0x0 1943 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 1944 #define DAGB1_RDCLI6__URG_HIGH__SHIFT 0x4 1945 #define DAGB1_RDCLI6__URG_LOW__SHIFT 0x8 1946 #define DAGB1_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 1947 #define DAGB1_RDCLI6__MAX_BW__SHIFT 0xd 1948 #define DAGB1_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 1949 #define DAGB1_RDCLI6__MIN_BW__SHIFT 0x16 1950 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 1951 #define DAGB1_RDCLI6__MAX_OSD__SHIFT 0x1a 1952 #define DAGB1_RDCLI6__VIRT_CHAN_MASK 0x00000007L 1953 #define DAGB1_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 1954 #define DAGB1_RDCLI6__URG_HIGH_MASK 0x000000F0L 1955 #define DAGB1_RDCLI6__URG_LOW_MASK 0x00000F00L 1956 #define DAGB1_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 1957 #define DAGB1_RDCLI6__MAX_BW_MASK 0x001FE000L 1958 #define DAGB1_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 1959 #define DAGB1_RDCLI6__MIN_BW_MASK 0x01C00000L 1960 #define DAGB1_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 1961 #define DAGB1_RDCLI6__MAX_OSD_MASK 0xFC000000L 1962 //DAGB1_RDCLI7 1963 #define DAGB1_RDCLI7__VIRT_CHAN__SHIFT 0x0 1964 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 1965 #define DAGB1_RDCLI7__URG_HIGH__SHIFT 0x4 1966 #define DAGB1_RDCLI7__URG_LOW__SHIFT 0x8 1967 #define DAGB1_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 1968 #define DAGB1_RDCLI7__MAX_BW__SHIFT 0xd 1969 #define DAGB1_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 1970 #define DAGB1_RDCLI7__MIN_BW__SHIFT 0x16 1971 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 1972 #define DAGB1_RDCLI7__MAX_OSD__SHIFT 0x1a 1973 #define DAGB1_RDCLI7__VIRT_CHAN_MASK 0x00000007L 1974 #define DAGB1_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 1975 #define DAGB1_RDCLI7__URG_HIGH_MASK 0x000000F0L 1976 #define DAGB1_RDCLI7__URG_LOW_MASK 0x00000F00L 1977 #define DAGB1_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 1978 #define DAGB1_RDCLI7__MAX_BW_MASK 0x001FE000L 1979 #define DAGB1_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 1980 #define DAGB1_RDCLI7__MIN_BW_MASK 0x01C00000L 1981 #define DAGB1_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 1982 #define DAGB1_RDCLI7__MAX_OSD_MASK 0xFC000000L 1983 //DAGB1_RDCLI8 1984 #define DAGB1_RDCLI8__VIRT_CHAN__SHIFT 0x0 1985 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 1986 #define DAGB1_RDCLI8__URG_HIGH__SHIFT 0x4 1987 #define DAGB1_RDCLI8__URG_LOW__SHIFT 0x8 1988 #define DAGB1_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 1989 #define DAGB1_RDCLI8__MAX_BW__SHIFT 0xd 1990 #define DAGB1_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 1991 #define DAGB1_RDCLI8__MIN_BW__SHIFT 0x16 1992 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 1993 #define DAGB1_RDCLI8__MAX_OSD__SHIFT 0x1a 1994 #define DAGB1_RDCLI8__VIRT_CHAN_MASK 0x00000007L 1995 #define DAGB1_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 1996 #define DAGB1_RDCLI8__URG_HIGH_MASK 0x000000F0L 1997 #define DAGB1_RDCLI8__URG_LOW_MASK 0x00000F00L 1998 #define DAGB1_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 1999 #define DAGB1_RDCLI8__MAX_BW_MASK 0x001FE000L 2000 #define DAGB1_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2001 #define DAGB1_RDCLI8__MIN_BW_MASK 0x01C00000L 2002 #define DAGB1_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2003 #define DAGB1_RDCLI8__MAX_OSD_MASK 0xFC000000L 2004 //DAGB1_RDCLI9 2005 #define DAGB1_RDCLI9__VIRT_CHAN__SHIFT 0x0 2006 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2007 #define DAGB1_RDCLI9__URG_HIGH__SHIFT 0x4 2008 #define DAGB1_RDCLI9__URG_LOW__SHIFT 0x8 2009 #define DAGB1_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 2010 #define DAGB1_RDCLI9__MAX_BW__SHIFT 0xd 2011 #define DAGB1_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 2012 #define DAGB1_RDCLI9__MIN_BW__SHIFT 0x16 2013 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2014 #define DAGB1_RDCLI9__MAX_OSD__SHIFT 0x1a 2015 #define DAGB1_RDCLI9__VIRT_CHAN_MASK 0x00000007L 2016 #define DAGB1_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2017 #define DAGB1_RDCLI9__URG_HIGH_MASK 0x000000F0L 2018 #define DAGB1_RDCLI9__URG_LOW_MASK 0x00000F00L 2019 #define DAGB1_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2020 #define DAGB1_RDCLI9__MAX_BW_MASK 0x001FE000L 2021 #define DAGB1_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2022 #define DAGB1_RDCLI9__MIN_BW_MASK 0x01C00000L 2023 #define DAGB1_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2024 #define DAGB1_RDCLI9__MAX_OSD_MASK 0xFC000000L 2025 //DAGB1_RDCLI10 2026 #define DAGB1_RDCLI10__VIRT_CHAN__SHIFT 0x0 2027 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2028 #define DAGB1_RDCLI10__URG_HIGH__SHIFT 0x4 2029 #define DAGB1_RDCLI10__URG_LOW__SHIFT 0x8 2030 #define DAGB1_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 2031 #define DAGB1_RDCLI10__MAX_BW__SHIFT 0xd 2032 #define DAGB1_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 2033 #define DAGB1_RDCLI10__MIN_BW__SHIFT 0x16 2034 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2035 #define DAGB1_RDCLI10__MAX_OSD__SHIFT 0x1a 2036 #define DAGB1_RDCLI10__VIRT_CHAN_MASK 0x00000007L 2037 #define DAGB1_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2038 #define DAGB1_RDCLI10__URG_HIGH_MASK 0x000000F0L 2039 #define DAGB1_RDCLI10__URG_LOW_MASK 0x00000F00L 2040 #define DAGB1_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2041 #define DAGB1_RDCLI10__MAX_BW_MASK 0x001FE000L 2042 #define DAGB1_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2043 #define DAGB1_RDCLI10__MIN_BW_MASK 0x01C00000L 2044 #define DAGB1_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2045 #define DAGB1_RDCLI10__MAX_OSD_MASK 0xFC000000L 2046 //DAGB1_RDCLI11 2047 #define DAGB1_RDCLI11__VIRT_CHAN__SHIFT 0x0 2048 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2049 #define DAGB1_RDCLI11__URG_HIGH__SHIFT 0x4 2050 #define DAGB1_RDCLI11__URG_LOW__SHIFT 0x8 2051 #define DAGB1_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 2052 #define DAGB1_RDCLI11__MAX_BW__SHIFT 0xd 2053 #define DAGB1_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 2054 #define DAGB1_RDCLI11__MIN_BW__SHIFT 0x16 2055 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2056 #define DAGB1_RDCLI11__MAX_OSD__SHIFT 0x1a 2057 #define DAGB1_RDCLI11__VIRT_CHAN_MASK 0x00000007L 2058 #define DAGB1_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2059 #define DAGB1_RDCLI11__URG_HIGH_MASK 0x000000F0L 2060 #define DAGB1_RDCLI11__URG_LOW_MASK 0x00000F00L 2061 #define DAGB1_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2062 #define DAGB1_RDCLI11__MAX_BW_MASK 0x001FE000L 2063 #define DAGB1_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2064 #define DAGB1_RDCLI11__MIN_BW_MASK 0x01C00000L 2065 #define DAGB1_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2066 #define DAGB1_RDCLI11__MAX_OSD_MASK 0xFC000000L 2067 //DAGB1_RDCLI12 2068 #define DAGB1_RDCLI12__VIRT_CHAN__SHIFT 0x0 2069 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2070 #define DAGB1_RDCLI12__URG_HIGH__SHIFT 0x4 2071 #define DAGB1_RDCLI12__URG_LOW__SHIFT 0x8 2072 #define DAGB1_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 2073 #define DAGB1_RDCLI12__MAX_BW__SHIFT 0xd 2074 #define DAGB1_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 2075 #define DAGB1_RDCLI12__MIN_BW__SHIFT 0x16 2076 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2077 #define DAGB1_RDCLI12__MAX_OSD__SHIFT 0x1a 2078 #define DAGB1_RDCLI12__VIRT_CHAN_MASK 0x00000007L 2079 #define DAGB1_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2080 #define DAGB1_RDCLI12__URG_HIGH_MASK 0x000000F0L 2081 #define DAGB1_RDCLI12__URG_LOW_MASK 0x00000F00L 2082 #define DAGB1_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2083 #define DAGB1_RDCLI12__MAX_BW_MASK 0x001FE000L 2084 #define DAGB1_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2085 #define DAGB1_RDCLI12__MIN_BW_MASK 0x01C00000L 2086 #define DAGB1_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2087 #define DAGB1_RDCLI12__MAX_OSD_MASK 0xFC000000L 2088 //DAGB1_RDCLI13 2089 #define DAGB1_RDCLI13__VIRT_CHAN__SHIFT 0x0 2090 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2091 #define DAGB1_RDCLI13__URG_HIGH__SHIFT 0x4 2092 #define DAGB1_RDCLI13__URG_LOW__SHIFT 0x8 2093 #define DAGB1_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 2094 #define DAGB1_RDCLI13__MAX_BW__SHIFT 0xd 2095 #define DAGB1_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 2096 #define DAGB1_RDCLI13__MIN_BW__SHIFT 0x16 2097 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2098 #define DAGB1_RDCLI13__MAX_OSD__SHIFT 0x1a 2099 #define DAGB1_RDCLI13__VIRT_CHAN_MASK 0x00000007L 2100 #define DAGB1_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2101 #define DAGB1_RDCLI13__URG_HIGH_MASK 0x000000F0L 2102 #define DAGB1_RDCLI13__URG_LOW_MASK 0x00000F00L 2103 #define DAGB1_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2104 #define DAGB1_RDCLI13__MAX_BW_MASK 0x001FE000L 2105 #define DAGB1_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2106 #define DAGB1_RDCLI13__MIN_BW_MASK 0x01C00000L 2107 #define DAGB1_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2108 #define DAGB1_RDCLI13__MAX_OSD_MASK 0xFC000000L 2109 //DAGB1_RDCLI14 2110 #define DAGB1_RDCLI14__VIRT_CHAN__SHIFT 0x0 2111 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2112 #define DAGB1_RDCLI14__URG_HIGH__SHIFT 0x4 2113 #define DAGB1_RDCLI14__URG_LOW__SHIFT 0x8 2114 #define DAGB1_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 2115 #define DAGB1_RDCLI14__MAX_BW__SHIFT 0xd 2116 #define DAGB1_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 2117 #define DAGB1_RDCLI14__MIN_BW__SHIFT 0x16 2118 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2119 #define DAGB1_RDCLI14__MAX_OSD__SHIFT 0x1a 2120 #define DAGB1_RDCLI14__VIRT_CHAN_MASK 0x00000007L 2121 #define DAGB1_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2122 #define DAGB1_RDCLI14__URG_HIGH_MASK 0x000000F0L 2123 #define DAGB1_RDCLI14__URG_LOW_MASK 0x00000F00L 2124 #define DAGB1_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2125 #define DAGB1_RDCLI14__MAX_BW_MASK 0x001FE000L 2126 #define DAGB1_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2127 #define DAGB1_RDCLI14__MIN_BW_MASK 0x01C00000L 2128 #define DAGB1_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2129 #define DAGB1_RDCLI14__MAX_OSD_MASK 0xFC000000L 2130 //DAGB1_RDCLI15 2131 #define DAGB1_RDCLI15__VIRT_CHAN__SHIFT 0x0 2132 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2133 #define DAGB1_RDCLI15__URG_HIGH__SHIFT 0x4 2134 #define DAGB1_RDCLI15__URG_LOW__SHIFT 0x8 2135 #define DAGB1_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 2136 #define DAGB1_RDCLI15__MAX_BW__SHIFT 0xd 2137 #define DAGB1_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 2138 #define DAGB1_RDCLI15__MIN_BW__SHIFT 0x16 2139 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2140 #define DAGB1_RDCLI15__MAX_OSD__SHIFT 0x1a 2141 #define DAGB1_RDCLI15__VIRT_CHAN_MASK 0x00000007L 2142 #define DAGB1_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2143 #define DAGB1_RDCLI15__URG_HIGH_MASK 0x000000F0L 2144 #define DAGB1_RDCLI15__URG_LOW_MASK 0x00000F00L 2145 #define DAGB1_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2146 #define DAGB1_RDCLI15__MAX_BW_MASK 0x001FE000L 2147 #define DAGB1_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2148 #define DAGB1_RDCLI15__MIN_BW_MASK 0x01C00000L 2149 #define DAGB1_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2150 #define DAGB1_RDCLI15__MAX_OSD_MASK 0xFC000000L 2151 //DAGB1_RD_CNTL 2152 #define DAGB1_RD_CNTL__SCLK_FREQ__SHIFT 0x0 2153 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2154 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2155 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2156 #define DAGB1_RD_CNTL__IO_LEVEL__SHIFT 0x11 2157 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2158 #define DAGB1_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 2159 #define DAGB1_RD_CNTL__FIX_JUMP__SHIFT 0x1a 2160 #define DAGB1_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 2161 #define DAGB1_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2162 #define DAGB1_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2163 #define DAGB1_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2164 #define DAGB1_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 2165 #define DAGB1_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2166 #define DAGB1_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2167 #define DAGB1_RD_CNTL__FIX_JUMP_MASK 0x04000000L 2168 //DAGB1_RD_GMI_CNTL 2169 #define DAGB1_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2170 #define DAGB1_RD_GMI_CNTL__LEVEL__SHIFT 0x6 2171 #define DAGB1_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 2172 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2173 #define DAGB1_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2174 #define DAGB1_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 2175 #define DAGB1_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2176 #define DAGB1_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2177 //DAGB1_RD_ADDR_DAGB 2178 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2179 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2180 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2181 #define DAGB1_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 2182 #define DAGB1_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 2183 #define DAGB1_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2184 #define DAGB1_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2185 #define DAGB1_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2186 #define DAGB1_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2187 #define DAGB1_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 2188 //DAGB1_RD_OUTPUT_DAGB_MAX_BURST 2189 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2190 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2191 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2192 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2193 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2194 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2195 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2196 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2197 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2198 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2199 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2200 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2201 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2202 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2203 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2204 #define DAGB1_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2205 //DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER 2206 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2207 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2208 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2209 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2210 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2211 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2212 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2213 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2214 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2215 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2216 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2217 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2218 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2219 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2220 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2221 #define DAGB1_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2222 //DAGB1_RD_CGTT_CLK_CTRL 2223 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2224 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2225 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2226 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2227 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2228 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2229 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2230 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2231 #define DAGB1_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2232 #define DAGB1_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2233 #define DAGB1_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2234 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2235 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2236 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2237 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2238 #define DAGB1_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2239 //DAGB1_L1TLB_RD_CGTT_CLK_CTRL 2240 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2241 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2242 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2243 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2244 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2245 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2246 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2247 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2248 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2249 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2250 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2251 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2252 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2253 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2254 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2255 #define DAGB1_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2256 //DAGB1_ATCVM_RD_CGTT_CLK_CTRL 2257 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2258 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2259 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2260 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2261 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2262 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2263 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2264 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2265 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2266 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2267 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2268 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2269 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2270 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2271 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2272 #define DAGB1_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2273 //DAGB1_RD_ADDR_DAGB_MAX_BURST0 2274 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 2275 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 2276 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 2277 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 2278 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 2279 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 2280 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 2281 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 2282 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 2283 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 2284 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 2285 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 2286 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 2287 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 2288 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 2289 #define DAGB1_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 2290 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER0 2291 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 2292 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 2293 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 2294 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 2295 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 2296 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 2297 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 2298 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 2299 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 2300 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 2301 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 2302 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 2303 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 2304 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 2305 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 2306 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 2307 //DAGB1_RD_ADDR_DAGB_MAX_BURST1 2308 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 2309 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 2310 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 2311 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 2312 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 2313 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 2314 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 2315 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 2316 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 2317 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 2318 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 2319 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 2320 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 2321 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 2322 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 2323 #define DAGB1_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 2324 //DAGB1_RD_ADDR_DAGB_LAZY_TIMER1 2325 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 2326 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 2327 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 2328 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 2329 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 2330 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 2331 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 2332 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 2333 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 2334 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 2335 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 2336 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 2337 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 2338 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 2339 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 2340 #define DAGB1_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 2341 //DAGB1_RD_VC0_CNTL 2342 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 2343 #define DAGB1_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 2344 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2345 #define DAGB1_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 2346 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2347 #define DAGB1_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 2348 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2349 #define DAGB1_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 2350 #define DAGB1_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 2351 #define DAGB1_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 2352 #define DAGB1_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2353 #define DAGB1_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 2354 #define DAGB1_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2355 #define DAGB1_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 2356 #define DAGB1_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2357 #define DAGB1_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 2358 //DAGB1_RD_VC1_CNTL 2359 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 2360 #define DAGB1_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 2361 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2362 #define DAGB1_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 2363 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2364 #define DAGB1_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 2365 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2366 #define DAGB1_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 2367 #define DAGB1_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 2368 #define DAGB1_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 2369 #define DAGB1_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2370 #define DAGB1_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 2371 #define DAGB1_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2372 #define DAGB1_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 2373 #define DAGB1_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2374 #define DAGB1_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 2375 //DAGB1_RD_VC2_CNTL 2376 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 2377 #define DAGB1_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 2378 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2379 #define DAGB1_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 2380 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2381 #define DAGB1_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 2382 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2383 #define DAGB1_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 2384 #define DAGB1_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 2385 #define DAGB1_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 2386 #define DAGB1_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2387 #define DAGB1_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 2388 #define DAGB1_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2389 #define DAGB1_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 2390 #define DAGB1_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2391 #define DAGB1_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 2392 //DAGB1_RD_VC3_CNTL 2393 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 2394 #define DAGB1_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 2395 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2396 #define DAGB1_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 2397 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2398 #define DAGB1_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 2399 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2400 #define DAGB1_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 2401 #define DAGB1_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 2402 #define DAGB1_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 2403 #define DAGB1_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2404 #define DAGB1_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 2405 #define DAGB1_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2406 #define DAGB1_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 2407 #define DAGB1_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2408 #define DAGB1_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 2409 //DAGB1_RD_VC4_CNTL 2410 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 2411 #define DAGB1_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 2412 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2413 #define DAGB1_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 2414 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2415 #define DAGB1_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 2416 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2417 #define DAGB1_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 2418 #define DAGB1_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 2419 #define DAGB1_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 2420 #define DAGB1_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2421 #define DAGB1_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 2422 #define DAGB1_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2423 #define DAGB1_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 2424 #define DAGB1_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2425 #define DAGB1_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 2426 //DAGB1_RD_VC5_CNTL 2427 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 2428 #define DAGB1_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 2429 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2430 #define DAGB1_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 2431 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2432 #define DAGB1_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 2433 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2434 #define DAGB1_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 2435 #define DAGB1_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 2436 #define DAGB1_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 2437 #define DAGB1_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2438 #define DAGB1_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 2439 #define DAGB1_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2440 #define DAGB1_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 2441 #define DAGB1_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2442 #define DAGB1_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 2443 //DAGB1_RD_VC6_CNTL 2444 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 2445 #define DAGB1_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 2446 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2447 #define DAGB1_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 2448 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2449 #define DAGB1_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 2450 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2451 #define DAGB1_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 2452 #define DAGB1_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 2453 #define DAGB1_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 2454 #define DAGB1_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2455 #define DAGB1_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 2456 #define DAGB1_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2457 #define DAGB1_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 2458 #define DAGB1_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2459 #define DAGB1_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 2460 //DAGB1_RD_VC7_CNTL 2461 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 2462 #define DAGB1_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 2463 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 2464 #define DAGB1_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 2465 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 2466 #define DAGB1_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 2467 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 2468 #define DAGB1_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 2469 #define DAGB1_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 2470 #define DAGB1_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 2471 #define DAGB1_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 2472 #define DAGB1_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 2473 #define DAGB1_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 2474 #define DAGB1_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 2475 #define DAGB1_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 2476 #define DAGB1_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 2477 //DAGB1_RD_CNTL_MISC 2478 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 2479 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 2480 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 2481 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 2482 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 2483 #define DAGB1_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 2484 #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 2485 #define DAGB1_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 2486 #define DAGB1_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 2487 #define DAGB1_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 2488 #define DAGB1_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 2489 #define DAGB1_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 2490 #define DAGB1_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 2491 #define DAGB1_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 2492 //DAGB1_RD_TLB_CREDIT 2493 #define DAGB1_RD_TLB_CREDIT__TLB0__SHIFT 0x0 2494 #define DAGB1_RD_TLB_CREDIT__TLB1__SHIFT 0x5 2495 #define DAGB1_RD_TLB_CREDIT__TLB2__SHIFT 0xa 2496 #define DAGB1_RD_TLB_CREDIT__TLB3__SHIFT 0xf 2497 #define DAGB1_RD_TLB_CREDIT__TLB4__SHIFT 0x14 2498 #define DAGB1_RD_TLB_CREDIT__TLB5__SHIFT 0x19 2499 #define DAGB1_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 2500 #define DAGB1_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 2501 #define DAGB1_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 2502 #define DAGB1_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 2503 #define DAGB1_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 2504 #define DAGB1_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 2505 //DAGB1_RD_RDRET_CREDIT_CNTL 2506 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 2507 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 2508 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc 2509 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 2510 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 2511 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 2512 #define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 2513 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL 2514 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L 2515 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L 2516 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L 2517 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L 2518 #define DAGB1_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 2519 #define DAGB1_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 2520 //DAGB1_RD_RDRET_CREDIT_CNTL2 2521 #define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 2522 #define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 2523 #define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc 2524 #define DAGB1_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL 2525 #define DAGB1_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L 2526 #define DAGB1_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L 2527 //DAGB1_RDCLI_ASK_PENDING 2528 #define DAGB1_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 2529 #define DAGB1_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 2530 //DAGB1_RDCLI_GO_PENDING 2531 #define DAGB1_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 2532 #define DAGB1_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 2533 //DAGB1_RDCLI_GBLSEND_PENDING 2534 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 2535 #define DAGB1_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 2536 //DAGB1_RDCLI_TLB_PENDING 2537 #define DAGB1_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 2538 #define DAGB1_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 2539 //DAGB1_RDCLI_OARB_PENDING 2540 #define DAGB1_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 2541 #define DAGB1_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 2542 //DAGB1_RDCLI_OSD_PENDING 2543 #define DAGB1_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 2544 #define DAGB1_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 2545 //DAGB1_WRCLI0 2546 #define DAGB1_WRCLI0__VIRT_CHAN__SHIFT 0x0 2547 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 2548 #define DAGB1_WRCLI0__URG_HIGH__SHIFT 0x4 2549 #define DAGB1_WRCLI0__URG_LOW__SHIFT 0x8 2550 #define DAGB1_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 2551 #define DAGB1_WRCLI0__MAX_BW__SHIFT 0xd 2552 #define DAGB1_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 2553 #define DAGB1_WRCLI0__MIN_BW__SHIFT 0x16 2554 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 2555 #define DAGB1_WRCLI0__MAX_OSD__SHIFT 0x1a 2556 #define DAGB1_WRCLI0__VIRT_CHAN_MASK 0x00000007L 2557 #define DAGB1_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 2558 #define DAGB1_WRCLI0__URG_HIGH_MASK 0x000000F0L 2559 #define DAGB1_WRCLI0__URG_LOW_MASK 0x00000F00L 2560 #define DAGB1_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 2561 #define DAGB1_WRCLI0__MAX_BW_MASK 0x001FE000L 2562 #define DAGB1_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 2563 #define DAGB1_WRCLI0__MIN_BW_MASK 0x01C00000L 2564 #define DAGB1_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 2565 #define DAGB1_WRCLI0__MAX_OSD_MASK 0xFC000000L 2566 //DAGB1_WRCLI1 2567 #define DAGB1_WRCLI1__VIRT_CHAN__SHIFT 0x0 2568 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 2569 #define DAGB1_WRCLI1__URG_HIGH__SHIFT 0x4 2570 #define DAGB1_WRCLI1__URG_LOW__SHIFT 0x8 2571 #define DAGB1_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 2572 #define DAGB1_WRCLI1__MAX_BW__SHIFT 0xd 2573 #define DAGB1_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 2574 #define DAGB1_WRCLI1__MIN_BW__SHIFT 0x16 2575 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 2576 #define DAGB1_WRCLI1__MAX_OSD__SHIFT 0x1a 2577 #define DAGB1_WRCLI1__VIRT_CHAN_MASK 0x00000007L 2578 #define DAGB1_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 2579 #define DAGB1_WRCLI1__URG_HIGH_MASK 0x000000F0L 2580 #define DAGB1_WRCLI1__URG_LOW_MASK 0x00000F00L 2581 #define DAGB1_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 2582 #define DAGB1_WRCLI1__MAX_BW_MASK 0x001FE000L 2583 #define DAGB1_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 2584 #define DAGB1_WRCLI1__MIN_BW_MASK 0x01C00000L 2585 #define DAGB1_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 2586 #define DAGB1_WRCLI1__MAX_OSD_MASK 0xFC000000L 2587 //DAGB1_WRCLI2 2588 #define DAGB1_WRCLI2__VIRT_CHAN__SHIFT 0x0 2589 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 2590 #define DAGB1_WRCLI2__URG_HIGH__SHIFT 0x4 2591 #define DAGB1_WRCLI2__URG_LOW__SHIFT 0x8 2592 #define DAGB1_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 2593 #define DAGB1_WRCLI2__MAX_BW__SHIFT 0xd 2594 #define DAGB1_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 2595 #define DAGB1_WRCLI2__MIN_BW__SHIFT 0x16 2596 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 2597 #define DAGB1_WRCLI2__MAX_OSD__SHIFT 0x1a 2598 #define DAGB1_WRCLI2__VIRT_CHAN_MASK 0x00000007L 2599 #define DAGB1_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 2600 #define DAGB1_WRCLI2__URG_HIGH_MASK 0x000000F0L 2601 #define DAGB1_WRCLI2__URG_LOW_MASK 0x00000F00L 2602 #define DAGB1_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 2603 #define DAGB1_WRCLI2__MAX_BW_MASK 0x001FE000L 2604 #define DAGB1_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 2605 #define DAGB1_WRCLI2__MIN_BW_MASK 0x01C00000L 2606 #define DAGB1_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 2607 #define DAGB1_WRCLI2__MAX_OSD_MASK 0xFC000000L 2608 //DAGB1_WRCLI3 2609 #define DAGB1_WRCLI3__VIRT_CHAN__SHIFT 0x0 2610 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 2611 #define DAGB1_WRCLI3__URG_HIGH__SHIFT 0x4 2612 #define DAGB1_WRCLI3__URG_LOW__SHIFT 0x8 2613 #define DAGB1_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 2614 #define DAGB1_WRCLI3__MAX_BW__SHIFT 0xd 2615 #define DAGB1_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 2616 #define DAGB1_WRCLI3__MIN_BW__SHIFT 0x16 2617 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 2618 #define DAGB1_WRCLI3__MAX_OSD__SHIFT 0x1a 2619 #define DAGB1_WRCLI3__VIRT_CHAN_MASK 0x00000007L 2620 #define DAGB1_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 2621 #define DAGB1_WRCLI3__URG_HIGH_MASK 0x000000F0L 2622 #define DAGB1_WRCLI3__URG_LOW_MASK 0x00000F00L 2623 #define DAGB1_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 2624 #define DAGB1_WRCLI3__MAX_BW_MASK 0x001FE000L 2625 #define DAGB1_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 2626 #define DAGB1_WRCLI3__MIN_BW_MASK 0x01C00000L 2627 #define DAGB1_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 2628 #define DAGB1_WRCLI3__MAX_OSD_MASK 0xFC000000L 2629 //DAGB1_WRCLI4 2630 #define DAGB1_WRCLI4__VIRT_CHAN__SHIFT 0x0 2631 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 2632 #define DAGB1_WRCLI4__URG_HIGH__SHIFT 0x4 2633 #define DAGB1_WRCLI4__URG_LOW__SHIFT 0x8 2634 #define DAGB1_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 2635 #define DAGB1_WRCLI4__MAX_BW__SHIFT 0xd 2636 #define DAGB1_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 2637 #define DAGB1_WRCLI4__MIN_BW__SHIFT 0x16 2638 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 2639 #define DAGB1_WRCLI4__MAX_OSD__SHIFT 0x1a 2640 #define DAGB1_WRCLI4__VIRT_CHAN_MASK 0x00000007L 2641 #define DAGB1_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 2642 #define DAGB1_WRCLI4__URG_HIGH_MASK 0x000000F0L 2643 #define DAGB1_WRCLI4__URG_LOW_MASK 0x00000F00L 2644 #define DAGB1_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 2645 #define DAGB1_WRCLI4__MAX_BW_MASK 0x001FE000L 2646 #define DAGB1_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 2647 #define DAGB1_WRCLI4__MIN_BW_MASK 0x01C00000L 2648 #define DAGB1_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 2649 #define DAGB1_WRCLI4__MAX_OSD_MASK 0xFC000000L 2650 //DAGB1_WRCLI5 2651 #define DAGB1_WRCLI5__VIRT_CHAN__SHIFT 0x0 2652 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 2653 #define DAGB1_WRCLI5__URG_HIGH__SHIFT 0x4 2654 #define DAGB1_WRCLI5__URG_LOW__SHIFT 0x8 2655 #define DAGB1_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 2656 #define DAGB1_WRCLI5__MAX_BW__SHIFT 0xd 2657 #define DAGB1_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 2658 #define DAGB1_WRCLI5__MIN_BW__SHIFT 0x16 2659 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 2660 #define DAGB1_WRCLI5__MAX_OSD__SHIFT 0x1a 2661 #define DAGB1_WRCLI5__VIRT_CHAN_MASK 0x00000007L 2662 #define DAGB1_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 2663 #define DAGB1_WRCLI5__URG_HIGH_MASK 0x000000F0L 2664 #define DAGB1_WRCLI5__URG_LOW_MASK 0x00000F00L 2665 #define DAGB1_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 2666 #define DAGB1_WRCLI5__MAX_BW_MASK 0x001FE000L 2667 #define DAGB1_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 2668 #define DAGB1_WRCLI5__MIN_BW_MASK 0x01C00000L 2669 #define DAGB1_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 2670 #define DAGB1_WRCLI5__MAX_OSD_MASK 0xFC000000L 2671 //DAGB1_WRCLI6 2672 #define DAGB1_WRCLI6__VIRT_CHAN__SHIFT 0x0 2673 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 2674 #define DAGB1_WRCLI6__URG_HIGH__SHIFT 0x4 2675 #define DAGB1_WRCLI6__URG_LOW__SHIFT 0x8 2676 #define DAGB1_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 2677 #define DAGB1_WRCLI6__MAX_BW__SHIFT 0xd 2678 #define DAGB1_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 2679 #define DAGB1_WRCLI6__MIN_BW__SHIFT 0x16 2680 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 2681 #define DAGB1_WRCLI6__MAX_OSD__SHIFT 0x1a 2682 #define DAGB1_WRCLI6__VIRT_CHAN_MASK 0x00000007L 2683 #define DAGB1_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 2684 #define DAGB1_WRCLI6__URG_HIGH_MASK 0x000000F0L 2685 #define DAGB1_WRCLI6__URG_LOW_MASK 0x00000F00L 2686 #define DAGB1_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 2687 #define DAGB1_WRCLI6__MAX_BW_MASK 0x001FE000L 2688 #define DAGB1_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 2689 #define DAGB1_WRCLI6__MIN_BW_MASK 0x01C00000L 2690 #define DAGB1_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 2691 #define DAGB1_WRCLI6__MAX_OSD_MASK 0xFC000000L 2692 //DAGB1_WRCLI7 2693 #define DAGB1_WRCLI7__VIRT_CHAN__SHIFT 0x0 2694 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 2695 #define DAGB1_WRCLI7__URG_HIGH__SHIFT 0x4 2696 #define DAGB1_WRCLI7__URG_LOW__SHIFT 0x8 2697 #define DAGB1_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 2698 #define DAGB1_WRCLI7__MAX_BW__SHIFT 0xd 2699 #define DAGB1_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 2700 #define DAGB1_WRCLI7__MIN_BW__SHIFT 0x16 2701 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 2702 #define DAGB1_WRCLI7__MAX_OSD__SHIFT 0x1a 2703 #define DAGB1_WRCLI7__VIRT_CHAN_MASK 0x00000007L 2704 #define DAGB1_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 2705 #define DAGB1_WRCLI7__URG_HIGH_MASK 0x000000F0L 2706 #define DAGB1_WRCLI7__URG_LOW_MASK 0x00000F00L 2707 #define DAGB1_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 2708 #define DAGB1_WRCLI7__MAX_BW_MASK 0x001FE000L 2709 #define DAGB1_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 2710 #define DAGB1_WRCLI7__MIN_BW_MASK 0x01C00000L 2711 #define DAGB1_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 2712 #define DAGB1_WRCLI7__MAX_OSD_MASK 0xFC000000L 2713 //DAGB1_WRCLI8 2714 #define DAGB1_WRCLI8__VIRT_CHAN__SHIFT 0x0 2715 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 2716 #define DAGB1_WRCLI8__URG_HIGH__SHIFT 0x4 2717 #define DAGB1_WRCLI8__URG_LOW__SHIFT 0x8 2718 #define DAGB1_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 2719 #define DAGB1_WRCLI8__MAX_BW__SHIFT 0xd 2720 #define DAGB1_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 2721 #define DAGB1_WRCLI8__MIN_BW__SHIFT 0x16 2722 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 2723 #define DAGB1_WRCLI8__MAX_OSD__SHIFT 0x1a 2724 #define DAGB1_WRCLI8__VIRT_CHAN_MASK 0x00000007L 2725 #define DAGB1_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 2726 #define DAGB1_WRCLI8__URG_HIGH_MASK 0x000000F0L 2727 #define DAGB1_WRCLI8__URG_LOW_MASK 0x00000F00L 2728 #define DAGB1_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 2729 #define DAGB1_WRCLI8__MAX_BW_MASK 0x001FE000L 2730 #define DAGB1_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 2731 #define DAGB1_WRCLI8__MIN_BW_MASK 0x01C00000L 2732 #define DAGB1_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 2733 #define DAGB1_WRCLI8__MAX_OSD_MASK 0xFC000000L 2734 //DAGB1_WRCLI9 2735 #define DAGB1_WRCLI9__VIRT_CHAN__SHIFT 0x0 2736 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 2737 #define DAGB1_WRCLI9__URG_HIGH__SHIFT 0x4 2738 #define DAGB1_WRCLI9__URG_LOW__SHIFT 0x8 2739 #define DAGB1_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 2740 #define DAGB1_WRCLI9__MAX_BW__SHIFT 0xd 2741 #define DAGB1_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 2742 #define DAGB1_WRCLI9__MIN_BW__SHIFT 0x16 2743 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 2744 #define DAGB1_WRCLI9__MAX_OSD__SHIFT 0x1a 2745 #define DAGB1_WRCLI9__VIRT_CHAN_MASK 0x00000007L 2746 #define DAGB1_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 2747 #define DAGB1_WRCLI9__URG_HIGH_MASK 0x000000F0L 2748 #define DAGB1_WRCLI9__URG_LOW_MASK 0x00000F00L 2749 #define DAGB1_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 2750 #define DAGB1_WRCLI9__MAX_BW_MASK 0x001FE000L 2751 #define DAGB1_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 2752 #define DAGB1_WRCLI9__MIN_BW_MASK 0x01C00000L 2753 #define DAGB1_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 2754 #define DAGB1_WRCLI9__MAX_OSD_MASK 0xFC000000L 2755 //DAGB1_WRCLI10 2756 #define DAGB1_WRCLI10__VIRT_CHAN__SHIFT 0x0 2757 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 2758 #define DAGB1_WRCLI10__URG_HIGH__SHIFT 0x4 2759 #define DAGB1_WRCLI10__URG_LOW__SHIFT 0x8 2760 #define DAGB1_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 2761 #define DAGB1_WRCLI10__MAX_BW__SHIFT 0xd 2762 #define DAGB1_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 2763 #define DAGB1_WRCLI10__MIN_BW__SHIFT 0x16 2764 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 2765 #define DAGB1_WRCLI10__MAX_OSD__SHIFT 0x1a 2766 #define DAGB1_WRCLI10__VIRT_CHAN_MASK 0x00000007L 2767 #define DAGB1_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 2768 #define DAGB1_WRCLI10__URG_HIGH_MASK 0x000000F0L 2769 #define DAGB1_WRCLI10__URG_LOW_MASK 0x00000F00L 2770 #define DAGB1_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 2771 #define DAGB1_WRCLI10__MAX_BW_MASK 0x001FE000L 2772 #define DAGB1_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 2773 #define DAGB1_WRCLI10__MIN_BW_MASK 0x01C00000L 2774 #define DAGB1_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 2775 #define DAGB1_WRCLI10__MAX_OSD_MASK 0xFC000000L 2776 //DAGB1_WRCLI11 2777 #define DAGB1_WRCLI11__VIRT_CHAN__SHIFT 0x0 2778 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 2779 #define DAGB1_WRCLI11__URG_HIGH__SHIFT 0x4 2780 #define DAGB1_WRCLI11__URG_LOW__SHIFT 0x8 2781 #define DAGB1_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 2782 #define DAGB1_WRCLI11__MAX_BW__SHIFT 0xd 2783 #define DAGB1_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 2784 #define DAGB1_WRCLI11__MIN_BW__SHIFT 0x16 2785 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 2786 #define DAGB1_WRCLI11__MAX_OSD__SHIFT 0x1a 2787 #define DAGB1_WRCLI11__VIRT_CHAN_MASK 0x00000007L 2788 #define DAGB1_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 2789 #define DAGB1_WRCLI11__URG_HIGH_MASK 0x000000F0L 2790 #define DAGB1_WRCLI11__URG_LOW_MASK 0x00000F00L 2791 #define DAGB1_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 2792 #define DAGB1_WRCLI11__MAX_BW_MASK 0x001FE000L 2793 #define DAGB1_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 2794 #define DAGB1_WRCLI11__MIN_BW_MASK 0x01C00000L 2795 #define DAGB1_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 2796 #define DAGB1_WRCLI11__MAX_OSD_MASK 0xFC000000L 2797 //DAGB1_WRCLI12 2798 #define DAGB1_WRCLI12__VIRT_CHAN__SHIFT 0x0 2799 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 2800 #define DAGB1_WRCLI12__URG_HIGH__SHIFT 0x4 2801 #define DAGB1_WRCLI12__URG_LOW__SHIFT 0x8 2802 #define DAGB1_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 2803 #define DAGB1_WRCLI12__MAX_BW__SHIFT 0xd 2804 #define DAGB1_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 2805 #define DAGB1_WRCLI12__MIN_BW__SHIFT 0x16 2806 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 2807 #define DAGB1_WRCLI12__MAX_OSD__SHIFT 0x1a 2808 #define DAGB1_WRCLI12__VIRT_CHAN_MASK 0x00000007L 2809 #define DAGB1_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 2810 #define DAGB1_WRCLI12__URG_HIGH_MASK 0x000000F0L 2811 #define DAGB1_WRCLI12__URG_LOW_MASK 0x00000F00L 2812 #define DAGB1_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 2813 #define DAGB1_WRCLI12__MAX_BW_MASK 0x001FE000L 2814 #define DAGB1_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 2815 #define DAGB1_WRCLI12__MIN_BW_MASK 0x01C00000L 2816 #define DAGB1_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 2817 #define DAGB1_WRCLI12__MAX_OSD_MASK 0xFC000000L 2818 //DAGB1_WRCLI13 2819 #define DAGB1_WRCLI13__VIRT_CHAN__SHIFT 0x0 2820 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 2821 #define DAGB1_WRCLI13__URG_HIGH__SHIFT 0x4 2822 #define DAGB1_WRCLI13__URG_LOW__SHIFT 0x8 2823 #define DAGB1_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 2824 #define DAGB1_WRCLI13__MAX_BW__SHIFT 0xd 2825 #define DAGB1_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 2826 #define DAGB1_WRCLI13__MIN_BW__SHIFT 0x16 2827 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 2828 #define DAGB1_WRCLI13__MAX_OSD__SHIFT 0x1a 2829 #define DAGB1_WRCLI13__VIRT_CHAN_MASK 0x00000007L 2830 #define DAGB1_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 2831 #define DAGB1_WRCLI13__URG_HIGH_MASK 0x000000F0L 2832 #define DAGB1_WRCLI13__URG_LOW_MASK 0x00000F00L 2833 #define DAGB1_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 2834 #define DAGB1_WRCLI13__MAX_BW_MASK 0x001FE000L 2835 #define DAGB1_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 2836 #define DAGB1_WRCLI13__MIN_BW_MASK 0x01C00000L 2837 #define DAGB1_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 2838 #define DAGB1_WRCLI13__MAX_OSD_MASK 0xFC000000L 2839 //DAGB1_WRCLI14 2840 #define DAGB1_WRCLI14__VIRT_CHAN__SHIFT 0x0 2841 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 2842 #define DAGB1_WRCLI14__URG_HIGH__SHIFT 0x4 2843 #define DAGB1_WRCLI14__URG_LOW__SHIFT 0x8 2844 #define DAGB1_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 2845 #define DAGB1_WRCLI14__MAX_BW__SHIFT 0xd 2846 #define DAGB1_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 2847 #define DAGB1_WRCLI14__MIN_BW__SHIFT 0x16 2848 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 2849 #define DAGB1_WRCLI14__MAX_OSD__SHIFT 0x1a 2850 #define DAGB1_WRCLI14__VIRT_CHAN_MASK 0x00000007L 2851 #define DAGB1_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 2852 #define DAGB1_WRCLI14__URG_HIGH_MASK 0x000000F0L 2853 #define DAGB1_WRCLI14__URG_LOW_MASK 0x00000F00L 2854 #define DAGB1_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 2855 #define DAGB1_WRCLI14__MAX_BW_MASK 0x001FE000L 2856 #define DAGB1_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 2857 #define DAGB1_WRCLI14__MIN_BW_MASK 0x01C00000L 2858 #define DAGB1_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 2859 #define DAGB1_WRCLI14__MAX_OSD_MASK 0xFC000000L 2860 //DAGB1_WRCLI15 2861 #define DAGB1_WRCLI15__VIRT_CHAN__SHIFT 0x0 2862 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 2863 #define DAGB1_WRCLI15__URG_HIGH__SHIFT 0x4 2864 #define DAGB1_WRCLI15__URG_LOW__SHIFT 0x8 2865 #define DAGB1_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 2866 #define DAGB1_WRCLI15__MAX_BW__SHIFT 0xd 2867 #define DAGB1_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 2868 #define DAGB1_WRCLI15__MIN_BW__SHIFT 0x16 2869 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 2870 #define DAGB1_WRCLI15__MAX_OSD__SHIFT 0x1a 2871 #define DAGB1_WRCLI15__VIRT_CHAN_MASK 0x00000007L 2872 #define DAGB1_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 2873 #define DAGB1_WRCLI15__URG_HIGH_MASK 0x000000F0L 2874 #define DAGB1_WRCLI15__URG_LOW_MASK 0x00000F00L 2875 #define DAGB1_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 2876 #define DAGB1_WRCLI15__MAX_BW_MASK 0x001FE000L 2877 #define DAGB1_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 2878 #define DAGB1_WRCLI15__MIN_BW_MASK 0x01C00000L 2879 #define DAGB1_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 2880 #define DAGB1_WRCLI15__MAX_OSD_MASK 0xFC000000L 2881 //DAGB1_WR_CNTL 2882 #define DAGB1_WR_CNTL__SCLK_FREQ__SHIFT 0x0 2883 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 2884 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 2885 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 2886 #define DAGB1_WR_CNTL__IO_LEVEL__SHIFT 0x11 2887 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 2888 #define DAGB1_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 2889 #define DAGB1_WR_CNTL__FIX_JUMP__SHIFT 0x1a 2890 #define DAGB1_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 2891 #define DAGB1_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 2892 #define DAGB1_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 2893 #define DAGB1_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 2894 #define DAGB1_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 2895 #define DAGB1_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 2896 #define DAGB1_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 2897 #define DAGB1_WR_CNTL__FIX_JUMP_MASK 0x04000000L 2898 //DAGB1_WR_GMI_CNTL 2899 #define DAGB1_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 2900 #define DAGB1_WR_GMI_CNTL__LEVEL__SHIFT 0x6 2901 #define DAGB1_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 2902 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 2903 #define DAGB1_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 2904 #define DAGB1_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 2905 #define DAGB1_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 2906 #define DAGB1_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 2907 //DAGB1_WR_ADDR_DAGB 2908 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 2909 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 2910 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 2911 #define DAGB1_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 2912 #define DAGB1_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 2913 #define DAGB1_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 2914 #define DAGB1_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 2915 #define DAGB1_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 2916 #define DAGB1_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 2917 #define DAGB1_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 2918 //DAGB1_WR_OUTPUT_DAGB_MAX_BURST 2919 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 2920 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 2921 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 2922 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 2923 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 2924 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 2925 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 2926 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 2927 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 2928 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 2929 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 2930 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 2931 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 2932 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 2933 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 2934 #define DAGB1_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 2935 //DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER 2936 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 2937 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 2938 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 2939 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 2940 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 2941 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 2942 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 2943 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 2944 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 2945 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 2946 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 2947 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 2948 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 2949 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 2950 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 2951 #define DAGB1_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 2952 //DAGB1_WR_CGTT_CLK_CTRL 2953 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2954 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2955 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2956 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2957 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2958 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2959 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2960 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2961 #define DAGB1_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2962 #define DAGB1_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2963 #define DAGB1_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2964 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2965 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2966 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2967 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2968 #define DAGB1_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2969 //DAGB1_L1TLB_WR_CGTT_CLK_CTRL 2970 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2971 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2972 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2973 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2974 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2975 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2976 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2977 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2978 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2979 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2980 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2981 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2982 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 2983 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 2984 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 2985 #define DAGB1_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 2986 //DAGB1_ATCVM_WR_CGTT_CLK_CTRL 2987 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 2988 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 2989 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 2990 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 2991 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 2992 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 2993 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 2994 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 2995 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 2996 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 2997 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 2998 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 2999 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 3000 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 3001 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 3002 #define DAGB1_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 3003 //DAGB1_WR_ADDR_DAGB_MAX_BURST0 3004 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 3005 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 3006 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 3007 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 3008 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 3009 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 3010 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 3011 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 3012 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 3013 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 3014 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 3015 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 3016 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 3017 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 3018 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 3019 #define DAGB1_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 3020 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER0 3021 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 3022 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 3023 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 3024 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 3025 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 3026 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 3027 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 3028 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 3029 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 3030 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 3031 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 3032 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 3033 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 3034 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 3035 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 3036 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 3037 //DAGB1_WR_ADDR_DAGB_MAX_BURST1 3038 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 3039 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 3040 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 3041 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 3042 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 3043 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 3044 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 3045 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 3046 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 3047 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 3048 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 3049 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 3050 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 3051 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 3052 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 3053 #define DAGB1_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 3054 //DAGB1_WR_ADDR_DAGB_LAZY_TIMER1 3055 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 3056 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 3057 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 3058 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 3059 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 3060 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 3061 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 3062 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 3063 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 3064 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 3065 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 3066 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3067 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3068 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3069 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3070 #define DAGB1_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3071 //DAGB1_WR_DATA_DAGB 3072 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 3073 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 3074 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 3075 #define DAGB1_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 3076 #define DAGB1_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 3077 #define DAGB1_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 3078 #define DAGB1_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 3079 #define DAGB1_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 3080 //DAGB1_WR_DATA_DAGB_MAX_BURST0 3081 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 3082 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 3083 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 3084 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 3085 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 3086 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 3087 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 3088 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 3089 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 3090 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 3091 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 3092 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 3093 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 3094 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 3095 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 3096 #define DAGB1_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 3097 //DAGB1_WR_DATA_DAGB_LAZY_TIMER0 3098 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 3099 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 3100 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 3101 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 3102 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 3103 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 3104 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 3105 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 3106 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 3107 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 3108 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 3109 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 3110 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 3111 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 3112 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 3113 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 3114 //DAGB1_WR_DATA_DAGB_MAX_BURST1 3115 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 3116 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 3117 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 3118 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 3119 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 3120 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 3121 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 3122 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 3123 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 3124 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 3125 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 3126 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 3127 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 3128 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 3129 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 3130 #define DAGB1_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 3131 //DAGB1_WR_DATA_DAGB_LAZY_TIMER1 3132 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 3133 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 3134 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 3135 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 3136 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 3137 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 3138 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 3139 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 3140 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 3141 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 3142 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 3143 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 3144 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 3145 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 3146 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 3147 #define DAGB1_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 3148 //DAGB1_WR_VC0_CNTL 3149 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 3150 #define DAGB1_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 3151 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3152 #define DAGB1_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 3153 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3154 #define DAGB1_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 3155 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3156 #define DAGB1_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 3157 #define DAGB1_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 3158 #define DAGB1_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 3159 #define DAGB1_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3160 #define DAGB1_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 3161 #define DAGB1_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3162 #define DAGB1_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 3163 #define DAGB1_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3164 #define DAGB1_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 3165 //DAGB1_WR_VC1_CNTL 3166 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 3167 #define DAGB1_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 3168 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3169 #define DAGB1_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 3170 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3171 #define DAGB1_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 3172 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3173 #define DAGB1_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 3174 #define DAGB1_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 3175 #define DAGB1_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 3176 #define DAGB1_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3177 #define DAGB1_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 3178 #define DAGB1_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3179 #define DAGB1_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 3180 #define DAGB1_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3181 #define DAGB1_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 3182 //DAGB1_WR_VC2_CNTL 3183 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 3184 #define DAGB1_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 3185 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3186 #define DAGB1_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 3187 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3188 #define DAGB1_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 3189 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3190 #define DAGB1_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 3191 #define DAGB1_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 3192 #define DAGB1_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 3193 #define DAGB1_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3194 #define DAGB1_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 3195 #define DAGB1_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3196 #define DAGB1_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 3197 #define DAGB1_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3198 #define DAGB1_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 3199 //DAGB1_WR_VC3_CNTL 3200 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 3201 #define DAGB1_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 3202 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3203 #define DAGB1_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 3204 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3205 #define DAGB1_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 3206 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3207 #define DAGB1_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 3208 #define DAGB1_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 3209 #define DAGB1_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 3210 #define DAGB1_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3211 #define DAGB1_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 3212 #define DAGB1_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3213 #define DAGB1_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 3214 #define DAGB1_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3215 #define DAGB1_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 3216 //DAGB1_WR_VC4_CNTL 3217 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 3218 #define DAGB1_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 3219 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3220 #define DAGB1_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 3221 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3222 #define DAGB1_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 3223 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3224 #define DAGB1_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 3225 #define DAGB1_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 3226 #define DAGB1_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 3227 #define DAGB1_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3228 #define DAGB1_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 3229 #define DAGB1_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3230 #define DAGB1_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 3231 #define DAGB1_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3232 #define DAGB1_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 3233 //DAGB1_WR_VC5_CNTL 3234 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 3235 #define DAGB1_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 3236 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3237 #define DAGB1_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 3238 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3239 #define DAGB1_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 3240 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3241 #define DAGB1_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 3242 #define DAGB1_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 3243 #define DAGB1_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 3244 #define DAGB1_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3245 #define DAGB1_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 3246 #define DAGB1_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3247 #define DAGB1_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 3248 #define DAGB1_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3249 #define DAGB1_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 3250 //DAGB1_WR_VC6_CNTL 3251 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 3252 #define DAGB1_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 3253 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3254 #define DAGB1_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 3255 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3256 #define DAGB1_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 3257 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3258 #define DAGB1_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 3259 #define DAGB1_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 3260 #define DAGB1_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 3261 #define DAGB1_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3262 #define DAGB1_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 3263 #define DAGB1_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3264 #define DAGB1_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 3265 #define DAGB1_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3266 #define DAGB1_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 3267 //DAGB1_WR_VC7_CNTL 3268 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 3269 #define DAGB1_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 3270 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 3271 #define DAGB1_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 3272 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 3273 #define DAGB1_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 3274 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 3275 #define DAGB1_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 3276 #define DAGB1_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 3277 #define DAGB1_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 3278 #define DAGB1_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 3279 #define DAGB1_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 3280 #define DAGB1_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 3281 #define DAGB1_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 3282 #define DAGB1_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 3283 #define DAGB1_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 3284 //DAGB1_WR_CNTL_MISC 3285 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 3286 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 3287 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 3288 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 3289 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 3290 #define DAGB1_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 3291 #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 3292 #define DAGB1_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 3293 #define DAGB1_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 3294 #define DAGB1_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 3295 #define DAGB1_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 3296 #define DAGB1_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 3297 #define DAGB1_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 3298 #define DAGB1_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 3299 //DAGB1_WR_TLB_CREDIT 3300 #define DAGB1_WR_TLB_CREDIT__TLB0__SHIFT 0x0 3301 #define DAGB1_WR_TLB_CREDIT__TLB1__SHIFT 0x5 3302 #define DAGB1_WR_TLB_CREDIT__TLB2__SHIFT 0xa 3303 #define DAGB1_WR_TLB_CREDIT__TLB3__SHIFT 0xf 3304 #define DAGB1_WR_TLB_CREDIT__TLB4__SHIFT 0x14 3305 #define DAGB1_WR_TLB_CREDIT__TLB5__SHIFT 0x19 3306 #define DAGB1_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 3307 #define DAGB1_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 3308 #define DAGB1_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 3309 #define DAGB1_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 3310 #define DAGB1_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 3311 #define DAGB1_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 3312 //DAGB1_WR_DATA_CREDIT 3313 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 3314 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 3315 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 3316 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 3317 #define DAGB1_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 3318 #define DAGB1_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 3319 #define DAGB1_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 3320 #define DAGB1_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 3321 //DAGB1_WR_MISC_CREDIT 3322 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 3323 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 3324 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 3325 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 3326 #define DAGB1_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 3327 #define DAGB1_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 3328 #define DAGB1_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 3329 #define DAGB1_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 3330 //DAGB1_WR_OSD_CREDIT_CNTL1 3331 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 3332 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 3333 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 3334 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc 3335 #define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 3336 #define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 3337 #define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 3338 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL 3339 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L 3340 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L 3341 #define DAGB1_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L 3342 #define DAGB1_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L 3343 #define DAGB1_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L 3344 #define DAGB1_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L 3345 //DAGB1_WR_OSD_CREDIT_CNTL2 3346 #define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 3347 #define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 3348 #define DAGB1_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL 3349 #define DAGB1_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L 3350 //DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1 3351 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 3352 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 3353 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 3354 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 3355 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 3356 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 3357 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 3358 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 3359 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 3360 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 3361 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 3362 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 3363 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 3364 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 3365 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 3366 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 3367 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 3368 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 3369 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 3370 #define DAGB1_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 3371 //DAGB1_WRCLI_GPU_SNOOP_OVERRIDE 3372 #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 3373 #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 3374 //DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 3375 #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 3376 #define DAGB1_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 3377 //DAGB1_WRCLI_ASK_PENDING 3378 #define DAGB1_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 3379 #define DAGB1_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3380 //DAGB1_WRCLI_GO_PENDING 3381 #define DAGB1_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 3382 #define DAGB1_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3383 //DAGB1_WRCLI_GBLSEND_PENDING 3384 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 3385 #define DAGB1_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 3386 //DAGB1_WRCLI_TLB_PENDING 3387 #define DAGB1_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 3388 #define DAGB1_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 3389 //DAGB1_WRCLI_OARB_PENDING 3390 #define DAGB1_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 3391 #define DAGB1_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 3392 //DAGB1_WRCLI_OSD_PENDING 3393 #define DAGB1_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 3394 #define DAGB1_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 3395 //DAGB1_WRCLI_DBUS_ASK_PENDING 3396 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 3397 #define DAGB1_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 3398 //DAGB1_WRCLI_DBUS_GO_PENDING 3399 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 3400 #define DAGB1_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 3401 //DAGB1_DAGB_DLY 3402 #define DAGB1_DAGB_DLY__DLY__SHIFT 0x0 3403 #define DAGB1_DAGB_DLY__CLI__SHIFT 0x8 3404 #define DAGB1_DAGB_DLY__POS__SHIFT 0x10 3405 #define DAGB1_DAGB_DLY__DLY_MASK 0x000000FFL 3406 #define DAGB1_DAGB_DLY__CLI_MASK 0x0000FF00L 3407 #define DAGB1_DAGB_DLY__POS_MASK 0x000F0000L 3408 //DAGB1_CNTL_MISC 3409 #define DAGB1_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 3410 #define DAGB1_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 3411 #define DAGB1_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 3412 #define DAGB1_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 3413 #define DAGB1_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 3414 #define DAGB1_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 3415 #define DAGB1_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 3416 #define DAGB1_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 3417 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 3418 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 3419 #define DAGB1_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 3420 #define DAGB1_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 3421 #define DAGB1_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 3422 #define DAGB1_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 3423 #define DAGB1_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 3424 #define DAGB1_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 3425 #define DAGB1_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 3426 #define DAGB1_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 3427 #define DAGB1_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 3428 #define DAGB1_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 3429 //DAGB1_CNTL_MISC2 3430 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 3431 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 3432 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 3433 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 3434 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 3435 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 3436 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 3437 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 3438 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 3439 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 3440 #define DAGB1_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 3441 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 3442 #define DAGB1_CNTL_MISC2__HDP_CID__SHIFT 0xc 3443 #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 3444 #define DAGB1_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 3445 #define DAGB1_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 3446 #define DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 3447 #define DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 3448 #define DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 3449 #define DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 3450 #define DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 3451 #define DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 3452 #define DAGB1_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 3453 #define DAGB1_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 3454 #define DAGB1_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 3455 #define DAGB1_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 3456 #define DAGB1_CNTL_MISC2__HDP_CID_MASK 0x0001F000L 3457 #define DAGB1_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 3458 //DAGB1_FATAL_ERROR_CNTL 3459 #define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 3460 #define DAGB1_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 3461 //DAGB1_FATAL_ERROR_CLEAR 3462 #define DAGB1_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 3463 #define DAGB1_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 3464 //DAGB1_FATAL_ERROR_STATUS0 3465 #define DAGB1_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 3466 #define DAGB1_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 3467 #define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 3468 #define DAGB1_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 3469 #define DAGB1_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 3470 #define DAGB1_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 3471 //DAGB1_FATAL_ERROR_STATUS1 3472 #define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 3473 #define DAGB1_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 3474 //DAGB1_FATAL_ERROR_STATUS2 3475 #define DAGB1_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 3476 #define DAGB1_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 3477 #define DAGB1_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 3478 #define DAGB1_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 3479 #define DAGB1_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 3480 #define DAGB1_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 3481 #define DAGB1_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 3482 #define DAGB1_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL 3483 #define DAGB1_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L 3484 #define DAGB1_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L 3485 #define DAGB1_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L 3486 #define DAGB1_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L 3487 #define DAGB1_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L 3488 #define DAGB1_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L 3489 //DAGB1_FATAL_ERROR_STATUS3 3490 #define DAGB1_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 3491 #define DAGB1_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 3492 #define DAGB1_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 3493 #define DAGB1_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 3494 #define DAGB1_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 3495 #define DAGB1_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 3496 #define DAGB1_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 3497 #define DAGB1_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 3498 #define DAGB1_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 3499 #define DAGB1_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 3500 #define DAGB1_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 3501 #define DAGB1_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 3502 #define DAGB1_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 3503 #define DAGB1_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 3504 #define DAGB1_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 3505 #define DAGB1_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 3506 #define DAGB1_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 3507 #define DAGB1_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L 3508 //DAGB1_FIFO_EMPTY 3509 #define DAGB1_FIFO_EMPTY__EMPTY__SHIFT 0x0 3510 #define DAGB1_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 3511 //DAGB1_FIFO_FULL 3512 #define DAGB1_FIFO_FULL__FULL__SHIFT 0x0 3513 #define DAGB1_FIFO_FULL__FULL_MASK 0x007FFFFFL 3514 //DAGB1_WR_CREDITS_FULL 3515 #define DAGB1_WR_CREDITS_FULL__FULL__SHIFT 0x0 3516 #define DAGB1_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 3517 //DAGB1_RD_CREDITS_FULL 3518 #define DAGB1_RD_CREDITS_FULL__FULL__SHIFT 0x0 3519 #define DAGB1_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 3520 //DAGB1_PERFCOUNTER_LO 3521 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 3522 #define DAGB1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 3523 //DAGB1_PERFCOUNTER_HI 3524 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 3525 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 3526 #define DAGB1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 3527 #define DAGB1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 3528 //DAGB1_PERFCOUNTER0_CFG 3529 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 3530 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 3531 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 3532 #define DAGB1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 3533 #define DAGB1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 3534 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 3535 #define DAGB1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 3536 #define DAGB1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 3537 #define DAGB1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 3538 #define DAGB1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 3539 //DAGB1_PERFCOUNTER1_CFG 3540 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 3541 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 3542 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 3543 #define DAGB1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 3544 #define DAGB1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 3545 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 3546 #define DAGB1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 3547 #define DAGB1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 3548 #define DAGB1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 3549 #define DAGB1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 3550 //DAGB1_PERFCOUNTER2_CFG 3551 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 3552 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 3553 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 3554 #define DAGB1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 3555 #define DAGB1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 3556 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 3557 #define DAGB1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 3558 #define DAGB1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 3559 #define DAGB1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 3560 #define DAGB1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 3561 //DAGB1_PERFCOUNTER_RSLT_CNTL 3562 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 3563 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 3564 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 3565 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 3566 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 3567 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 3568 #define DAGB1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 3569 #define DAGB1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 3570 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 3571 #define DAGB1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 3572 #define DAGB1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 3573 #define DAGB1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 3574 //DAGB1_L1TLB_REG_RW 3575 #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 3576 #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 3577 #define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 3578 #define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 3579 #define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 3580 #define DAGB1_L1TLB_REG_RW__RESERVE__SHIFT 0x6 3581 #define DAGB1_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 3582 #define DAGB1_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 3583 #define DAGB1_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L 3584 #define DAGB1_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L 3585 #define DAGB1_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L 3586 #define DAGB1_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L 3587 //DAGB1_RESERVE1 3588 #define DAGB1_RESERVE1__RESERVE__SHIFT 0x0 3589 #define DAGB1_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 3590 //DAGB1_RESERVE2 3591 #define DAGB1_RESERVE2__RESERVE__SHIFT 0x0 3592 #define DAGB1_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 3593 //DAGB1_RESERVE3 3594 #define DAGB1_RESERVE3__RESERVE__SHIFT 0x0 3595 #define DAGB1_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 3596 //DAGB1_RESERVE4 3597 #define DAGB1_RESERVE4__RESERVE__SHIFT 0x0 3598 #define DAGB1_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 3599 3600 3601 // addressBlock: mmhub_dagb_dagbdec2 3602 //DAGB2_RDCLI0 3603 #define DAGB2_RDCLI0__VIRT_CHAN__SHIFT 0x0 3604 #define DAGB2_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 3605 #define DAGB2_RDCLI0__URG_HIGH__SHIFT 0x4 3606 #define DAGB2_RDCLI0__URG_LOW__SHIFT 0x8 3607 #define DAGB2_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 3608 #define DAGB2_RDCLI0__MAX_BW__SHIFT 0xd 3609 #define DAGB2_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 3610 #define DAGB2_RDCLI0__MIN_BW__SHIFT 0x16 3611 #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 3612 #define DAGB2_RDCLI0__MAX_OSD__SHIFT 0x1a 3613 #define DAGB2_RDCLI0__VIRT_CHAN_MASK 0x00000007L 3614 #define DAGB2_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 3615 #define DAGB2_RDCLI0__URG_HIGH_MASK 0x000000F0L 3616 #define DAGB2_RDCLI0__URG_LOW_MASK 0x00000F00L 3617 #define DAGB2_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 3618 #define DAGB2_RDCLI0__MAX_BW_MASK 0x001FE000L 3619 #define DAGB2_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 3620 #define DAGB2_RDCLI0__MIN_BW_MASK 0x01C00000L 3621 #define DAGB2_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 3622 #define DAGB2_RDCLI0__MAX_OSD_MASK 0xFC000000L 3623 //DAGB2_RDCLI1 3624 #define DAGB2_RDCLI1__VIRT_CHAN__SHIFT 0x0 3625 #define DAGB2_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 3626 #define DAGB2_RDCLI1__URG_HIGH__SHIFT 0x4 3627 #define DAGB2_RDCLI1__URG_LOW__SHIFT 0x8 3628 #define DAGB2_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 3629 #define DAGB2_RDCLI1__MAX_BW__SHIFT 0xd 3630 #define DAGB2_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 3631 #define DAGB2_RDCLI1__MIN_BW__SHIFT 0x16 3632 #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 3633 #define DAGB2_RDCLI1__MAX_OSD__SHIFT 0x1a 3634 #define DAGB2_RDCLI1__VIRT_CHAN_MASK 0x00000007L 3635 #define DAGB2_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 3636 #define DAGB2_RDCLI1__URG_HIGH_MASK 0x000000F0L 3637 #define DAGB2_RDCLI1__URG_LOW_MASK 0x00000F00L 3638 #define DAGB2_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 3639 #define DAGB2_RDCLI1__MAX_BW_MASK 0x001FE000L 3640 #define DAGB2_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 3641 #define DAGB2_RDCLI1__MIN_BW_MASK 0x01C00000L 3642 #define DAGB2_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 3643 #define DAGB2_RDCLI1__MAX_OSD_MASK 0xFC000000L 3644 //DAGB2_RDCLI2 3645 #define DAGB2_RDCLI2__VIRT_CHAN__SHIFT 0x0 3646 #define DAGB2_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 3647 #define DAGB2_RDCLI2__URG_HIGH__SHIFT 0x4 3648 #define DAGB2_RDCLI2__URG_LOW__SHIFT 0x8 3649 #define DAGB2_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 3650 #define DAGB2_RDCLI2__MAX_BW__SHIFT 0xd 3651 #define DAGB2_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 3652 #define DAGB2_RDCLI2__MIN_BW__SHIFT 0x16 3653 #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 3654 #define DAGB2_RDCLI2__MAX_OSD__SHIFT 0x1a 3655 #define DAGB2_RDCLI2__VIRT_CHAN_MASK 0x00000007L 3656 #define DAGB2_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 3657 #define DAGB2_RDCLI2__URG_HIGH_MASK 0x000000F0L 3658 #define DAGB2_RDCLI2__URG_LOW_MASK 0x00000F00L 3659 #define DAGB2_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 3660 #define DAGB2_RDCLI2__MAX_BW_MASK 0x001FE000L 3661 #define DAGB2_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 3662 #define DAGB2_RDCLI2__MIN_BW_MASK 0x01C00000L 3663 #define DAGB2_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 3664 #define DAGB2_RDCLI2__MAX_OSD_MASK 0xFC000000L 3665 //DAGB2_RDCLI3 3666 #define DAGB2_RDCLI3__VIRT_CHAN__SHIFT 0x0 3667 #define DAGB2_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 3668 #define DAGB2_RDCLI3__URG_HIGH__SHIFT 0x4 3669 #define DAGB2_RDCLI3__URG_LOW__SHIFT 0x8 3670 #define DAGB2_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 3671 #define DAGB2_RDCLI3__MAX_BW__SHIFT 0xd 3672 #define DAGB2_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 3673 #define DAGB2_RDCLI3__MIN_BW__SHIFT 0x16 3674 #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 3675 #define DAGB2_RDCLI3__MAX_OSD__SHIFT 0x1a 3676 #define DAGB2_RDCLI3__VIRT_CHAN_MASK 0x00000007L 3677 #define DAGB2_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 3678 #define DAGB2_RDCLI3__URG_HIGH_MASK 0x000000F0L 3679 #define DAGB2_RDCLI3__URG_LOW_MASK 0x00000F00L 3680 #define DAGB2_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 3681 #define DAGB2_RDCLI3__MAX_BW_MASK 0x001FE000L 3682 #define DAGB2_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 3683 #define DAGB2_RDCLI3__MIN_BW_MASK 0x01C00000L 3684 #define DAGB2_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 3685 #define DAGB2_RDCLI3__MAX_OSD_MASK 0xFC000000L 3686 //DAGB2_RDCLI4 3687 #define DAGB2_RDCLI4__VIRT_CHAN__SHIFT 0x0 3688 #define DAGB2_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 3689 #define DAGB2_RDCLI4__URG_HIGH__SHIFT 0x4 3690 #define DAGB2_RDCLI4__URG_LOW__SHIFT 0x8 3691 #define DAGB2_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 3692 #define DAGB2_RDCLI4__MAX_BW__SHIFT 0xd 3693 #define DAGB2_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 3694 #define DAGB2_RDCLI4__MIN_BW__SHIFT 0x16 3695 #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 3696 #define DAGB2_RDCLI4__MAX_OSD__SHIFT 0x1a 3697 #define DAGB2_RDCLI4__VIRT_CHAN_MASK 0x00000007L 3698 #define DAGB2_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 3699 #define DAGB2_RDCLI4__URG_HIGH_MASK 0x000000F0L 3700 #define DAGB2_RDCLI4__URG_LOW_MASK 0x00000F00L 3701 #define DAGB2_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 3702 #define DAGB2_RDCLI4__MAX_BW_MASK 0x001FE000L 3703 #define DAGB2_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 3704 #define DAGB2_RDCLI4__MIN_BW_MASK 0x01C00000L 3705 #define DAGB2_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 3706 #define DAGB2_RDCLI4__MAX_OSD_MASK 0xFC000000L 3707 //DAGB2_RDCLI5 3708 #define DAGB2_RDCLI5__VIRT_CHAN__SHIFT 0x0 3709 #define DAGB2_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 3710 #define DAGB2_RDCLI5__URG_HIGH__SHIFT 0x4 3711 #define DAGB2_RDCLI5__URG_LOW__SHIFT 0x8 3712 #define DAGB2_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 3713 #define DAGB2_RDCLI5__MAX_BW__SHIFT 0xd 3714 #define DAGB2_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 3715 #define DAGB2_RDCLI5__MIN_BW__SHIFT 0x16 3716 #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 3717 #define DAGB2_RDCLI5__MAX_OSD__SHIFT 0x1a 3718 #define DAGB2_RDCLI5__VIRT_CHAN_MASK 0x00000007L 3719 #define DAGB2_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 3720 #define DAGB2_RDCLI5__URG_HIGH_MASK 0x000000F0L 3721 #define DAGB2_RDCLI5__URG_LOW_MASK 0x00000F00L 3722 #define DAGB2_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 3723 #define DAGB2_RDCLI5__MAX_BW_MASK 0x001FE000L 3724 #define DAGB2_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 3725 #define DAGB2_RDCLI5__MIN_BW_MASK 0x01C00000L 3726 #define DAGB2_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 3727 #define DAGB2_RDCLI5__MAX_OSD_MASK 0xFC000000L 3728 //DAGB2_RDCLI6 3729 #define DAGB2_RDCLI6__VIRT_CHAN__SHIFT 0x0 3730 #define DAGB2_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 3731 #define DAGB2_RDCLI6__URG_HIGH__SHIFT 0x4 3732 #define DAGB2_RDCLI6__URG_LOW__SHIFT 0x8 3733 #define DAGB2_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 3734 #define DAGB2_RDCLI6__MAX_BW__SHIFT 0xd 3735 #define DAGB2_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 3736 #define DAGB2_RDCLI6__MIN_BW__SHIFT 0x16 3737 #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 3738 #define DAGB2_RDCLI6__MAX_OSD__SHIFT 0x1a 3739 #define DAGB2_RDCLI6__VIRT_CHAN_MASK 0x00000007L 3740 #define DAGB2_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 3741 #define DAGB2_RDCLI6__URG_HIGH_MASK 0x000000F0L 3742 #define DAGB2_RDCLI6__URG_LOW_MASK 0x00000F00L 3743 #define DAGB2_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 3744 #define DAGB2_RDCLI6__MAX_BW_MASK 0x001FE000L 3745 #define DAGB2_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 3746 #define DAGB2_RDCLI6__MIN_BW_MASK 0x01C00000L 3747 #define DAGB2_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 3748 #define DAGB2_RDCLI6__MAX_OSD_MASK 0xFC000000L 3749 //DAGB2_RDCLI7 3750 #define DAGB2_RDCLI7__VIRT_CHAN__SHIFT 0x0 3751 #define DAGB2_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 3752 #define DAGB2_RDCLI7__URG_HIGH__SHIFT 0x4 3753 #define DAGB2_RDCLI7__URG_LOW__SHIFT 0x8 3754 #define DAGB2_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 3755 #define DAGB2_RDCLI7__MAX_BW__SHIFT 0xd 3756 #define DAGB2_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 3757 #define DAGB2_RDCLI7__MIN_BW__SHIFT 0x16 3758 #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 3759 #define DAGB2_RDCLI7__MAX_OSD__SHIFT 0x1a 3760 #define DAGB2_RDCLI7__VIRT_CHAN_MASK 0x00000007L 3761 #define DAGB2_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 3762 #define DAGB2_RDCLI7__URG_HIGH_MASK 0x000000F0L 3763 #define DAGB2_RDCLI7__URG_LOW_MASK 0x00000F00L 3764 #define DAGB2_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 3765 #define DAGB2_RDCLI7__MAX_BW_MASK 0x001FE000L 3766 #define DAGB2_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 3767 #define DAGB2_RDCLI7__MIN_BW_MASK 0x01C00000L 3768 #define DAGB2_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 3769 #define DAGB2_RDCLI7__MAX_OSD_MASK 0xFC000000L 3770 //DAGB2_RDCLI8 3771 #define DAGB2_RDCLI8__VIRT_CHAN__SHIFT 0x0 3772 #define DAGB2_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 3773 #define DAGB2_RDCLI8__URG_HIGH__SHIFT 0x4 3774 #define DAGB2_RDCLI8__URG_LOW__SHIFT 0x8 3775 #define DAGB2_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 3776 #define DAGB2_RDCLI8__MAX_BW__SHIFT 0xd 3777 #define DAGB2_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 3778 #define DAGB2_RDCLI8__MIN_BW__SHIFT 0x16 3779 #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 3780 #define DAGB2_RDCLI8__MAX_OSD__SHIFT 0x1a 3781 #define DAGB2_RDCLI8__VIRT_CHAN_MASK 0x00000007L 3782 #define DAGB2_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 3783 #define DAGB2_RDCLI8__URG_HIGH_MASK 0x000000F0L 3784 #define DAGB2_RDCLI8__URG_LOW_MASK 0x00000F00L 3785 #define DAGB2_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 3786 #define DAGB2_RDCLI8__MAX_BW_MASK 0x001FE000L 3787 #define DAGB2_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 3788 #define DAGB2_RDCLI8__MIN_BW_MASK 0x01C00000L 3789 #define DAGB2_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 3790 #define DAGB2_RDCLI8__MAX_OSD_MASK 0xFC000000L 3791 //DAGB2_RDCLI9 3792 #define DAGB2_RDCLI9__VIRT_CHAN__SHIFT 0x0 3793 #define DAGB2_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 3794 #define DAGB2_RDCLI9__URG_HIGH__SHIFT 0x4 3795 #define DAGB2_RDCLI9__URG_LOW__SHIFT 0x8 3796 #define DAGB2_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 3797 #define DAGB2_RDCLI9__MAX_BW__SHIFT 0xd 3798 #define DAGB2_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 3799 #define DAGB2_RDCLI9__MIN_BW__SHIFT 0x16 3800 #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 3801 #define DAGB2_RDCLI9__MAX_OSD__SHIFT 0x1a 3802 #define DAGB2_RDCLI9__VIRT_CHAN_MASK 0x00000007L 3803 #define DAGB2_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 3804 #define DAGB2_RDCLI9__URG_HIGH_MASK 0x000000F0L 3805 #define DAGB2_RDCLI9__URG_LOW_MASK 0x00000F00L 3806 #define DAGB2_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 3807 #define DAGB2_RDCLI9__MAX_BW_MASK 0x001FE000L 3808 #define DAGB2_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 3809 #define DAGB2_RDCLI9__MIN_BW_MASK 0x01C00000L 3810 #define DAGB2_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 3811 #define DAGB2_RDCLI9__MAX_OSD_MASK 0xFC000000L 3812 //DAGB2_RDCLI10 3813 #define DAGB2_RDCLI10__VIRT_CHAN__SHIFT 0x0 3814 #define DAGB2_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 3815 #define DAGB2_RDCLI10__URG_HIGH__SHIFT 0x4 3816 #define DAGB2_RDCLI10__URG_LOW__SHIFT 0x8 3817 #define DAGB2_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 3818 #define DAGB2_RDCLI10__MAX_BW__SHIFT 0xd 3819 #define DAGB2_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 3820 #define DAGB2_RDCLI10__MIN_BW__SHIFT 0x16 3821 #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 3822 #define DAGB2_RDCLI10__MAX_OSD__SHIFT 0x1a 3823 #define DAGB2_RDCLI10__VIRT_CHAN_MASK 0x00000007L 3824 #define DAGB2_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 3825 #define DAGB2_RDCLI10__URG_HIGH_MASK 0x000000F0L 3826 #define DAGB2_RDCLI10__URG_LOW_MASK 0x00000F00L 3827 #define DAGB2_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 3828 #define DAGB2_RDCLI10__MAX_BW_MASK 0x001FE000L 3829 #define DAGB2_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 3830 #define DAGB2_RDCLI10__MIN_BW_MASK 0x01C00000L 3831 #define DAGB2_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 3832 #define DAGB2_RDCLI10__MAX_OSD_MASK 0xFC000000L 3833 //DAGB2_RDCLI11 3834 #define DAGB2_RDCLI11__VIRT_CHAN__SHIFT 0x0 3835 #define DAGB2_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 3836 #define DAGB2_RDCLI11__URG_HIGH__SHIFT 0x4 3837 #define DAGB2_RDCLI11__URG_LOW__SHIFT 0x8 3838 #define DAGB2_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 3839 #define DAGB2_RDCLI11__MAX_BW__SHIFT 0xd 3840 #define DAGB2_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 3841 #define DAGB2_RDCLI11__MIN_BW__SHIFT 0x16 3842 #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 3843 #define DAGB2_RDCLI11__MAX_OSD__SHIFT 0x1a 3844 #define DAGB2_RDCLI11__VIRT_CHAN_MASK 0x00000007L 3845 #define DAGB2_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 3846 #define DAGB2_RDCLI11__URG_HIGH_MASK 0x000000F0L 3847 #define DAGB2_RDCLI11__URG_LOW_MASK 0x00000F00L 3848 #define DAGB2_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 3849 #define DAGB2_RDCLI11__MAX_BW_MASK 0x001FE000L 3850 #define DAGB2_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 3851 #define DAGB2_RDCLI11__MIN_BW_MASK 0x01C00000L 3852 #define DAGB2_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 3853 #define DAGB2_RDCLI11__MAX_OSD_MASK 0xFC000000L 3854 //DAGB2_RDCLI12 3855 #define DAGB2_RDCLI12__VIRT_CHAN__SHIFT 0x0 3856 #define DAGB2_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 3857 #define DAGB2_RDCLI12__URG_HIGH__SHIFT 0x4 3858 #define DAGB2_RDCLI12__URG_LOW__SHIFT 0x8 3859 #define DAGB2_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 3860 #define DAGB2_RDCLI12__MAX_BW__SHIFT 0xd 3861 #define DAGB2_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 3862 #define DAGB2_RDCLI12__MIN_BW__SHIFT 0x16 3863 #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 3864 #define DAGB2_RDCLI12__MAX_OSD__SHIFT 0x1a 3865 #define DAGB2_RDCLI12__VIRT_CHAN_MASK 0x00000007L 3866 #define DAGB2_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 3867 #define DAGB2_RDCLI12__URG_HIGH_MASK 0x000000F0L 3868 #define DAGB2_RDCLI12__URG_LOW_MASK 0x00000F00L 3869 #define DAGB2_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 3870 #define DAGB2_RDCLI12__MAX_BW_MASK 0x001FE000L 3871 #define DAGB2_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 3872 #define DAGB2_RDCLI12__MIN_BW_MASK 0x01C00000L 3873 #define DAGB2_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 3874 #define DAGB2_RDCLI12__MAX_OSD_MASK 0xFC000000L 3875 //DAGB2_RDCLI13 3876 #define DAGB2_RDCLI13__VIRT_CHAN__SHIFT 0x0 3877 #define DAGB2_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 3878 #define DAGB2_RDCLI13__URG_HIGH__SHIFT 0x4 3879 #define DAGB2_RDCLI13__URG_LOW__SHIFT 0x8 3880 #define DAGB2_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 3881 #define DAGB2_RDCLI13__MAX_BW__SHIFT 0xd 3882 #define DAGB2_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 3883 #define DAGB2_RDCLI13__MIN_BW__SHIFT 0x16 3884 #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 3885 #define DAGB2_RDCLI13__MAX_OSD__SHIFT 0x1a 3886 #define DAGB2_RDCLI13__VIRT_CHAN_MASK 0x00000007L 3887 #define DAGB2_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 3888 #define DAGB2_RDCLI13__URG_HIGH_MASK 0x000000F0L 3889 #define DAGB2_RDCLI13__URG_LOW_MASK 0x00000F00L 3890 #define DAGB2_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 3891 #define DAGB2_RDCLI13__MAX_BW_MASK 0x001FE000L 3892 #define DAGB2_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 3893 #define DAGB2_RDCLI13__MIN_BW_MASK 0x01C00000L 3894 #define DAGB2_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 3895 #define DAGB2_RDCLI13__MAX_OSD_MASK 0xFC000000L 3896 //DAGB2_RDCLI14 3897 #define DAGB2_RDCLI14__VIRT_CHAN__SHIFT 0x0 3898 #define DAGB2_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 3899 #define DAGB2_RDCLI14__URG_HIGH__SHIFT 0x4 3900 #define DAGB2_RDCLI14__URG_LOW__SHIFT 0x8 3901 #define DAGB2_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 3902 #define DAGB2_RDCLI14__MAX_BW__SHIFT 0xd 3903 #define DAGB2_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 3904 #define DAGB2_RDCLI14__MIN_BW__SHIFT 0x16 3905 #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 3906 #define DAGB2_RDCLI14__MAX_OSD__SHIFT 0x1a 3907 #define DAGB2_RDCLI14__VIRT_CHAN_MASK 0x00000007L 3908 #define DAGB2_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 3909 #define DAGB2_RDCLI14__URG_HIGH_MASK 0x000000F0L 3910 #define DAGB2_RDCLI14__URG_LOW_MASK 0x00000F00L 3911 #define DAGB2_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 3912 #define DAGB2_RDCLI14__MAX_BW_MASK 0x001FE000L 3913 #define DAGB2_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 3914 #define DAGB2_RDCLI14__MIN_BW_MASK 0x01C00000L 3915 #define DAGB2_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 3916 #define DAGB2_RDCLI14__MAX_OSD_MASK 0xFC000000L 3917 //DAGB2_RDCLI15 3918 #define DAGB2_RDCLI15__VIRT_CHAN__SHIFT 0x0 3919 #define DAGB2_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 3920 #define DAGB2_RDCLI15__URG_HIGH__SHIFT 0x4 3921 #define DAGB2_RDCLI15__URG_LOW__SHIFT 0x8 3922 #define DAGB2_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 3923 #define DAGB2_RDCLI15__MAX_BW__SHIFT 0xd 3924 #define DAGB2_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 3925 #define DAGB2_RDCLI15__MIN_BW__SHIFT 0x16 3926 #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 3927 #define DAGB2_RDCLI15__MAX_OSD__SHIFT 0x1a 3928 #define DAGB2_RDCLI15__VIRT_CHAN_MASK 0x00000007L 3929 #define DAGB2_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 3930 #define DAGB2_RDCLI15__URG_HIGH_MASK 0x000000F0L 3931 #define DAGB2_RDCLI15__URG_LOW_MASK 0x00000F00L 3932 #define DAGB2_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 3933 #define DAGB2_RDCLI15__MAX_BW_MASK 0x001FE000L 3934 #define DAGB2_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 3935 #define DAGB2_RDCLI15__MIN_BW_MASK 0x01C00000L 3936 #define DAGB2_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 3937 #define DAGB2_RDCLI15__MAX_OSD_MASK 0xFC000000L 3938 //DAGB2_RD_CNTL 3939 #define DAGB2_RD_CNTL__SCLK_FREQ__SHIFT 0x0 3940 #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 3941 #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 3942 #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 3943 #define DAGB2_RD_CNTL__IO_LEVEL__SHIFT 0x11 3944 #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 3945 #define DAGB2_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 3946 #define DAGB2_RD_CNTL__FIX_JUMP__SHIFT 0x1a 3947 #define DAGB2_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 3948 #define DAGB2_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 3949 #define DAGB2_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 3950 #define DAGB2_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 3951 #define DAGB2_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 3952 #define DAGB2_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 3953 #define DAGB2_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 3954 #define DAGB2_RD_CNTL__FIX_JUMP_MASK 0x04000000L 3955 //DAGB2_RD_GMI_CNTL 3956 #define DAGB2_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 3957 #define DAGB2_RD_GMI_CNTL__LEVEL__SHIFT 0x6 3958 #define DAGB2_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 3959 #define DAGB2_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 3960 #define DAGB2_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 3961 #define DAGB2_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 3962 #define DAGB2_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 3963 #define DAGB2_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 3964 //DAGB2_RD_ADDR_DAGB 3965 #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 3966 #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 3967 #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 3968 #define DAGB2_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 3969 #define DAGB2_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 3970 #define DAGB2_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 3971 #define DAGB2_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 3972 #define DAGB2_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 3973 #define DAGB2_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 3974 #define DAGB2_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 3975 //DAGB2_RD_OUTPUT_DAGB_MAX_BURST 3976 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 3977 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 3978 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 3979 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 3980 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 3981 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 3982 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 3983 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 3984 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 3985 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 3986 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 3987 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 3988 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 3989 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 3990 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 3991 #define DAGB2_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 3992 //DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER 3993 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 3994 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 3995 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 3996 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 3997 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 3998 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 3999 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 4000 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 4001 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 4002 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 4003 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 4004 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 4005 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 4006 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 4007 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 4008 #define DAGB2_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 4009 //DAGB2_RD_CGTT_CLK_CTRL 4010 #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4011 #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4012 #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4013 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4014 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4015 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4016 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4017 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4018 #define DAGB2_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4019 #define DAGB2_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4020 #define DAGB2_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4021 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4022 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4023 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4024 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4025 #define DAGB2_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4026 //DAGB2_L1TLB_RD_CGTT_CLK_CTRL 4027 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4028 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4029 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4030 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4031 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4032 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4033 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4034 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4035 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4036 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4037 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4038 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4039 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4040 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4041 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4042 #define DAGB2_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4043 //DAGB2_ATCVM_RD_CGTT_CLK_CTRL 4044 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4045 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4046 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4047 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4048 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4049 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4050 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4051 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4052 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4053 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4054 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4055 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4056 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4057 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4058 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4059 #define DAGB2_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4060 //DAGB2_RD_ADDR_DAGB_MAX_BURST0 4061 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 4062 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 4063 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 4064 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 4065 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 4066 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 4067 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 4068 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 4069 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 4070 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 4071 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 4072 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 4073 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 4074 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 4075 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 4076 #define DAGB2_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 4077 //DAGB2_RD_ADDR_DAGB_LAZY_TIMER0 4078 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 4079 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 4080 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 4081 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 4082 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 4083 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 4084 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 4085 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 4086 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 4087 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 4088 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 4089 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 4090 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 4091 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 4092 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 4093 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 4094 //DAGB2_RD_ADDR_DAGB_MAX_BURST1 4095 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 4096 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 4097 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 4098 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 4099 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 4100 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 4101 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 4102 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 4103 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 4104 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 4105 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 4106 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 4107 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 4108 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 4109 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 4110 #define DAGB2_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 4111 //DAGB2_RD_ADDR_DAGB_LAZY_TIMER1 4112 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 4113 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 4114 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 4115 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 4116 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 4117 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 4118 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 4119 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 4120 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 4121 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 4122 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 4123 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 4124 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 4125 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 4126 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 4127 #define DAGB2_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 4128 //DAGB2_RD_VC0_CNTL 4129 #define DAGB2_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 4130 #define DAGB2_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 4131 #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4132 #define DAGB2_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 4133 #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4134 #define DAGB2_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 4135 #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4136 #define DAGB2_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 4137 #define DAGB2_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 4138 #define DAGB2_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 4139 #define DAGB2_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4140 #define DAGB2_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 4141 #define DAGB2_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4142 #define DAGB2_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 4143 #define DAGB2_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4144 #define DAGB2_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 4145 //DAGB2_RD_VC1_CNTL 4146 #define DAGB2_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 4147 #define DAGB2_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 4148 #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4149 #define DAGB2_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 4150 #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4151 #define DAGB2_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 4152 #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4153 #define DAGB2_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 4154 #define DAGB2_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 4155 #define DAGB2_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 4156 #define DAGB2_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4157 #define DAGB2_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 4158 #define DAGB2_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4159 #define DAGB2_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 4160 #define DAGB2_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4161 #define DAGB2_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 4162 //DAGB2_RD_VC2_CNTL 4163 #define DAGB2_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 4164 #define DAGB2_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 4165 #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4166 #define DAGB2_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 4167 #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4168 #define DAGB2_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 4169 #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4170 #define DAGB2_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 4171 #define DAGB2_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 4172 #define DAGB2_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 4173 #define DAGB2_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4174 #define DAGB2_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 4175 #define DAGB2_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4176 #define DAGB2_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 4177 #define DAGB2_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4178 #define DAGB2_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 4179 //DAGB2_RD_VC3_CNTL 4180 #define DAGB2_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 4181 #define DAGB2_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 4182 #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4183 #define DAGB2_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 4184 #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4185 #define DAGB2_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 4186 #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4187 #define DAGB2_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 4188 #define DAGB2_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 4189 #define DAGB2_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 4190 #define DAGB2_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4191 #define DAGB2_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 4192 #define DAGB2_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4193 #define DAGB2_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 4194 #define DAGB2_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4195 #define DAGB2_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 4196 //DAGB2_RD_VC4_CNTL 4197 #define DAGB2_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 4198 #define DAGB2_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 4199 #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4200 #define DAGB2_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 4201 #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4202 #define DAGB2_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 4203 #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4204 #define DAGB2_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 4205 #define DAGB2_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 4206 #define DAGB2_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 4207 #define DAGB2_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4208 #define DAGB2_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 4209 #define DAGB2_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4210 #define DAGB2_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 4211 #define DAGB2_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4212 #define DAGB2_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 4213 //DAGB2_RD_VC5_CNTL 4214 #define DAGB2_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 4215 #define DAGB2_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 4216 #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4217 #define DAGB2_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 4218 #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4219 #define DAGB2_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 4220 #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4221 #define DAGB2_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 4222 #define DAGB2_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 4223 #define DAGB2_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 4224 #define DAGB2_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4225 #define DAGB2_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 4226 #define DAGB2_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4227 #define DAGB2_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 4228 #define DAGB2_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4229 #define DAGB2_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 4230 //DAGB2_RD_VC6_CNTL 4231 #define DAGB2_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 4232 #define DAGB2_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 4233 #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4234 #define DAGB2_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 4235 #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4236 #define DAGB2_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 4237 #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4238 #define DAGB2_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 4239 #define DAGB2_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 4240 #define DAGB2_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 4241 #define DAGB2_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4242 #define DAGB2_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 4243 #define DAGB2_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4244 #define DAGB2_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 4245 #define DAGB2_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4246 #define DAGB2_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 4247 //DAGB2_RD_VC7_CNTL 4248 #define DAGB2_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 4249 #define DAGB2_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 4250 #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4251 #define DAGB2_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 4252 #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4253 #define DAGB2_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 4254 #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4255 #define DAGB2_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 4256 #define DAGB2_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 4257 #define DAGB2_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 4258 #define DAGB2_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4259 #define DAGB2_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 4260 #define DAGB2_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4261 #define DAGB2_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 4262 #define DAGB2_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4263 #define DAGB2_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 4264 //DAGB2_RD_CNTL_MISC 4265 #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 4266 #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 4267 #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 4268 #define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 4269 #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 4270 #define DAGB2_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 4271 #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 4272 #define DAGB2_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 4273 #define DAGB2_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 4274 #define DAGB2_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 4275 #define DAGB2_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 4276 #define DAGB2_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 4277 #define DAGB2_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 4278 #define DAGB2_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 4279 //DAGB2_RD_TLB_CREDIT 4280 #define DAGB2_RD_TLB_CREDIT__TLB0__SHIFT 0x0 4281 #define DAGB2_RD_TLB_CREDIT__TLB1__SHIFT 0x5 4282 #define DAGB2_RD_TLB_CREDIT__TLB2__SHIFT 0xa 4283 #define DAGB2_RD_TLB_CREDIT__TLB3__SHIFT 0xf 4284 #define DAGB2_RD_TLB_CREDIT__TLB4__SHIFT 0x14 4285 #define DAGB2_RD_TLB_CREDIT__TLB5__SHIFT 0x19 4286 #define DAGB2_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 4287 #define DAGB2_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 4288 #define DAGB2_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 4289 #define DAGB2_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 4290 #define DAGB2_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 4291 #define DAGB2_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 4292 //DAGB2_RD_RDRET_CREDIT_CNTL 4293 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 4294 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 4295 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc 4296 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 4297 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 4298 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 4299 #define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 4300 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL 4301 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L 4302 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L 4303 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L 4304 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L 4305 #define DAGB2_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 4306 #define DAGB2_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 4307 //DAGB2_RD_RDRET_CREDIT_CNTL2 4308 #define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 4309 #define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 4310 #define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc 4311 #define DAGB2_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL 4312 #define DAGB2_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L 4313 #define DAGB2_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L 4314 //DAGB2_RDCLI_ASK_PENDING 4315 #define DAGB2_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 4316 #define DAGB2_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 4317 //DAGB2_RDCLI_GO_PENDING 4318 #define DAGB2_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 4319 #define DAGB2_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 4320 //DAGB2_RDCLI_GBLSEND_PENDING 4321 #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 4322 #define DAGB2_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 4323 //DAGB2_RDCLI_TLB_PENDING 4324 #define DAGB2_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 4325 #define DAGB2_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 4326 //DAGB2_RDCLI_OARB_PENDING 4327 #define DAGB2_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 4328 #define DAGB2_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 4329 //DAGB2_RDCLI_OSD_PENDING 4330 #define DAGB2_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 4331 #define DAGB2_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 4332 //DAGB2_WRCLI0 4333 #define DAGB2_WRCLI0__VIRT_CHAN__SHIFT 0x0 4334 #define DAGB2_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 4335 #define DAGB2_WRCLI0__URG_HIGH__SHIFT 0x4 4336 #define DAGB2_WRCLI0__URG_LOW__SHIFT 0x8 4337 #define DAGB2_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 4338 #define DAGB2_WRCLI0__MAX_BW__SHIFT 0xd 4339 #define DAGB2_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 4340 #define DAGB2_WRCLI0__MIN_BW__SHIFT 0x16 4341 #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 4342 #define DAGB2_WRCLI0__MAX_OSD__SHIFT 0x1a 4343 #define DAGB2_WRCLI0__VIRT_CHAN_MASK 0x00000007L 4344 #define DAGB2_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 4345 #define DAGB2_WRCLI0__URG_HIGH_MASK 0x000000F0L 4346 #define DAGB2_WRCLI0__URG_LOW_MASK 0x00000F00L 4347 #define DAGB2_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 4348 #define DAGB2_WRCLI0__MAX_BW_MASK 0x001FE000L 4349 #define DAGB2_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 4350 #define DAGB2_WRCLI0__MIN_BW_MASK 0x01C00000L 4351 #define DAGB2_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 4352 #define DAGB2_WRCLI0__MAX_OSD_MASK 0xFC000000L 4353 //DAGB2_WRCLI1 4354 #define DAGB2_WRCLI1__VIRT_CHAN__SHIFT 0x0 4355 #define DAGB2_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 4356 #define DAGB2_WRCLI1__URG_HIGH__SHIFT 0x4 4357 #define DAGB2_WRCLI1__URG_LOW__SHIFT 0x8 4358 #define DAGB2_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 4359 #define DAGB2_WRCLI1__MAX_BW__SHIFT 0xd 4360 #define DAGB2_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 4361 #define DAGB2_WRCLI1__MIN_BW__SHIFT 0x16 4362 #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 4363 #define DAGB2_WRCLI1__MAX_OSD__SHIFT 0x1a 4364 #define DAGB2_WRCLI1__VIRT_CHAN_MASK 0x00000007L 4365 #define DAGB2_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 4366 #define DAGB2_WRCLI1__URG_HIGH_MASK 0x000000F0L 4367 #define DAGB2_WRCLI1__URG_LOW_MASK 0x00000F00L 4368 #define DAGB2_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 4369 #define DAGB2_WRCLI1__MAX_BW_MASK 0x001FE000L 4370 #define DAGB2_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 4371 #define DAGB2_WRCLI1__MIN_BW_MASK 0x01C00000L 4372 #define DAGB2_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 4373 #define DAGB2_WRCLI1__MAX_OSD_MASK 0xFC000000L 4374 //DAGB2_WRCLI2 4375 #define DAGB2_WRCLI2__VIRT_CHAN__SHIFT 0x0 4376 #define DAGB2_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 4377 #define DAGB2_WRCLI2__URG_HIGH__SHIFT 0x4 4378 #define DAGB2_WRCLI2__URG_LOW__SHIFT 0x8 4379 #define DAGB2_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 4380 #define DAGB2_WRCLI2__MAX_BW__SHIFT 0xd 4381 #define DAGB2_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 4382 #define DAGB2_WRCLI2__MIN_BW__SHIFT 0x16 4383 #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 4384 #define DAGB2_WRCLI2__MAX_OSD__SHIFT 0x1a 4385 #define DAGB2_WRCLI2__VIRT_CHAN_MASK 0x00000007L 4386 #define DAGB2_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 4387 #define DAGB2_WRCLI2__URG_HIGH_MASK 0x000000F0L 4388 #define DAGB2_WRCLI2__URG_LOW_MASK 0x00000F00L 4389 #define DAGB2_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 4390 #define DAGB2_WRCLI2__MAX_BW_MASK 0x001FE000L 4391 #define DAGB2_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 4392 #define DAGB2_WRCLI2__MIN_BW_MASK 0x01C00000L 4393 #define DAGB2_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 4394 #define DAGB2_WRCLI2__MAX_OSD_MASK 0xFC000000L 4395 //DAGB2_WRCLI3 4396 #define DAGB2_WRCLI3__VIRT_CHAN__SHIFT 0x0 4397 #define DAGB2_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 4398 #define DAGB2_WRCLI3__URG_HIGH__SHIFT 0x4 4399 #define DAGB2_WRCLI3__URG_LOW__SHIFT 0x8 4400 #define DAGB2_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 4401 #define DAGB2_WRCLI3__MAX_BW__SHIFT 0xd 4402 #define DAGB2_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 4403 #define DAGB2_WRCLI3__MIN_BW__SHIFT 0x16 4404 #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 4405 #define DAGB2_WRCLI3__MAX_OSD__SHIFT 0x1a 4406 #define DAGB2_WRCLI3__VIRT_CHAN_MASK 0x00000007L 4407 #define DAGB2_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 4408 #define DAGB2_WRCLI3__URG_HIGH_MASK 0x000000F0L 4409 #define DAGB2_WRCLI3__URG_LOW_MASK 0x00000F00L 4410 #define DAGB2_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 4411 #define DAGB2_WRCLI3__MAX_BW_MASK 0x001FE000L 4412 #define DAGB2_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 4413 #define DAGB2_WRCLI3__MIN_BW_MASK 0x01C00000L 4414 #define DAGB2_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 4415 #define DAGB2_WRCLI3__MAX_OSD_MASK 0xFC000000L 4416 //DAGB2_WRCLI4 4417 #define DAGB2_WRCLI4__VIRT_CHAN__SHIFT 0x0 4418 #define DAGB2_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 4419 #define DAGB2_WRCLI4__URG_HIGH__SHIFT 0x4 4420 #define DAGB2_WRCLI4__URG_LOW__SHIFT 0x8 4421 #define DAGB2_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 4422 #define DAGB2_WRCLI4__MAX_BW__SHIFT 0xd 4423 #define DAGB2_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 4424 #define DAGB2_WRCLI4__MIN_BW__SHIFT 0x16 4425 #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 4426 #define DAGB2_WRCLI4__MAX_OSD__SHIFT 0x1a 4427 #define DAGB2_WRCLI4__VIRT_CHAN_MASK 0x00000007L 4428 #define DAGB2_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 4429 #define DAGB2_WRCLI4__URG_HIGH_MASK 0x000000F0L 4430 #define DAGB2_WRCLI4__URG_LOW_MASK 0x00000F00L 4431 #define DAGB2_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 4432 #define DAGB2_WRCLI4__MAX_BW_MASK 0x001FE000L 4433 #define DAGB2_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 4434 #define DAGB2_WRCLI4__MIN_BW_MASK 0x01C00000L 4435 #define DAGB2_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 4436 #define DAGB2_WRCLI4__MAX_OSD_MASK 0xFC000000L 4437 //DAGB2_WRCLI5 4438 #define DAGB2_WRCLI5__VIRT_CHAN__SHIFT 0x0 4439 #define DAGB2_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 4440 #define DAGB2_WRCLI5__URG_HIGH__SHIFT 0x4 4441 #define DAGB2_WRCLI5__URG_LOW__SHIFT 0x8 4442 #define DAGB2_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 4443 #define DAGB2_WRCLI5__MAX_BW__SHIFT 0xd 4444 #define DAGB2_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 4445 #define DAGB2_WRCLI5__MIN_BW__SHIFT 0x16 4446 #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 4447 #define DAGB2_WRCLI5__MAX_OSD__SHIFT 0x1a 4448 #define DAGB2_WRCLI5__VIRT_CHAN_MASK 0x00000007L 4449 #define DAGB2_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 4450 #define DAGB2_WRCLI5__URG_HIGH_MASK 0x000000F0L 4451 #define DAGB2_WRCLI5__URG_LOW_MASK 0x00000F00L 4452 #define DAGB2_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 4453 #define DAGB2_WRCLI5__MAX_BW_MASK 0x001FE000L 4454 #define DAGB2_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 4455 #define DAGB2_WRCLI5__MIN_BW_MASK 0x01C00000L 4456 #define DAGB2_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 4457 #define DAGB2_WRCLI5__MAX_OSD_MASK 0xFC000000L 4458 //DAGB2_WRCLI6 4459 #define DAGB2_WRCLI6__VIRT_CHAN__SHIFT 0x0 4460 #define DAGB2_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 4461 #define DAGB2_WRCLI6__URG_HIGH__SHIFT 0x4 4462 #define DAGB2_WRCLI6__URG_LOW__SHIFT 0x8 4463 #define DAGB2_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 4464 #define DAGB2_WRCLI6__MAX_BW__SHIFT 0xd 4465 #define DAGB2_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 4466 #define DAGB2_WRCLI6__MIN_BW__SHIFT 0x16 4467 #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 4468 #define DAGB2_WRCLI6__MAX_OSD__SHIFT 0x1a 4469 #define DAGB2_WRCLI6__VIRT_CHAN_MASK 0x00000007L 4470 #define DAGB2_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 4471 #define DAGB2_WRCLI6__URG_HIGH_MASK 0x000000F0L 4472 #define DAGB2_WRCLI6__URG_LOW_MASK 0x00000F00L 4473 #define DAGB2_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 4474 #define DAGB2_WRCLI6__MAX_BW_MASK 0x001FE000L 4475 #define DAGB2_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 4476 #define DAGB2_WRCLI6__MIN_BW_MASK 0x01C00000L 4477 #define DAGB2_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 4478 #define DAGB2_WRCLI6__MAX_OSD_MASK 0xFC000000L 4479 //DAGB2_WRCLI7 4480 #define DAGB2_WRCLI7__VIRT_CHAN__SHIFT 0x0 4481 #define DAGB2_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 4482 #define DAGB2_WRCLI7__URG_HIGH__SHIFT 0x4 4483 #define DAGB2_WRCLI7__URG_LOW__SHIFT 0x8 4484 #define DAGB2_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 4485 #define DAGB2_WRCLI7__MAX_BW__SHIFT 0xd 4486 #define DAGB2_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 4487 #define DAGB2_WRCLI7__MIN_BW__SHIFT 0x16 4488 #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 4489 #define DAGB2_WRCLI7__MAX_OSD__SHIFT 0x1a 4490 #define DAGB2_WRCLI7__VIRT_CHAN_MASK 0x00000007L 4491 #define DAGB2_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 4492 #define DAGB2_WRCLI7__URG_HIGH_MASK 0x000000F0L 4493 #define DAGB2_WRCLI7__URG_LOW_MASK 0x00000F00L 4494 #define DAGB2_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 4495 #define DAGB2_WRCLI7__MAX_BW_MASK 0x001FE000L 4496 #define DAGB2_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 4497 #define DAGB2_WRCLI7__MIN_BW_MASK 0x01C00000L 4498 #define DAGB2_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 4499 #define DAGB2_WRCLI7__MAX_OSD_MASK 0xFC000000L 4500 //DAGB2_WRCLI8 4501 #define DAGB2_WRCLI8__VIRT_CHAN__SHIFT 0x0 4502 #define DAGB2_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 4503 #define DAGB2_WRCLI8__URG_HIGH__SHIFT 0x4 4504 #define DAGB2_WRCLI8__URG_LOW__SHIFT 0x8 4505 #define DAGB2_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 4506 #define DAGB2_WRCLI8__MAX_BW__SHIFT 0xd 4507 #define DAGB2_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 4508 #define DAGB2_WRCLI8__MIN_BW__SHIFT 0x16 4509 #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 4510 #define DAGB2_WRCLI8__MAX_OSD__SHIFT 0x1a 4511 #define DAGB2_WRCLI8__VIRT_CHAN_MASK 0x00000007L 4512 #define DAGB2_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 4513 #define DAGB2_WRCLI8__URG_HIGH_MASK 0x000000F0L 4514 #define DAGB2_WRCLI8__URG_LOW_MASK 0x00000F00L 4515 #define DAGB2_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 4516 #define DAGB2_WRCLI8__MAX_BW_MASK 0x001FE000L 4517 #define DAGB2_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 4518 #define DAGB2_WRCLI8__MIN_BW_MASK 0x01C00000L 4519 #define DAGB2_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 4520 #define DAGB2_WRCLI8__MAX_OSD_MASK 0xFC000000L 4521 //DAGB2_WRCLI9 4522 #define DAGB2_WRCLI9__VIRT_CHAN__SHIFT 0x0 4523 #define DAGB2_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 4524 #define DAGB2_WRCLI9__URG_HIGH__SHIFT 0x4 4525 #define DAGB2_WRCLI9__URG_LOW__SHIFT 0x8 4526 #define DAGB2_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 4527 #define DAGB2_WRCLI9__MAX_BW__SHIFT 0xd 4528 #define DAGB2_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 4529 #define DAGB2_WRCLI9__MIN_BW__SHIFT 0x16 4530 #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 4531 #define DAGB2_WRCLI9__MAX_OSD__SHIFT 0x1a 4532 #define DAGB2_WRCLI9__VIRT_CHAN_MASK 0x00000007L 4533 #define DAGB2_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 4534 #define DAGB2_WRCLI9__URG_HIGH_MASK 0x000000F0L 4535 #define DAGB2_WRCLI9__URG_LOW_MASK 0x00000F00L 4536 #define DAGB2_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 4537 #define DAGB2_WRCLI9__MAX_BW_MASK 0x001FE000L 4538 #define DAGB2_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 4539 #define DAGB2_WRCLI9__MIN_BW_MASK 0x01C00000L 4540 #define DAGB2_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 4541 #define DAGB2_WRCLI9__MAX_OSD_MASK 0xFC000000L 4542 //DAGB2_WRCLI10 4543 #define DAGB2_WRCLI10__VIRT_CHAN__SHIFT 0x0 4544 #define DAGB2_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 4545 #define DAGB2_WRCLI10__URG_HIGH__SHIFT 0x4 4546 #define DAGB2_WRCLI10__URG_LOW__SHIFT 0x8 4547 #define DAGB2_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 4548 #define DAGB2_WRCLI10__MAX_BW__SHIFT 0xd 4549 #define DAGB2_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 4550 #define DAGB2_WRCLI10__MIN_BW__SHIFT 0x16 4551 #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 4552 #define DAGB2_WRCLI10__MAX_OSD__SHIFT 0x1a 4553 #define DAGB2_WRCLI10__VIRT_CHAN_MASK 0x00000007L 4554 #define DAGB2_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 4555 #define DAGB2_WRCLI10__URG_HIGH_MASK 0x000000F0L 4556 #define DAGB2_WRCLI10__URG_LOW_MASK 0x00000F00L 4557 #define DAGB2_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 4558 #define DAGB2_WRCLI10__MAX_BW_MASK 0x001FE000L 4559 #define DAGB2_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 4560 #define DAGB2_WRCLI10__MIN_BW_MASK 0x01C00000L 4561 #define DAGB2_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 4562 #define DAGB2_WRCLI10__MAX_OSD_MASK 0xFC000000L 4563 //DAGB2_WRCLI11 4564 #define DAGB2_WRCLI11__VIRT_CHAN__SHIFT 0x0 4565 #define DAGB2_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 4566 #define DAGB2_WRCLI11__URG_HIGH__SHIFT 0x4 4567 #define DAGB2_WRCLI11__URG_LOW__SHIFT 0x8 4568 #define DAGB2_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 4569 #define DAGB2_WRCLI11__MAX_BW__SHIFT 0xd 4570 #define DAGB2_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 4571 #define DAGB2_WRCLI11__MIN_BW__SHIFT 0x16 4572 #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 4573 #define DAGB2_WRCLI11__MAX_OSD__SHIFT 0x1a 4574 #define DAGB2_WRCLI11__VIRT_CHAN_MASK 0x00000007L 4575 #define DAGB2_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 4576 #define DAGB2_WRCLI11__URG_HIGH_MASK 0x000000F0L 4577 #define DAGB2_WRCLI11__URG_LOW_MASK 0x00000F00L 4578 #define DAGB2_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 4579 #define DAGB2_WRCLI11__MAX_BW_MASK 0x001FE000L 4580 #define DAGB2_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 4581 #define DAGB2_WRCLI11__MIN_BW_MASK 0x01C00000L 4582 #define DAGB2_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 4583 #define DAGB2_WRCLI11__MAX_OSD_MASK 0xFC000000L 4584 //DAGB2_WRCLI12 4585 #define DAGB2_WRCLI12__VIRT_CHAN__SHIFT 0x0 4586 #define DAGB2_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 4587 #define DAGB2_WRCLI12__URG_HIGH__SHIFT 0x4 4588 #define DAGB2_WRCLI12__URG_LOW__SHIFT 0x8 4589 #define DAGB2_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 4590 #define DAGB2_WRCLI12__MAX_BW__SHIFT 0xd 4591 #define DAGB2_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 4592 #define DAGB2_WRCLI12__MIN_BW__SHIFT 0x16 4593 #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 4594 #define DAGB2_WRCLI12__MAX_OSD__SHIFT 0x1a 4595 #define DAGB2_WRCLI12__VIRT_CHAN_MASK 0x00000007L 4596 #define DAGB2_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 4597 #define DAGB2_WRCLI12__URG_HIGH_MASK 0x000000F0L 4598 #define DAGB2_WRCLI12__URG_LOW_MASK 0x00000F00L 4599 #define DAGB2_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 4600 #define DAGB2_WRCLI12__MAX_BW_MASK 0x001FE000L 4601 #define DAGB2_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 4602 #define DAGB2_WRCLI12__MIN_BW_MASK 0x01C00000L 4603 #define DAGB2_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 4604 #define DAGB2_WRCLI12__MAX_OSD_MASK 0xFC000000L 4605 //DAGB2_WRCLI13 4606 #define DAGB2_WRCLI13__VIRT_CHAN__SHIFT 0x0 4607 #define DAGB2_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 4608 #define DAGB2_WRCLI13__URG_HIGH__SHIFT 0x4 4609 #define DAGB2_WRCLI13__URG_LOW__SHIFT 0x8 4610 #define DAGB2_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 4611 #define DAGB2_WRCLI13__MAX_BW__SHIFT 0xd 4612 #define DAGB2_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 4613 #define DAGB2_WRCLI13__MIN_BW__SHIFT 0x16 4614 #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 4615 #define DAGB2_WRCLI13__MAX_OSD__SHIFT 0x1a 4616 #define DAGB2_WRCLI13__VIRT_CHAN_MASK 0x00000007L 4617 #define DAGB2_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 4618 #define DAGB2_WRCLI13__URG_HIGH_MASK 0x000000F0L 4619 #define DAGB2_WRCLI13__URG_LOW_MASK 0x00000F00L 4620 #define DAGB2_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 4621 #define DAGB2_WRCLI13__MAX_BW_MASK 0x001FE000L 4622 #define DAGB2_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 4623 #define DAGB2_WRCLI13__MIN_BW_MASK 0x01C00000L 4624 #define DAGB2_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 4625 #define DAGB2_WRCLI13__MAX_OSD_MASK 0xFC000000L 4626 //DAGB2_WRCLI14 4627 #define DAGB2_WRCLI14__VIRT_CHAN__SHIFT 0x0 4628 #define DAGB2_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 4629 #define DAGB2_WRCLI14__URG_HIGH__SHIFT 0x4 4630 #define DAGB2_WRCLI14__URG_LOW__SHIFT 0x8 4631 #define DAGB2_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 4632 #define DAGB2_WRCLI14__MAX_BW__SHIFT 0xd 4633 #define DAGB2_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 4634 #define DAGB2_WRCLI14__MIN_BW__SHIFT 0x16 4635 #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 4636 #define DAGB2_WRCLI14__MAX_OSD__SHIFT 0x1a 4637 #define DAGB2_WRCLI14__VIRT_CHAN_MASK 0x00000007L 4638 #define DAGB2_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 4639 #define DAGB2_WRCLI14__URG_HIGH_MASK 0x000000F0L 4640 #define DAGB2_WRCLI14__URG_LOW_MASK 0x00000F00L 4641 #define DAGB2_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 4642 #define DAGB2_WRCLI14__MAX_BW_MASK 0x001FE000L 4643 #define DAGB2_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 4644 #define DAGB2_WRCLI14__MIN_BW_MASK 0x01C00000L 4645 #define DAGB2_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 4646 #define DAGB2_WRCLI14__MAX_OSD_MASK 0xFC000000L 4647 //DAGB2_WRCLI15 4648 #define DAGB2_WRCLI15__VIRT_CHAN__SHIFT 0x0 4649 #define DAGB2_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 4650 #define DAGB2_WRCLI15__URG_HIGH__SHIFT 0x4 4651 #define DAGB2_WRCLI15__URG_LOW__SHIFT 0x8 4652 #define DAGB2_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 4653 #define DAGB2_WRCLI15__MAX_BW__SHIFT 0xd 4654 #define DAGB2_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 4655 #define DAGB2_WRCLI15__MIN_BW__SHIFT 0x16 4656 #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 4657 #define DAGB2_WRCLI15__MAX_OSD__SHIFT 0x1a 4658 #define DAGB2_WRCLI15__VIRT_CHAN_MASK 0x00000007L 4659 #define DAGB2_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 4660 #define DAGB2_WRCLI15__URG_HIGH_MASK 0x000000F0L 4661 #define DAGB2_WRCLI15__URG_LOW_MASK 0x00000F00L 4662 #define DAGB2_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 4663 #define DAGB2_WRCLI15__MAX_BW_MASK 0x001FE000L 4664 #define DAGB2_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 4665 #define DAGB2_WRCLI15__MIN_BW_MASK 0x01C00000L 4666 #define DAGB2_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 4667 #define DAGB2_WRCLI15__MAX_OSD_MASK 0xFC000000L 4668 //DAGB2_WR_CNTL 4669 #define DAGB2_WR_CNTL__SCLK_FREQ__SHIFT 0x0 4670 #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 4671 #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 4672 #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 4673 #define DAGB2_WR_CNTL__IO_LEVEL__SHIFT 0x11 4674 #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 4675 #define DAGB2_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 4676 #define DAGB2_WR_CNTL__FIX_JUMP__SHIFT 0x1a 4677 #define DAGB2_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 4678 #define DAGB2_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 4679 #define DAGB2_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 4680 #define DAGB2_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 4681 #define DAGB2_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 4682 #define DAGB2_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 4683 #define DAGB2_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 4684 #define DAGB2_WR_CNTL__FIX_JUMP_MASK 0x04000000L 4685 //DAGB2_WR_GMI_CNTL 4686 #define DAGB2_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 4687 #define DAGB2_WR_GMI_CNTL__LEVEL__SHIFT 0x6 4688 #define DAGB2_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 4689 #define DAGB2_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 4690 #define DAGB2_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 4691 #define DAGB2_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 4692 #define DAGB2_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 4693 #define DAGB2_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 4694 //DAGB2_WR_ADDR_DAGB 4695 #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 4696 #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 4697 #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 4698 #define DAGB2_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 4699 #define DAGB2_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 4700 #define DAGB2_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 4701 #define DAGB2_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 4702 #define DAGB2_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 4703 #define DAGB2_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 4704 #define DAGB2_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 4705 //DAGB2_WR_OUTPUT_DAGB_MAX_BURST 4706 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 4707 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 4708 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 4709 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 4710 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 4711 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 4712 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 4713 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 4714 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 4715 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 4716 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 4717 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 4718 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 4719 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 4720 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 4721 #define DAGB2_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 4722 //DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER 4723 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 4724 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 4725 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 4726 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 4727 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 4728 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 4729 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 4730 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 4731 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 4732 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 4733 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 4734 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 4735 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 4736 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 4737 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 4738 #define DAGB2_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 4739 //DAGB2_WR_CGTT_CLK_CTRL 4740 #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4741 #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4742 #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4743 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4744 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4745 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4746 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4747 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4748 #define DAGB2_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4749 #define DAGB2_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4750 #define DAGB2_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4751 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4752 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4753 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4754 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4755 #define DAGB2_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4756 //DAGB2_L1TLB_WR_CGTT_CLK_CTRL 4757 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4758 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4759 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4760 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4761 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4762 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4763 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4764 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4765 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4766 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4767 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4768 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4769 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4770 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4771 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4772 #define DAGB2_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4773 //DAGB2_ATCVM_WR_CGTT_CLK_CTRL 4774 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 4775 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 4776 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 4777 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 4778 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 4779 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 4780 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 4781 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 4782 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 4783 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 4784 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 4785 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 4786 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 4787 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 4788 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 4789 #define DAGB2_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 4790 //DAGB2_WR_ADDR_DAGB_MAX_BURST0 4791 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 4792 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 4793 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 4794 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 4795 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 4796 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 4797 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 4798 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 4799 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 4800 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 4801 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 4802 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 4803 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 4804 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 4805 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 4806 #define DAGB2_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 4807 //DAGB2_WR_ADDR_DAGB_LAZY_TIMER0 4808 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 4809 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 4810 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 4811 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 4812 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 4813 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 4814 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 4815 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 4816 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 4817 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 4818 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 4819 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 4820 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 4821 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 4822 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 4823 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 4824 //DAGB2_WR_ADDR_DAGB_MAX_BURST1 4825 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 4826 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 4827 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 4828 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 4829 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 4830 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 4831 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 4832 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 4833 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 4834 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 4835 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 4836 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 4837 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 4838 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 4839 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 4840 #define DAGB2_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 4841 //DAGB2_WR_ADDR_DAGB_LAZY_TIMER1 4842 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 4843 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 4844 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 4845 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 4846 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 4847 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 4848 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 4849 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 4850 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 4851 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 4852 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 4853 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 4854 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 4855 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 4856 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 4857 #define DAGB2_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 4858 //DAGB2_WR_DATA_DAGB 4859 #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 4860 #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 4861 #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 4862 #define DAGB2_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 4863 #define DAGB2_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 4864 #define DAGB2_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 4865 #define DAGB2_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 4866 #define DAGB2_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 4867 //DAGB2_WR_DATA_DAGB_MAX_BURST0 4868 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 4869 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 4870 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 4871 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 4872 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 4873 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 4874 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 4875 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 4876 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 4877 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 4878 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 4879 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 4880 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 4881 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 4882 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 4883 #define DAGB2_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 4884 //DAGB2_WR_DATA_DAGB_LAZY_TIMER0 4885 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 4886 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 4887 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 4888 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 4889 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 4890 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 4891 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 4892 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 4893 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 4894 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 4895 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 4896 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 4897 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 4898 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 4899 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 4900 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 4901 //DAGB2_WR_DATA_DAGB_MAX_BURST1 4902 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 4903 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 4904 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 4905 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 4906 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 4907 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 4908 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 4909 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 4910 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 4911 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 4912 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 4913 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 4914 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 4915 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 4916 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 4917 #define DAGB2_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 4918 //DAGB2_WR_DATA_DAGB_LAZY_TIMER1 4919 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 4920 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 4921 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 4922 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 4923 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 4924 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 4925 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 4926 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 4927 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 4928 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 4929 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 4930 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 4931 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 4932 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 4933 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 4934 #define DAGB2_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 4935 //DAGB2_WR_VC0_CNTL 4936 #define DAGB2_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 4937 #define DAGB2_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 4938 #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4939 #define DAGB2_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 4940 #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4941 #define DAGB2_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 4942 #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4943 #define DAGB2_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 4944 #define DAGB2_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 4945 #define DAGB2_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 4946 #define DAGB2_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4947 #define DAGB2_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 4948 #define DAGB2_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4949 #define DAGB2_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 4950 #define DAGB2_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4951 #define DAGB2_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 4952 //DAGB2_WR_VC1_CNTL 4953 #define DAGB2_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 4954 #define DAGB2_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 4955 #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4956 #define DAGB2_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 4957 #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4958 #define DAGB2_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 4959 #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4960 #define DAGB2_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 4961 #define DAGB2_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 4962 #define DAGB2_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 4963 #define DAGB2_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4964 #define DAGB2_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 4965 #define DAGB2_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4966 #define DAGB2_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 4967 #define DAGB2_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4968 #define DAGB2_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 4969 //DAGB2_WR_VC2_CNTL 4970 #define DAGB2_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 4971 #define DAGB2_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 4972 #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4973 #define DAGB2_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 4974 #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4975 #define DAGB2_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 4976 #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4977 #define DAGB2_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 4978 #define DAGB2_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 4979 #define DAGB2_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 4980 #define DAGB2_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4981 #define DAGB2_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 4982 #define DAGB2_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 4983 #define DAGB2_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 4984 #define DAGB2_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 4985 #define DAGB2_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 4986 //DAGB2_WR_VC3_CNTL 4987 #define DAGB2_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 4988 #define DAGB2_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 4989 #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 4990 #define DAGB2_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 4991 #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 4992 #define DAGB2_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 4993 #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 4994 #define DAGB2_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 4995 #define DAGB2_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 4996 #define DAGB2_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 4997 #define DAGB2_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 4998 #define DAGB2_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 4999 #define DAGB2_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5000 #define DAGB2_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 5001 #define DAGB2_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5002 #define DAGB2_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 5003 //DAGB2_WR_VC4_CNTL 5004 #define DAGB2_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 5005 #define DAGB2_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 5006 #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5007 #define DAGB2_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 5008 #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5009 #define DAGB2_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 5010 #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5011 #define DAGB2_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 5012 #define DAGB2_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 5013 #define DAGB2_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 5014 #define DAGB2_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5015 #define DAGB2_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 5016 #define DAGB2_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5017 #define DAGB2_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 5018 #define DAGB2_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5019 #define DAGB2_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 5020 //DAGB2_WR_VC5_CNTL 5021 #define DAGB2_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 5022 #define DAGB2_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 5023 #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5024 #define DAGB2_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 5025 #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5026 #define DAGB2_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 5027 #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5028 #define DAGB2_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 5029 #define DAGB2_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 5030 #define DAGB2_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 5031 #define DAGB2_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5032 #define DAGB2_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 5033 #define DAGB2_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5034 #define DAGB2_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 5035 #define DAGB2_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5036 #define DAGB2_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 5037 //DAGB2_WR_VC6_CNTL 5038 #define DAGB2_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 5039 #define DAGB2_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 5040 #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5041 #define DAGB2_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 5042 #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5043 #define DAGB2_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 5044 #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5045 #define DAGB2_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 5046 #define DAGB2_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 5047 #define DAGB2_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 5048 #define DAGB2_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5049 #define DAGB2_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 5050 #define DAGB2_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5051 #define DAGB2_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 5052 #define DAGB2_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5053 #define DAGB2_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 5054 //DAGB2_WR_VC7_CNTL 5055 #define DAGB2_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 5056 #define DAGB2_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 5057 #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5058 #define DAGB2_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 5059 #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5060 #define DAGB2_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 5061 #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5062 #define DAGB2_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 5063 #define DAGB2_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 5064 #define DAGB2_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 5065 #define DAGB2_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5066 #define DAGB2_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 5067 #define DAGB2_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5068 #define DAGB2_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 5069 #define DAGB2_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5070 #define DAGB2_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 5071 //DAGB2_WR_CNTL_MISC 5072 #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 5073 #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 5074 #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 5075 #define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 5076 #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 5077 #define DAGB2_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 5078 #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 5079 #define DAGB2_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 5080 #define DAGB2_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 5081 #define DAGB2_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 5082 #define DAGB2_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 5083 #define DAGB2_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 5084 #define DAGB2_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 5085 #define DAGB2_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 5086 //DAGB2_WR_TLB_CREDIT 5087 #define DAGB2_WR_TLB_CREDIT__TLB0__SHIFT 0x0 5088 #define DAGB2_WR_TLB_CREDIT__TLB1__SHIFT 0x5 5089 #define DAGB2_WR_TLB_CREDIT__TLB2__SHIFT 0xa 5090 #define DAGB2_WR_TLB_CREDIT__TLB3__SHIFT 0xf 5091 #define DAGB2_WR_TLB_CREDIT__TLB4__SHIFT 0x14 5092 #define DAGB2_WR_TLB_CREDIT__TLB5__SHIFT 0x19 5093 #define DAGB2_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 5094 #define DAGB2_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 5095 #define DAGB2_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 5096 #define DAGB2_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 5097 #define DAGB2_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 5098 #define DAGB2_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 5099 //DAGB2_WR_DATA_CREDIT 5100 #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 5101 #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 5102 #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 5103 #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 5104 #define DAGB2_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 5105 #define DAGB2_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 5106 #define DAGB2_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 5107 #define DAGB2_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 5108 //DAGB2_WR_MISC_CREDIT 5109 #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 5110 #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 5111 #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 5112 #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 5113 #define DAGB2_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 5114 #define DAGB2_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 5115 #define DAGB2_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 5116 #define DAGB2_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 5117 //DAGB2_WR_OSD_CREDIT_CNTL1 5118 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 5119 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 5120 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 5121 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc 5122 #define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 5123 #define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 5124 #define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 5125 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL 5126 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L 5127 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L 5128 #define DAGB2_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L 5129 #define DAGB2_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L 5130 #define DAGB2_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L 5131 #define DAGB2_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L 5132 //DAGB2_WR_OSD_CREDIT_CNTL2 5133 #define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 5134 #define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 5135 #define DAGB2_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL 5136 #define DAGB2_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L 5137 //DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1 5138 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 5139 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 5140 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 5141 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 5142 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 5143 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 5144 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 5145 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 5146 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 5147 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 5148 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 5149 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 5150 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 5151 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 5152 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 5153 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 5154 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 5155 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 5156 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 5157 #define DAGB2_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 5158 //DAGB2_WRCLI_GPU_SNOOP_OVERRIDE 5159 #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 5160 #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 5161 //DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 5162 #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 5163 #define DAGB2_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 5164 //DAGB2_WRCLI_ASK_PENDING 5165 #define DAGB2_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 5166 #define DAGB2_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 5167 //DAGB2_WRCLI_GO_PENDING 5168 #define DAGB2_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 5169 #define DAGB2_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 5170 //DAGB2_WRCLI_GBLSEND_PENDING 5171 #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 5172 #define DAGB2_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 5173 //DAGB2_WRCLI_TLB_PENDING 5174 #define DAGB2_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 5175 #define DAGB2_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 5176 //DAGB2_WRCLI_OARB_PENDING 5177 #define DAGB2_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 5178 #define DAGB2_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 5179 //DAGB2_WRCLI_OSD_PENDING 5180 #define DAGB2_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 5181 #define DAGB2_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 5182 //DAGB2_WRCLI_DBUS_ASK_PENDING 5183 #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 5184 #define DAGB2_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 5185 //DAGB2_WRCLI_DBUS_GO_PENDING 5186 #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 5187 #define DAGB2_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 5188 //DAGB2_DAGB_DLY 5189 #define DAGB2_DAGB_DLY__DLY__SHIFT 0x0 5190 #define DAGB2_DAGB_DLY__CLI__SHIFT 0x8 5191 #define DAGB2_DAGB_DLY__POS__SHIFT 0x10 5192 #define DAGB2_DAGB_DLY__DLY_MASK 0x000000FFL 5193 #define DAGB2_DAGB_DLY__CLI_MASK 0x0000FF00L 5194 #define DAGB2_DAGB_DLY__POS_MASK 0x000F0000L 5195 //DAGB2_CNTL_MISC 5196 #define DAGB2_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 5197 #define DAGB2_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 5198 #define DAGB2_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 5199 #define DAGB2_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 5200 #define DAGB2_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 5201 #define DAGB2_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 5202 #define DAGB2_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 5203 #define DAGB2_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 5204 #define DAGB2_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 5205 #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 5206 #define DAGB2_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 5207 #define DAGB2_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 5208 #define DAGB2_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 5209 #define DAGB2_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 5210 #define DAGB2_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 5211 #define DAGB2_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 5212 #define DAGB2_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 5213 #define DAGB2_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 5214 #define DAGB2_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 5215 #define DAGB2_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 5216 //DAGB2_CNTL_MISC2 5217 #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 5218 #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 5219 #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 5220 #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 5221 #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 5222 #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 5223 #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 5224 #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 5225 #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 5226 #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 5227 #define DAGB2_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 5228 #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 5229 #define DAGB2_CNTL_MISC2__HDP_CID__SHIFT 0xc 5230 #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 5231 #define DAGB2_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 5232 #define DAGB2_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 5233 #define DAGB2_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 5234 #define DAGB2_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 5235 #define DAGB2_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 5236 #define DAGB2_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 5237 #define DAGB2_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 5238 #define DAGB2_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 5239 #define DAGB2_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 5240 #define DAGB2_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 5241 #define DAGB2_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 5242 #define DAGB2_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 5243 #define DAGB2_CNTL_MISC2__HDP_CID_MASK 0x0001F000L 5244 #define DAGB2_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 5245 //DAGB2_FATAL_ERROR_CNTL 5246 #define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 5247 #define DAGB2_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 5248 //DAGB2_FATAL_ERROR_CLEAR 5249 #define DAGB2_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 5250 #define DAGB2_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 5251 //DAGB2_FATAL_ERROR_STATUS0 5252 #define DAGB2_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 5253 #define DAGB2_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 5254 #define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 5255 #define DAGB2_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 5256 #define DAGB2_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 5257 #define DAGB2_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 5258 //DAGB2_FATAL_ERROR_STATUS1 5259 #define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 5260 #define DAGB2_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 5261 //DAGB2_FATAL_ERROR_STATUS2 5262 #define DAGB2_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 5263 #define DAGB2_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 5264 #define DAGB2_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 5265 #define DAGB2_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 5266 #define DAGB2_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 5267 #define DAGB2_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 5268 #define DAGB2_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 5269 #define DAGB2_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL 5270 #define DAGB2_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L 5271 #define DAGB2_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L 5272 #define DAGB2_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L 5273 #define DAGB2_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L 5274 #define DAGB2_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L 5275 #define DAGB2_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L 5276 //DAGB2_FATAL_ERROR_STATUS3 5277 #define DAGB2_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 5278 #define DAGB2_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 5279 #define DAGB2_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 5280 #define DAGB2_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 5281 #define DAGB2_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 5282 #define DAGB2_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 5283 #define DAGB2_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 5284 #define DAGB2_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 5285 #define DAGB2_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 5286 #define DAGB2_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 5287 #define DAGB2_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 5288 #define DAGB2_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 5289 #define DAGB2_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 5290 #define DAGB2_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 5291 #define DAGB2_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 5292 #define DAGB2_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 5293 #define DAGB2_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 5294 #define DAGB2_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L 5295 //DAGB2_FIFO_EMPTY 5296 #define DAGB2_FIFO_EMPTY__EMPTY__SHIFT 0x0 5297 #define DAGB2_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 5298 //DAGB2_FIFO_FULL 5299 #define DAGB2_FIFO_FULL__FULL__SHIFT 0x0 5300 #define DAGB2_FIFO_FULL__FULL_MASK 0x007FFFFFL 5301 //DAGB2_WR_CREDITS_FULL 5302 #define DAGB2_WR_CREDITS_FULL__FULL__SHIFT 0x0 5303 #define DAGB2_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 5304 //DAGB2_RD_CREDITS_FULL 5305 #define DAGB2_RD_CREDITS_FULL__FULL__SHIFT 0x0 5306 #define DAGB2_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 5307 //DAGB2_PERFCOUNTER_LO 5308 #define DAGB2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 5309 #define DAGB2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 5310 //DAGB2_PERFCOUNTER_HI 5311 #define DAGB2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 5312 #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 5313 #define DAGB2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 5314 #define DAGB2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 5315 //DAGB2_PERFCOUNTER0_CFG 5316 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 5317 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 5318 #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 5319 #define DAGB2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 5320 #define DAGB2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 5321 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 5322 #define DAGB2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 5323 #define DAGB2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 5324 #define DAGB2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 5325 #define DAGB2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 5326 //DAGB2_PERFCOUNTER1_CFG 5327 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 5328 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 5329 #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 5330 #define DAGB2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 5331 #define DAGB2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 5332 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 5333 #define DAGB2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 5334 #define DAGB2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 5335 #define DAGB2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 5336 #define DAGB2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 5337 //DAGB2_PERFCOUNTER2_CFG 5338 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 5339 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 5340 #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 5341 #define DAGB2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 5342 #define DAGB2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 5343 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 5344 #define DAGB2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 5345 #define DAGB2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 5346 #define DAGB2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 5347 #define DAGB2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 5348 //DAGB2_PERFCOUNTER_RSLT_CNTL 5349 #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 5350 #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 5351 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 5352 #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 5353 #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 5354 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 5355 #define DAGB2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 5356 #define DAGB2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 5357 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 5358 #define DAGB2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 5359 #define DAGB2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 5360 #define DAGB2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 5361 //DAGB2_L1TLB_REG_RW 5362 #define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 5363 #define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 5364 #define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 5365 #define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 5366 #define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 5367 #define DAGB2_L1TLB_REG_RW__RESERVE__SHIFT 0x6 5368 #define DAGB2_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 5369 #define DAGB2_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 5370 #define DAGB2_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L 5371 #define DAGB2_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L 5372 #define DAGB2_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L 5373 #define DAGB2_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L 5374 //DAGB2_RESERVE1 5375 #define DAGB2_RESERVE1__RESERVE__SHIFT 0x0 5376 #define DAGB2_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 5377 //DAGB2_RESERVE2 5378 #define DAGB2_RESERVE2__RESERVE__SHIFT 0x0 5379 #define DAGB2_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 5380 //DAGB2_RESERVE3 5381 #define DAGB2_RESERVE3__RESERVE__SHIFT 0x0 5382 #define DAGB2_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 5383 //DAGB2_RESERVE4 5384 #define DAGB2_RESERVE4__RESERVE__SHIFT 0x0 5385 #define DAGB2_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 5386 5387 5388 // addressBlock: mmhub_dagb_dagbdec3 5389 //DAGB3_RDCLI0 5390 #define DAGB3_RDCLI0__VIRT_CHAN__SHIFT 0x0 5391 #define DAGB3_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 5392 #define DAGB3_RDCLI0__URG_HIGH__SHIFT 0x4 5393 #define DAGB3_RDCLI0__URG_LOW__SHIFT 0x8 5394 #define DAGB3_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 5395 #define DAGB3_RDCLI0__MAX_BW__SHIFT 0xd 5396 #define DAGB3_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 5397 #define DAGB3_RDCLI0__MIN_BW__SHIFT 0x16 5398 #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 5399 #define DAGB3_RDCLI0__MAX_OSD__SHIFT 0x1a 5400 #define DAGB3_RDCLI0__VIRT_CHAN_MASK 0x00000007L 5401 #define DAGB3_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 5402 #define DAGB3_RDCLI0__URG_HIGH_MASK 0x000000F0L 5403 #define DAGB3_RDCLI0__URG_LOW_MASK 0x00000F00L 5404 #define DAGB3_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 5405 #define DAGB3_RDCLI0__MAX_BW_MASK 0x001FE000L 5406 #define DAGB3_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 5407 #define DAGB3_RDCLI0__MIN_BW_MASK 0x01C00000L 5408 #define DAGB3_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 5409 #define DAGB3_RDCLI0__MAX_OSD_MASK 0xFC000000L 5410 //DAGB3_RDCLI1 5411 #define DAGB3_RDCLI1__VIRT_CHAN__SHIFT 0x0 5412 #define DAGB3_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 5413 #define DAGB3_RDCLI1__URG_HIGH__SHIFT 0x4 5414 #define DAGB3_RDCLI1__URG_LOW__SHIFT 0x8 5415 #define DAGB3_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 5416 #define DAGB3_RDCLI1__MAX_BW__SHIFT 0xd 5417 #define DAGB3_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 5418 #define DAGB3_RDCLI1__MIN_BW__SHIFT 0x16 5419 #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 5420 #define DAGB3_RDCLI1__MAX_OSD__SHIFT 0x1a 5421 #define DAGB3_RDCLI1__VIRT_CHAN_MASK 0x00000007L 5422 #define DAGB3_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 5423 #define DAGB3_RDCLI1__URG_HIGH_MASK 0x000000F0L 5424 #define DAGB3_RDCLI1__URG_LOW_MASK 0x00000F00L 5425 #define DAGB3_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 5426 #define DAGB3_RDCLI1__MAX_BW_MASK 0x001FE000L 5427 #define DAGB3_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 5428 #define DAGB3_RDCLI1__MIN_BW_MASK 0x01C00000L 5429 #define DAGB3_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 5430 #define DAGB3_RDCLI1__MAX_OSD_MASK 0xFC000000L 5431 //DAGB3_RDCLI2 5432 #define DAGB3_RDCLI2__VIRT_CHAN__SHIFT 0x0 5433 #define DAGB3_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 5434 #define DAGB3_RDCLI2__URG_HIGH__SHIFT 0x4 5435 #define DAGB3_RDCLI2__URG_LOW__SHIFT 0x8 5436 #define DAGB3_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 5437 #define DAGB3_RDCLI2__MAX_BW__SHIFT 0xd 5438 #define DAGB3_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 5439 #define DAGB3_RDCLI2__MIN_BW__SHIFT 0x16 5440 #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 5441 #define DAGB3_RDCLI2__MAX_OSD__SHIFT 0x1a 5442 #define DAGB3_RDCLI2__VIRT_CHAN_MASK 0x00000007L 5443 #define DAGB3_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 5444 #define DAGB3_RDCLI2__URG_HIGH_MASK 0x000000F0L 5445 #define DAGB3_RDCLI2__URG_LOW_MASK 0x00000F00L 5446 #define DAGB3_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 5447 #define DAGB3_RDCLI2__MAX_BW_MASK 0x001FE000L 5448 #define DAGB3_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 5449 #define DAGB3_RDCLI2__MIN_BW_MASK 0x01C00000L 5450 #define DAGB3_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 5451 #define DAGB3_RDCLI2__MAX_OSD_MASK 0xFC000000L 5452 //DAGB3_RDCLI3 5453 #define DAGB3_RDCLI3__VIRT_CHAN__SHIFT 0x0 5454 #define DAGB3_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 5455 #define DAGB3_RDCLI3__URG_HIGH__SHIFT 0x4 5456 #define DAGB3_RDCLI3__URG_LOW__SHIFT 0x8 5457 #define DAGB3_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 5458 #define DAGB3_RDCLI3__MAX_BW__SHIFT 0xd 5459 #define DAGB3_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 5460 #define DAGB3_RDCLI3__MIN_BW__SHIFT 0x16 5461 #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 5462 #define DAGB3_RDCLI3__MAX_OSD__SHIFT 0x1a 5463 #define DAGB3_RDCLI3__VIRT_CHAN_MASK 0x00000007L 5464 #define DAGB3_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 5465 #define DAGB3_RDCLI3__URG_HIGH_MASK 0x000000F0L 5466 #define DAGB3_RDCLI3__URG_LOW_MASK 0x00000F00L 5467 #define DAGB3_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 5468 #define DAGB3_RDCLI3__MAX_BW_MASK 0x001FE000L 5469 #define DAGB3_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 5470 #define DAGB3_RDCLI3__MIN_BW_MASK 0x01C00000L 5471 #define DAGB3_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 5472 #define DAGB3_RDCLI3__MAX_OSD_MASK 0xFC000000L 5473 //DAGB3_RDCLI4 5474 #define DAGB3_RDCLI4__VIRT_CHAN__SHIFT 0x0 5475 #define DAGB3_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 5476 #define DAGB3_RDCLI4__URG_HIGH__SHIFT 0x4 5477 #define DAGB3_RDCLI4__URG_LOW__SHIFT 0x8 5478 #define DAGB3_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 5479 #define DAGB3_RDCLI4__MAX_BW__SHIFT 0xd 5480 #define DAGB3_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 5481 #define DAGB3_RDCLI4__MIN_BW__SHIFT 0x16 5482 #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 5483 #define DAGB3_RDCLI4__MAX_OSD__SHIFT 0x1a 5484 #define DAGB3_RDCLI4__VIRT_CHAN_MASK 0x00000007L 5485 #define DAGB3_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 5486 #define DAGB3_RDCLI4__URG_HIGH_MASK 0x000000F0L 5487 #define DAGB3_RDCLI4__URG_LOW_MASK 0x00000F00L 5488 #define DAGB3_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 5489 #define DAGB3_RDCLI4__MAX_BW_MASK 0x001FE000L 5490 #define DAGB3_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 5491 #define DAGB3_RDCLI4__MIN_BW_MASK 0x01C00000L 5492 #define DAGB3_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 5493 #define DAGB3_RDCLI4__MAX_OSD_MASK 0xFC000000L 5494 //DAGB3_RDCLI5 5495 #define DAGB3_RDCLI5__VIRT_CHAN__SHIFT 0x0 5496 #define DAGB3_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 5497 #define DAGB3_RDCLI5__URG_HIGH__SHIFT 0x4 5498 #define DAGB3_RDCLI5__URG_LOW__SHIFT 0x8 5499 #define DAGB3_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 5500 #define DAGB3_RDCLI5__MAX_BW__SHIFT 0xd 5501 #define DAGB3_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 5502 #define DAGB3_RDCLI5__MIN_BW__SHIFT 0x16 5503 #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 5504 #define DAGB3_RDCLI5__MAX_OSD__SHIFT 0x1a 5505 #define DAGB3_RDCLI5__VIRT_CHAN_MASK 0x00000007L 5506 #define DAGB3_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 5507 #define DAGB3_RDCLI5__URG_HIGH_MASK 0x000000F0L 5508 #define DAGB3_RDCLI5__URG_LOW_MASK 0x00000F00L 5509 #define DAGB3_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 5510 #define DAGB3_RDCLI5__MAX_BW_MASK 0x001FE000L 5511 #define DAGB3_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 5512 #define DAGB3_RDCLI5__MIN_BW_MASK 0x01C00000L 5513 #define DAGB3_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 5514 #define DAGB3_RDCLI5__MAX_OSD_MASK 0xFC000000L 5515 //DAGB3_RDCLI6 5516 #define DAGB3_RDCLI6__VIRT_CHAN__SHIFT 0x0 5517 #define DAGB3_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 5518 #define DAGB3_RDCLI6__URG_HIGH__SHIFT 0x4 5519 #define DAGB3_RDCLI6__URG_LOW__SHIFT 0x8 5520 #define DAGB3_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 5521 #define DAGB3_RDCLI6__MAX_BW__SHIFT 0xd 5522 #define DAGB3_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 5523 #define DAGB3_RDCLI6__MIN_BW__SHIFT 0x16 5524 #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 5525 #define DAGB3_RDCLI6__MAX_OSD__SHIFT 0x1a 5526 #define DAGB3_RDCLI6__VIRT_CHAN_MASK 0x00000007L 5527 #define DAGB3_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 5528 #define DAGB3_RDCLI6__URG_HIGH_MASK 0x000000F0L 5529 #define DAGB3_RDCLI6__URG_LOW_MASK 0x00000F00L 5530 #define DAGB3_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 5531 #define DAGB3_RDCLI6__MAX_BW_MASK 0x001FE000L 5532 #define DAGB3_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 5533 #define DAGB3_RDCLI6__MIN_BW_MASK 0x01C00000L 5534 #define DAGB3_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 5535 #define DAGB3_RDCLI6__MAX_OSD_MASK 0xFC000000L 5536 //DAGB3_RDCLI7 5537 #define DAGB3_RDCLI7__VIRT_CHAN__SHIFT 0x0 5538 #define DAGB3_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 5539 #define DAGB3_RDCLI7__URG_HIGH__SHIFT 0x4 5540 #define DAGB3_RDCLI7__URG_LOW__SHIFT 0x8 5541 #define DAGB3_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 5542 #define DAGB3_RDCLI7__MAX_BW__SHIFT 0xd 5543 #define DAGB3_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 5544 #define DAGB3_RDCLI7__MIN_BW__SHIFT 0x16 5545 #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 5546 #define DAGB3_RDCLI7__MAX_OSD__SHIFT 0x1a 5547 #define DAGB3_RDCLI7__VIRT_CHAN_MASK 0x00000007L 5548 #define DAGB3_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 5549 #define DAGB3_RDCLI7__URG_HIGH_MASK 0x000000F0L 5550 #define DAGB3_RDCLI7__URG_LOW_MASK 0x00000F00L 5551 #define DAGB3_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 5552 #define DAGB3_RDCLI7__MAX_BW_MASK 0x001FE000L 5553 #define DAGB3_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 5554 #define DAGB3_RDCLI7__MIN_BW_MASK 0x01C00000L 5555 #define DAGB3_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 5556 #define DAGB3_RDCLI7__MAX_OSD_MASK 0xFC000000L 5557 //DAGB3_RDCLI8 5558 #define DAGB3_RDCLI8__VIRT_CHAN__SHIFT 0x0 5559 #define DAGB3_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 5560 #define DAGB3_RDCLI8__URG_HIGH__SHIFT 0x4 5561 #define DAGB3_RDCLI8__URG_LOW__SHIFT 0x8 5562 #define DAGB3_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 5563 #define DAGB3_RDCLI8__MAX_BW__SHIFT 0xd 5564 #define DAGB3_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 5565 #define DAGB3_RDCLI8__MIN_BW__SHIFT 0x16 5566 #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 5567 #define DAGB3_RDCLI8__MAX_OSD__SHIFT 0x1a 5568 #define DAGB3_RDCLI8__VIRT_CHAN_MASK 0x00000007L 5569 #define DAGB3_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 5570 #define DAGB3_RDCLI8__URG_HIGH_MASK 0x000000F0L 5571 #define DAGB3_RDCLI8__URG_LOW_MASK 0x00000F00L 5572 #define DAGB3_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 5573 #define DAGB3_RDCLI8__MAX_BW_MASK 0x001FE000L 5574 #define DAGB3_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 5575 #define DAGB3_RDCLI8__MIN_BW_MASK 0x01C00000L 5576 #define DAGB3_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 5577 #define DAGB3_RDCLI8__MAX_OSD_MASK 0xFC000000L 5578 //DAGB3_RDCLI9 5579 #define DAGB3_RDCLI9__VIRT_CHAN__SHIFT 0x0 5580 #define DAGB3_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 5581 #define DAGB3_RDCLI9__URG_HIGH__SHIFT 0x4 5582 #define DAGB3_RDCLI9__URG_LOW__SHIFT 0x8 5583 #define DAGB3_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 5584 #define DAGB3_RDCLI9__MAX_BW__SHIFT 0xd 5585 #define DAGB3_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 5586 #define DAGB3_RDCLI9__MIN_BW__SHIFT 0x16 5587 #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 5588 #define DAGB3_RDCLI9__MAX_OSD__SHIFT 0x1a 5589 #define DAGB3_RDCLI9__VIRT_CHAN_MASK 0x00000007L 5590 #define DAGB3_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 5591 #define DAGB3_RDCLI9__URG_HIGH_MASK 0x000000F0L 5592 #define DAGB3_RDCLI9__URG_LOW_MASK 0x00000F00L 5593 #define DAGB3_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 5594 #define DAGB3_RDCLI9__MAX_BW_MASK 0x001FE000L 5595 #define DAGB3_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 5596 #define DAGB3_RDCLI9__MIN_BW_MASK 0x01C00000L 5597 #define DAGB3_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 5598 #define DAGB3_RDCLI9__MAX_OSD_MASK 0xFC000000L 5599 //DAGB3_RDCLI10 5600 #define DAGB3_RDCLI10__VIRT_CHAN__SHIFT 0x0 5601 #define DAGB3_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 5602 #define DAGB3_RDCLI10__URG_HIGH__SHIFT 0x4 5603 #define DAGB3_RDCLI10__URG_LOW__SHIFT 0x8 5604 #define DAGB3_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 5605 #define DAGB3_RDCLI10__MAX_BW__SHIFT 0xd 5606 #define DAGB3_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 5607 #define DAGB3_RDCLI10__MIN_BW__SHIFT 0x16 5608 #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 5609 #define DAGB3_RDCLI10__MAX_OSD__SHIFT 0x1a 5610 #define DAGB3_RDCLI10__VIRT_CHAN_MASK 0x00000007L 5611 #define DAGB3_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 5612 #define DAGB3_RDCLI10__URG_HIGH_MASK 0x000000F0L 5613 #define DAGB3_RDCLI10__URG_LOW_MASK 0x00000F00L 5614 #define DAGB3_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 5615 #define DAGB3_RDCLI10__MAX_BW_MASK 0x001FE000L 5616 #define DAGB3_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 5617 #define DAGB3_RDCLI10__MIN_BW_MASK 0x01C00000L 5618 #define DAGB3_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 5619 #define DAGB3_RDCLI10__MAX_OSD_MASK 0xFC000000L 5620 //DAGB3_RDCLI11 5621 #define DAGB3_RDCLI11__VIRT_CHAN__SHIFT 0x0 5622 #define DAGB3_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 5623 #define DAGB3_RDCLI11__URG_HIGH__SHIFT 0x4 5624 #define DAGB3_RDCLI11__URG_LOW__SHIFT 0x8 5625 #define DAGB3_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 5626 #define DAGB3_RDCLI11__MAX_BW__SHIFT 0xd 5627 #define DAGB3_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 5628 #define DAGB3_RDCLI11__MIN_BW__SHIFT 0x16 5629 #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 5630 #define DAGB3_RDCLI11__MAX_OSD__SHIFT 0x1a 5631 #define DAGB3_RDCLI11__VIRT_CHAN_MASK 0x00000007L 5632 #define DAGB3_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 5633 #define DAGB3_RDCLI11__URG_HIGH_MASK 0x000000F0L 5634 #define DAGB3_RDCLI11__URG_LOW_MASK 0x00000F00L 5635 #define DAGB3_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 5636 #define DAGB3_RDCLI11__MAX_BW_MASK 0x001FE000L 5637 #define DAGB3_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 5638 #define DAGB3_RDCLI11__MIN_BW_MASK 0x01C00000L 5639 #define DAGB3_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 5640 #define DAGB3_RDCLI11__MAX_OSD_MASK 0xFC000000L 5641 //DAGB3_RDCLI12 5642 #define DAGB3_RDCLI12__VIRT_CHAN__SHIFT 0x0 5643 #define DAGB3_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 5644 #define DAGB3_RDCLI12__URG_HIGH__SHIFT 0x4 5645 #define DAGB3_RDCLI12__URG_LOW__SHIFT 0x8 5646 #define DAGB3_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 5647 #define DAGB3_RDCLI12__MAX_BW__SHIFT 0xd 5648 #define DAGB3_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 5649 #define DAGB3_RDCLI12__MIN_BW__SHIFT 0x16 5650 #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 5651 #define DAGB3_RDCLI12__MAX_OSD__SHIFT 0x1a 5652 #define DAGB3_RDCLI12__VIRT_CHAN_MASK 0x00000007L 5653 #define DAGB3_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 5654 #define DAGB3_RDCLI12__URG_HIGH_MASK 0x000000F0L 5655 #define DAGB3_RDCLI12__URG_LOW_MASK 0x00000F00L 5656 #define DAGB3_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 5657 #define DAGB3_RDCLI12__MAX_BW_MASK 0x001FE000L 5658 #define DAGB3_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 5659 #define DAGB3_RDCLI12__MIN_BW_MASK 0x01C00000L 5660 #define DAGB3_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 5661 #define DAGB3_RDCLI12__MAX_OSD_MASK 0xFC000000L 5662 //DAGB3_RDCLI13 5663 #define DAGB3_RDCLI13__VIRT_CHAN__SHIFT 0x0 5664 #define DAGB3_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 5665 #define DAGB3_RDCLI13__URG_HIGH__SHIFT 0x4 5666 #define DAGB3_RDCLI13__URG_LOW__SHIFT 0x8 5667 #define DAGB3_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 5668 #define DAGB3_RDCLI13__MAX_BW__SHIFT 0xd 5669 #define DAGB3_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 5670 #define DAGB3_RDCLI13__MIN_BW__SHIFT 0x16 5671 #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 5672 #define DAGB3_RDCLI13__MAX_OSD__SHIFT 0x1a 5673 #define DAGB3_RDCLI13__VIRT_CHAN_MASK 0x00000007L 5674 #define DAGB3_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 5675 #define DAGB3_RDCLI13__URG_HIGH_MASK 0x000000F0L 5676 #define DAGB3_RDCLI13__URG_LOW_MASK 0x00000F00L 5677 #define DAGB3_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 5678 #define DAGB3_RDCLI13__MAX_BW_MASK 0x001FE000L 5679 #define DAGB3_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 5680 #define DAGB3_RDCLI13__MIN_BW_MASK 0x01C00000L 5681 #define DAGB3_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 5682 #define DAGB3_RDCLI13__MAX_OSD_MASK 0xFC000000L 5683 //DAGB3_RDCLI14 5684 #define DAGB3_RDCLI14__VIRT_CHAN__SHIFT 0x0 5685 #define DAGB3_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 5686 #define DAGB3_RDCLI14__URG_HIGH__SHIFT 0x4 5687 #define DAGB3_RDCLI14__URG_LOW__SHIFT 0x8 5688 #define DAGB3_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 5689 #define DAGB3_RDCLI14__MAX_BW__SHIFT 0xd 5690 #define DAGB3_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 5691 #define DAGB3_RDCLI14__MIN_BW__SHIFT 0x16 5692 #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 5693 #define DAGB3_RDCLI14__MAX_OSD__SHIFT 0x1a 5694 #define DAGB3_RDCLI14__VIRT_CHAN_MASK 0x00000007L 5695 #define DAGB3_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 5696 #define DAGB3_RDCLI14__URG_HIGH_MASK 0x000000F0L 5697 #define DAGB3_RDCLI14__URG_LOW_MASK 0x00000F00L 5698 #define DAGB3_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 5699 #define DAGB3_RDCLI14__MAX_BW_MASK 0x001FE000L 5700 #define DAGB3_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 5701 #define DAGB3_RDCLI14__MIN_BW_MASK 0x01C00000L 5702 #define DAGB3_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 5703 #define DAGB3_RDCLI14__MAX_OSD_MASK 0xFC000000L 5704 //DAGB3_RDCLI15 5705 #define DAGB3_RDCLI15__VIRT_CHAN__SHIFT 0x0 5706 #define DAGB3_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 5707 #define DAGB3_RDCLI15__URG_HIGH__SHIFT 0x4 5708 #define DAGB3_RDCLI15__URG_LOW__SHIFT 0x8 5709 #define DAGB3_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 5710 #define DAGB3_RDCLI15__MAX_BW__SHIFT 0xd 5711 #define DAGB3_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 5712 #define DAGB3_RDCLI15__MIN_BW__SHIFT 0x16 5713 #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 5714 #define DAGB3_RDCLI15__MAX_OSD__SHIFT 0x1a 5715 #define DAGB3_RDCLI15__VIRT_CHAN_MASK 0x00000007L 5716 #define DAGB3_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 5717 #define DAGB3_RDCLI15__URG_HIGH_MASK 0x000000F0L 5718 #define DAGB3_RDCLI15__URG_LOW_MASK 0x00000F00L 5719 #define DAGB3_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 5720 #define DAGB3_RDCLI15__MAX_BW_MASK 0x001FE000L 5721 #define DAGB3_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 5722 #define DAGB3_RDCLI15__MIN_BW_MASK 0x01C00000L 5723 #define DAGB3_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 5724 #define DAGB3_RDCLI15__MAX_OSD_MASK 0xFC000000L 5725 //DAGB3_RD_CNTL 5726 #define DAGB3_RD_CNTL__SCLK_FREQ__SHIFT 0x0 5727 #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 5728 #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 5729 #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 5730 #define DAGB3_RD_CNTL__IO_LEVEL__SHIFT 0x11 5731 #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 5732 #define DAGB3_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 5733 #define DAGB3_RD_CNTL__FIX_JUMP__SHIFT 0x1a 5734 #define DAGB3_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 5735 #define DAGB3_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 5736 #define DAGB3_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 5737 #define DAGB3_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 5738 #define DAGB3_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 5739 #define DAGB3_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 5740 #define DAGB3_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 5741 #define DAGB3_RD_CNTL__FIX_JUMP_MASK 0x04000000L 5742 //DAGB3_RD_GMI_CNTL 5743 #define DAGB3_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 5744 #define DAGB3_RD_GMI_CNTL__LEVEL__SHIFT 0x6 5745 #define DAGB3_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 5746 #define DAGB3_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 5747 #define DAGB3_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 5748 #define DAGB3_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 5749 #define DAGB3_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 5750 #define DAGB3_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 5751 //DAGB3_RD_ADDR_DAGB 5752 #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 5753 #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 5754 #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 5755 #define DAGB3_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 5756 #define DAGB3_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 5757 #define DAGB3_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 5758 #define DAGB3_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 5759 #define DAGB3_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 5760 #define DAGB3_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 5761 #define DAGB3_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 5762 //DAGB3_RD_OUTPUT_DAGB_MAX_BURST 5763 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 5764 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 5765 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 5766 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 5767 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 5768 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 5769 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 5770 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 5771 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 5772 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 5773 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 5774 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 5775 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 5776 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 5777 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 5778 #define DAGB3_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 5779 //DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER 5780 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 5781 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 5782 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 5783 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 5784 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 5785 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 5786 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 5787 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 5788 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 5789 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 5790 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 5791 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 5792 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 5793 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 5794 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 5795 #define DAGB3_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 5796 //DAGB3_RD_CGTT_CLK_CTRL 5797 #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5798 #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5799 #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 5800 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5801 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 5802 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 5803 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 5804 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 5805 #define DAGB3_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5806 #define DAGB3_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5807 #define DAGB3_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 5808 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5809 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 5810 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 5811 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 5812 #define DAGB3_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 5813 //DAGB3_L1TLB_RD_CGTT_CLK_CTRL 5814 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5815 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5816 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 5817 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5818 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 5819 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 5820 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 5821 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 5822 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5823 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5824 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 5825 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5826 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 5827 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 5828 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 5829 #define DAGB3_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 5830 //DAGB3_ATCVM_RD_CGTT_CLK_CTRL 5831 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 5832 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 5833 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 5834 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 5835 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 5836 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 5837 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 5838 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 5839 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 5840 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 5841 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 5842 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 5843 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 5844 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 5845 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 5846 #define DAGB3_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 5847 //DAGB3_RD_ADDR_DAGB_MAX_BURST0 5848 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 5849 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 5850 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 5851 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 5852 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 5853 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 5854 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 5855 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 5856 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 5857 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 5858 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 5859 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 5860 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 5861 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 5862 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 5863 #define DAGB3_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 5864 //DAGB3_RD_ADDR_DAGB_LAZY_TIMER0 5865 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 5866 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 5867 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 5868 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 5869 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 5870 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 5871 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 5872 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 5873 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 5874 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 5875 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 5876 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 5877 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 5878 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 5879 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 5880 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 5881 //DAGB3_RD_ADDR_DAGB_MAX_BURST1 5882 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 5883 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 5884 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 5885 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 5886 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 5887 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 5888 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 5889 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 5890 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 5891 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 5892 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 5893 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 5894 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 5895 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 5896 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 5897 #define DAGB3_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 5898 //DAGB3_RD_ADDR_DAGB_LAZY_TIMER1 5899 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 5900 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 5901 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 5902 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 5903 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 5904 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 5905 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 5906 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 5907 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 5908 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 5909 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 5910 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 5911 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 5912 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 5913 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 5914 #define DAGB3_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 5915 //DAGB3_RD_VC0_CNTL 5916 #define DAGB3_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 5917 #define DAGB3_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 5918 #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5919 #define DAGB3_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 5920 #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5921 #define DAGB3_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 5922 #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5923 #define DAGB3_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 5924 #define DAGB3_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 5925 #define DAGB3_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 5926 #define DAGB3_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5927 #define DAGB3_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 5928 #define DAGB3_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5929 #define DAGB3_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 5930 #define DAGB3_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5931 #define DAGB3_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 5932 //DAGB3_RD_VC1_CNTL 5933 #define DAGB3_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 5934 #define DAGB3_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 5935 #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5936 #define DAGB3_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 5937 #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5938 #define DAGB3_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 5939 #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5940 #define DAGB3_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 5941 #define DAGB3_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 5942 #define DAGB3_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 5943 #define DAGB3_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5944 #define DAGB3_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 5945 #define DAGB3_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5946 #define DAGB3_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 5947 #define DAGB3_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5948 #define DAGB3_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 5949 //DAGB3_RD_VC2_CNTL 5950 #define DAGB3_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 5951 #define DAGB3_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 5952 #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5953 #define DAGB3_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 5954 #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5955 #define DAGB3_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 5956 #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5957 #define DAGB3_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 5958 #define DAGB3_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 5959 #define DAGB3_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 5960 #define DAGB3_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5961 #define DAGB3_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 5962 #define DAGB3_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5963 #define DAGB3_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 5964 #define DAGB3_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5965 #define DAGB3_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 5966 //DAGB3_RD_VC3_CNTL 5967 #define DAGB3_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 5968 #define DAGB3_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 5969 #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5970 #define DAGB3_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 5971 #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5972 #define DAGB3_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 5973 #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5974 #define DAGB3_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 5975 #define DAGB3_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 5976 #define DAGB3_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 5977 #define DAGB3_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5978 #define DAGB3_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 5979 #define DAGB3_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5980 #define DAGB3_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 5981 #define DAGB3_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5982 #define DAGB3_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 5983 //DAGB3_RD_VC4_CNTL 5984 #define DAGB3_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 5985 #define DAGB3_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 5986 #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 5987 #define DAGB3_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 5988 #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 5989 #define DAGB3_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 5990 #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 5991 #define DAGB3_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 5992 #define DAGB3_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 5993 #define DAGB3_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 5994 #define DAGB3_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 5995 #define DAGB3_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 5996 #define DAGB3_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 5997 #define DAGB3_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 5998 #define DAGB3_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 5999 #define DAGB3_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 6000 //DAGB3_RD_VC5_CNTL 6001 #define DAGB3_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 6002 #define DAGB3_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 6003 #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6004 #define DAGB3_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 6005 #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6006 #define DAGB3_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 6007 #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6008 #define DAGB3_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 6009 #define DAGB3_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 6010 #define DAGB3_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 6011 #define DAGB3_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6012 #define DAGB3_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 6013 #define DAGB3_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6014 #define DAGB3_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 6015 #define DAGB3_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6016 #define DAGB3_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 6017 //DAGB3_RD_VC6_CNTL 6018 #define DAGB3_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 6019 #define DAGB3_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 6020 #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6021 #define DAGB3_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 6022 #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6023 #define DAGB3_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 6024 #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6025 #define DAGB3_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 6026 #define DAGB3_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 6027 #define DAGB3_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 6028 #define DAGB3_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6029 #define DAGB3_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 6030 #define DAGB3_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6031 #define DAGB3_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 6032 #define DAGB3_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6033 #define DAGB3_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 6034 //DAGB3_RD_VC7_CNTL 6035 #define DAGB3_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 6036 #define DAGB3_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 6037 #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6038 #define DAGB3_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 6039 #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6040 #define DAGB3_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 6041 #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6042 #define DAGB3_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 6043 #define DAGB3_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 6044 #define DAGB3_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 6045 #define DAGB3_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6046 #define DAGB3_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 6047 #define DAGB3_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6048 #define DAGB3_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 6049 #define DAGB3_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6050 #define DAGB3_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 6051 //DAGB3_RD_CNTL_MISC 6052 #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 6053 #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 6054 #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 6055 #define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 6056 #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 6057 #define DAGB3_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 6058 #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 6059 #define DAGB3_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 6060 #define DAGB3_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 6061 #define DAGB3_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 6062 #define DAGB3_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 6063 #define DAGB3_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 6064 #define DAGB3_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 6065 #define DAGB3_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 6066 //DAGB3_RD_TLB_CREDIT 6067 #define DAGB3_RD_TLB_CREDIT__TLB0__SHIFT 0x0 6068 #define DAGB3_RD_TLB_CREDIT__TLB1__SHIFT 0x5 6069 #define DAGB3_RD_TLB_CREDIT__TLB2__SHIFT 0xa 6070 #define DAGB3_RD_TLB_CREDIT__TLB3__SHIFT 0xf 6071 #define DAGB3_RD_TLB_CREDIT__TLB4__SHIFT 0x14 6072 #define DAGB3_RD_TLB_CREDIT__TLB5__SHIFT 0x19 6073 #define DAGB3_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 6074 #define DAGB3_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 6075 #define DAGB3_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 6076 #define DAGB3_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 6077 #define DAGB3_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 6078 #define DAGB3_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 6079 //DAGB3_RD_RDRET_CREDIT_CNTL 6080 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 6081 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 6082 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc 6083 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 6084 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 6085 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 6086 #define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 6087 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL 6088 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L 6089 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L 6090 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L 6091 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L 6092 #define DAGB3_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 6093 #define DAGB3_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 6094 //DAGB3_RD_RDRET_CREDIT_CNTL2 6095 #define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 6096 #define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 6097 #define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc 6098 #define DAGB3_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL 6099 #define DAGB3_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L 6100 #define DAGB3_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L 6101 //DAGB3_RDCLI_ASK_PENDING 6102 #define DAGB3_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 6103 #define DAGB3_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 6104 //DAGB3_RDCLI_GO_PENDING 6105 #define DAGB3_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 6106 #define DAGB3_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 6107 //DAGB3_RDCLI_GBLSEND_PENDING 6108 #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 6109 #define DAGB3_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 6110 //DAGB3_RDCLI_TLB_PENDING 6111 #define DAGB3_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 6112 #define DAGB3_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 6113 //DAGB3_RDCLI_OARB_PENDING 6114 #define DAGB3_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 6115 #define DAGB3_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 6116 //DAGB3_RDCLI_OSD_PENDING 6117 #define DAGB3_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 6118 #define DAGB3_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 6119 //DAGB3_WRCLI0 6120 #define DAGB3_WRCLI0__VIRT_CHAN__SHIFT 0x0 6121 #define DAGB3_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 6122 #define DAGB3_WRCLI0__URG_HIGH__SHIFT 0x4 6123 #define DAGB3_WRCLI0__URG_LOW__SHIFT 0x8 6124 #define DAGB3_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 6125 #define DAGB3_WRCLI0__MAX_BW__SHIFT 0xd 6126 #define DAGB3_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 6127 #define DAGB3_WRCLI0__MIN_BW__SHIFT 0x16 6128 #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 6129 #define DAGB3_WRCLI0__MAX_OSD__SHIFT 0x1a 6130 #define DAGB3_WRCLI0__VIRT_CHAN_MASK 0x00000007L 6131 #define DAGB3_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 6132 #define DAGB3_WRCLI0__URG_HIGH_MASK 0x000000F0L 6133 #define DAGB3_WRCLI0__URG_LOW_MASK 0x00000F00L 6134 #define DAGB3_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 6135 #define DAGB3_WRCLI0__MAX_BW_MASK 0x001FE000L 6136 #define DAGB3_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 6137 #define DAGB3_WRCLI0__MIN_BW_MASK 0x01C00000L 6138 #define DAGB3_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 6139 #define DAGB3_WRCLI0__MAX_OSD_MASK 0xFC000000L 6140 //DAGB3_WRCLI1 6141 #define DAGB3_WRCLI1__VIRT_CHAN__SHIFT 0x0 6142 #define DAGB3_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 6143 #define DAGB3_WRCLI1__URG_HIGH__SHIFT 0x4 6144 #define DAGB3_WRCLI1__URG_LOW__SHIFT 0x8 6145 #define DAGB3_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 6146 #define DAGB3_WRCLI1__MAX_BW__SHIFT 0xd 6147 #define DAGB3_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 6148 #define DAGB3_WRCLI1__MIN_BW__SHIFT 0x16 6149 #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 6150 #define DAGB3_WRCLI1__MAX_OSD__SHIFT 0x1a 6151 #define DAGB3_WRCLI1__VIRT_CHAN_MASK 0x00000007L 6152 #define DAGB3_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 6153 #define DAGB3_WRCLI1__URG_HIGH_MASK 0x000000F0L 6154 #define DAGB3_WRCLI1__URG_LOW_MASK 0x00000F00L 6155 #define DAGB3_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 6156 #define DAGB3_WRCLI1__MAX_BW_MASK 0x001FE000L 6157 #define DAGB3_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 6158 #define DAGB3_WRCLI1__MIN_BW_MASK 0x01C00000L 6159 #define DAGB3_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 6160 #define DAGB3_WRCLI1__MAX_OSD_MASK 0xFC000000L 6161 //DAGB3_WRCLI2 6162 #define DAGB3_WRCLI2__VIRT_CHAN__SHIFT 0x0 6163 #define DAGB3_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 6164 #define DAGB3_WRCLI2__URG_HIGH__SHIFT 0x4 6165 #define DAGB3_WRCLI2__URG_LOW__SHIFT 0x8 6166 #define DAGB3_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 6167 #define DAGB3_WRCLI2__MAX_BW__SHIFT 0xd 6168 #define DAGB3_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 6169 #define DAGB3_WRCLI2__MIN_BW__SHIFT 0x16 6170 #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 6171 #define DAGB3_WRCLI2__MAX_OSD__SHIFT 0x1a 6172 #define DAGB3_WRCLI2__VIRT_CHAN_MASK 0x00000007L 6173 #define DAGB3_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 6174 #define DAGB3_WRCLI2__URG_HIGH_MASK 0x000000F0L 6175 #define DAGB3_WRCLI2__URG_LOW_MASK 0x00000F00L 6176 #define DAGB3_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 6177 #define DAGB3_WRCLI2__MAX_BW_MASK 0x001FE000L 6178 #define DAGB3_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 6179 #define DAGB3_WRCLI2__MIN_BW_MASK 0x01C00000L 6180 #define DAGB3_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 6181 #define DAGB3_WRCLI2__MAX_OSD_MASK 0xFC000000L 6182 //DAGB3_WRCLI3 6183 #define DAGB3_WRCLI3__VIRT_CHAN__SHIFT 0x0 6184 #define DAGB3_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 6185 #define DAGB3_WRCLI3__URG_HIGH__SHIFT 0x4 6186 #define DAGB3_WRCLI3__URG_LOW__SHIFT 0x8 6187 #define DAGB3_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 6188 #define DAGB3_WRCLI3__MAX_BW__SHIFT 0xd 6189 #define DAGB3_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 6190 #define DAGB3_WRCLI3__MIN_BW__SHIFT 0x16 6191 #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 6192 #define DAGB3_WRCLI3__MAX_OSD__SHIFT 0x1a 6193 #define DAGB3_WRCLI3__VIRT_CHAN_MASK 0x00000007L 6194 #define DAGB3_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 6195 #define DAGB3_WRCLI3__URG_HIGH_MASK 0x000000F0L 6196 #define DAGB3_WRCLI3__URG_LOW_MASK 0x00000F00L 6197 #define DAGB3_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 6198 #define DAGB3_WRCLI3__MAX_BW_MASK 0x001FE000L 6199 #define DAGB3_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 6200 #define DAGB3_WRCLI3__MIN_BW_MASK 0x01C00000L 6201 #define DAGB3_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 6202 #define DAGB3_WRCLI3__MAX_OSD_MASK 0xFC000000L 6203 //DAGB3_WRCLI4 6204 #define DAGB3_WRCLI4__VIRT_CHAN__SHIFT 0x0 6205 #define DAGB3_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 6206 #define DAGB3_WRCLI4__URG_HIGH__SHIFT 0x4 6207 #define DAGB3_WRCLI4__URG_LOW__SHIFT 0x8 6208 #define DAGB3_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 6209 #define DAGB3_WRCLI4__MAX_BW__SHIFT 0xd 6210 #define DAGB3_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 6211 #define DAGB3_WRCLI4__MIN_BW__SHIFT 0x16 6212 #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 6213 #define DAGB3_WRCLI4__MAX_OSD__SHIFT 0x1a 6214 #define DAGB3_WRCLI4__VIRT_CHAN_MASK 0x00000007L 6215 #define DAGB3_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 6216 #define DAGB3_WRCLI4__URG_HIGH_MASK 0x000000F0L 6217 #define DAGB3_WRCLI4__URG_LOW_MASK 0x00000F00L 6218 #define DAGB3_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 6219 #define DAGB3_WRCLI4__MAX_BW_MASK 0x001FE000L 6220 #define DAGB3_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 6221 #define DAGB3_WRCLI4__MIN_BW_MASK 0x01C00000L 6222 #define DAGB3_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 6223 #define DAGB3_WRCLI4__MAX_OSD_MASK 0xFC000000L 6224 //DAGB3_WRCLI5 6225 #define DAGB3_WRCLI5__VIRT_CHAN__SHIFT 0x0 6226 #define DAGB3_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 6227 #define DAGB3_WRCLI5__URG_HIGH__SHIFT 0x4 6228 #define DAGB3_WRCLI5__URG_LOW__SHIFT 0x8 6229 #define DAGB3_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 6230 #define DAGB3_WRCLI5__MAX_BW__SHIFT 0xd 6231 #define DAGB3_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 6232 #define DAGB3_WRCLI5__MIN_BW__SHIFT 0x16 6233 #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 6234 #define DAGB3_WRCLI5__MAX_OSD__SHIFT 0x1a 6235 #define DAGB3_WRCLI5__VIRT_CHAN_MASK 0x00000007L 6236 #define DAGB3_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 6237 #define DAGB3_WRCLI5__URG_HIGH_MASK 0x000000F0L 6238 #define DAGB3_WRCLI5__URG_LOW_MASK 0x00000F00L 6239 #define DAGB3_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 6240 #define DAGB3_WRCLI5__MAX_BW_MASK 0x001FE000L 6241 #define DAGB3_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 6242 #define DAGB3_WRCLI5__MIN_BW_MASK 0x01C00000L 6243 #define DAGB3_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 6244 #define DAGB3_WRCLI5__MAX_OSD_MASK 0xFC000000L 6245 //DAGB3_WRCLI6 6246 #define DAGB3_WRCLI6__VIRT_CHAN__SHIFT 0x0 6247 #define DAGB3_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 6248 #define DAGB3_WRCLI6__URG_HIGH__SHIFT 0x4 6249 #define DAGB3_WRCLI6__URG_LOW__SHIFT 0x8 6250 #define DAGB3_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 6251 #define DAGB3_WRCLI6__MAX_BW__SHIFT 0xd 6252 #define DAGB3_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 6253 #define DAGB3_WRCLI6__MIN_BW__SHIFT 0x16 6254 #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 6255 #define DAGB3_WRCLI6__MAX_OSD__SHIFT 0x1a 6256 #define DAGB3_WRCLI6__VIRT_CHAN_MASK 0x00000007L 6257 #define DAGB3_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 6258 #define DAGB3_WRCLI6__URG_HIGH_MASK 0x000000F0L 6259 #define DAGB3_WRCLI6__URG_LOW_MASK 0x00000F00L 6260 #define DAGB3_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 6261 #define DAGB3_WRCLI6__MAX_BW_MASK 0x001FE000L 6262 #define DAGB3_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 6263 #define DAGB3_WRCLI6__MIN_BW_MASK 0x01C00000L 6264 #define DAGB3_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 6265 #define DAGB3_WRCLI6__MAX_OSD_MASK 0xFC000000L 6266 //DAGB3_WRCLI7 6267 #define DAGB3_WRCLI7__VIRT_CHAN__SHIFT 0x0 6268 #define DAGB3_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 6269 #define DAGB3_WRCLI7__URG_HIGH__SHIFT 0x4 6270 #define DAGB3_WRCLI7__URG_LOW__SHIFT 0x8 6271 #define DAGB3_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 6272 #define DAGB3_WRCLI7__MAX_BW__SHIFT 0xd 6273 #define DAGB3_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 6274 #define DAGB3_WRCLI7__MIN_BW__SHIFT 0x16 6275 #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 6276 #define DAGB3_WRCLI7__MAX_OSD__SHIFT 0x1a 6277 #define DAGB3_WRCLI7__VIRT_CHAN_MASK 0x00000007L 6278 #define DAGB3_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 6279 #define DAGB3_WRCLI7__URG_HIGH_MASK 0x000000F0L 6280 #define DAGB3_WRCLI7__URG_LOW_MASK 0x00000F00L 6281 #define DAGB3_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 6282 #define DAGB3_WRCLI7__MAX_BW_MASK 0x001FE000L 6283 #define DAGB3_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 6284 #define DAGB3_WRCLI7__MIN_BW_MASK 0x01C00000L 6285 #define DAGB3_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 6286 #define DAGB3_WRCLI7__MAX_OSD_MASK 0xFC000000L 6287 //DAGB3_WRCLI8 6288 #define DAGB3_WRCLI8__VIRT_CHAN__SHIFT 0x0 6289 #define DAGB3_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 6290 #define DAGB3_WRCLI8__URG_HIGH__SHIFT 0x4 6291 #define DAGB3_WRCLI8__URG_LOW__SHIFT 0x8 6292 #define DAGB3_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 6293 #define DAGB3_WRCLI8__MAX_BW__SHIFT 0xd 6294 #define DAGB3_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 6295 #define DAGB3_WRCLI8__MIN_BW__SHIFT 0x16 6296 #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 6297 #define DAGB3_WRCLI8__MAX_OSD__SHIFT 0x1a 6298 #define DAGB3_WRCLI8__VIRT_CHAN_MASK 0x00000007L 6299 #define DAGB3_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 6300 #define DAGB3_WRCLI8__URG_HIGH_MASK 0x000000F0L 6301 #define DAGB3_WRCLI8__URG_LOW_MASK 0x00000F00L 6302 #define DAGB3_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 6303 #define DAGB3_WRCLI8__MAX_BW_MASK 0x001FE000L 6304 #define DAGB3_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 6305 #define DAGB3_WRCLI8__MIN_BW_MASK 0x01C00000L 6306 #define DAGB3_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 6307 #define DAGB3_WRCLI8__MAX_OSD_MASK 0xFC000000L 6308 //DAGB3_WRCLI9 6309 #define DAGB3_WRCLI9__VIRT_CHAN__SHIFT 0x0 6310 #define DAGB3_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 6311 #define DAGB3_WRCLI9__URG_HIGH__SHIFT 0x4 6312 #define DAGB3_WRCLI9__URG_LOW__SHIFT 0x8 6313 #define DAGB3_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 6314 #define DAGB3_WRCLI9__MAX_BW__SHIFT 0xd 6315 #define DAGB3_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 6316 #define DAGB3_WRCLI9__MIN_BW__SHIFT 0x16 6317 #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 6318 #define DAGB3_WRCLI9__MAX_OSD__SHIFT 0x1a 6319 #define DAGB3_WRCLI9__VIRT_CHAN_MASK 0x00000007L 6320 #define DAGB3_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 6321 #define DAGB3_WRCLI9__URG_HIGH_MASK 0x000000F0L 6322 #define DAGB3_WRCLI9__URG_LOW_MASK 0x00000F00L 6323 #define DAGB3_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 6324 #define DAGB3_WRCLI9__MAX_BW_MASK 0x001FE000L 6325 #define DAGB3_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 6326 #define DAGB3_WRCLI9__MIN_BW_MASK 0x01C00000L 6327 #define DAGB3_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 6328 #define DAGB3_WRCLI9__MAX_OSD_MASK 0xFC000000L 6329 //DAGB3_WRCLI10 6330 #define DAGB3_WRCLI10__VIRT_CHAN__SHIFT 0x0 6331 #define DAGB3_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 6332 #define DAGB3_WRCLI10__URG_HIGH__SHIFT 0x4 6333 #define DAGB3_WRCLI10__URG_LOW__SHIFT 0x8 6334 #define DAGB3_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 6335 #define DAGB3_WRCLI10__MAX_BW__SHIFT 0xd 6336 #define DAGB3_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 6337 #define DAGB3_WRCLI10__MIN_BW__SHIFT 0x16 6338 #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 6339 #define DAGB3_WRCLI10__MAX_OSD__SHIFT 0x1a 6340 #define DAGB3_WRCLI10__VIRT_CHAN_MASK 0x00000007L 6341 #define DAGB3_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 6342 #define DAGB3_WRCLI10__URG_HIGH_MASK 0x000000F0L 6343 #define DAGB3_WRCLI10__URG_LOW_MASK 0x00000F00L 6344 #define DAGB3_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 6345 #define DAGB3_WRCLI10__MAX_BW_MASK 0x001FE000L 6346 #define DAGB3_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 6347 #define DAGB3_WRCLI10__MIN_BW_MASK 0x01C00000L 6348 #define DAGB3_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 6349 #define DAGB3_WRCLI10__MAX_OSD_MASK 0xFC000000L 6350 //DAGB3_WRCLI11 6351 #define DAGB3_WRCLI11__VIRT_CHAN__SHIFT 0x0 6352 #define DAGB3_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 6353 #define DAGB3_WRCLI11__URG_HIGH__SHIFT 0x4 6354 #define DAGB3_WRCLI11__URG_LOW__SHIFT 0x8 6355 #define DAGB3_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 6356 #define DAGB3_WRCLI11__MAX_BW__SHIFT 0xd 6357 #define DAGB3_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 6358 #define DAGB3_WRCLI11__MIN_BW__SHIFT 0x16 6359 #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 6360 #define DAGB3_WRCLI11__MAX_OSD__SHIFT 0x1a 6361 #define DAGB3_WRCLI11__VIRT_CHAN_MASK 0x00000007L 6362 #define DAGB3_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 6363 #define DAGB3_WRCLI11__URG_HIGH_MASK 0x000000F0L 6364 #define DAGB3_WRCLI11__URG_LOW_MASK 0x00000F00L 6365 #define DAGB3_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 6366 #define DAGB3_WRCLI11__MAX_BW_MASK 0x001FE000L 6367 #define DAGB3_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 6368 #define DAGB3_WRCLI11__MIN_BW_MASK 0x01C00000L 6369 #define DAGB3_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 6370 #define DAGB3_WRCLI11__MAX_OSD_MASK 0xFC000000L 6371 //DAGB3_WRCLI12 6372 #define DAGB3_WRCLI12__VIRT_CHAN__SHIFT 0x0 6373 #define DAGB3_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 6374 #define DAGB3_WRCLI12__URG_HIGH__SHIFT 0x4 6375 #define DAGB3_WRCLI12__URG_LOW__SHIFT 0x8 6376 #define DAGB3_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 6377 #define DAGB3_WRCLI12__MAX_BW__SHIFT 0xd 6378 #define DAGB3_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 6379 #define DAGB3_WRCLI12__MIN_BW__SHIFT 0x16 6380 #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 6381 #define DAGB3_WRCLI12__MAX_OSD__SHIFT 0x1a 6382 #define DAGB3_WRCLI12__VIRT_CHAN_MASK 0x00000007L 6383 #define DAGB3_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 6384 #define DAGB3_WRCLI12__URG_HIGH_MASK 0x000000F0L 6385 #define DAGB3_WRCLI12__URG_LOW_MASK 0x00000F00L 6386 #define DAGB3_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 6387 #define DAGB3_WRCLI12__MAX_BW_MASK 0x001FE000L 6388 #define DAGB3_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 6389 #define DAGB3_WRCLI12__MIN_BW_MASK 0x01C00000L 6390 #define DAGB3_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 6391 #define DAGB3_WRCLI12__MAX_OSD_MASK 0xFC000000L 6392 //DAGB3_WRCLI13 6393 #define DAGB3_WRCLI13__VIRT_CHAN__SHIFT 0x0 6394 #define DAGB3_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 6395 #define DAGB3_WRCLI13__URG_HIGH__SHIFT 0x4 6396 #define DAGB3_WRCLI13__URG_LOW__SHIFT 0x8 6397 #define DAGB3_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 6398 #define DAGB3_WRCLI13__MAX_BW__SHIFT 0xd 6399 #define DAGB3_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 6400 #define DAGB3_WRCLI13__MIN_BW__SHIFT 0x16 6401 #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 6402 #define DAGB3_WRCLI13__MAX_OSD__SHIFT 0x1a 6403 #define DAGB3_WRCLI13__VIRT_CHAN_MASK 0x00000007L 6404 #define DAGB3_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 6405 #define DAGB3_WRCLI13__URG_HIGH_MASK 0x000000F0L 6406 #define DAGB3_WRCLI13__URG_LOW_MASK 0x00000F00L 6407 #define DAGB3_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 6408 #define DAGB3_WRCLI13__MAX_BW_MASK 0x001FE000L 6409 #define DAGB3_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 6410 #define DAGB3_WRCLI13__MIN_BW_MASK 0x01C00000L 6411 #define DAGB3_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 6412 #define DAGB3_WRCLI13__MAX_OSD_MASK 0xFC000000L 6413 //DAGB3_WRCLI14 6414 #define DAGB3_WRCLI14__VIRT_CHAN__SHIFT 0x0 6415 #define DAGB3_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 6416 #define DAGB3_WRCLI14__URG_HIGH__SHIFT 0x4 6417 #define DAGB3_WRCLI14__URG_LOW__SHIFT 0x8 6418 #define DAGB3_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 6419 #define DAGB3_WRCLI14__MAX_BW__SHIFT 0xd 6420 #define DAGB3_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 6421 #define DAGB3_WRCLI14__MIN_BW__SHIFT 0x16 6422 #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 6423 #define DAGB3_WRCLI14__MAX_OSD__SHIFT 0x1a 6424 #define DAGB3_WRCLI14__VIRT_CHAN_MASK 0x00000007L 6425 #define DAGB3_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 6426 #define DAGB3_WRCLI14__URG_HIGH_MASK 0x000000F0L 6427 #define DAGB3_WRCLI14__URG_LOW_MASK 0x00000F00L 6428 #define DAGB3_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 6429 #define DAGB3_WRCLI14__MAX_BW_MASK 0x001FE000L 6430 #define DAGB3_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 6431 #define DAGB3_WRCLI14__MIN_BW_MASK 0x01C00000L 6432 #define DAGB3_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 6433 #define DAGB3_WRCLI14__MAX_OSD_MASK 0xFC000000L 6434 //DAGB3_WRCLI15 6435 #define DAGB3_WRCLI15__VIRT_CHAN__SHIFT 0x0 6436 #define DAGB3_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 6437 #define DAGB3_WRCLI15__URG_HIGH__SHIFT 0x4 6438 #define DAGB3_WRCLI15__URG_LOW__SHIFT 0x8 6439 #define DAGB3_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 6440 #define DAGB3_WRCLI15__MAX_BW__SHIFT 0xd 6441 #define DAGB3_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 6442 #define DAGB3_WRCLI15__MIN_BW__SHIFT 0x16 6443 #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 6444 #define DAGB3_WRCLI15__MAX_OSD__SHIFT 0x1a 6445 #define DAGB3_WRCLI15__VIRT_CHAN_MASK 0x00000007L 6446 #define DAGB3_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 6447 #define DAGB3_WRCLI15__URG_HIGH_MASK 0x000000F0L 6448 #define DAGB3_WRCLI15__URG_LOW_MASK 0x00000F00L 6449 #define DAGB3_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 6450 #define DAGB3_WRCLI15__MAX_BW_MASK 0x001FE000L 6451 #define DAGB3_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 6452 #define DAGB3_WRCLI15__MIN_BW_MASK 0x01C00000L 6453 #define DAGB3_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 6454 #define DAGB3_WRCLI15__MAX_OSD_MASK 0xFC000000L 6455 //DAGB3_WR_CNTL 6456 #define DAGB3_WR_CNTL__SCLK_FREQ__SHIFT 0x0 6457 #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 6458 #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 6459 #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 6460 #define DAGB3_WR_CNTL__IO_LEVEL__SHIFT 0x11 6461 #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 6462 #define DAGB3_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 6463 #define DAGB3_WR_CNTL__FIX_JUMP__SHIFT 0x1a 6464 #define DAGB3_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 6465 #define DAGB3_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 6466 #define DAGB3_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 6467 #define DAGB3_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 6468 #define DAGB3_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 6469 #define DAGB3_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 6470 #define DAGB3_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 6471 #define DAGB3_WR_CNTL__FIX_JUMP_MASK 0x04000000L 6472 //DAGB3_WR_GMI_CNTL 6473 #define DAGB3_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 6474 #define DAGB3_WR_GMI_CNTL__LEVEL__SHIFT 0x6 6475 #define DAGB3_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 6476 #define DAGB3_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 6477 #define DAGB3_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 6478 #define DAGB3_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 6479 #define DAGB3_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 6480 #define DAGB3_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 6481 //DAGB3_WR_ADDR_DAGB 6482 #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 6483 #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 6484 #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 6485 #define DAGB3_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 6486 #define DAGB3_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 6487 #define DAGB3_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 6488 #define DAGB3_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 6489 #define DAGB3_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 6490 #define DAGB3_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 6491 #define DAGB3_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 6492 //DAGB3_WR_OUTPUT_DAGB_MAX_BURST 6493 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 6494 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 6495 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 6496 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 6497 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 6498 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 6499 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 6500 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 6501 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 6502 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 6503 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 6504 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 6505 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 6506 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 6507 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 6508 #define DAGB3_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 6509 //DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER 6510 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 6511 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 6512 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 6513 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 6514 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 6515 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 6516 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 6517 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 6518 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 6519 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 6520 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 6521 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 6522 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 6523 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 6524 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 6525 #define DAGB3_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 6526 //DAGB3_WR_CGTT_CLK_CTRL 6527 #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6528 #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6529 #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 6530 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 6531 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 6532 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 6533 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 6534 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 6535 #define DAGB3_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6536 #define DAGB3_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6537 #define DAGB3_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 6538 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 6539 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 6540 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 6541 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 6542 #define DAGB3_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 6543 //DAGB3_L1TLB_WR_CGTT_CLK_CTRL 6544 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6545 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6546 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 6547 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 6548 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 6549 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 6550 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 6551 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 6552 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6553 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6554 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 6555 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 6556 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 6557 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 6558 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 6559 #define DAGB3_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 6560 //DAGB3_ATCVM_WR_CGTT_CLK_CTRL 6561 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 6562 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 6563 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 6564 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 6565 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 6566 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 6567 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 6568 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 6569 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 6570 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 6571 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 6572 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 6573 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 6574 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 6575 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 6576 #define DAGB3_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 6577 //DAGB3_WR_ADDR_DAGB_MAX_BURST0 6578 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 6579 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 6580 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 6581 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 6582 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 6583 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 6584 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 6585 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 6586 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 6587 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 6588 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 6589 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 6590 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 6591 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 6592 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 6593 #define DAGB3_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 6594 //DAGB3_WR_ADDR_DAGB_LAZY_TIMER0 6595 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 6596 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 6597 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 6598 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 6599 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 6600 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 6601 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 6602 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 6603 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 6604 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 6605 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 6606 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 6607 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 6608 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 6609 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 6610 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 6611 //DAGB3_WR_ADDR_DAGB_MAX_BURST1 6612 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 6613 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 6614 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 6615 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 6616 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 6617 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 6618 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 6619 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 6620 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 6621 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 6622 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 6623 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 6624 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 6625 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 6626 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 6627 #define DAGB3_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 6628 //DAGB3_WR_ADDR_DAGB_LAZY_TIMER1 6629 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 6630 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 6631 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 6632 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 6633 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 6634 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 6635 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 6636 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 6637 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 6638 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 6639 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 6640 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 6641 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 6642 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 6643 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 6644 #define DAGB3_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 6645 //DAGB3_WR_DATA_DAGB 6646 #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 6647 #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 6648 #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 6649 #define DAGB3_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 6650 #define DAGB3_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 6651 #define DAGB3_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 6652 #define DAGB3_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 6653 #define DAGB3_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 6654 //DAGB3_WR_DATA_DAGB_MAX_BURST0 6655 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 6656 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 6657 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 6658 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 6659 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 6660 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 6661 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 6662 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 6663 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 6664 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 6665 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 6666 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 6667 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 6668 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 6669 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 6670 #define DAGB3_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 6671 //DAGB3_WR_DATA_DAGB_LAZY_TIMER0 6672 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 6673 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 6674 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 6675 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 6676 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 6677 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 6678 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 6679 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 6680 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 6681 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 6682 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 6683 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 6684 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 6685 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 6686 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 6687 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 6688 //DAGB3_WR_DATA_DAGB_MAX_BURST1 6689 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 6690 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 6691 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 6692 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 6693 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 6694 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 6695 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 6696 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 6697 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 6698 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 6699 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 6700 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 6701 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 6702 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 6703 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 6704 #define DAGB3_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 6705 //DAGB3_WR_DATA_DAGB_LAZY_TIMER1 6706 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 6707 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 6708 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 6709 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 6710 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 6711 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 6712 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 6713 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 6714 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 6715 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 6716 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 6717 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 6718 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 6719 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 6720 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 6721 #define DAGB3_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 6722 //DAGB3_WR_VC0_CNTL 6723 #define DAGB3_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 6724 #define DAGB3_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 6725 #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6726 #define DAGB3_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 6727 #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6728 #define DAGB3_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 6729 #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6730 #define DAGB3_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 6731 #define DAGB3_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 6732 #define DAGB3_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 6733 #define DAGB3_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6734 #define DAGB3_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 6735 #define DAGB3_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6736 #define DAGB3_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 6737 #define DAGB3_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6738 #define DAGB3_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 6739 //DAGB3_WR_VC1_CNTL 6740 #define DAGB3_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 6741 #define DAGB3_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 6742 #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6743 #define DAGB3_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 6744 #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6745 #define DAGB3_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 6746 #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6747 #define DAGB3_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 6748 #define DAGB3_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 6749 #define DAGB3_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 6750 #define DAGB3_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6751 #define DAGB3_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 6752 #define DAGB3_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6753 #define DAGB3_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 6754 #define DAGB3_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6755 #define DAGB3_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 6756 //DAGB3_WR_VC2_CNTL 6757 #define DAGB3_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 6758 #define DAGB3_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 6759 #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6760 #define DAGB3_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 6761 #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6762 #define DAGB3_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 6763 #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6764 #define DAGB3_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 6765 #define DAGB3_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 6766 #define DAGB3_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 6767 #define DAGB3_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6768 #define DAGB3_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 6769 #define DAGB3_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6770 #define DAGB3_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 6771 #define DAGB3_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6772 #define DAGB3_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 6773 //DAGB3_WR_VC3_CNTL 6774 #define DAGB3_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 6775 #define DAGB3_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 6776 #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6777 #define DAGB3_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 6778 #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6779 #define DAGB3_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 6780 #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6781 #define DAGB3_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 6782 #define DAGB3_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 6783 #define DAGB3_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 6784 #define DAGB3_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6785 #define DAGB3_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 6786 #define DAGB3_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6787 #define DAGB3_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 6788 #define DAGB3_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6789 #define DAGB3_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 6790 //DAGB3_WR_VC4_CNTL 6791 #define DAGB3_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 6792 #define DAGB3_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 6793 #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6794 #define DAGB3_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 6795 #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6796 #define DAGB3_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 6797 #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6798 #define DAGB3_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 6799 #define DAGB3_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 6800 #define DAGB3_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 6801 #define DAGB3_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6802 #define DAGB3_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 6803 #define DAGB3_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6804 #define DAGB3_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 6805 #define DAGB3_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6806 #define DAGB3_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 6807 //DAGB3_WR_VC5_CNTL 6808 #define DAGB3_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 6809 #define DAGB3_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 6810 #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6811 #define DAGB3_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 6812 #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6813 #define DAGB3_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 6814 #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6815 #define DAGB3_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 6816 #define DAGB3_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 6817 #define DAGB3_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 6818 #define DAGB3_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6819 #define DAGB3_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 6820 #define DAGB3_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6821 #define DAGB3_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 6822 #define DAGB3_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6823 #define DAGB3_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 6824 //DAGB3_WR_VC6_CNTL 6825 #define DAGB3_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 6826 #define DAGB3_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 6827 #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6828 #define DAGB3_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 6829 #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6830 #define DAGB3_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 6831 #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6832 #define DAGB3_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 6833 #define DAGB3_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 6834 #define DAGB3_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 6835 #define DAGB3_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6836 #define DAGB3_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 6837 #define DAGB3_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6838 #define DAGB3_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 6839 #define DAGB3_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6840 #define DAGB3_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 6841 //DAGB3_WR_VC7_CNTL 6842 #define DAGB3_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 6843 #define DAGB3_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 6844 #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 6845 #define DAGB3_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 6846 #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 6847 #define DAGB3_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 6848 #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 6849 #define DAGB3_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 6850 #define DAGB3_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 6851 #define DAGB3_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 6852 #define DAGB3_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 6853 #define DAGB3_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 6854 #define DAGB3_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 6855 #define DAGB3_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 6856 #define DAGB3_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 6857 #define DAGB3_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 6858 //DAGB3_WR_CNTL_MISC 6859 #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 6860 #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 6861 #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 6862 #define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 6863 #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 6864 #define DAGB3_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 6865 #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 6866 #define DAGB3_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 6867 #define DAGB3_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 6868 #define DAGB3_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 6869 #define DAGB3_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 6870 #define DAGB3_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 6871 #define DAGB3_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 6872 #define DAGB3_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 6873 //DAGB3_WR_TLB_CREDIT 6874 #define DAGB3_WR_TLB_CREDIT__TLB0__SHIFT 0x0 6875 #define DAGB3_WR_TLB_CREDIT__TLB1__SHIFT 0x5 6876 #define DAGB3_WR_TLB_CREDIT__TLB2__SHIFT 0xa 6877 #define DAGB3_WR_TLB_CREDIT__TLB3__SHIFT 0xf 6878 #define DAGB3_WR_TLB_CREDIT__TLB4__SHIFT 0x14 6879 #define DAGB3_WR_TLB_CREDIT__TLB5__SHIFT 0x19 6880 #define DAGB3_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 6881 #define DAGB3_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 6882 #define DAGB3_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 6883 #define DAGB3_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 6884 #define DAGB3_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 6885 #define DAGB3_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 6886 //DAGB3_WR_DATA_CREDIT 6887 #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 6888 #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 6889 #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 6890 #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 6891 #define DAGB3_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 6892 #define DAGB3_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 6893 #define DAGB3_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 6894 #define DAGB3_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 6895 //DAGB3_WR_MISC_CREDIT 6896 #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 6897 #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 6898 #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 6899 #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 6900 #define DAGB3_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 6901 #define DAGB3_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 6902 #define DAGB3_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 6903 #define DAGB3_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 6904 //DAGB3_WR_OSD_CREDIT_CNTL1 6905 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 6906 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 6907 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 6908 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc 6909 #define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 6910 #define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 6911 #define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 6912 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL 6913 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L 6914 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L 6915 #define DAGB3_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L 6916 #define DAGB3_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L 6917 #define DAGB3_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L 6918 #define DAGB3_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L 6919 //DAGB3_WR_OSD_CREDIT_CNTL2 6920 #define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 6921 #define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 6922 #define DAGB3_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL 6923 #define DAGB3_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L 6924 //DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1 6925 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 6926 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 6927 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 6928 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 6929 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 6930 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 6931 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 6932 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 6933 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 6934 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 6935 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 6936 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 6937 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 6938 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 6939 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 6940 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 6941 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 6942 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 6943 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 6944 #define DAGB3_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 6945 //DAGB3_WRCLI_GPU_SNOOP_OVERRIDE 6946 #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 6947 #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 6948 //DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 6949 #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 6950 #define DAGB3_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 6951 //DAGB3_WRCLI_ASK_PENDING 6952 #define DAGB3_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 6953 #define DAGB3_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 6954 //DAGB3_WRCLI_GO_PENDING 6955 #define DAGB3_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 6956 #define DAGB3_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 6957 //DAGB3_WRCLI_GBLSEND_PENDING 6958 #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 6959 #define DAGB3_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 6960 //DAGB3_WRCLI_TLB_PENDING 6961 #define DAGB3_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 6962 #define DAGB3_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 6963 //DAGB3_WRCLI_OARB_PENDING 6964 #define DAGB3_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 6965 #define DAGB3_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 6966 //DAGB3_WRCLI_OSD_PENDING 6967 #define DAGB3_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 6968 #define DAGB3_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 6969 //DAGB3_WRCLI_DBUS_ASK_PENDING 6970 #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 6971 #define DAGB3_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 6972 //DAGB3_WRCLI_DBUS_GO_PENDING 6973 #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 6974 #define DAGB3_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 6975 //DAGB3_DAGB_DLY 6976 #define DAGB3_DAGB_DLY__DLY__SHIFT 0x0 6977 #define DAGB3_DAGB_DLY__CLI__SHIFT 0x8 6978 #define DAGB3_DAGB_DLY__POS__SHIFT 0x10 6979 #define DAGB3_DAGB_DLY__DLY_MASK 0x000000FFL 6980 #define DAGB3_DAGB_DLY__CLI_MASK 0x0000FF00L 6981 #define DAGB3_DAGB_DLY__POS_MASK 0x000F0000L 6982 //DAGB3_CNTL_MISC 6983 #define DAGB3_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 6984 #define DAGB3_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 6985 #define DAGB3_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 6986 #define DAGB3_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 6987 #define DAGB3_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 6988 #define DAGB3_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 6989 #define DAGB3_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 6990 #define DAGB3_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 6991 #define DAGB3_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 6992 #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 6993 #define DAGB3_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 6994 #define DAGB3_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 6995 #define DAGB3_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 6996 #define DAGB3_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 6997 #define DAGB3_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 6998 #define DAGB3_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 6999 #define DAGB3_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 7000 #define DAGB3_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 7001 #define DAGB3_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 7002 #define DAGB3_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 7003 //DAGB3_CNTL_MISC2 7004 #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 7005 #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 7006 #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 7007 #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 7008 #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 7009 #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 7010 #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 7011 #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 7012 #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 7013 #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 7014 #define DAGB3_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 7015 #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 7016 #define DAGB3_CNTL_MISC2__HDP_CID__SHIFT 0xc 7017 #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 7018 #define DAGB3_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 7019 #define DAGB3_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 7020 #define DAGB3_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 7021 #define DAGB3_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 7022 #define DAGB3_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 7023 #define DAGB3_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 7024 #define DAGB3_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 7025 #define DAGB3_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 7026 #define DAGB3_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 7027 #define DAGB3_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 7028 #define DAGB3_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 7029 #define DAGB3_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 7030 #define DAGB3_CNTL_MISC2__HDP_CID_MASK 0x0001F000L 7031 #define DAGB3_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 7032 //DAGB3_FATAL_ERROR_CNTL 7033 #define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 7034 #define DAGB3_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 7035 //DAGB3_FATAL_ERROR_CLEAR 7036 #define DAGB3_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 7037 #define DAGB3_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 7038 //DAGB3_FATAL_ERROR_STATUS0 7039 #define DAGB3_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 7040 #define DAGB3_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 7041 #define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 7042 #define DAGB3_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 7043 #define DAGB3_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 7044 #define DAGB3_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 7045 //DAGB3_FATAL_ERROR_STATUS1 7046 #define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 7047 #define DAGB3_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 7048 //DAGB3_FATAL_ERROR_STATUS2 7049 #define DAGB3_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 7050 #define DAGB3_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 7051 #define DAGB3_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 7052 #define DAGB3_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 7053 #define DAGB3_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 7054 #define DAGB3_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 7055 #define DAGB3_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 7056 #define DAGB3_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL 7057 #define DAGB3_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L 7058 #define DAGB3_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L 7059 #define DAGB3_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L 7060 #define DAGB3_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L 7061 #define DAGB3_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L 7062 #define DAGB3_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L 7063 //DAGB3_FATAL_ERROR_STATUS3 7064 #define DAGB3_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 7065 #define DAGB3_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 7066 #define DAGB3_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 7067 #define DAGB3_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 7068 #define DAGB3_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 7069 #define DAGB3_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 7070 #define DAGB3_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 7071 #define DAGB3_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 7072 #define DAGB3_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 7073 #define DAGB3_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 7074 #define DAGB3_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 7075 #define DAGB3_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 7076 #define DAGB3_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 7077 #define DAGB3_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 7078 #define DAGB3_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 7079 #define DAGB3_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 7080 #define DAGB3_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 7081 #define DAGB3_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L 7082 //DAGB3_FIFO_EMPTY 7083 #define DAGB3_FIFO_EMPTY__EMPTY__SHIFT 0x0 7084 #define DAGB3_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 7085 //DAGB3_FIFO_FULL 7086 #define DAGB3_FIFO_FULL__FULL__SHIFT 0x0 7087 #define DAGB3_FIFO_FULL__FULL_MASK 0x007FFFFFL 7088 //DAGB3_WR_CREDITS_FULL 7089 #define DAGB3_WR_CREDITS_FULL__FULL__SHIFT 0x0 7090 #define DAGB3_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 7091 //DAGB3_RD_CREDITS_FULL 7092 #define DAGB3_RD_CREDITS_FULL__FULL__SHIFT 0x0 7093 #define DAGB3_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 7094 //DAGB3_PERFCOUNTER_LO 7095 #define DAGB3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 7096 #define DAGB3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 7097 //DAGB3_PERFCOUNTER_HI 7098 #define DAGB3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 7099 #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 7100 #define DAGB3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 7101 #define DAGB3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 7102 //DAGB3_PERFCOUNTER0_CFG 7103 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 7104 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 7105 #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 7106 #define DAGB3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 7107 #define DAGB3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 7108 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 7109 #define DAGB3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 7110 #define DAGB3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 7111 #define DAGB3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 7112 #define DAGB3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 7113 //DAGB3_PERFCOUNTER1_CFG 7114 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 7115 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 7116 #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 7117 #define DAGB3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 7118 #define DAGB3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 7119 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 7120 #define DAGB3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 7121 #define DAGB3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 7122 #define DAGB3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 7123 #define DAGB3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 7124 //DAGB3_PERFCOUNTER2_CFG 7125 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 7126 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 7127 #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 7128 #define DAGB3_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 7129 #define DAGB3_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 7130 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 7131 #define DAGB3_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 7132 #define DAGB3_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 7133 #define DAGB3_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 7134 #define DAGB3_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 7135 //DAGB3_PERFCOUNTER_RSLT_CNTL 7136 #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 7137 #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 7138 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 7139 #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 7140 #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 7141 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 7142 #define DAGB3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 7143 #define DAGB3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 7144 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 7145 #define DAGB3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 7146 #define DAGB3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 7147 #define DAGB3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 7148 //DAGB3_L1TLB_REG_RW 7149 #define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 7150 #define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 7151 #define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 7152 #define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 7153 #define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 7154 #define DAGB3_L1TLB_REG_RW__RESERVE__SHIFT 0x6 7155 #define DAGB3_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 7156 #define DAGB3_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 7157 #define DAGB3_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L 7158 #define DAGB3_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L 7159 #define DAGB3_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L 7160 #define DAGB3_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L 7161 //DAGB3_RESERVE1 7162 #define DAGB3_RESERVE1__RESERVE__SHIFT 0x0 7163 #define DAGB3_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 7164 //DAGB3_RESERVE2 7165 #define DAGB3_RESERVE2__RESERVE__SHIFT 0x0 7166 #define DAGB3_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 7167 //DAGB3_RESERVE3 7168 #define DAGB3_RESERVE3__RESERVE__SHIFT 0x0 7169 #define DAGB3_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 7170 //DAGB3_RESERVE4 7171 #define DAGB3_RESERVE4__RESERVE__SHIFT 0x0 7172 #define DAGB3_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 7173 7174 7175 // addressBlock: mmhub_dagb_dagbdec4 7176 //DAGB4_RDCLI0 7177 #define DAGB4_RDCLI0__VIRT_CHAN__SHIFT 0x0 7178 #define DAGB4_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 7179 #define DAGB4_RDCLI0__URG_HIGH__SHIFT 0x4 7180 #define DAGB4_RDCLI0__URG_LOW__SHIFT 0x8 7181 #define DAGB4_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 7182 #define DAGB4_RDCLI0__MAX_BW__SHIFT 0xd 7183 #define DAGB4_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 7184 #define DAGB4_RDCLI0__MIN_BW__SHIFT 0x16 7185 #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 7186 #define DAGB4_RDCLI0__MAX_OSD__SHIFT 0x1a 7187 #define DAGB4_RDCLI0__VIRT_CHAN_MASK 0x00000007L 7188 #define DAGB4_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 7189 #define DAGB4_RDCLI0__URG_HIGH_MASK 0x000000F0L 7190 #define DAGB4_RDCLI0__URG_LOW_MASK 0x00000F00L 7191 #define DAGB4_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 7192 #define DAGB4_RDCLI0__MAX_BW_MASK 0x001FE000L 7193 #define DAGB4_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 7194 #define DAGB4_RDCLI0__MIN_BW_MASK 0x01C00000L 7195 #define DAGB4_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 7196 #define DAGB4_RDCLI0__MAX_OSD_MASK 0xFC000000L 7197 //DAGB4_RDCLI1 7198 #define DAGB4_RDCLI1__VIRT_CHAN__SHIFT 0x0 7199 #define DAGB4_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 7200 #define DAGB4_RDCLI1__URG_HIGH__SHIFT 0x4 7201 #define DAGB4_RDCLI1__URG_LOW__SHIFT 0x8 7202 #define DAGB4_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 7203 #define DAGB4_RDCLI1__MAX_BW__SHIFT 0xd 7204 #define DAGB4_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 7205 #define DAGB4_RDCLI1__MIN_BW__SHIFT 0x16 7206 #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 7207 #define DAGB4_RDCLI1__MAX_OSD__SHIFT 0x1a 7208 #define DAGB4_RDCLI1__VIRT_CHAN_MASK 0x00000007L 7209 #define DAGB4_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 7210 #define DAGB4_RDCLI1__URG_HIGH_MASK 0x000000F0L 7211 #define DAGB4_RDCLI1__URG_LOW_MASK 0x00000F00L 7212 #define DAGB4_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 7213 #define DAGB4_RDCLI1__MAX_BW_MASK 0x001FE000L 7214 #define DAGB4_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 7215 #define DAGB4_RDCLI1__MIN_BW_MASK 0x01C00000L 7216 #define DAGB4_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 7217 #define DAGB4_RDCLI1__MAX_OSD_MASK 0xFC000000L 7218 //DAGB4_RDCLI2 7219 #define DAGB4_RDCLI2__VIRT_CHAN__SHIFT 0x0 7220 #define DAGB4_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 7221 #define DAGB4_RDCLI2__URG_HIGH__SHIFT 0x4 7222 #define DAGB4_RDCLI2__URG_LOW__SHIFT 0x8 7223 #define DAGB4_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 7224 #define DAGB4_RDCLI2__MAX_BW__SHIFT 0xd 7225 #define DAGB4_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 7226 #define DAGB4_RDCLI2__MIN_BW__SHIFT 0x16 7227 #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 7228 #define DAGB4_RDCLI2__MAX_OSD__SHIFT 0x1a 7229 #define DAGB4_RDCLI2__VIRT_CHAN_MASK 0x00000007L 7230 #define DAGB4_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 7231 #define DAGB4_RDCLI2__URG_HIGH_MASK 0x000000F0L 7232 #define DAGB4_RDCLI2__URG_LOW_MASK 0x00000F00L 7233 #define DAGB4_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 7234 #define DAGB4_RDCLI2__MAX_BW_MASK 0x001FE000L 7235 #define DAGB4_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 7236 #define DAGB4_RDCLI2__MIN_BW_MASK 0x01C00000L 7237 #define DAGB4_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 7238 #define DAGB4_RDCLI2__MAX_OSD_MASK 0xFC000000L 7239 //DAGB4_RDCLI3 7240 #define DAGB4_RDCLI3__VIRT_CHAN__SHIFT 0x0 7241 #define DAGB4_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 7242 #define DAGB4_RDCLI3__URG_HIGH__SHIFT 0x4 7243 #define DAGB4_RDCLI3__URG_LOW__SHIFT 0x8 7244 #define DAGB4_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 7245 #define DAGB4_RDCLI3__MAX_BW__SHIFT 0xd 7246 #define DAGB4_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 7247 #define DAGB4_RDCLI3__MIN_BW__SHIFT 0x16 7248 #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 7249 #define DAGB4_RDCLI3__MAX_OSD__SHIFT 0x1a 7250 #define DAGB4_RDCLI3__VIRT_CHAN_MASK 0x00000007L 7251 #define DAGB4_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 7252 #define DAGB4_RDCLI3__URG_HIGH_MASK 0x000000F0L 7253 #define DAGB4_RDCLI3__URG_LOW_MASK 0x00000F00L 7254 #define DAGB4_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 7255 #define DAGB4_RDCLI3__MAX_BW_MASK 0x001FE000L 7256 #define DAGB4_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 7257 #define DAGB4_RDCLI3__MIN_BW_MASK 0x01C00000L 7258 #define DAGB4_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 7259 #define DAGB4_RDCLI3__MAX_OSD_MASK 0xFC000000L 7260 //DAGB4_RDCLI4 7261 #define DAGB4_RDCLI4__VIRT_CHAN__SHIFT 0x0 7262 #define DAGB4_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 7263 #define DAGB4_RDCLI4__URG_HIGH__SHIFT 0x4 7264 #define DAGB4_RDCLI4__URG_LOW__SHIFT 0x8 7265 #define DAGB4_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 7266 #define DAGB4_RDCLI4__MAX_BW__SHIFT 0xd 7267 #define DAGB4_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 7268 #define DAGB4_RDCLI4__MIN_BW__SHIFT 0x16 7269 #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 7270 #define DAGB4_RDCLI4__MAX_OSD__SHIFT 0x1a 7271 #define DAGB4_RDCLI4__VIRT_CHAN_MASK 0x00000007L 7272 #define DAGB4_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 7273 #define DAGB4_RDCLI4__URG_HIGH_MASK 0x000000F0L 7274 #define DAGB4_RDCLI4__URG_LOW_MASK 0x00000F00L 7275 #define DAGB4_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 7276 #define DAGB4_RDCLI4__MAX_BW_MASK 0x001FE000L 7277 #define DAGB4_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 7278 #define DAGB4_RDCLI4__MIN_BW_MASK 0x01C00000L 7279 #define DAGB4_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 7280 #define DAGB4_RDCLI4__MAX_OSD_MASK 0xFC000000L 7281 //DAGB4_RDCLI5 7282 #define DAGB4_RDCLI5__VIRT_CHAN__SHIFT 0x0 7283 #define DAGB4_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 7284 #define DAGB4_RDCLI5__URG_HIGH__SHIFT 0x4 7285 #define DAGB4_RDCLI5__URG_LOW__SHIFT 0x8 7286 #define DAGB4_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 7287 #define DAGB4_RDCLI5__MAX_BW__SHIFT 0xd 7288 #define DAGB4_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 7289 #define DAGB4_RDCLI5__MIN_BW__SHIFT 0x16 7290 #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 7291 #define DAGB4_RDCLI5__MAX_OSD__SHIFT 0x1a 7292 #define DAGB4_RDCLI5__VIRT_CHAN_MASK 0x00000007L 7293 #define DAGB4_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 7294 #define DAGB4_RDCLI5__URG_HIGH_MASK 0x000000F0L 7295 #define DAGB4_RDCLI5__URG_LOW_MASK 0x00000F00L 7296 #define DAGB4_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 7297 #define DAGB4_RDCLI5__MAX_BW_MASK 0x001FE000L 7298 #define DAGB4_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 7299 #define DAGB4_RDCLI5__MIN_BW_MASK 0x01C00000L 7300 #define DAGB4_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 7301 #define DAGB4_RDCLI5__MAX_OSD_MASK 0xFC000000L 7302 //DAGB4_RDCLI6 7303 #define DAGB4_RDCLI6__VIRT_CHAN__SHIFT 0x0 7304 #define DAGB4_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 7305 #define DAGB4_RDCLI6__URG_HIGH__SHIFT 0x4 7306 #define DAGB4_RDCLI6__URG_LOW__SHIFT 0x8 7307 #define DAGB4_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 7308 #define DAGB4_RDCLI6__MAX_BW__SHIFT 0xd 7309 #define DAGB4_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 7310 #define DAGB4_RDCLI6__MIN_BW__SHIFT 0x16 7311 #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 7312 #define DAGB4_RDCLI6__MAX_OSD__SHIFT 0x1a 7313 #define DAGB4_RDCLI6__VIRT_CHAN_MASK 0x00000007L 7314 #define DAGB4_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 7315 #define DAGB4_RDCLI6__URG_HIGH_MASK 0x000000F0L 7316 #define DAGB4_RDCLI6__URG_LOW_MASK 0x00000F00L 7317 #define DAGB4_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 7318 #define DAGB4_RDCLI6__MAX_BW_MASK 0x001FE000L 7319 #define DAGB4_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 7320 #define DAGB4_RDCLI6__MIN_BW_MASK 0x01C00000L 7321 #define DAGB4_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 7322 #define DAGB4_RDCLI6__MAX_OSD_MASK 0xFC000000L 7323 //DAGB4_RDCLI7 7324 #define DAGB4_RDCLI7__VIRT_CHAN__SHIFT 0x0 7325 #define DAGB4_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 7326 #define DAGB4_RDCLI7__URG_HIGH__SHIFT 0x4 7327 #define DAGB4_RDCLI7__URG_LOW__SHIFT 0x8 7328 #define DAGB4_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 7329 #define DAGB4_RDCLI7__MAX_BW__SHIFT 0xd 7330 #define DAGB4_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 7331 #define DAGB4_RDCLI7__MIN_BW__SHIFT 0x16 7332 #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 7333 #define DAGB4_RDCLI7__MAX_OSD__SHIFT 0x1a 7334 #define DAGB4_RDCLI7__VIRT_CHAN_MASK 0x00000007L 7335 #define DAGB4_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 7336 #define DAGB4_RDCLI7__URG_HIGH_MASK 0x000000F0L 7337 #define DAGB4_RDCLI7__URG_LOW_MASK 0x00000F00L 7338 #define DAGB4_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 7339 #define DAGB4_RDCLI7__MAX_BW_MASK 0x001FE000L 7340 #define DAGB4_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 7341 #define DAGB4_RDCLI7__MIN_BW_MASK 0x01C00000L 7342 #define DAGB4_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 7343 #define DAGB4_RDCLI7__MAX_OSD_MASK 0xFC000000L 7344 //DAGB4_RDCLI8 7345 #define DAGB4_RDCLI8__VIRT_CHAN__SHIFT 0x0 7346 #define DAGB4_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 7347 #define DAGB4_RDCLI8__URG_HIGH__SHIFT 0x4 7348 #define DAGB4_RDCLI8__URG_LOW__SHIFT 0x8 7349 #define DAGB4_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 7350 #define DAGB4_RDCLI8__MAX_BW__SHIFT 0xd 7351 #define DAGB4_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 7352 #define DAGB4_RDCLI8__MIN_BW__SHIFT 0x16 7353 #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 7354 #define DAGB4_RDCLI8__MAX_OSD__SHIFT 0x1a 7355 #define DAGB4_RDCLI8__VIRT_CHAN_MASK 0x00000007L 7356 #define DAGB4_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 7357 #define DAGB4_RDCLI8__URG_HIGH_MASK 0x000000F0L 7358 #define DAGB4_RDCLI8__URG_LOW_MASK 0x00000F00L 7359 #define DAGB4_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 7360 #define DAGB4_RDCLI8__MAX_BW_MASK 0x001FE000L 7361 #define DAGB4_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 7362 #define DAGB4_RDCLI8__MIN_BW_MASK 0x01C00000L 7363 #define DAGB4_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 7364 #define DAGB4_RDCLI8__MAX_OSD_MASK 0xFC000000L 7365 //DAGB4_RDCLI9 7366 #define DAGB4_RDCLI9__VIRT_CHAN__SHIFT 0x0 7367 #define DAGB4_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 7368 #define DAGB4_RDCLI9__URG_HIGH__SHIFT 0x4 7369 #define DAGB4_RDCLI9__URG_LOW__SHIFT 0x8 7370 #define DAGB4_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 7371 #define DAGB4_RDCLI9__MAX_BW__SHIFT 0xd 7372 #define DAGB4_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 7373 #define DAGB4_RDCLI9__MIN_BW__SHIFT 0x16 7374 #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 7375 #define DAGB4_RDCLI9__MAX_OSD__SHIFT 0x1a 7376 #define DAGB4_RDCLI9__VIRT_CHAN_MASK 0x00000007L 7377 #define DAGB4_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 7378 #define DAGB4_RDCLI9__URG_HIGH_MASK 0x000000F0L 7379 #define DAGB4_RDCLI9__URG_LOW_MASK 0x00000F00L 7380 #define DAGB4_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 7381 #define DAGB4_RDCLI9__MAX_BW_MASK 0x001FE000L 7382 #define DAGB4_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 7383 #define DAGB4_RDCLI9__MIN_BW_MASK 0x01C00000L 7384 #define DAGB4_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 7385 #define DAGB4_RDCLI9__MAX_OSD_MASK 0xFC000000L 7386 //DAGB4_RDCLI10 7387 #define DAGB4_RDCLI10__VIRT_CHAN__SHIFT 0x0 7388 #define DAGB4_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 7389 #define DAGB4_RDCLI10__URG_HIGH__SHIFT 0x4 7390 #define DAGB4_RDCLI10__URG_LOW__SHIFT 0x8 7391 #define DAGB4_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 7392 #define DAGB4_RDCLI10__MAX_BW__SHIFT 0xd 7393 #define DAGB4_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 7394 #define DAGB4_RDCLI10__MIN_BW__SHIFT 0x16 7395 #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 7396 #define DAGB4_RDCLI10__MAX_OSD__SHIFT 0x1a 7397 #define DAGB4_RDCLI10__VIRT_CHAN_MASK 0x00000007L 7398 #define DAGB4_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 7399 #define DAGB4_RDCLI10__URG_HIGH_MASK 0x000000F0L 7400 #define DAGB4_RDCLI10__URG_LOW_MASK 0x00000F00L 7401 #define DAGB4_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 7402 #define DAGB4_RDCLI10__MAX_BW_MASK 0x001FE000L 7403 #define DAGB4_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 7404 #define DAGB4_RDCLI10__MIN_BW_MASK 0x01C00000L 7405 #define DAGB4_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 7406 #define DAGB4_RDCLI10__MAX_OSD_MASK 0xFC000000L 7407 //DAGB4_RDCLI11 7408 #define DAGB4_RDCLI11__VIRT_CHAN__SHIFT 0x0 7409 #define DAGB4_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 7410 #define DAGB4_RDCLI11__URG_HIGH__SHIFT 0x4 7411 #define DAGB4_RDCLI11__URG_LOW__SHIFT 0x8 7412 #define DAGB4_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 7413 #define DAGB4_RDCLI11__MAX_BW__SHIFT 0xd 7414 #define DAGB4_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 7415 #define DAGB4_RDCLI11__MIN_BW__SHIFT 0x16 7416 #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 7417 #define DAGB4_RDCLI11__MAX_OSD__SHIFT 0x1a 7418 #define DAGB4_RDCLI11__VIRT_CHAN_MASK 0x00000007L 7419 #define DAGB4_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 7420 #define DAGB4_RDCLI11__URG_HIGH_MASK 0x000000F0L 7421 #define DAGB4_RDCLI11__URG_LOW_MASK 0x00000F00L 7422 #define DAGB4_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 7423 #define DAGB4_RDCLI11__MAX_BW_MASK 0x001FE000L 7424 #define DAGB4_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 7425 #define DAGB4_RDCLI11__MIN_BW_MASK 0x01C00000L 7426 #define DAGB4_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 7427 #define DAGB4_RDCLI11__MAX_OSD_MASK 0xFC000000L 7428 //DAGB4_RDCLI12 7429 #define DAGB4_RDCLI12__VIRT_CHAN__SHIFT 0x0 7430 #define DAGB4_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 7431 #define DAGB4_RDCLI12__URG_HIGH__SHIFT 0x4 7432 #define DAGB4_RDCLI12__URG_LOW__SHIFT 0x8 7433 #define DAGB4_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 7434 #define DAGB4_RDCLI12__MAX_BW__SHIFT 0xd 7435 #define DAGB4_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 7436 #define DAGB4_RDCLI12__MIN_BW__SHIFT 0x16 7437 #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 7438 #define DAGB4_RDCLI12__MAX_OSD__SHIFT 0x1a 7439 #define DAGB4_RDCLI12__VIRT_CHAN_MASK 0x00000007L 7440 #define DAGB4_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 7441 #define DAGB4_RDCLI12__URG_HIGH_MASK 0x000000F0L 7442 #define DAGB4_RDCLI12__URG_LOW_MASK 0x00000F00L 7443 #define DAGB4_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 7444 #define DAGB4_RDCLI12__MAX_BW_MASK 0x001FE000L 7445 #define DAGB4_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 7446 #define DAGB4_RDCLI12__MIN_BW_MASK 0x01C00000L 7447 #define DAGB4_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 7448 #define DAGB4_RDCLI12__MAX_OSD_MASK 0xFC000000L 7449 //DAGB4_RDCLI13 7450 #define DAGB4_RDCLI13__VIRT_CHAN__SHIFT 0x0 7451 #define DAGB4_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 7452 #define DAGB4_RDCLI13__URG_HIGH__SHIFT 0x4 7453 #define DAGB4_RDCLI13__URG_LOW__SHIFT 0x8 7454 #define DAGB4_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 7455 #define DAGB4_RDCLI13__MAX_BW__SHIFT 0xd 7456 #define DAGB4_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 7457 #define DAGB4_RDCLI13__MIN_BW__SHIFT 0x16 7458 #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 7459 #define DAGB4_RDCLI13__MAX_OSD__SHIFT 0x1a 7460 #define DAGB4_RDCLI13__VIRT_CHAN_MASK 0x00000007L 7461 #define DAGB4_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 7462 #define DAGB4_RDCLI13__URG_HIGH_MASK 0x000000F0L 7463 #define DAGB4_RDCLI13__URG_LOW_MASK 0x00000F00L 7464 #define DAGB4_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 7465 #define DAGB4_RDCLI13__MAX_BW_MASK 0x001FE000L 7466 #define DAGB4_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 7467 #define DAGB4_RDCLI13__MIN_BW_MASK 0x01C00000L 7468 #define DAGB4_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 7469 #define DAGB4_RDCLI13__MAX_OSD_MASK 0xFC000000L 7470 //DAGB4_RDCLI14 7471 #define DAGB4_RDCLI14__VIRT_CHAN__SHIFT 0x0 7472 #define DAGB4_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 7473 #define DAGB4_RDCLI14__URG_HIGH__SHIFT 0x4 7474 #define DAGB4_RDCLI14__URG_LOW__SHIFT 0x8 7475 #define DAGB4_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 7476 #define DAGB4_RDCLI14__MAX_BW__SHIFT 0xd 7477 #define DAGB4_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 7478 #define DAGB4_RDCLI14__MIN_BW__SHIFT 0x16 7479 #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 7480 #define DAGB4_RDCLI14__MAX_OSD__SHIFT 0x1a 7481 #define DAGB4_RDCLI14__VIRT_CHAN_MASK 0x00000007L 7482 #define DAGB4_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 7483 #define DAGB4_RDCLI14__URG_HIGH_MASK 0x000000F0L 7484 #define DAGB4_RDCLI14__URG_LOW_MASK 0x00000F00L 7485 #define DAGB4_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 7486 #define DAGB4_RDCLI14__MAX_BW_MASK 0x001FE000L 7487 #define DAGB4_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 7488 #define DAGB4_RDCLI14__MIN_BW_MASK 0x01C00000L 7489 #define DAGB4_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 7490 #define DAGB4_RDCLI14__MAX_OSD_MASK 0xFC000000L 7491 //DAGB4_RDCLI15 7492 #define DAGB4_RDCLI15__VIRT_CHAN__SHIFT 0x0 7493 #define DAGB4_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 7494 #define DAGB4_RDCLI15__URG_HIGH__SHIFT 0x4 7495 #define DAGB4_RDCLI15__URG_LOW__SHIFT 0x8 7496 #define DAGB4_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 7497 #define DAGB4_RDCLI15__MAX_BW__SHIFT 0xd 7498 #define DAGB4_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 7499 #define DAGB4_RDCLI15__MIN_BW__SHIFT 0x16 7500 #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 7501 #define DAGB4_RDCLI15__MAX_OSD__SHIFT 0x1a 7502 #define DAGB4_RDCLI15__VIRT_CHAN_MASK 0x00000007L 7503 #define DAGB4_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 7504 #define DAGB4_RDCLI15__URG_HIGH_MASK 0x000000F0L 7505 #define DAGB4_RDCLI15__URG_LOW_MASK 0x00000F00L 7506 #define DAGB4_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 7507 #define DAGB4_RDCLI15__MAX_BW_MASK 0x001FE000L 7508 #define DAGB4_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 7509 #define DAGB4_RDCLI15__MIN_BW_MASK 0x01C00000L 7510 #define DAGB4_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 7511 #define DAGB4_RDCLI15__MAX_OSD_MASK 0xFC000000L 7512 //DAGB4_RD_CNTL 7513 #define DAGB4_RD_CNTL__SCLK_FREQ__SHIFT 0x0 7514 #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 7515 #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 7516 #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 7517 #define DAGB4_RD_CNTL__IO_LEVEL__SHIFT 0x11 7518 #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 7519 #define DAGB4_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 7520 #define DAGB4_RD_CNTL__FIX_JUMP__SHIFT 0x1a 7521 #define DAGB4_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 7522 #define DAGB4_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 7523 #define DAGB4_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 7524 #define DAGB4_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 7525 #define DAGB4_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 7526 #define DAGB4_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 7527 #define DAGB4_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 7528 #define DAGB4_RD_CNTL__FIX_JUMP_MASK 0x04000000L 7529 //DAGB4_RD_GMI_CNTL 7530 #define DAGB4_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 7531 #define DAGB4_RD_GMI_CNTL__LEVEL__SHIFT 0x6 7532 #define DAGB4_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 7533 #define DAGB4_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 7534 #define DAGB4_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 7535 #define DAGB4_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 7536 #define DAGB4_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 7537 #define DAGB4_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 7538 //DAGB4_RD_ADDR_DAGB 7539 #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 7540 #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 7541 #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 7542 #define DAGB4_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 7543 #define DAGB4_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 7544 #define DAGB4_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 7545 #define DAGB4_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 7546 #define DAGB4_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 7547 #define DAGB4_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 7548 #define DAGB4_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 7549 //DAGB4_RD_OUTPUT_DAGB_MAX_BURST 7550 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 7551 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 7552 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 7553 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 7554 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 7555 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 7556 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 7557 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 7558 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 7559 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 7560 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 7561 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 7562 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 7563 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 7564 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 7565 #define DAGB4_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 7566 //DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER 7567 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 7568 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 7569 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 7570 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 7571 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 7572 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 7573 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 7574 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 7575 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 7576 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 7577 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 7578 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 7579 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 7580 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 7581 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 7582 #define DAGB4_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 7583 //DAGB4_RD_CGTT_CLK_CTRL 7584 #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7585 #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7586 #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7587 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7588 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7589 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7590 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7591 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7592 #define DAGB4_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7593 #define DAGB4_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7594 #define DAGB4_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7595 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7596 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7597 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7598 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7599 #define DAGB4_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7600 //DAGB4_L1TLB_RD_CGTT_CLK_CTRL 7601 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7602 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7603 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7604 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7605 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7606 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7607 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7608 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7609 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7610 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7611 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7612 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7613 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7614 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7615 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7616 #define DAGB4_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7617 //DAGB4_ATCVM_RD_CGTT_CLK_CTRL 7618 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 7619 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 7620 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 7621 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 7622 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 7623 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 7624 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 7625 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 7626 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 7627 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 7628 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 7629 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 7630 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 7631 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 7632 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 7633 #define DAGB4_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 7634 //DAGB4_RD_ADDR_DAGB_MAX_BURST0 7635 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 7636 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 7637 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 7638 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 7639 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 7640 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 7641 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 7642 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 7643 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 7644 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 7645 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 7646 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 7647 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 7648 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 7649 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 7650 #define DAGB4_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 7651 //DAGB4_RD_ADDR_DAGB_LAZY_TIMER0 7652 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 7653 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 7654 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 7655 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 7656 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 7657 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 7658 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 7659 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 7660 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 7661 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 7662 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 7663 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 7664 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 7665 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 7666 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 7667 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 7668 //DAGB4_RD_ADDR_DAGB_MAX_BURST1 7669 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 7670 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 7671 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 7672 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 7673 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 7674 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 7675 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 7676 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 7677 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 7678 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 7679 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 7680 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 7681 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 7682 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 7683 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 7684 #define DAGB4_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 7685 //DAGB4_RD_ADDR_DAGB_LAZY_TIMER1 7686 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 7687 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 7688 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 7689 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 7690 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 7691 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 7692 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 7693 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 7694 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 7695 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 7696 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 7697 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 7698 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 7699 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 7700 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 7701 #define DAGB4_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 7702 //DAGB4_RD_VC0_CNTL 7703 #define DAGB4_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 7704 #define DAGB4_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 7705 #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7706 #define DAGB4_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 7707 #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7708 #define DAGB4_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 7709 #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7710 #define DAGB4_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 7711 #define DAGB4_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 7712 #define DAGB4_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 7713 #define DAGB4_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7714 #define DAGB4_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 7715 #define DAGB4_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7716 #define DAGB4_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 7717 #define DAGB4_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7718 #define DAGB4_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 7719 //DAGB4_RD_VC1_CNTL 7720 #define DAGB4_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 7721 #define DAGB4_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 7722 #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7723 #define DAGB4_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 7724 #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7725 #define DAGB4_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 7726 #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7727 #define DAGB4_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 7728 #define DAGB4_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 7729 #define DAGB4_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 7730 #define DAGB4_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7731 #define DAGB4_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 7732 #define DAGB4_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7733 #define DAGB4_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 7734 #define DAGB4_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7735 #define DAGB4_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 7736 //DAGB4_RD_VC2_CNTL 7737 #define DAGB4_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 7738 #define DAGB4_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 7739 #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7740 #define DAGB4_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 7741 #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7742 #define DAGB4_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 7743 #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7744 #define DAGB4_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 7745 #define DAGB4_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 7746 #define DAGB4_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 7747 #define DAGB4_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7748 #define DAGB4_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 7749 #define DAGB4_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7750 #define DAGB4_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 7751 #define DAGB4_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7752 #define DAGB4_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 7753 //DAGB4_RD_VC3_CNTL 7754 #define DAGB4_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 7755 #define DAGB4_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 7756 #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7757 #define DAGB4_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 7758 #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7759 #define DAGB4_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 7760 #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7761 #define DAGB4_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 7762 #define DAGB4_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 7763 #define DAGB4_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 7764 #define DAGB4_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7765 #define DAGB4_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 7766 #define DAGB4_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7767 #define DAGB4_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 7768 #define DAGB4_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7769 #define DAGB4_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 7770 //DAGB4_RD_VC4_CNTL 7771 #define DAGB4_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 7772 #define DAGB4_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 7773 #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7774 #define DAGB4_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 7775 #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7776 #define DAGB4_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 7777 #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7778 #define DAGB4_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 7779 #define DAGB4_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 7780 #define DAGB4_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 7781 #define DAGB4_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7782 #define DAGB4_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 7783 #define DAGB4_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7784 #define DAGB4_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 7785 #define DAGB4_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7786 #define DAGB4_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 7787 //DAGB4_RD_VC5_CNTL 7788 #define DAGB4_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 7789 #define DAGB4_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 7790 #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7791 #define DAGB4_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 7792 #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7793 #define DAGB4_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 7794 #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7795 #define DAGB4_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 7796 #define DAGB4_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 7797 #define DAGB4_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 7798 #define DAGB4_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7799 #define DAGB4_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 7800 #define DAGB4_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7801 #define DAGB4_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 7802 #define DAGB4_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7803 #define DAGB4_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 7804 //DAGB4_RD_VC6_CNTL 7805 #define DAGB4_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 7806 #define DAGB4_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 7807 #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7808 #define DAGB4_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 7809 #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7810 #define DAGB4_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 7811 #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7812 #define DAGB4_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 7813 #define DAGB4_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 7814 #define DAGB4_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 7815 #define DAGB4_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7816 #define DAGB4_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 7817 #define DAGB4_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7818 #define DAGB4_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 7819 #define DAGB4_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7820 #define DAGB4_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 7821 //DAGB4_RD_VC7_CNTL 7822 #define DAGB4_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 7823 #define DAGB4_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 7824 #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 7825 #define DAGB4_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 7826 #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 7827 #define DAGB4_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 7828 #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 7829 #define DAGB4_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 7830 #define DAGB4_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 7831 #define DAGB4_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 7832 #define DAGB4_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 7833 #define DAGB4_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 7834 #define DAGB4_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 7835 #define DAGB4_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 7836 #define DAGB4_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 7837 #define DAGB4_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 7838 //DAGB4_RD_CNTL_MISC 7839 #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 7840 #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 7841 #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 7842 #define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 7843 #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 7844 #define DAGB4_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 7845 #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 7846 #define DAGB4_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 7847 #define DAGB4_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 7848 #define DAGB4_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 7849 #define DAGB4_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 7850 #define DAGB4_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 7851 #define DAGB4_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 7852 #define DAGB4_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 7853 //DAGB4_RD_TLB_CREDIT 7854 #define DAGB4_RD_TLB_CREDIT__TLB0__SHIFT 0x0 7855 #define DAGB4_RD_TLB_CREDIT__TLB1__SHIFT 0x5 7856 #define DAGB4_RD_TLB_CREDIT__TLB2__SHIFT 0xa 7857 #define DAGB4_RD_TLB_CREDIT__TLB3__SHIFT 0xf 7858 #define DAGB4_RD_TLB_CREDIT__TLB4__SHIFT 0x14 7859 #define DAGB4_RD_TLB_CREDIT__TLB5__SHIFT 0x19 7860 #define DAGB4_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 7861 #define DAGB4_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 7862 #define DAGB4_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 7863 #define DAGB4_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 7864 #define DAGB4_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 7865 #define DAGB4_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 7866 //DAGB4_RD_RDRET_CREDIT_CNTL 7867 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 7868 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 7869 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc 7870 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 7871 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 7872 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 7873 #define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 7874 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL 7875 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L 7876 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L 7877 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L 7878 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L 7879 #define DAGB4_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 7880 #define DAGB4_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 7881 //DAGB4_RD_RDRET_CREDIT_CNTL2 7882 #define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 7883 #define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 7884 #define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc 7885 #define DAGB4_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL 7886 #define DAGB4_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L 7887 #define DAGB4_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L 7888 //DAGB4_RDCLI_ASK_PENDING 7889 #define DAGB4_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 7890 #define DAGB4_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 7891 //DAGB4_RDCLI_GO_PENDING 7892 #define DAGB4_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 7893 #define DAGB4_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 7894 //DAGB4_RDCLI_GBLSEND_PENDING 7895 #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 7896 #define DAGB4_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 7897 //DAGB4_RDCLI_TLB_PENDING 7898 #define DAGB4_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 7899 #define DAGB4_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 7900 //DAGB4_RDCLI_OARB_PENDING 7901 #define DAGB4_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 7902 #define DAGB4_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 7903 //DAGB4_RDCLI_OSD_PENDING 7904 #define DAGB4_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 7905 #define DAGB4_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 7906 //DAGB4_WRCLI0 7907 #define DAGB4_WRCLI0__VIRT_CHAN__SHIFT 0x0 7908 #define DAGB4_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 7909 #define DAGB4_WRCLI0__URG_HIGH__SHIFT 0x4 7910 #define DAGB4_WRCLI0__URG_LOW__SHIFT 0x8 7911 #define DAGB4_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 7912 #define DAGB4_WRCLI0__MAX_BW__SHIFT 0xd 7913 #define DAGB4_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 7914 #define DAGB4_WRCLI0__MIN_BW__SHIFT 0x16 7915 #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 7916 #define DAGB4_WRCLI0__MAX_OSD__SHIFT 0x1a 7917 #define DAGB4_WRCLI0__VIRT_CHAN_MASK 0x00000007L 7918 #define DAGB4_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 7919 #define DAGB4_WRCLI0__URG_HIGH_MASK 0x000000F0L 7920 #define DAGB4_WRCLI0__URG_LOW_MASK 0x00000F00L 7921 #define DAGB4_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 7922 #define DAGB4_WRCLI0__MAX_BW_MASK 0x001FE000L 7923 #define DAGB4_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 7924 #define DAGB4_WRCLI0__MIN_BW_MASK 0x01C00000L 7925 #define DAGB4_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 7926 #define DAGB4_WRCLI0__MAX_OSD_MASK 0xFC000000L 7927 //DAGB4_WRCLI1 7928 #define DAGB4_WRCLI1__VIRT_CHAN__SHIFT 0x0 7929 #define DAGB4_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 7930 #define DAGB4_WRCLI1__URG_HIGH__SHIFT 0x4 7931 #define DAGB4_WRCLI1__URG_LOW__SHIFT 0x8 7932 #define DAGB4_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 7933 #define DAGB4_WRCLI1__MAX_BW__SHIFT 0xd 7934 #define DAGB4_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 7935 #define DAGB4_WRCLI1__MIN_BW__SHIFT 0x16 7936 #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 7937 #define DAGB4_WRCLI1__MAX_OSD__SHIFT 0x1a 7938 #define DAGB4_WRCLI1__VIRT_CHAN_MASK 0x00000007L 7939 #define DAGB4_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 7940 #define DAGB4_WRCLI1__URG_HIGH_MASK 0x000000F0L 7941 #define DAGB4_WRCLI1__URG_LOW_MASK 0x00000F00L 7942 #define DAGB4_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 7943 #define DAGB4_WRCLI1__MAX_BW_MASK 0x001FE000L 7944 #define DAGB4_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 7945 #define DAGB4_WRCLI1__MIN_BW_MASK 0x01C00000L 7946 #define DAGB4_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 7947 #define DAGB4_WRCLI1__MAX_OSD_MASK 0xFC000000L 7948 //DAGB4_WRCLI2 7949 #define DAGB4_WRCLI2__VIRT_CHAN__SHIFT 0x0 7950 #define DAGB4_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 7951 #define DAGB4_WRCLI2__URG_HIGH__SHIFT 0x4 7952 #define DAGB4_WRCLI2__URG_LOW__SHIFT 0x8 7953 #define DAGB4_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 7954 #define DAGB4_WRCLI2__MAX_BW__SHIFT 0xd 7955 #define DAGB4_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 7956 #define DAGB4_WRCLI2__MIN_BW__SHIFT 0x16 7957 #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 7958 #define DAGB4_WRCLI2__MAX_OSD__SHIFT 0x1a 7959 #define DAGB4_WRCLI2__VIRT_CHAN_MASK 0x00000007L 7960 #define DAGB4_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 7961 #define DAGB4_WRCLI2__URG_HIGH_MASK 0x000000F0L 7962 #define DAGB4_WRCLI2__URG_LOW_MASK 0x00000F00L 7963 #define DAGB4_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 7964 #define DAGB4_WRCLI2__MAX_BW_MASK 0x001FE000L 7965 #define DAGB4_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 7966 #define DAGB4_WRCLI2__MIN_BW_MASK 0x01C00000L 7967 #define DAGB4_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 7968 #define DAGB4_WRCLI2__MAX_OSD_MASK 0xFC000000L 7969 //DAGB4_WRCLI3 7970 #define DAGB4_WRCLI3__VIRT_CHAN__SHIFT 0x0 7971 #define DAGB4_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 7972 #define DAGB4_WRCLI3__URG_HIGH__SHIFT 0x4 7973 #define DAGB4_WRCLI3__URG_LOW__SHIFT 0x8 7974 #define DAGB4_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 7975 #define DAGB4_WRCLI3__MAX_BW__SHIFT 0xd 7976 #define DAGB4_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 7977 #define DAGB4_WRCLI3__MIN_BW__SHIFT 0x16 7978 #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 7979 #define DAGB4_WRCLI3__MAX_OSD__SHIFT 0x1a 7980 #define DAGB4_WRCLI3__VIRT_CHAN_MASK 0x00000007L 7981 #define DAGB4_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 7982 #define DAGB4_WRCLI3__URG_HIGH_MASK 0x000000F0L 7983 #define DAGB4_WRCLI3__URG_LOW_MASK 0x00000F00L 7984 #define DAGB4_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 7985 #define DAGB4_WRCLI3__MAX_BW_MASK 0x001FE000L 7986 #define DAGB4_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 7987 #define DAGB4_WRCLI3__MIN_BW_MASK 0x01C00000L 7988 #define DAGB4_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 7989 #define DAGB4_WRCLI3__MAX_OSD_MASK 0xFC000000L 7990 //DAGB4_WRCLI4 7991 #define DAGB4_WRCLI4__VIRT_CHAN__SHIFT 0x0 7992 #define DAGB4_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 7993 #define DAGB4_WRCLI4__URG_HIGH__SHIFT 0x4 7994 #define DAGB4_WRCLI4__URG_LOW__SHIFT 0x8 7995 #define DAGB4_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 7996 #define DAGB4_WRCLI4__MAX_BW__SHIFT 0xd 7997 #define DAGB4_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 7998 #define DAGB4_WRCLI4__MIN_BW__SHIFT 0x16 7999 #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 8000 #define DAGB4_WRCLI4__MAX_OSD__SHIFT 0x1a 8001 #define DAGB4_WRCLI4__VIRT_CHAN_MASK 0x00000007L 8002 #define DAGB4_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 8003 #define DAGB4_WRCLI4__URG_HIGH_MASK 0x000000F0L 8004 #define DAGB4_WRCLI4__URG_LOW_MASK 0x00000F00L 8005 #define DAGB4_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 8006 #define DAGB4_WRCLI4__MAX_BW_MASK 0x001FE000L 8007 #define DAGB4_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 8008 #define DAGB4_WRCLI4__MIN_BW_MASK 0x01C00000L 8009 #define DAGB4_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 8010 #define DAGB4_WRCLI4__MAX_OSD_MASK 0xFC000000L 8011 //DAGB4_WRCLI5 8012 #define DAGB4_WRCLI5__VIRT_CHAN__SHIFT 0x0 8013 #define DAGB4_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 8014 #define DAGB4_WRCLI5__URG_HIGH__SHIFT 0x4 8015 #define DAGB4_WRCLI5__URG_LOW__SHIFT 0x8 8016 #define DAGB4_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 8017 #define DAGB4_WRCLI5__MAX_BW__SHIFT 0xd 8018 #define DAGB4_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 8019 #define DAGB4_WRCLI5__MIN_BW__SHIFT 0x16 8020 #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 8021 #define DAGB4_WRCLI5__MAX_OSD__SHIFT 0x1a 8022 #define DAGB4_WRCLI5__VIRT_CHAN_MASK 0x00000007L 8023 #define DAGB4_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 8024 #define DAGB4_WRCLI5__URG_HIGH_MASK 0x000000F0L 8025 #define DAGB4_WRCLI5__URG_LOW_MASK 0x00000F00L 8026 #define DAGB4_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 8027 #define DAGB4_WRCLI5__MAX_BW_MASK 0x001FE000L 8028 #define DAGB4_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 8029 #define DAGB4_WRCLI5__MIN_BW_MASK 0x01C00000L 8030 #define DAGB4_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 8031 #define DAGB4_WRCLI5__MAX_OSD_MASK 0xFC000000L 8032 //DAGB4_WRCLI6 8033 #define DAGB4_WRCLI6__VIRT_CHAN__SHIFT 0x0 8034 #define DAGB4_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 8035 #define DAGB4_WRCLI6__URG_HIGH__SHIFT 0x4 8036 #define DAGB4_WRCLI6__URG_LOW__SHIFT 0x8 8037 #define DAGB4_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 8038 #define DAGB4_WRCLI6__MAX_BW__SHIFT 0xd 8039 #define DAGB4_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 8040 #define DAGB4_WRCLI6__MIN_BW__SHIFT 0x16 8041 #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 8042 #define DAGB4_WRCLI6__MAX_OSD__SHIFT 0x1a 8043 #define DAGB4_WRCLI6__VIRT_CHAN_MASK 0x00000007L 8044 #define DAGB4_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 8045 #define DAGB4_WRCLI6__URG_HIGH_MASK 0x000000F0L 8046 #define DAGB4_WRCLI6__URG_LOW_MASK 0x00000F00L 8047 #define DAGB4_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 8048 #define DAGB4_WRCLI6__MAX_BW_MASK 0x001FE000L 8049 #define DAGB4_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 8050 #define DAGB4_WRCLI6__MIN_BW_MASK 0x01C00000L 8051 #define DAGB4_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 8052 #define DAGB4_WRCLI6__MAX_OSD_MASK 0xFC000000L 8053 //DAGB4_WRCLI7 8054 #define DAGB4_WRCLI7__VIRT_CHAN__SHIFT 0x0 8055 #define DAGB4_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 8056 #define DAGB4_WRCLI7__URG_HIGH__SHIFT 0x4 8057 #define DAGB4_WRCLI7__URG_LOW__SHIFT 0x8 8058 #define DAGB4_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 8059 #define DAGB4_WRCLI7__MAX_BW__SHIFT 0xd 8060 #define DAGB4_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 8061 #define DAGB4_WRCLI7__MIN_BW__SHIFT 0x16 8062 #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 8063 #define DAGB4_WRCLI7__MAX_OSD__SHIFT 0x1a 8064 #define DAGB4_WRCLI7__VIRT_CHAN_MASK 0x00000007L 8065 #define DAGB4_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 8066 #define DAGB4_WRCLI7__URG_HIGH_MASK 0x000000F0L 8067 #define DAGB4_WRCLI7__URG_LOW_MASK 0x00000F00L 8068 #define DAGB4_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 8069 #define DAGB4_WRCLI7__MAX_BW_MASK 0x001FE000L 8070 #define DAGB4_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 8071 #define DAGB4_WRCLI7__MIN_BW_MASK 0x01C00000L 8072 #define DAGB4_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 8073 #define DAGB4_WRCLI7__MAX_OSD_MASK 0xFC000000L 8074 //DAGB4_WRCLI8 8075 #define DAGB4_WRCLI8__VIRT_CHAN__SHIFT 0x0 8076 #define DAGB4_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 8077 #define DAGB4_WRCLI8__URG_HIGH__SHIFT 0x4 8078 #define DAGB4_WRCLI8__URG_LOW__SHIFT 0x8 8079 #define DAGB4_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 8080 #define DAGB4_WRCLI8__MAX_BW__SHIFT 0xd 8081 #define DAGB4_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 8082 #define DAGB4_WRCLI8__MIN_BW__SHIFT 0x16 8083 #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 8084 #define DAGB4_WRCLI8__MAX_OSD__SHIFT 0x1a 8085 #define DAGB4_WRCLI8__VIRT_CHAN_MASK 0x00000007L 8086 #define DAGB4_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 8087 #define DAGB4_WRCLI8__URG_HIGH_MASK 0x000000F0L 8088 #define DAGB4_WRCLI8__URG_LOW_MASK 0x00000F00L 8089 #define DAGB4_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 8090 #define DAGB4_WRCLI8__MAX_BW_MASK 0x001FE000L 8091 #define DAGB4_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 8092 #define DAGB4_WRCLI8__MIN_BW_MASK 0x01C00000L 8093 #define DAGB4_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 8094 #define DAGB4_WRCLI8__MAX_OSD_MASK 0xFC000000L 8095 //DAGB4_WRCLI9 8096 #define DAGB4_WRCLI9__VIRT_CHAN__SHIFT 0x0 8097 #define DAGB4_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 8098 #define DAGB4_WRCLI9__URG_HIGH__SHIFT 0x4 8099 #define DAGB4_WRCLI9__URG_LOW__SHIFT 0x8 8100 #define DAGB4_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 8101 #define DAGB4_WRCLI9__MAX_BW__SHIFT 0xd 8102 #define DAGB4_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 8103 #define DAGB4_WRCLI9__MIN_BW__SHIFT 0x16 8104 #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 8105 #define DAGB4_WRCLI9__MAX_OSD__SHIFT 0x1a 8106 #define DAGB4_WRCLI9__VIRT_CHAN_MASK 0x00000007L 8107 #define DAGB4_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 8108 #define DAGB4_WRCLI9__URG_HIGH_MASK 0x000000F0L 8109 #define DAGB4_WRCLI9__URG_LOW_MASK 0x00000F00L 8110 #define DAGB4_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 8111 #define DAGB4_WRCLI9__MAX_BW_MASK 0x001FE000L 8112 #define DAGB4_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 8113 #define DAGB4_WRCLI9__MIN_BW_MASK 0x01C00000L 8114 #define DAGB4_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 8115 #define DAGB4_WRCLI9__MAX_OSD_MASK 0xFC000000L 8116 //DAGB4_WRCLI10 8117 #define DAGB4_WRCLI10__VIRT_CHAN__SHIFT 0x0 8118 #define DAGB4_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 8119 #define DAGB4_WRCLI10__URG_HIGH__SHIFT 0x4 8120 #define DAGB4_WRCLI10__URG_LOW__SHIFT 0x8 8121 #define DAGB4_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 8122 #define DAGB4_WRCLI10__MAX_BW__SHIFT 0xd 8123 #define DAGB4_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 8124 #define DAGB4_WRCLI10__MIN_BW__SHIFT 0x16 8125 #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 8126 #define DAGB4_WRCLI10__MAX_OSD__SHIFT 0x1a 8127 #define DAGB4_WRCLI10__VIRT_CHAN_MASK 0x00000007L 8128 #define DAGB4_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 8129 #define DAGB4_WRCLI10__URG_HIGH_MASK 0x000000F0L 8130 #define DAGB4_WRCLI10__URG_LOW_MASK 0x00000F00L 8131 #define DAGB4_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 8132 #define DAGB4_WRCLI10__MAX_BW_MASK 0x001FE000L 8133 #define DAGB4_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 8134 #define DAGB4_WRCLI10__MIN_BW_MASK 0x01C00000L 8135 #define DAGB4_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 8136 #define DAGB4_WRCLI10__MAX_OSD_MASK 0xFC000000L 8137 //DAGB4_WRCLI11 8138 #define DAGB4_WRCLI11__VIRT_CHAN__SHIFT 0x0 8139 #define DAGB4_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 8140 #define DAGB4_WRCLI11__URG_HIGH__SHIFT 0x4 8141 #define DAGB4_WRCLI11__URG_LOW__SHIFT 0x8 8142 #define DAGB4_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 8143 #define DAGB4_WRCLI11__MAX_BW__SHIFT 0xd 8144 #define DAGB4_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 8145 #define DAGB4_WRCLI11__MIN_BW__SHIFT 0x16 8146 #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 8147 #define DAGB4_WRCLI11__MAX_OSD__SHIFT 0x1a 8148 #define DAGB4_WRCLI11__VIRT_CHAN_MASK 0x00000007L 8149 #define DAGB4_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 8150 #define DAGB4_WRCLI11__URG_HIGH_MASK 0x000000F0L 8151 #define DAGB4_WRCLI11__URG_LOW_MASK 0x00000F00L 8152 #define DAGB4_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 8153 #define DAGB4_WRCLI11__MAX_BW_MASK 0x001FE000L 8154 #define DAGB4_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 8155 #define DAGB4_WRCLI11__MIN_BW_MASK 0x01C00000L 8156 #define DAGB4_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 8157 #define DAGB4_WRCLI11__MAX_OSD_MASK 0xFC000000L 8158 //DAGB4_WRCLI12 8159 #define DAGB4_WRCLI12__VIRT_CHAN__SHIFT 0x0 8160 #define DAGB4_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 8161 #define DAGB4_WRCLI12__URG_HIGH__SHIFT 0x4 8162 #define DAGB4_WRCLI12__URG_LOW__SHIFT 0x8 8163 #define DAGB4_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 8164 #define DAGB4_WRCLI12__MAX_BW__SHIFT 0xd 8165 #define DAGB4_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 8166 #define DAGB4_WRCLI12__MIN_BW__SHIFT 0x16 8167 #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 8168 #define DAGB4_WRCLI12__MAX_OSD__SHIFT 0x1a 8169 #define DAGB4_WRCLI12__VIRT_CHAN_MASK 0x00000007L 8170 #define DAGB4_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 8171 #define DAGB4_WRCLI12__URG_HIGH_MASK 0x000000F0L 8172 #define DAGB4_WRCLI12__URG_LOW_MASK 0x00000F00L 8173 #define DAGB4_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 8174 #define DAGB4_WRCLI12__MAX_BW_MASK 0x001FE000L 8175 #define DAGB4_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 8176 #define DAGB4_WRCLI12__MIN_BW_MASK 0x01C00000L 8177 #define DAGB4_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 8178 #define DAGB4_WRCLI12__MAX_OSD_MASK 0xFC000000L 8179 //DAGB4_WRCLI13 8180 #define DAGB4_WRCLI13__VIRT_CHAN__SHIFT 0x0 8181 #define DAGB4_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 8182 #define DAGB4_WRCLI13__URG_HIGH__SHIFT 0x4 8183 #define DAGB4_WRCLI13__URG_LOW__SHIFT 0x8 8184 #define DAGB4_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 8185 #define DAGB4_WRCLI13__MAX_BW__SHIFT 0xd 8186 #define DAGB4_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 8187 #define DAGB4_WRCLI13__MIN_BW__SHIFT 0x16 8188 #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 8189 #define DAGB4_WRCLI13__MAX_OSD__SHIFT 0x1a 8190 #define DAGB4_WRCLI13__VIRT_CHAN_MASK 0x00000007L 8191 #define DAGB4_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 8192 #define DAGB4_WRCLI13__URG_HIGH_MASK 0x000000F0L 8193 #define DAGB4_WRCLI13__URG_LOW_MASK 0x00000F00L 8194 #define DAGB4_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 8195 #define DAGB4_WRCLI13__MAX_BW_MASK 0x001FE000L 8196 #define DAGB4_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 8197 #define DAGB4_WRCLI13__MIN_BW_MASK 0x01C00000L 8198 #define DAGB4_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 8199 #define DAGB4_WRCLI13__MAX_OSD_MASK 0xFC000000L 8200 //DAGB4_WRCLI14 8201 #define DAGB4_WRCLI14__VIRT_CHAN__SHIFT 0x0 8202 #define DAGB4_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 8203 #define DAGB4_WRCLI14__URG_HIGH__SHIFT 0x4 8204 #define DAGB4_WRCLI14__URG_LOW__SHIFT 0x8 8205 #define DAGB4_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 8206 #define DAGB4_WRCLI14__MAX_BW__SHIFT 0xd 8207 #define DAGB4_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 8208 #define DAGB4_WRCLI14__MIN_BW__SHIFT 0x16 8209 #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 8210 #define DAGB4_WRCLI14__MAX_OSD__SHIFT 0x1a 8211 #define DAGB4_WRCLI14__VIRT_CHAN_MASK 0x00000007L 8212 #define DAGB4_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 8213 #define DAGB4_WRCLI14__URG_HIGH_MASK 0x000000F0L 8214 #define DAGB4_WRCLI14__URG_LOW_MASK 0x00000F00L 8215 #define DAGB4_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 8216 #define DAGB4_WRCLI14__MAX_BW_MASK 0x001FE000L 8217 #define DAGB4_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 8218 #define DAGB4_WRCLI14__MIN_BW_MASK 0x01C00000L 8219 #define DAGB4_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 8220 #define DAGB4_WRCLI14__MAX_OSD_MASK 0xFC000000L 8221 //DAGB4_WRCLI15 8222 #define DAGB4_WRCLI15__VIRT_CHAN__SHIFT 0x0 8223 #define DAGB4_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 8224 #define DAGB4_WRCLI15__URG_HIGH__SHIFT 0x4 8225 #define DAGB4_WRCLI15__URG_LOW__SHIFT 0x8 8226 #define DAGB4_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 8227 #define DAGB4_WRCLI15__MAX_BW__SHIFT 0xd 8228 #define DAGB4_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 8229 #define DAGB4_WRCLI15__MIN_BW__SHIFT 0x16 8230 #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 8231 #define DAGB4_WRCLI15__MAX_OSD__SHIFT 0x1a 8232 #define DAGB4_WRCLI15__VIRT_CHAN_MASK 0x00000007L 8233 #define DAGB4_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 8234 #define DAGB4_WRCLI15__URG_HIGH_MASK 0x000000F0L 8235 #define DAGB4_WRCLI15__URG_LOW_MASK 0x00000F00L 8236 #define DAGB4_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 8237 #define DAGB4_WRCLI15__MAX_BW_MASK 0x001FE000L 8238 #define DAGB4_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 8239 #define DAGB4_WRCLI15__MIN_BW_MASK 0x01C00000L 8240 #define DAGB4_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 8241 #define DAGB4_WRCLI15__MAX_OSD_MASK 0xFC000000L 8242 //DAGB4_WR_CNTL 8243 #define DAGB4_WR_CNTL__SCLK_FREQ__SHIFT 0x0 8244 #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 8245 #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 8246 #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 8247 #define DAGB4_WR_CNTL__IO_LEVEL__SHIFT 0x11 8248 #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 8249 #define DAGB4_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 8250 #define DAGB4_WR_CNTL__FIX_JUMP__SHIFT 0x1a 8251 #define DAGB4_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 8252 #define DAGB4_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 8253 #define DAGB4_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 8254 #define DAGB4_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 8255 #define DAGB4_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 8256 #define DAGB4_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 8257 #define DAGB4_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 8258 #define DAGB4_WR_CNTL__FIX_JUMP_MASK 0x04000000L 8259 //DAGB4_WR_GMI_CNTL 8260 #define DAGB4_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 8261 #define DAGB4_WR_GMI_CNTL__LEVEL__SHIFT 0x6 8262 #define DAGB4_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 8263 #define DAGB4_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 8264 #define DAGB4_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 8265 #define DAGB4_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 8266 #define DAGB4_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 8267 #define DAGB4_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 8268 //DAGB4_WR_ADDR_DAGB 8269 #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 8270 #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 8271 #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 8272 #define DAGB4_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 8273 #define DAGB4_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 8274 #define DAGB4_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 8275 #define DAGB4_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 8276 #define DAGB4_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 8277 #define DAGB4_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 8278 #define DAGB4_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 8279 //DAGB4_WR_OUTPUT_DAGB_MAX_BURST 8280 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 8281 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 8282 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 8283 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 8284 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 8285 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 8286 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 8287 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 8288 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 8289 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 8290 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 8291 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 8292 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 8293 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 8294 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 8295 #define DAGB4_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 8296 //DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER 8297 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 8298 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 8299 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 8300 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 8301 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 8302 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 8303 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 8304 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 8305 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 8306 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 8307 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 8308 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 8309 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 8310 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 8311 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 8312 #define DAGB4_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 8313 //DAGB4_WR_CGTT_CLK_CTRL 8314 #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 8315 #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8316 #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 8317 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 8318 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 8319 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 8320 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 8321 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 8322 #define DAGB4_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 8323 #define DAGB4_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 8324 #define DAGB4_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 8325 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 8326 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 8327 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 8328 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 8329 #define DAGB4_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 8330 //DAGB4_L1TLB_WR_CGTT_CLK_CTRL 8331 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 8332 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8333 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 8334 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 8335 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 8336 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 8337 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 8338 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 8339 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 8340 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 8341 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 8342 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 8343 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 8344 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 8345 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 8346 #define DAGB4_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 8347 //DAGB4_ATCVM_WR_CGTT_CLK_CTRL 8348 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 8349 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 8350 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 8351 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 8352 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 8353 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 8354 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 8355 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 8356 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 8357 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 8358 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 8359 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 8360 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 8361 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 8362 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 8363 #define DAGB4_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 8364 //DAGB4_WR_ADDR_DAGB_MAX_BURST0 8365 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 8366 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 8367 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 8368 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 8369 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 8370 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 8371 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 8372 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 8373 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 8374 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 8375 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 8376 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 8377 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 8378 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 8379 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 8380 #define DAGB4_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 8381 //DAGB4_WR_ADDR_DAGB_LAZY_TIMER0 8382 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 8383 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 8384 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 8385 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 8386 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 8387 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 8388 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 8389 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 8390 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 8391 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 8392 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 8393 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 8394 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 8395 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 8396 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 8397 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 8398 //DAGB4_WR_ADDR_DAGB_MAX_BURST1 8399 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 8400 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 8401 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 8402 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 8403 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 8404 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 8405 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 8406 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 8407 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 8408 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 8409 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 8410 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 8411 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 8412 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 8413 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 8414 #define DAGB4_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 8415 //DAGB4_WR_ADDR_DAGB_LAZY_TIMER1 8416 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 8417 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 8418 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 8419 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 8420 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 8421 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 8422 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 8423 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 8424 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 8425 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 8426 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 8427 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 8428 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 8429 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 8430 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 8431 #define DAGB4_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 8432 //DAGB4_WR_DATA_DAGB 8433 #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 8434 #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 8435 #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 8436 #define DAGB4_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 8437 #define DAGB4_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 8438 #define DAGB4_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 8439 #define DAGB4_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 8440 #define DAGB4_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 8441 //DAGB4_WR_DATA_DAGB_MAX_BURST0 8442 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 8443 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 8444 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 8445 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 8446 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 8447 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 8448 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 8449 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 8450 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 8451 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 8452 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 8453 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 8454 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 8455 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 8456 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 8457 #define DAGB4_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 8458 //DAGB4_WR_DATA_DAGB_LAZY_TIMER0 8459 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 8460 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 8461 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 8462 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 8463 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 8464 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 8465 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 8466 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 8467 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 8468 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 8469 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 8470 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 8471 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 8472 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 8473 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 8474 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 8475 //DAGB4_WR_DATA_DAGB_MAX_BURST1 8476 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 8477 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 8478 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 8479 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 8480 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 8481 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 8482 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 8483 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 8484 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 8485 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 8486 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 8487 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 8488 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 8489 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 8490 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 8491 #define DAGB4_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 8492 //DAGB4_WR_DATA_DAGB_LAZY_TIMER1 8493 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 8494 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 8495 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 8496 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 8497 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 8498 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 8499 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 8500 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 8501 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 8502 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 8503 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 8504 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 8505 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 8506 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 8507 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 8508 #define DAGB4_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 8509 //DAGB4_WR_VC0_CNTL 8510 #define DAGB4_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 8511 #define DAGB4_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 8512 #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8513 #define DAGB4_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 8514 #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8515 #define DAGB4_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 8516 #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8517 #define DAGB4_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 8518 #define DAGB4_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 8519 #define DAGB4_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 8520 #define DAGB4_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8521 #define DAGB4_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 8522 #define DAGB4_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8523 #define DAGB4_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 8524 #define DAGB4_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8525 #define DAGB4_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 8526 //DAGB4_WR_VC1_CNTL 8527 #define DAGB4_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 8528 #define DAGB4_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 8529 #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8530 #define DAGB4_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 8531 #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8532 #define DAGB4_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 8533 #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8534 #define DAGB4_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 8535 #define DAGB4_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 8536 #define DAGB4_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 8537 #define DAGB4_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8538 #define DAGB4_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 8539 #define DAGB4_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8540 #define DAGB4_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 8541 #define DAGB4_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8542 #define DAGB4_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 8543 //DAGB4_WR_VC2_CNTL 8544 #define DAGB4_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 8545 #define DAGB4_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 8546 #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8547 #define DAGB4_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 8548 #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8549 #define DAGB4_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 8550 #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8551 #define DAGB4_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 8552 #define DAGB4_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 8553 #define DAGB4_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 8554 #define DAGB4_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8555 #define DAGB4_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 8556 #define DAGB4_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8557 #define DAGB4_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 8558 #define DAGB4_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8559 #define DAGB4_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 8560 //DAGB4_WR_VC3_CNTL 8561 #define DAGB4_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 8562 #define DAGB4_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 8563 #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8564 #define DAGB4_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 8565 #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8566 #define DAGB4_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 8567 #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8568 #define DAGB4_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 8569 #define DAGB4_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 8570 #define DAGB4_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 8571 #define DAGB4_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8572 #define DAGB4_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 8573 #define DAGB4_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8574 #define DAGB4_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 8575 #define DAGB4_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8576 #define DAGB4_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 8577 //DAGB4_WR_VC4_CNTL 8578 #define DAGB4_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 8579 #define DAGB4_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 8580 #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8581 #define DAGB4_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 8582 #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8583 #define DAGB4_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 8584 #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8585 #define DAGB4_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 8586 #define DAGB4_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 8587 #define DAGB4_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 8588 #define DAGB4_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8589 #define DAGB4_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 8590 #define DAGB4_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8591 #define DAGB4_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 8592 #define DAGB4_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8593 #define DAGB4_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 8594 //DAGB4_WR_VC5_CNTL 8595 #define DAGB4_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 8596 #define DAGB4_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 8597 #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8598 #define DAGB4_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 8599 #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8600 #define DAGB4_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 8601 #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8602 #define DAGB4_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 8603 #define DAGB4_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 8604 #define DAGB4_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 8605 #define DAGB4_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8606 #define DAGB4_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 8607 #define DAGB4_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8608 #define DAGB4_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 8609 #define DAGB4_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8610 #define DAGB4_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 8611 //DAGB4_WR_VC6_CNTL 8612 #define DAGB4_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 8613 #define DAGB4_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 8614 #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8615 #define DAGB4_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 8616 #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8617 #define DAGB4_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 8618 #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8619 #define DAGB4_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 8620 #define DAGB4_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 8621 #define DAGB4_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 8622 #define DAGB4_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8623 #define DAGB4_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 8624 #define DAGB4_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8625 #define DAGB4_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 8626 #define DAGB4_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8627 #define DAGB4_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 8628 //DAGB4_WR_VC7_CNTL 8629 #define DAGB4_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 8630 #define DAGB4_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 8631 #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 8632 #define DAGB4_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 8633 #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 8634 #define DAGB4_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 8635 #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 8636 #define DAGB4_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 8637 #define DAGB4_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 8638 #define DAGB4_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 8639 #define DAGB4_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 8640 #define DAGB4_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 8641 #define DAGB4_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 8642 #define DAGB4_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 8643 #define DAGB4_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 8644 #define DAGB4_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 8645 //DAGB4_WR_CNTL_MISC 8646 #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 8647 #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 8648 #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 8649 #define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 8650 #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 8651 #define DAGB4_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 8652 #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 8653 #define DAGB4_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 8654 #define DAGB4_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 8655 #define DAGB4_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 8656 #define DAGB4_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 8657 #define DAGB4_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 8658 #define DAGB4_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 8659 #define DAGB4_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 8660 //DAGB4_WR_TLB_CREDIT 8661 #define DAGB4_WR_TLB_CREDIT__TLB0__SHIFT 0x0 8662 #define DAGB4_WR_TLB_CREDIT__TLB1__SHIFT 0x5 8663 #define DAGB4_WR_TLB_CREDIT__TLB2__SHIFT 0xa 8664 #define DAGB4_WR_TLB_CREDIT__TLB3__SHIFT 0xf 8665 #define DAGB4_WR_TLB_CREDIT__TLB4__SHIFT 0x14 8666 #define DAGB4_WR_TLB_CREDIT__TLB5__SHIFT 0x19 8667 #define DAGB4_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 8668 #define DAGB4_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 8669 #define DAGB4_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 8670 #define DAGB4_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 8671 #define DAGB4_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 8672 #define DAGB4_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 8673 //DAGB4_WR_DATA_CREDIT 8674 #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 8675 #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 8676 #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 8677 #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 8678 #define DAGB4_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 8679 #define DAGB4_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 8680 #define DAGB4_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 8681 #define DAGB4_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 8682 //DAGB4_WR_MISC_CREDIT 8683 #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 8684 #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 8685 #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 8686 #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 8687 #define DAGB4_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 8688 #define DAGB4_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 8689 #define DAGB4_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 8690 #define DAGB4_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 8691 //DAGB4_WR_OSD_CREDIT_CNTL1 8692 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 8693 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 8694 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 8695 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc 8696 #define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 8697 #define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 8698 #define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 8699 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL 8700 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L 8701 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L 8702 #define DAGB4_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L 8703 #define DAGB4_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L 8704 #define DAGB4_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L 8705 #define DAGB4_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L 8706 //DAGB4_WR_OSD_CREDIT_CNTL2 8707 #define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 8708 #define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 8709 #define DAGB4_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL 8710 #define DAGB4_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L 8711 //DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1 8712 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 8713 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 8714 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 8715 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 8716 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 8717 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 8718 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 8719 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 8720 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 8721 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 8722 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 8723 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 8724 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 8725 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 8726 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 8727 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 8728 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 8729 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 8730 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 8731 #define DAGB4_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 8732 //DAGB4_WRCLI_GPU_SNOOP_OVERRIDE 8733 #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 8734 #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 8735 //DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 8736 #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 8737 #define DAGB4_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 8738 //DAGB4_WRCLI_ASK_PENDING 8739 #define DAGB4_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 8740 #define DAGB4_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 8741 //DAGB4_WRCLI_GO_PENDING 8742 #define DAGB4_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 8743 #define DAGB4_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 8744 //DAGB4_WRCLI_GBLSEND_PENDING 8745 #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 8746 #define DAGB4_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 8747 //DAGB4_WRCLI_TLB_PENDING 8748 #define DAGB4_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 8749 #define DAGB4_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 8750 //DAGB4_WRCLI_OARB_PENDING 8751 #define DAGB4_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 8752 #define DAGB4_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 8753 //DAGB4_WRCLI_OSD_PENDING 8754 #define DAGB4_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 8755 #define DAGB4_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 8756 //DAGB4_WRCLI_DBUS_ASK_PENDING 8757 #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 8758 #define DAGB4_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 8759 //DAGB4_WRCLI_DBUS_GO_PENDING 8760 #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 8761 #define DAGB4_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 8762 //DAGB4_DAGB_DLY 8763 #define DAGB4_DAGB_DLY__DLY__SHIFT 0x0 8764 #define DAGB4_DAGB_DLY__CLI__SHIFT 0x8 8765 #define DAGB4_DAGB_DLY__POS__SHIFT 0x10 8766 #define DAGB4_DAGB_DLY__DLY_MASK 0x000000FFL 8767 #define DAGB4_DAGB_DLY__CLI_MASK 0x0000FF00L 8768 #define DAGB4_DAGB_DLY__POS_MASK 0x000F0000L 8769 //DAGB4_CNTL_MISC 8770 #define DAGB4_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 8771 #define DAGB4_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 8772 #define DAGB4_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 8773 #define DAGB4_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 8774 #define DAGB4_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 8775 #define DAGB4_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 8776 #define DAGB4_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 8777 #define DAGB4_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 8778 #define DAGB4_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 8779 #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 8780 #define DAGB4_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 8781 #define DAGB4_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 8782 #define DAGB4_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 8783 #define DAGB4_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 8784 #define DAGB4_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 8785 #define DAGB4_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 8786 #define DAGB4_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 8787 #define DAGB4_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 8788 #define DAGB4_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 8789 #define DAGB4_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 8790 //DAGB4_CNTL_MISC2 8791 #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 8792 #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 8793 #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 8794 #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 8795 #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 8796 #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 8797 #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 8798 #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 8799 #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 8800 #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 8801 #define DAGB4_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 8802 #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 8803 #define DAGB4_CNTL_MISC2__HDP_CID__SHIFT 0xc 8804 #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 8805 #define DAGB4_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 8806 #define DAGB4_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 8807 #define DAGB4_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 8808 #define DAGB4_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 8809 #define DAGB4_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 8810 #define DAGB4_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 8811 #define DAGB4_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 8812 #define DAGB4_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 8813 #define DAGB4_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 8814 #define DAGB4_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 8815 #define DAGB4_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 8816 #define DAGB4_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 8817 #define DAGB4_CNTL_MISC2__HDP_CID_MASK 0x0001F000L 8818 #define DAGB4_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 8819 //DAGB4_FATAL_ERROR_CNTL 8820 #define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 8821 #define DAGB4_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 8822 //DAGB4_FATAL_ERROR_CLEAR 8823 #define DAGB4_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 8824 #define DAGB4_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 8825 //DAGB4_FATAL_ERROR_STATUS0 8826 #define DAGB4_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 8827 #define DAGB4_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 8828 #define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 8829 #define DAGB4_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 8830 #define DAGB4_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 8831 #define DAGB4_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 8832 //DAGB4_FATAL_ERROR_STATUS1 8833 #define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 8834 #define DAGB4_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 8835 //DAGB4_FATAL_ERROR_STATUS2 8836 #define DAGB4_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 8837 #define DAGB4_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 8838 #define DAGB4_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 8839 #define DAGB4_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 8840 #define DAGB4_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 8841 #define DAGB4_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 8842 #define DAGB4_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 8843 #define DAGB4_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL 8844 #define DAGB4_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L 8845 #define DAGB4_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L 8846 #define DAGB4_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L 8847 #define DAGB4_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L 8848 #define DAGB4_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L 8849 #define DAGB4_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L 8850 //DAGB4_FATAL_ERROR_STATUS3 8851 #define DAGB4_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 8852 #define DAGB4_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 8853 #define DAGB4_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 8854 #define DAGB4_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 8855 #define DAGB4_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 8856 #define DAGB4_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 8857 #define DAGB4_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 8858 #define DAGB4_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 8859 #define DAGB4_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 8860 #define DAGB4_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 8861 #define DAGB4_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 8862 #define DAGB4_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 8863 #define DAGB4_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 8864 #define DAGB4_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 8865 #define DAGB4_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 8866 #define DAGB4_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 8867 #define DAGB4_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 8868 #define DAGB4_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L 8869 //DAGB4_FIFO_EMPTY 8870 #define DAGB4_FIFO_EMPTY__EMPTY__SHIFT 0x0 8871 #define DAGB4_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 8872 //DAGB4_FIFO_FULL 8873 #define DAGB4_FIFO_FULL__FULL__SHIFT 0x0 8874 #define DAGB4_FIFO_FULL__FULL_MASK 0x007FFFFFL 8875 //DAGB4_WR_CREDITS_FULL 8876 #define DAGB4_WR_CREDITS_FULL__FULL__SHIFT 0x0 8877 #define DAGB4_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 8878 //DAGB4_RD_CREDITS_FULL 8879 #define DAGB4_RD_CREDITS_FULL__FULL__SHIFT 0x0 8880 #define DAGB4_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 8881 //DAGB4_PERFCOUNTER_LO 8882 #define DAGB4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 8883 #define DAGB4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 8884 //DAGB4_PERFCOUNTER_HI 8885 #define DAGB4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 8886 #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 8887 #define DAGB4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 8888 #define DAGB4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 8889 //DAGB4_PERFCOUNTER0_CFG 8890 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 8891 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 8892 #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 8893 #define DAGB4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 8894 #define DAGB4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 8895 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 8896 #define DAGB4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 8897 #define DAGB4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 8898 #define DAGB4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 8899 #define DAGB4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 8900 //DAGB4_PERFCOUNTER1_CFG 8901 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 8902 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 8903 #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 8904 #define DAGB4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 8905 #define DAGB4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 8906 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 8907 #define DAGB4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 8908 #define DAGB4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 8909 #define DAGB4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 8910 #define DAGB4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 8911 //DAGB4_PERFCOUNTER2_CFG 8912 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 8913 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 8914 #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 8915 #define DAGB4_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 8916 #define DAGB4_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 8917 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 8918 #define DAGB4_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 8919 #define DAGB4_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 8920 #define DAGB4_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 8921 #define DAGB4_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 8922 //DAGB4_PERFCOUNTER_RSLT_CNTL 8923 #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 8924 #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 8925 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 8926 #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 8927 #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 8928 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 8929 #define DAGB4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 8930 #define DAGB4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 8931 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 8932 #define DAGB4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 8933 #define DAGB4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 8934 #define DAGB4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 8935 //DAGB4_L1TLB_REG_RW 8936 #define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 8937 #define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 8938 #define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 8939 #define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 8940 #define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 8941 #define DAGB4_L1TLB_REG_RW__RESERVE__SHIFT 0x6 8942 #define DAGB4_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 8943 #define DAGB4_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 8944 #define DAGB4_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L 8945 #define DAGB4_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L 8946 #define DAGB4_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L 8947 #define DAGB4_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L 8948 //DAGB4_RESERVE1 8949 #define DAGB4_RESERVE1__RESERVE__SHIFT 0x0 8950 #define DAGB4_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 8951 //DAGB4_RESERVE2 8952 #define DAGB4_RESERVE2__RESERVE__SHIFT 0x0 8953 #define DAGB4_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 8954 //DAGB4_RESERVE3 8955 #define DAGB4_RESERVE3__RESERVE__SHIFT 0x0 8956 #define DAGB4_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 8957 //DAGB4_RESERVE4 8958 #define DAGB4_RESERVE4__RESERVE__SHIFT 0x0 8959 #define DAGB4_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 8960 8961 8962 // addressBlock: mmhub_dagb_dagbdec5 8963 //DAGB5_RDCLI0 8964 #define DAGB5_RDCLI0__VIRT_CHAN__SHIFT 0x0 8965 #define DAGB5_RDCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 8966 #define DAGB5_RDCLI0__URG_HIGH__SHIFT 0x4 8967 #define DAGB5_RDCLI0__URG_LOW__SHIFT 0x8 8968 #define DAGB5_RDCLI0__MAX_BW_ENABLE__SHIFT 0xc 8969 #define DAGB5_RDCLI0__MAX_BW__SHIFT 0xd 8970 #define DAGB5_RDCLI0__MIN_BW_ENABLE__SHIFT 0x15 8971 #define DAGB5_RDCLI0__MIN_BW__SHIFT 0x16 8972 #define DAGB5_RDCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 8973 #define DAGB5_RDCLI0__MAX_OSD__SHIFT 0x1a 8974 #define DAGB5_RDCLI0__VIRT_CHAN_MASK 0x00000007L 8975 #define DAGB5_RDCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 8976 #define DAGB5_RDCLI0__URG_HIGH_MASK 0x000000F0L 8977 #define DAGB5_RDCLI0__URG_LOW_MASK 0x00000F00L 8978 #define DAGB5_RDCLI0__MAX_BW_ENABLE_MASK 0x00001000L 8979 #define DAGB5_RDCLI0__MAX_BW_MASK 0x001FE000L 8980 #define DAGB5_RDCLI0__MIN_BW_ENABLE_MASK 0x00200000L 8981 #define DAGB5_RDCLI0__MIN_BW_MASK 0x01C00000L 8982 #define DAGB5_RDCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 8983 #define DAGB5_RDCLI0__MAX_OSD_MASK 0xFC000000L 8984 //DAGB5_RDCLI1 8985 #define DAGB5_RDCLI1__VIRT_CHAN__SHIFT 0x0 8986 #define DAGB5_RDCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 8987 #define DAGB5_RDCLI1__URG_HIGH__SHIFT 0x4 8988 #define DAGB5_RDCLI1__URG_LOW__SHIFT 0x8 8989 #define DAGB5_RDCLI1__MAX_BW_ENABLE__SHIFT 0xc 8990 #define DAGB5_RDCLI1__MAX_BW__SHIFT 0xd 8991 #define DAGB5_RDCLI1__MIN_BW_ENABLE__SHIFT 0x15 8992 #define DAGB5_RDCLI1__MIN_BW__SHIFT 0x16 8993 #define DAGB5_RDCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 8994 #define DAGB5_RDCLI1__MAX_OSD__SHIFT 0x1a 8995 #define DAGB5_RDCLI1__VIRT_CHAN_MASK 0x00000007L 8996 #define DAGB5_RDCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 8997 #define DAGB5_RDCLI1__URG_HIGH_MASK 0x000000F0L 8998 #define DAGB5_RDCLI1__URG_LOW_MASK 0x00000F00L 8999 #define DAGB5_RDCLI1__MAX_BW_ENABLE_MASK 0x00001000L 9000 #define DAGB5_RDCLI1__MAX_BW_MASK 0x001FE000L 9001 #define DAGB5_RDCLI1__MIN_BW_ENABLE_MASK 0x00200000L 9002 #define DAGB5_RDCLI1__MIN_BW_MASK 0x01C00000L 9003 #define DAGB5_RDCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 9004 #define DAGB5_RDCLI1__MAX_OSD_MASK 0xFC000000L 9005 //DAGB5_RDCLI2 9006 #define DAGB5_RDCLI2__VIRT_CHAN__SHIFT 0x0 9007 #define DAGB5_RDCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 9008 #define DAGB5_RDCLI2__URG_HIGH__SHIFT 0x4 9009 #define DAGB5_RDCLI2__URG_LOW__SHIFT 0x8 9010 #define DAGB5_RDCLI2__MAX_BW_ENABLE__SHIFT 0xc 9011 #define DAGB5_RDCLI2__MAX_BW__SHIFT 0xd 9012 #define DAGB5_RDCLI2__MIN_BW_ENABLE__SHIFT 0x15 9013 #define DAGB5_RDCLI2__MIN_BW__SHIFT 0x16 9014 #define DAGB5_RDCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 9015 #define DAGB5_RDCLI2__MAX_OSD__SHIFT 0x1a 9016 #define DAGB5_RDCLI2__VIRT_CHAN_MASK 0x00000007L 9017 #define DAGB5_RDCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 9018 #define DAGB5_RDCLI2__URG_HIGH_MASK 0x000000F0L 9019 #define DAGB5_RDCLI2__URG_LOW_MASK 0x00000F00L 9020 #define DAGB5_RDCLI2__MAX_BW_ENABLE_MASK 0x00001000L 9021 #define DAGB5_RDCLI2__MAX_BW_MASK 0x001FE000L 9022 #define DAGB5_RDCLI2__MIN_BW_ENABLE_MASK 0x00200000L 9023 #define DAGB5_RDCLI2__MIN_BW_MASK 0x01C00000L 9024 #define DAGB5_RDCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 9025 #define DAGB5_RDCLI2__MAX_OSD_MASK 0xFC000000L 9026 //DAGB5_RDCLI3 9027 #define DAGB5_RDCLI3__VIRT_CHAN__SHIFT 0x0 9028 #define DAGB5_RDCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 9029 #define DAGB5_RDCLI3__URG_HIGH__SHIFT 0x4 9030 #define DAGB5_RDCLI3__URG_LOW__SHIFT 0x8 9031 #define DAGB5_RDCLI3__MAX_BW_ENABLE__SHIFT 0xc 9032 #define DAGB5_RDCLI3__MAX_BW__SHIFT 0xd 9033 #define DAGB5_RDCLI3__MIN_BW_ENABLE__SHIFT 0x15 9034 #define DAGB5_RDCLI3__MIN_BW__SHIFT 0x16 9035 #define DAGB5_RDCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 9036 #define DAGB5_RDCLI3__MAX_OSD__SHIFT 0x1a 9037 #define DAGB5_RDCLI3__VIRT_CHAN_MASK 0x00000007L 9038 #define DAGB5_RDCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 9039 #define DAGB5_RDCLI3__URG_HIGH_MASK 0x000000F0L 9040 #define DAGB5_RDCLI3__URG_LOW_MASK 0x00000F00L 9041 #define DAGB5_RDCLI3__MAX_BW_ENABLE_MASK 0x00001000L 9042 #define DAGB5_RDCLI3__MAX_BW_MASK 0x001FE000L 9043 #define DAGB5_RDCLI3__MIN_BW_ENABLE_MASK 0x00200000L 9044 #define DAGB5_RDCLI3__MIN_BW_MASK 0x01C00000L 9045 #define DAGB5_RDCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 9046 #define DAGB5_RDCLI3__MAX_OSD_MASK 0xFC000000L 9047 //DAGB5_RDCLI4 9048 #define DAGB5_RDCLI4__VIRT_CHAN__SHIFT 0x0 9049 #define DAGB5_RDCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 9050 #define DAGB5_RDCLI4__URG_HIGH__SHIFT 0x4 9051 #define DAGB5_RDCLI4__URG_LOW__SHIFT 0x8 9052 #define DAGB5_RDCLI4__MAX_BW_ENABLE__SHIFT 0xc 9053 #define DAGB5_RDCLI4__MAX_BW__SHIFT 0xd 9054 #define DAGB5_RDCLI4__MIN_BW_ENABLE__SHIFT 0x15 9055 #define DAGB5_RDCLI4__MIN_BW__SHIFT 0x16 9056 #define DAGB5_RDCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 9057 #define DAGB5_RDCLI4__MAX_OSD__SHIFT 0x1a 9058 #define DAGB5_RDCLI4__VIRT_CHAN_MASK 0x00000007L 9059 #define DAGB5_RDCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 9060 #define DAGB5_RDCLI4__URG_HIGH_MASK 0x000000F0L 9061 #define DAGB5_RDCLI4__URG_LOW_MASK 0x00000F00L 9062 #define DAGB5_RDCLI4__MAX_BW_ENABLE_MASK 0x00001000L 9063 #define DAGB5_RDCLI4__MAX_BW_MASK 0x001FE000L 9064 #define DAGB5_RDCLI4__MIN_BW_ENABLE_MASK 0x00200000L 9065 #define DAGB5_RDCLI4__MIN_BW_MASK 0x01C00000L 9066 #define DAGB5_RDCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 9067 #define DAGB5_RDCLI4__MAX_OSD_MASK 0xFC000000L 9068 //DAGB5_RDCLI5 9069 #define DAGB5_RDCLI5__VIRT_CHAN__SHIFT 0x0 9070 #define DAGB5_RDCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 9071 #define DAGB5_RDCLI5__URG_HIGH__SHIFT 0x4 9072 #define DAGB5_RDCLI5__URG_LOW__SHIFT 0x8 9073 #define DAGB5_RDCLI5__MAX_BW_ENABLE__SHIFT 0xc 9074 #define DAGB5_RDCLI5__MAX_BW__SHIFT 0xd 9075 #define DAGB5_RDCLI5__MIN_BW_ENABLE__SHIFT 0x15 9076 #define DAGB5_RDCLI5__MIN_BW__SHIFT 0x16 9077 #define DAGB5_RDCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 9078 #define DAGB5_RDCLI5__MAX_OSD__SHIFT 0x1a 9079 #define DAGB5_RDCLI5__VIRT_CHAN_MASK 0x00000007L 9080 #define DAGB5_RDCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 9081 #define DAGB5_RDCLI5__URG_HIGH_MASK 0x000000F0L 9082 #define DAGB5_RDCLI5__URG_LOW_MASK 0x00000F00L 9083 #define DAGB5_RDCLI5__MAX_BW_ENABLE_MASK 0x00001000L 9084 #define DAGB5_RDCLI5__MAX_BW_MASK 0x001FE000L 9085 #define DAGB5_RDCLI5__MIN_BW_ENABLE_MASK 0x00200000L 9086 #define DAGB5_RDCLI5__MIN_BW_MASK 0x01C00000L 9087 #define DAGB5_RDCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 9088 #define DAGB5_RDCLI5__MAX_OSD_MASK 0xFC000000L 9089 //DAGB5_RDCLI6 9090 #define DAGB5_RDCLI6__VIRT_CHAN__SHIFT 0x0 9091 #define DAGB5_RDCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 9092 #define DAGB5_RDCLI6__URG_HIGH__SHIFT 0x4 9093 #define DAGB5_RDCLI6__URG_LOW__SHIFT 0x8 9094 #define DAGB5_RDCLI6__MAX_BW_ENABLE__SHIFT 0xc 9095 #define DAGB5_RDCLI6__MAX_BW__SHIFT 0xd 9096 #define DAGB5_RDCLI6__MIN_BW_ENABLE__SHIFT 0x15 9097 #define DAGB5_RDCLI6__MIN_BW__SHIFT 0x16 9098 #define DAGB5_RDCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 9099 #define DAGB5_RDCLI6__MAX_OSD__SHIFT 0x1a 9100 #define DAGB5_RDCLI6__VIRT_CHAN_MASK 0x00000007L 9101 #define DAGB5_RDCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 9102 #define DAGB5_RDCLI6__URG_HIGH_MASK 0x000000F0L 9103 #define DAGB5_RDCLI6__URG_LOW_MASK 0x00000F00L 9104 #define DAGB5_RDCLI6__MAX_BW_ENABLE_MASK 0x00001000L 9105 #define DAGB5_RDCLI6__MAX_BW_MASK 0x001FE000L 9106 #define DAGB5_RDCLI6__MIN_BW_ENABLE_MASK 0x00200000L 9107 #define DAGB5_RDCLI6__MIN_BW_MASK 0x01C00000L 9108 #define DAGB5_RDCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 9109 #define DAGB5_RDCLI6__MAX_OSD_MASK 0xFC000000L 9110 //DAGB5_RDCLI7 9111 #define DAGB5_RDCLI7__VIRT_CHAN__SHIFT 0x0 9112 #define DAGB5_RDCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 9113 #define DAGB5_RDCLI7__URG_HIGH__SHIFT 0x4 9114 #define DAGB5_RDCLI7__URG_LOW__SHIFT 0x8 9115 #define DAGB5_RDCLI7__MAX_BW_ENABLE__SHIFT 0xc 9116 #define DAGB5_RDCLI7__MAX_BW__SHIFT 0xd 9117 #define DAGB5_RDCLI7__MIN_BW_ENABLE__SHIFT 0x15 9118 #define DAGB5_RDCLI7__MIN_BW__SHIFT 0x16 9119 #define DAGB5_RDCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 9120 #define DAGB5_RDCLI7__MAX_OSD__SHIFT 0x1a 9121 #define DAGB5_RDCLI7__VIRT_CHAN_MASK 0x00000007L 9122 #define DAGB5_RDCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 9123 #define DAGB5_RDCLI7__URG_HIGH_MASK 0x000000F0L 9124 #define DAGB5_RDCLI7__URG_LOW_MASK 0x00000F00L 9125 #define DAGB5_RDCLI7__MAX_BW_ENABLE_MASK 0x00001000L 9126 #define DAGB5_RDCLI7__MAX_BW_MASK 0x001FE000L 9127 #define DAGB5_RDCLI7__MIN_BW_ENABLE_MASK 0x00200000L 9128 #define DAGB5_RDCLI7__MIN_BW_MASK 0x01C00000L 9129 #define DAGB5_RDCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 9130 #define DAGB5_RDCLI7__MAX_OSD_MASK 0xFC000000L 9131 //DAGB5_RDCLI8 9132 #define DAGB5_RDCLI8__VIRT_CHAN__SHIFT 0x0 9133 #define DAGB5_RDCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 9134 #define DAGB5_RDCLI8__URG_HIGH__SHIFT 0x4 9135 #define DAGB5_RDCLI8__URG_LOW__SHIFT 0x8 9136 #define DAGB5_RDCLI8__MAX_BW_ENABLE__SHIFT 0xc 9137 #define DAGB5_RDCLI8__MAX_BW__SHIFT 0xd 9138 #define DAGB5_RDCLI8__MIN_BW_ENABLE__SHIFT 0x15 9139 #define DAGB5_RDCLI8__MIN_BW__SHIFT 0x16 9140 #define DAGB5_RDCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 9141 #define DAGB5_RDCLI8__MAX_OSD__SHIFT 0x1a 9142 #define DAGB5_RDCLI8__VIRT_CHAN_MASK 0x00000007L 9143 #define DAGB5_RDCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 9144 #define DAGB5_RDCLI8__URG_HIGH_MASK 0x000000F0L 9145 #define DAGB5_RDCLI8__URG_LOW_MASK 0x00000F00L 9146 #define DAGB5_RDCLI8__MAX_BW_ENABLE_MASK 0x00001000L 9147 #define DAGB5_RDCLI8__MAX_BW_MASK 0x001FE000L 9148 #define DAGB5_RDCLI8__MIN_BW_ENABLE_MASK 0x00200000L 9149 #define DAGB5_RDCLI8__MIN_BW_MASK 0x01C00000L 9150 #define DAGB5_RDCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 9151 #define DAGB5_RDCLI8__MAX_OSD_MASK 0xFC000000L 9152 //DAGB5_RDCLI9 9153 #define DAGB5_RDCLI9__VIRT_CHAN__SHIFT 0x0 9154 #define DAGB5_RDCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 9155 #define DAGB5_RDCLI9__URG_HIGH__SHIFT 0x4 9156 #define DAGB5_RDCLI9__URG_LOW__SHIFT 0x8 9157 #define DAGB5_RDCLI9__MAX_BW_ENABLE__SHIFT 0xc 9158 #define DAGB5_RDCLI9__MAX_BW__SHIFT 0xd 9159 #define DAGB5_RDCLI9__MIN_BW_ENABLE__SHIFT 0x15 9160 #define DAGB5_RDCLI9__MIN_BW__SHIFT 0x16 9161 #define DAGB5_RDCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 9162 #define DAGB5_RDCLI9__MAX_OSD__SHIFT 0x1a 9163 #define DAGB5_RDCLI9__VIRT_CHAN_MASK 0x00000007L 9164 #define DAGB5_RDCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 9165 #define DAGB5_RDCLI9__URG_HIGH_MASK 0x000000F0L 9166 #define DAGB5_RDCLI9__URG_LOW_MASK 0x00000F00L 9167 #define DAGB5_RDCLI9__MAX_BW_ENABLE_MASK 0x00001000L 9168 #define DAGB5_RDCLI9__MAX_BW_MASK 0x001FE000L 9169 #define DAGB5_RDCLI9__MIN_BW_ENABLE_MASK 0x00200000L 9170 #define DAGB5_RDCLI9__MIN_BW_MASK 0x01C00000L 9171 #define DAGB5_RDCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 9172 #define DAGB5_RDCLI9__MAX_OSD_MASK 0xFC000000L 9173 //DAGB5_RDCLI10 9174 #define DAGB5_RDCLI10__VIRT_CHAN__SHIFT 0x0 9175 #define DAGB5_RDCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 9176 #define DAGB5_RDCLI10__URG_HIGH__SHIFT 0x4 9177 #define DAGB5_RDCLI10__URG_LOW__SHIFT 0x8 9178 #define DAGB5_RDCLI10__MAX_BW_ENABLE__SHIFT 0xc 9179 #define DAGB5_RDCLI10__MAX_BW__SHIFT 0xd 9180 #define DAGB5_RDCLI10__MIN_BW_ENABLE__SHIFT 0x15 9181 #define DAGB5_RDCLI10__MIN_BW__SHIFT 0x16 9182 #define DAGB5_RDCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 9183 #define DAGB5_RDCLI10__MAX_OSD__SHIFT 0x1a 9184 #define DAGB5_RDCLI10__VIRT_CHAN_MASK 0x00000007L 9185 #define DAGB5_RDCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 9186 #define DAGB5_RDCLI10__URG_HIGH_MASK 0x000000F0L 9187 #define DAGB5_RDCLI10__URG_LOW_MASK 0x00000F00L 9188 #define DAGB5_RDCLI10__MAX_BW_ENABLE_MASK 0x00001000L 9189 #define DAGB5_RDCLI10__MAX_BW_MASK 0x001FE000L 9190 #define DAGB5_RDCLI10__MIN_BW_ENABLE_MASK 0x00200000L 9191 #define DAGB5_RDCLI10__MIN_BW_MASK 0x01C00000L 9192 #define DAGB5_RDCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 9193 #define DAGB5_RDCLI10__MAX_OSD_MASK 0xFC000000L 9194 //DAGB5_RDCLI11 9195 #define DAGB5_RDCLI11__VIRT_CHAN__SHIFT 0x0 9196 #define DAGB5_RDCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 9197 #define DAGB5_RDCLI11__URG_HIGH__SHIFT 0x4 9198 #define DAGB5_RDCLI11__URG_LOW__SHIFT 0x8 9199 #define DAGB5_RDCLI11__MAX_BW_ENABLE__SHIFT 0xc 9200 #define DAGB5_RDCLI11__MAX_BW__SHIFT 0xd 9201 #define DAGB5_RDCLI11__MIN_BW_ENABLE__SHIFT 0x15 9202 #define DAGB5_RDCLI11__MIN_BW__SHIFT 0x16 9203 #define DAGB5_RDCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 9204 #define DAGB5_RDCLI11__MAX_OSD__SHIFT 0x1a 9205 #define DAGB5_RDCLI11__VIRT_CHAN_MASK 0x00000007L 9206 #define DAGB5_RDCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 9207 #define DAGB5_RDCLI11__URG_HIGH_MASK 0x000000F0L 9208 #define DAGB5_RDCLI11__URG_LOW_MASK 0x00000F00L 9209 #define DAGB5_RDCLI11__MAX_BW_ENABLE_MASK 0x00001000L 9210 #define DAGB5_RDCLI11__MAX_BW_MASK 0x001FE000L 9211 #define DAGB5_RDCLI11__MIN_BW_ENABLE_MASK 0x00200000L 9212 #define DAGB5_RDCLI11__MIN_BW_MASK 0x01C00000L 9213 #define DAGB5_RDCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 9214 #define DAGB5_RDCLI11__MAX_OSD_MASK 0xFC000000L 9215 //DAGB5_RDCLI12 9216 #define DAGB5_RDCLI12__VIRT_CHAN__SHIFT 0x0 9217 #define DAGB5_RDCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 9218 #define DAGB5_RDCLI12__URG_HIGH__SHIFT 0x4 9219 #define DAGB5_RDCLI12__URG_LOW__SHIFT 0x8 9220 #define DAGB5_RDCLI12__MAX_BW_ENABLE__SHIFT 0xc 9221 #define DAGB5_RDCLI12__MAX_BW__SHIFT 0xd 9222 #define DAGB5_RDCLI12__MIN_BW_ENABLE__SHIFT 0x15 9223 #define DAGB5_RDCLI12__MIN_BW__SHIFT 0x16 9224 #define DAGB5_RDCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 9225 #define DAGB5_RDCLI12__MAX_OSD__SHIFT 0x1a 9226 #define DAGB5_RDCLI12__VIRT_CHAN_MASK 0x00000007L 9227 #define DAGB5_RDCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 9228 #define DAGB5_RDCLI12__URG_HIGH_MASK 0x000000F0L 9229 #define DAGB5_RDCLI12__URG_LOW_MASK 0x00000F00L 9230 #define DAGB5_RDCLI12__MAX_BW_ENABLE_MASK 0x00001000L 9231 #define DAGB5_RDCLI12__MAX_BW_MASK 0x001FE000L 9232 #define DAGB5_RDCLI12__MIN_BW_ENABLE_MASK 0x00200000L 9233 #define DAGB5_RDCLI12__MIN_BW_MASK 0x01C00000L 9234 #define DAGB5_RDCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 9235 #define DAGB5_RDCLI12__MAX_OSD_MASK 0xFC000000L 9236 //DAGB5_RDCLI13 9237 #define DAGB5_RDCLI13__VIRT_CHAN__SHIFT 0x0 9238 #define DAGB5_RDCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 9239 #define DAGB5_RDCLI13__URG_HIGH__SHIFT 0x4 9240 #define DAGB5_RDCLI13__URG_LOW__SHIFT 0x8 9241 #define DAGB5_RDCLI13__MAX_BW_ENABLE__SHIFT 0xc 9242 #define DAGB5_RDCLI13__MAX_BW__SHIFT 0xd 9243 #define DAGB5_RDCLI13__MIN_BW_ENABLE__SHIFT 0x15 9244 #define DAGB5_RDCLI13__MIN_BW__SHIFT 0x16 9245 #define DAGB5_RDCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 9246 #define DAGB5_RDCLI13__MAX_OSD__SHIFT 0x1a 9247 #define DAGB5_RDCLI13__VIRT_CHAN_MASK 0x00000007L 9248 #define DAGB5_RDCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 9249 #define DAGB5_RDCLI13__URG_HIGH_MASK 0x000000F0L 9250 #define DAGB5_RDCLI13__URG_LOW_MASK 0x00000F00L 9251 #define DAGB5_RDCLI13__MAX_BW_ENABLE_MASK 0x00001000L 9252 #define DAGB5_RDCLI13__MAX_BW_MASK 0x001FE000L 9253 #define DAGB5_RDCLI13__MIN_BW_ENABLE_MASK 0x00200000L 9254 #define DAGB5_RDCLI13__MIN_BW_MASK 0x01C00000L 9255 #define DAGB5_RDCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 9256 #define DAGB5_RDCLI13__MAX_OSD_MASK 0xFC000000L 9257 //DAGB5_RDCLI14 9258 #define DAGB5_RDCLI14__VIRT_CHAN__SHIFT 0x0 9259 #define DAGB5_RDCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 9260 #define DAGB5_RDCLI14__URG_HIGH__SHIFT 0x4 9261 #define DAGB5_RDCLI14__URG_LOW__SHIFT 0x8 9262 #define DAGB5_RDCLI14__MAX_BW_ENABLE__SHIFT 0xc 9263 #define DAGB5_RDCLI14__MAX_BW__SHIFT 0xd 9264 #define DAGB5_RDCLI14__MIN_BW_ENABLE__SHIFT 0x15 9265 #define DAGB5_RDCLI14__MIN_BW__SHIFT 0x16 9266 #define DAGB5_RDCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 9267 #define DAGB5_RDCLI14__MAX_OSD__SHIFT 0x1a 9268 #define DAGB5_RDCLI14__VIRT_CHAN_MASK 0x00000007L 9269 #define DAGB5_RDCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 9270 #define DAGB5_RDCLI14__URG_HIGH_MASK 0x000000F0L 9271 #define DAGB5_RDCLI14__URG_LOW_MASK 0x00000F00L 9272 #define DAGB5_RDCLI14__MAX_BW_ENABLE_MASK 0x00001000L 9273 #define DAGB5_RDCLI14__MAX_BW_MASK 0x001FE000L 9274 #define DAGB5_RDCLI14__MIN_BW_ENABLE_MASK 0x00200000L 9275 #define DAGB5_RDCLI14__MIN_BW_MASK 0x01C00000L 9276 #define DAGB5_RDCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 9277 #define DAGB5_RDCLI14__MAX_OSD_MASK 0xFC000000L 9278 //DAGB5_RDCLI15 9279 #define DAGB5_RDCLI15__VIRT_CHAN__SHIFT 0x0 9280 #define DAGB5_RDCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 9281 #define DAGB5_RDCLI15__URG_HIGH__SHIFT 0x4 9282 #define DAGB5_RDCLI15__URG_LOW__SHIFT 0x8 9283 #define DAGB5_RDCLI15__MAX_BW_ENABLE__SHIFT 0xc 9284 #define DAGB5_RDCLI15__MAX_BW__SHIFT 0xd 9285 #define DAGB5_RDCLI15__MIN_BW_ENABLE__SHIFT 0x15 9286 #define DAGB5_RDCLI15__MIN_BW__SHIFT 0x16 9287 #define DAGB5_RDCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 9288 #define DAGB5_RDCLI15__MAX_OSD__SHIFT 0x1a 9289 #define DAGB5_RDCLI15__VIRT_CHAN_MASK 0x00000007L 9290 #define DAGB5_RDCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 9291 #define DAGB5_RDCLI15__URG_HIGH_MASK 0x000000F0L 9292 #define DAGB5_RDCLI15__URG_LOW_MASK 0x00000F00L 9293 #define DAGB5_RDCLI15__MAX_BW_ENABLE_MASK 0x00001000L 9294 #define DAGB5_RDCLI15__MAX_BW_MASK 0x001FE000L 9295 #define DAGB5_RDCLI15__MIN_BW_ENABLE_MASK 0x00200000L 9296 #define DAGB5_RDCLI15__MIN_BW_MASK 0x01C00000L 9297 #define DAGB5_RDCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 9298 #define DAGB5_RDCLI15__MAX_OSD_MASK 0xFC000000L 9299 //DAGB5_RD_CNTL 9300 #define DAGB5_RD_CNTL__SCLK_FREQ__SHIFT 0x0 9301 #define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 9302 #define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 9303 #define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 9304 #define DAGB5_RD_CNTL__IO_LEVEL__SHIFT 0x11 9305 #define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 9306 #define DAGB5_RD_CNTL__SHARE_VC_NUM__SHIFT 0x17 9307 #define DAGB5_RD_CNTL__FIX_JUMP__SHIFT 0x1a 9308 #define DAGB5_RD_CNTL__SCLK_FREQ_MASK 0x0000000FL 9309 #define DAGB5_RD_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 9310 #define DAGB5_RD_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 9311 #define DAGB5_RD_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 9312 #define DAGB5_RD_CNTL__IO_LEVEL_MASK 0x000E0000L 9313 #define DAGB5_RD_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 9314 #define DAGB5_RD_CNTL__SHARE_VC_NUM_MASK 0x03800000L 9315 #define DAGB5_RD_CNTL__FIX_JUMP_MASK 0x04000000L 9316 //DAGB5_RD_GMI_CNTL 9317 #define DAGB5_RD_GMI_CNTL__EA_CREDIT__SHIFT 0x0 9318 #define DAGB5_RD_GMI_CNTL__LEVEL__SHIFT 0x6 9319 #define DAGB5_RD_GMI_CNTL__MAX_BURST__SHIFT 0x9 9320 #define DAGB5_RD_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 9321 #define DAGB5_RD_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 9322 #define DAGB5_RD_GMI_CNTL__LEVEL_MASK 0x000001C0L 9323 #define DAGB5_RD_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 9324 #define DAGB5_RD_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 9325 //DAGB5_RD_ADDR_DAGB 9326 #define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 9327 #define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 9328 #define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 9329 #define DAGB5_RD_ADDR_DAGB__WHOAMI__SHIFT 0x7 9330 #define DAGB5_RD_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 9331 #define DAGB5_RD_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 9332 #define DAGB5_RD_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 9333 #define DAGB5_RD_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 9334 #define DAGB5_RD_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 9335 #define DAGB5_RD_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 9336 //DAGB5_RD_OUTPUT_DAGB_MAX_BURST 9337 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 9338 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 9339 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 9340 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 9341 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 9342 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 9343 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 9344 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 9345 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 9346 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 9347 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 9348 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 9349 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 9350 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 9351 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 9352 #define DAGB5_RD_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 9353 //DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER 9354 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 9355 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 9356 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 9357 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 9358 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 9359 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 9360 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 9361 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 9362 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 9363 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 9364 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 9365 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 9366 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 9367 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 9368 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 9369 #define DAGB5_RD_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 9370 //DAGB5_RD_CGTT_CLK_CTRL 9371 #define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 9372 #define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 9373 #define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 9374 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 9375 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 9376 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 9377 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 9378 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 9379 #define DAGB5_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 9380 #define DAGB5_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 9381 #define DAGB5_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 9382 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 9383 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 9384 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 9385 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 9386 #define DAGB5_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 9387 //DAGB5_L1TLB_RD_CGTT_CLK_CTRL 9388 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 9389 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 9390 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 9391 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 9392 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 9393 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 9394 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 9395 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 9396 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 9397 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 9398 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 9399 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 9400 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 9401 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 9402 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 9403 #define DAGB5_L1TLB_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 9404 //DAGB5_ATCVM_RD_CGTT_CLK_CTRL 9405 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 9406 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 9407 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 9408 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 9409 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 9410 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 9411 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 9412 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 9413 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 9414 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 9415 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 9416 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 9417 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 9418 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 9419 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 9420 #define DAGB5_ATCVM_RD_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 9421 //DAGB5_RD_ADDR_DAGB_MAX_BURST0 9422 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 9423 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 9424 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 9425 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 9426 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 9427 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 9428 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 9429 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 9430 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 9431 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 9432 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 9433 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 9434 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 9435 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 9436 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 9437 #define DAGB5_RD_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 9438 //DAGB5_RD_ADDR_DAGB_LAZY_TIMER0 9439 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 9440 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 9441 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 9442 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 9443 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 9444 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 9445 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 9446 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 9447 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 9448 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 9449 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 9450 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 9451 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 9452 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 9453 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 9454 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 9455 //DAGB5_RD_ADDR_DAGB_MAX_BURST1 9456 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 9457 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 9458 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 9459 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 9460 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 9461 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 9462 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 9463 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 9464 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 9465 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 9466 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 9467 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 9468 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 9469 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 9470 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 9471 #define DAGB5_RD_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 9472 //DAGB5_RD_ADDR_DAGB_LAZY_TIMER1 9473 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 9474 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 9475 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 9476 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 9477 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 9478 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 9479 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 9480 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 9481 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 9482 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 9483 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 9484 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 9485 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 9486 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 9487 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 9488 #define DAGB5_RD_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 9489 //DAGB5_RD_VC0_CNTL 9490 #define DAGB5_RD_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 9491 #define DAGB5_RD_VC0_CNTL__EA_CREDIT__SHIFT 0x5 9492 #define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9493 #define DAGB5_RD_VC0_CNTL__MAX_BW__SHIFT 0xc 9494 #define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9495 #define DAGB5_RD_VC0_CNTL__MIN_BW__SHIFT 0x15 9496 #define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9497 #define DAGB5_RD_VC0_CNTL__MAX_OSD__SHIFT 0x19 9498 #define DAGB5_RD_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 9499 #define DAGB5_RD_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 9500 #define DAGB5_RD_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9501 #define DAGB5_RD_VC0_CNTL__MAX_BW_MASK 0x000FF000L 9502 #define DAGB5_RD_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9503 #define DAGB5_RD_VC0_CNTL__MIN_BW_MASK 0x00E00000L 9504 #define DAGB5_RD_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9505 #define DAGB5_RD_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 9506 //DAGB5_RD_VC1_CNTL 9507 #define DAGB5_RD_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 9508 #define DAGB5_RD_VC1_CNTL__EA_CREDIT__SHIFT 0x5 9509 #define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9510 #define DAGB5_RD_VC1_CNTL__MAX_BW__SHIFT 0xc 9511 #define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9512 #define DAGB5_RD_VC1_CNTL__MIN_BW__SHIFT 0x15 9513 #define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9514 #define DAGB5_RD_VC1_CNTL__MAX_OSD__SHIFT 0x19 9515 #define DAGB5_RD_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 9516 #define DAGB5_RD_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 9517 #define DAGB5_RD_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9518 #define DAGB5_RD_VC1_CNTL__MAX_BW_MASK 0x000FF000L 9519 #define DAGB5_RD_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9520 #define DAGB5_RD_VC1_CNTL__MIN_BW_MASK 0x00E00000L 9521 #define DAGB5_RD_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9522 #define DAGB5_RD_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 9523 //DAGB5_RD_VC2_CNTL 9524 #define DAGB5_RD_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 9525 #define DAGB5_RD_VC2_CNTL__EA_CREDIT__SHIFT 0x5 9526 #define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9527 #define DAGB5_RD_VC2_CNTL__MAX_BW__SHIFT 0xc 9528 #define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9529 #define DAGB5_RD_VC2_CNTL__MIN_BW__SHIFT 0x15 9530 #define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9531 #define DAGB5_RD_VC2_CNTL__MAX_OSD__SHIFT 0x19 9532 #define DAGB5_RD_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 9533 #define DAGB5_RD_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 9534 #define DAGB5_RD_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9535 #define DAGB5_RD_VC2_CNTL__MAX_BW_MASK 0x000FF000L 9536 #define DAGB5_RD_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9537 #define DAGB5_RD_VC2_CNTL__MIN_BW_MASK 0x00E00000L 9538 #define DAGB5_RD_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9539 #define DAGB5_RD_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 9540 //DAGB5_RD_VC3_CNTL 9541 #define DAGB5_RD_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 9542 #define DAGB5_RD_VC3_CNTL__EA_CREDIT__SHIFT 0x5 9543 #define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9544 #define DAGB5_RD_VC3_CNTL__MAX_BW__SHIFT 0xc 9545 #define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9546 #define DAGB5_RD_VC3_CNTL__MIN_BW__SHIFT 0x15 9547 #define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9548 #define DAGB5_RD_VC3_CNTL__MAX_OSD__SHIFT 0x19 9549 #define DAGB5_RD_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 9550 #define DAGB5_RD_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 9551 #define DAGB5_RD_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9552 #define DAGB5_RD_VC3_CNTL__MAX_BW_MASK 0x000FF000L 9553 #define DAGB5_RD_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9554 #define DAGB5_RD_VC3_CNTL__MIN_BW_MASK 0x00E00000L 9555 #define DAGB5_RD_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9556 #define DAGB5_RD_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 9557 //DAGB5_RD_VC4_CNTL 9558 #define DAGB5_RD_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 9559 #define DAGB5_RD_VC4_CNTL__EA_CREDIT__SHIFT 0x5 9560 #define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9561 #define DAGB5_RD_VC4_CNTL__MAX_BW__SHIFT 0xc 9562 #define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9563 #define DAGB5_RD_VC4_CNTL__MIN_BW__SHIFT 0x15 9564 #define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9565 #define DAGB5_RD_VC4_CNTL__MAX_OSD__SHIFT 0x19 9566 #define DAGB5_RD_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 9567 #define DAGB5_RD_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 9568 #define DAGB5_RD_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9569 #define DAGB5_RD_VC4_CNTL__MAX_BW_MASK 0x000FF000L 9570 #define DAGB5_RD_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9571 #define DAGB5_RD_VC4_CNTL__MIN_BW_MASK 0x00E00000L 9572 #define DAGB5_RD_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9573 #define DAGB5_RD_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 9574 //DAGB5_RD_VC5_CNTL 9575 #define DAGB5_RD_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 9576 #define DAGB5_RD_VC5_CNTL__EA_CREDIT__SHIFT 0x5 9577 #define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9578 #define DAGB5_RD_VC5_CNTL__MAX_BW__SHIFT 0xc 9579 #define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9580 #define DAGB5_RD_VC5_CNTL__MIN_BW__SHIFT 0x15 9581 #define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9582 #define DAGB5_RD_VC5_CNTL__MAX_OSD__SHIFT 0x19 9583 #define DAGB5_RD_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 9584 #define DAGB5_RD_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 9585 #define DAGB5_RD_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9586 #define DAGB5_RD_VC5_CNTL__MAX_BW_MASK 0x000FF000L 9587 #define DAGB5_RD_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9588 #define DAGB5_RD_VC5_CNTL__MIN_BW_MASK 0x00E00000L 9589 #define DAGB5_RD_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9590 #define DAGB5_RD_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 9591 //DAGB5_RD_VC6_CNTL 9592 #define DAGB5_RD_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 9593 #define DAGB5_RD_VC6_CNTL__EA_CREDIT__SHIFT 0x5 9594 #define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9595 #define DAGB5_RD_VC6_CNTL__MAX_BW__SHIFT 0xc 9596 #define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9597 #define DAGB5_RD_VC6_CNTL__MIN_BW__SHIFT 0x15 9598 #define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9599 #define DAGB5_RD_VC6_CNTL__MAX_OSD__SHIFT 0x19 9600 #define DAGB5_RD_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 9601 #define DAGB5_RD_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 9602 #define DAGB5_RD_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9603 #define DAGB5_RD_VC6_CNTL__MAX_BW_MASK 0x000FF000L 9604 #define DAGB5_RD_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9605 #define DAGB5_RD_VC6_CNTL__MIN_BW_MASK 0x00E00000L 9606 #define DAGB5_RD_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9607 #define DAGB5_RD_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 9608 //DAGB5_RD_VC7_CNTL 9609 #define DAGB5_RD_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 9610 #define DAGB5_RD_VC7_CNTL__EA_CREDIT__SHIFT 0x5 9611 #define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 9612 #define DAGB5_RD_VC7_CNTL__MAX_BW__SHIFT 0xc 9613 #define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 9614 #define DAGB5_RD_VC7_CNTL__MIN_BW__SHIFT 0x15 9615 #define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 9616 #define DAGB5_RD_VC7_CNTL__MAX_OSD__SHIFT 0x19 9617 #define DAGB5_RD_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 9618 #define DAGB5_RD_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 9619 #define DAGB5_RD_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 9620 #define DAGB5_RD_VC7_CNTL__MAX_BW_MASK 0x000FF000L 9621 #define DAGB5_RD_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 9622 #define DAGB5_RD_VC7_CNTL__MIN_BW_MASK 0x00E00000L 9623 #define DAGB5_RD_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 9624 #define DAGB5_RD_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 9625 //DAGB5_RD_CNTL_MISC 9626 #define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 9627 #define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 9628 #define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 9629 #define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 9630 #define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 9631 #define DAGB5_RD_CNTL_MISC__UTCL2_CID__SHIFT 0x15 9632 #define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 9633 #define DAGB5_RD_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 9634 #define DAGB5_RD_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 9635 #define DAGB5_RD_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 9636 #define DAGB5_RD_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 9637 #define DAGB5_RD_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 9638 #define DAGB5_RD_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 9639 #define DAGB5_RD_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 9640 //DAGB5_RD_TLB_CREDIT 9641 #define DAGB5_RD_TLB_CREDIT__TLB0__SHIFT 0x0 9642 #define DAGB5_RD_TLB_CREDIT__TLB1__SHIFT 0x5 9643 #define DAGB5_RD_TLB_CREDIT__TLB2__SHIFT 0xa 9644 #define DAGB5_RD_TLB_CREDIT__TLB3__SHIFT 0xf 9645 #define DAGB5_RD_TLB_CREDIT__TLB4__SHIFT 0x14 9646 #define DAGB5_RD_TLB_CREDIT__TLB5__SHIFT 0x19 9647 #define DAGB5_RD_TLB_CREDIT__TLB0_MASK 0x0000001FL 9648 #define DAGB5_RD_TLB_CREDIT__TLB1_MASK 0x000003E0L 9649 #define DAGB5_RD_TLB_CREDIT__TLB2_MASK 0x00007C00L 9650 #define DAGB5_RD_TLB_CREDIT__TLB3_MASK 0x000F8000L 9651 #define DAGB5_RD_TLB_CREDIT__TLB4_MASK 0x01F00000L 9652 #define DAGB5_RD_TLB_CREDIT__TLB5_MASK 0x3E000000L 9653 //DAGB5_RD_RDRET_CREDIT_CNTL 9654 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT__SHIFT 0x0 9655 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT__SHIFT 0x6 9656 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT__SHIFT 0xc 9657 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT__SHIFT 0x12 9658 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT__SHIFT 0x18 9659 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE__SHIFT 0x1e 9660 #define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ__SHIFT 0x1f 9661 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC0_CREDIT_MASK 0x0000003FL 9662 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC1_CREDIT_MASK 0x00000FC0L 9663 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC2_CREDIT_MASK 0x0003F000L 9664 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC3_CREDIT_MASK 0x00FC0000L 9665 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC4_CREDIT_MASK 0x3F000000L 9666 #define DAGB5_RD_RDRET_CREDIT_CNTL__VC_MODE_MASK 0x40000000L 9667 #define DAGB5_RD_RDRET_CREDIT_CNTL__FIX_EQ_MASK 0x80000000L 9668 //DAGB5_RD_RDRET_CREDIT_CNTL2 9669 #define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT__SHIFT 0x0 9670 #define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT__SHIFT 0x6 9671 #define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT__SHIFT 0xc 9672 #define DAGB5_RD_RDRET_CREDIT_CNTL2__IO_CREDIT_MASK 0x0000003FL 9673 #define DAGB5_RD_RDRET_CREDIT_CNTL2__GMI_CREDIT_MASK 0x00000FC0L 9674 #define DAGB5_RD_RDRET_CREDIT_CNTL2__POOL_CREDIT_MASK 0x0007F000L 9675 //DAGB5_RDCLI_ASK_PENDING 9676 #define DAGB5_RDCLI_ASK_PENDING__BUSY__SHIFT 0x0 9677 #define DAGB5_RDCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 9678 //DAGB5_RDCLI_GO_PENDING 9679 #define DAGB5_RDCLI_GO_PENDING__BUSY__SHIFT 0x0 9680 #define DAGB5_RDCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 9681 //DAGB5_RDCLI_GBLSEND_PENDING 9682 #define DAGB5_RDCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 9683 #define DAGB5_RDCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 9684 //DAGB5_RDCLI_TLB_PENDING 9685 #define DAGB5_RDCLI_TLB_PENDING__BUSY__SHIFT 0x0 9686 #define DAGB5_RDCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 9687 //DAGB5_RDCLI_OARB_PENDING 9688 #define DAGB5_RDCLI_OARB_PENDING__BUSY__SHIFT 0x0 9689 #define DAGB5_RDCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 9690 //DAGB5_RDCLI_OSD_PENDING 9691 #define DAGB5_RDCLI_OSD_PENDING__BUSY__SHIFT 0x0 9692 #define DAGB5_RDCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 9693 //DAGB5_WRCLI0 9694 #define DAGB5_WRCLI0__VIRT_CHAN__SHIFT 0x0 9695 #define DAGB5_WRCLI0__CHECK_TLB_CREDIT__SHIFT 0x3 9696 #define DAGB5_WRCLI0__URG_HIGH__SHIFT 0x4 9697 #define DAGB5_WRCLI0__URG_LOW__SHIFT 0x8 9698 #define DAGB5_WRCLI0__MAX_BW_ENABLE__SHIFT 0xc 9699 #define DAGB5_WRCLI0__MAX_BW__SHIFT 0xd 9700 #define DAGB5_WRCLI0__MIN_BW_ENABLE__SHIFT 0x15 9701 #define DAGB5_WRCLI0__MIN_BW__SHIFT 0x16 9702 #define DAGB5_WRCLI0__OSD_LIMITER_ENABLE__SHIFT 0x19 9703 #define DAGB5_WRCLI0__MAX_OSD__SHIFT 0x1a 9704 #define DAGB5_WRCLI0__VIRT_CHAN_MASK 0x00000007L 9705 #define DAGB5_WRCLI0__CHECK_TLB_CREDIT_MASK 0x00000008L 9706 #define DAGB5_WRCLI0__URG_HIGH_MASK 0x000000F0L 9707 #define DAGB5_WRCLI0__URG_LOW_MASK 0x00000F00L 9708 #define DAGB5_WRCLI0__MAX_BW_ENABLE_MASK 0x00001000L 9709 #define DAGB5_WRCLI0__MAX_BW_MASK 0x001FE000L 9710 #define DAGB5_WRCLI0__MIN_BW_ENABLE_MASK 0x00200000L 9711 #define DAGB5_WRCLI0__MIN_BW_MASK 0x01C00000L 9712 #define DAGB5_WRCLI0__OSD_LIMITER_ENABLE_MASK 0x02000000L 9713 #define DAGB5_WRCLI0__MAX_OSD_MASK 0xFC000000L 9714 //DAGB5_WRCLI1 9715 #define DAGB5_WRCLI1__VIRT_CHAN__SHIFT 0x0 9716 #define DAGB5_WRCLI1__CHECK_TLB_CREDIT__SHIFT 0x3 9717 #define DAGB5_WRCLI1__URG_HIGH__SHIFT 0x4 9718 #define DAGB5_WRCLI1__URG_LOW__SHIFT 0x8 9719 #define DAGB5_WRCLI1__MAX_BW_ENABLE__SHIFT 0xc 9720 #define DAGB5_WRCLI1__MAX_BW__SHIFT 0xd 9721 #define DAGB5_WRCLI1__MIN_BW_ENABLE__SHIFT 0x15 9722 #define DAGB5_WRCLI1__MIN_BW__SHIFT 0x16 9723 #define DAGB5_WRCLI1__OSD_LIMITER_ENABLE__SHIFT 0x19 9724 #define DAGB5_WRCLI1__MAX_OSD__SHIFT 0x1a 9725 #define DAGB5_WRCLI1__VIRT_CHAN_MASK 0x00000007L 9726 #define DAGB5_WRCLI1__CHECK_TLB_CREDIT_MASK 0x00000008L 9727 #define DAGB5_WRCLI1__URG_HIGH_MASK 0x000000F0L 9728 #define DAGB5_WRCLI1__URG_LOW_MASK 0x00000F00L 9729 #define DAGB5_WRCLI1__MAX_BW_ENABLE_MASK 0x00001000L 9730 #define DAGB5_WRCLI1__MAX_BW_MASK 0x001FE000L 9731 #define DAGB5_WRCLI1__MIN_BW_ENABLE_MASK 0x00200000L 9732 #define DAGB5_WRCLI1__MIN_BW_MASK 0x01C00000L 9733 #define DAGB5_WRCLI1__OSD_LIMITER_ENABLE_MASK 0x02000000L 9734 #define DAGB5_WRCLI1__MAX_OSD_MASK 0xFC000000L 9735 //DAGB5_WRCLI2 9736 #define DAGB5_WRCLI2__VIRT_CHAN__SHIFT 0x0 9737 #define DAGB5_WRCLI2__CHECK_TLB_CREDIT__SHIFT 0x3 9738 #define DAGB5_WRCLI2__URG_HIGH__SHIFT 0x4 9739 #define DAGB5_WRCLI2__URG_LOW__SHIFT 0x8 9740 #define DAGB5_WRCLI2__MAX_BW_ENABLE__SHIFT 0xc 9741 #define DAGB5_WRCLI2__MAX_BW__SHIFT 0xd 9742 #define DAGB5_WRCLI2__MIN_BW_ENABLE__SHIFT 0x15 9743 #define DAGB5_WRCLI2__MIN_BW__SHIFT 0x16 9744 #define DAGB5_WRCLI2__OSD_LIMITER_ENABLE__SHIFT 0x19 9745 #define DAGB5_WRCLI2__MAX_OSD__SHIFT 0x1a 9746 #define DAGB5_WRCLI2__VIRT_CHAN_MASK 0x00000007L 9747 #define DAGB5_WRCLI2__CHECK_TLB_CREDIT_MASK 0x00000008L 9748 #define DAGB5_WRCLI2__URG_HIGH_MASK 0x000000F0L 9749 #define DAGB5_WRCLI2__URG_LOW_MASK 0x00000F00L 9750 #define DAGB5_WRCLI2__MAX_BW_ENABLE_MASK 0x00001000L 9751 #define DAGB5_WRCLI2__MAX_BW_MASK 0x001FE000L 9752 #define DAGB5_WRCLI2__MIN_BW_ENABLE_MASK 0x00200000L 9753 #define DAGB5_WRCLI2__MIN_BW_MASK 0x01C00000L 9754 #define DAGB5_WRCLI2__OSD_LIMITER_ENABLE_MASK 0x02000000L 9755 #define DAGB5_WRCLI2__MAX_OSD_MASK 0xFC000000L 9756 //DAGB5_WRCLI3 9757 #define DAGB5_WRCLI3__VIRT_CHAN__SHIFT 0x0 9758 #define DAGB5_WRCLI3__CHECK_TLB_CREDIT__SHIFT 0x3 9759 #define DAGB5_WRCLI3__URG_HIGH__SHIFT 0x4 9760 #define DAGB5_WRCLI3__URG_LOW__SHIFT 0x8 9761 #define DAGB5_WRCLI3__MAX_BW_ENABLE__SHIFT 0xc 9762 #define DAGB5_WRCLI3__MAX_BW__SHIFT 0xd 9763 #define DAGB5_WRCLI3__MIN_BW_ENABLE__SHIFT 0x15 9764 #define DAGB5_WRCLI3__MIN_BW__SHIFT 0x16 9765 #define DAGB5_WRCLI3__OSD_LIMITER_ENABLE__SHIFT 0x19 9766 #define DAGB5_WRCLI3__MAX_OSD__SHIFT 0x1a 9767 #define DAGB5_WRCLI3__VIRT_CHAN_MASK 0x00000007L 9768 #define DAGB5_WRCLI3__CHECK_TLB_CREDIT_MASK 0x00000008L 9769 #define DAGB5_WRCLI3__URG_HIGH_MASK 0x000000F0L 9770 #define DAGB5_WRCLI3__URG_LOW_MASK 0x00000F00L 9771 #define DAGB5_WRCLI3__MAX_BW_ENABLE_MASK 0x00001000L 9772 #define DAGB5_WRCLI3__MAX_BW_MASK 0x001FE000L 9773 #define DAGB5_WRCLI3__MIN_BW_ENABLE_MASK 0x00200000L 9774 #define DAGB5_WRCLI3__MIN_BW_MASK 0x01C00000L 9775 #define DAGB5_WRCLI3__OSD_LIMITER_ENABLE_MASK 0x02000000L 9776 #define DAGB5_WRCLI3__MAX_OSD_MASK 0xFC000000L 9777 //DAGB5_WRCLI4 9778 #define DAGB5_WRCLI4__VIRT_CHAN__SHIFT 0x0 9779 #define DAGB5_WRCLI4__CHECK_TLB_CREDIT__SHIFT 0x3 9780 #define DAGB5_WRCLI4__URG_HIGH__SHIFT 0x4 9781 #define DAGB5_WRCLI4__URG_LOW__SHIFT 0x8 9782 #define DAGB5_WRCLI4__MAX_BW_ENABLE__SHIFT 0xc 9783 #define DAGB5_WRCLI4__MAX_BW__SHIFT 0xd 9784 #define DAGB5_WRCLI4__MIN_BW_ENABLE__SHIFT 0x15 9785 #define DAGB5_WRCLI4__MIN_BW__SHIFT 0x16 9786 #define DAGB5_WRCLI4__OSD_LIMITER_ENABLE__SHIFT 0x19 9787 #define DAGB5_WRCLI4__MAX_OSD__SHIFT 0x1a 9788 #define DAGB5_WRCLI4__VIRT_CHAN_MASK 0x00000007L 9789 #define DAGB5_WRCLI4__CHECK_TLB_CREDIT_MASK 0x00000008L 9790 #define DAGB5_WRCLI4__URG_HIGH_MASK 0x000000F0L 9791 #define DAGB5_WRCLI4__URG_LOW_MASK 0x00000F00L 9792 #define DAGB5_WRCLI4__MAX_BW_ENABLE_MASK 0x00001000L 9793 #define DAGB5_WRCLI4__MAX_BW_MASK 0x001FE000L 9794 #define DAGB5_WRCLI4__MIN_BW_ENABLE_MASK 0x00200000L 9795 #define DAGB5_WRCLI4__MIN_BW_MASK 0x01C00000L 9796 #define DAGB5_WRCLI4__OSD_LIMITER_ENABLE_MASK 0x02000000L 9797 #define DAGB5_WRCLI4__MAX_OSD_MASK 0xFC000000L 9798 //DAGB5_WRCLI5 9799 #define DAGB5_WRCLI5__VIRT_CHAN__SHIFT 0x0 9800 #define DAGB5_WRCLI5__CHECK_TLB_CREDIT__SHIFT 0x3 9801 #define DAGB5_WRCLI5__URG_HIGH__SHIFT 0x4 9802 #define DAGB5_WRCLI5__URG_LOW__SHIFT 0x8 9803 #define DAGB5_WRCLI5__MAX_BW_ENABLE__SHIFT 0xc 9804 #define DAGB5_WRCLI5__MAX_BW__SHIFT 0xd 9805 #define DAGB5_WRCLI5__MIN_BW_ENABLE__SHIFT 0x15 9806 #define DAGB5_WRCLI5__MIN_BW__SHIFT 0x16 9807 #define DAGB5_WRCLI5__OSD_LIMITER_ENABLE__SHIFT 0x19 9808 #define DAGB5_WRCLI5__MAX_OSD__SHIFT 0x1a 9809 #define DAGB5_WRCLI5__VIRT_CHAN_MASK 0x00000007L 9810 #define DAGB5_WRCLI5__CHECK_TLB_CREDIT_MASK 0x00000008L 9811 #define DAGB5_WRCLI5__URG_HIGH_MASK 0x000000F0L 9812 #define DAGB5_WRCLI5__URG_LOW_MASK 0x00000F00L 9813 #define DAGB5_WRCLI5__MAX_BW_ENABLE_MASK 0x00001000L 9814 #define DAGB5_WRCLI5__MAX_BW_MASK 0x001FE000L 9815 #define DAGB5_WRCLI5__MIN_BW_ENABLE_MASK 0x00200000L 9816 #define DAGB5_WRCLI5__MIN_BW_MASK 0x01C00000L 9817 #define DAGB5_WRCLI5__OSD_LIMITER_ENABLE_MASK 0x02000000L 9818 #define DAGB5_WRCLI5__MAX_OSD_MASK 0xFC000000L 9819 //DAGB5_WRCLI6 9820 #define DAGB5_WRCLI6__VIRT_CHAN__SHIFT 0x0 9821 #define DAGB5_WRCLI6__CHECK_TLB_CREDIT__SHIFT 0x3 9822 #define DAGB5_WRCLI6__URG_HIGH__SHIFT 0x4 9823 #define DAGB5_WRCLI6__URG_LOW__SHIFT 0x8 9824 #define DAGB5_WRCLI6__MAX_BW_ENABLE__SHIFT 0xc 9825 #define DAGB5_WRCLI6__MAX_BW__SHIFT 0xd 9826 #define DAGB5_WRCLI6__MIN_BW_ENABLE__SHIFT 0x15 9827 #define DAGB5_WRCLI6__MIN_BW__SHIFT 0x16 9828 #define DAGB5_WRCLI6__OSD_LIMITER_ENABLE__SHIFT 0x19 9829 #define DAGB5_WRCLI6__MAX_OSD__SHIFT 0x1a 9830 #define DAGB5_WRCLI6__VIRT_CHAN_MASK 0x00000007L 9831 #define DAGB5_WRCLI6__CHECK_TLB_CREDIT_MASK 0x00000008L 9832 #define DAGB5_WRCLI6__URG_HIGH_MASK 0x000000F0L 9833 #define DAGB5_WRCLI6__URG_LOW_MASK 0x00000F00L 9834 #define DAGB5_WRCLI6__MAX_BW_ENABLE_MASK 0x00001000L 9835 #define DAGB5_WRCLI6__MAX_BW_MASK 0x001FE000L 9836 #define DAGB5_WRCLI6__MIN_BW_ENABLE_MASK 0x00200000L 9837 #define DAGB5_WRCLI6__MIN_BW_MASK 0x01C00000L 9838 #define DAGB5_WRCLI6__OSD_LIMITER_ENABLE_MASK 0x02000000L 9839 #define DAGB5_WRCLI6__MAX_OSD_MASK 0xFC000000L 9840 //DAGB5_WRCLI7 9841 #define DAGB5_WRCLI7__VIRT_CHAN__SHIFT 0x0 9842 #define DAGB5_WRCLI7__CHECK_TLB_CREDIT__SHIFT 0x3 9843 #define DAGB5_WRCLI7__URG_HIGH__SHIFT 0x4 9844 #define DAGB5_WRCLI7__URG_LOW__SHIFT 0x8 9845 #define DAGB5_WRCLI7__MAX_BW_ENABLE__SHIFT 0xc 9846 #define DAGB5_WRCLI7__MAX_BW__SHIFT 0xd 9847 #define DAGB5_WRCLI7__MIN_BW_ENABLE__SHIFT 0x15 9848 #define DAGB5_WRCLI7__MIN_BW__SHIFT 0x16 9849 #define DAGB5_WRCLI7__OSD_LIMITER_ENABLE__SHIFT 0x19 9850 #define DAGB5_WRCLI7__MAX_OSD__SHIFT 0x1a 9851 #define DAGB5_WRCLI7__VIRT_CHAN_MASK 0x00000007L 9852 #define DAGB5_WRCLI7__CHECK_TLB_CREDIT_MASK 0x00000008L 9853 #define DAGB5_WRCLI7__URG_HIGH_MASK 0x000000F0L 9854 #define DAGB5_WRCLI7__URG_LOW_MASK 0x00000F00L 9855 #define DAGB5_WRCLI7__MAX_BW_ENABLE_MASK 0x00001000L 9856 #define DAGB5_WRCLI7__MAX_BW_MASK 0x001FE000L 9857 #define DAGB5_WRCLI7__MIN_BW_ENABLE_MASK 0x00200000L 9858 #define DAGB5_WRCLI7__MIN_BW_MASK 0x01C00000L 9859 #define DAGB5_WRCLI7__OSD_LIMITER_ENABLE_MASK 0x02000000L 9860 #define DAGB5_WRCLI7__MAX_OSD_MASK 0xFC000000L 9861 //DAGB5_WRCLI8 9862 #define DAGB5_WRCLI8__VIRT_CHAN__SHIFT 0x0 9863 #define DAGB5_WRCLI8__CHECK_TLB_CREDIT__SHIFT 0x3 9864 #define DAGB5_WRCLI8__URG_HIGH__SHIFT 0x4 9865 #define DAGB5_WRCLI8__URG_LOW__SHIFT 0x8 9866 #define DAGB5_WRCLI8__MAX_BW_ENABLE__SHIFT 0xc 9867 #define DAGB5_WRCLI8__MAX_BW__SHIFT 0xd 9868 #define DAGB5_WRCLI8__MIN_BW_ENABLE__SHIFT 0x15 9869 #define DAGB5_WRCLI8__MIN_BW__SHIFT 0x16 9870 #define DAGB5_WRCLI8__OSD_LIMITER_ENABLE__SHIFT 0x19 9871 #define DAGB5_WRCLI8__MAX_OSD__SHIFT 0x1a 9872 #define DAGB5_WRCLI8__VIRT_CHAN_MASK 0x00000007L 9873 #define DAGB5_WRCLI8__CHECK_TLB_CREDIT_MASK 0x00000008L 9874 #define DAGB5_WRCLI8__URG_HIGH_MASK 0x000000F0L 9875 #define DAGB5_WRCLI8__URG_LOW_MASK 0x00000F00L 9876 #define DAGB5_WRCLI8__MAX_BW_ENABLE_MASK 0x00001000L 9877 #define DAGB5_WRCLI8__MAX_BW_MASK 0x001FE000L 9878 #define DAGB5_WRCLI8__MIN_BW_ENABLE_MASK 0x00200000L 9879 #define DAGB5_WRCLI8__MIN_BW_MASK 0x01C00000L 9880 #define DAGB5_WRCLI8__OSD_LIMITER_ENABLE_MASK 0x02000000L 9881 #define DAGB5_WRCLI8__MAX_OSD_MASK 0xFC000000L 9882 //DAGB5_WRCLI9 9883 #define DAGB5_WRCLI9__VIRT_CHAN__SHIFT 0x0 9884 #define DAGB5_WRCLI9__CHECK_TLB_CREDIT__SHIFT 0x3 9885 #define DAGB5_WRCLI9__URG_HIGH__SHIFT 0x4 9886 #define DAGB5_WRCLI9__URG_LOW__SHIFT 0x8 9887 #define DAGB5_WRCLI9__MAX_BW_ENABLE__SHIFT 0xc 9888 #define DAGB5_WRCLI9__MAX_BW__SHIFT 0xd 9889 #define DAGB5_WRCLI9__MIN_BW_ENABLE__SHIFT 0x15 9890 #define DAGB5_WRCLI9__MIN_BW__SHIFT 0x16 9891 #define DAGB5_WRCLI9__OSD_LIMITER_ENABLE__SHIFT 0x19 9892 #define DAGB5_WRCLI9__MAX_OSD__SHIFT 0x1a 9893 #define DAGB5_WRCLI9__VIRT_CHAN_MASK 0x00000007L 9894 #define DAGB5_WRCLI9__CHECK_TLB_CREDIT_MASK 0x00000008L 9895 #define DAGB5_WRCLI9__URG_HIGH_MASK 0x000000F0L 9896 #define DAGB5_WRCLI9__URG_LOW_MASK 0x00000F00L 9897 #define DAGB5_WRCLI9__MAX_BW_ENABLE_MASK 0x00001000L 9898 #define DAGB5_WRCLI9__MAX_BW_MASK 0x001FE000L 9899 #define DAGB5_WRCLI9__MIN_BW_ENABLE_MASK 0x00200000L 9900 #define DAGB5_WRCLI9__MIN_BW_MASK 0x01C00000L 9901 #define DAGB5_WRCLI9__OSD_LIMITER_ENABLE_MASK 0x02000000L 9902 #define DAGB5_WRCLI9__MAX_OSD_MASK 0xFC000000L 9903 //DAGB5_WRCLI10 9904 #define DAGB5_WRCLI10__VIRT_CHAN__SHIFT 0x0 9905 #define DAGB5_WRCLI10__CHECK_TLB_CREDIT__SHIFT 0x3 9906 #define DAGB5_WRCLI10__URG_HIGH__SHIFT 0x4 9907 #define DAGB5_WRCLI10__URG_LOW__SHIFT 0x8 9908 #define DAGB5_WRCLI10__MAX_BW_ENABLE__SHIFT 0xc 9909 #define DAGB5_WRCLI10__MAX_BW__SHIFT 0xd 9910 #define DAGB5_WRCLI10__MIN_BW_ENABLE__SHIFT 0x15 9911 #define DAGB5_WRCLI10__MIN_BW__SHIFT 0x16 9912 #define DAGB5_WRCLI10__OSD_LIMITER_ENABLE__SHIFT 0x19 9913 #define DAGB5_WRCLI10__MAX_OSD__SHIFT 0x1a 9914 #define DAGB5_WRCLI10__VIRT_CHAN_MASK 0x00000007L 9915 #define DAGB5_WRCLI10__CHECK_TLB_CREDIT_MASK 0x00000008L 9916 #define DAGB5_WRCLI10__URG_HIGH_MASK 0x000000F0L 9917 #define DAGB5_WRCLI10__URG_LOW_MASK 0x00000F00L 9918 #define DAGB5_WRCLI10__MAX_BW_ENABLE_MASK 0x00001000L 9919 #define DAGB5_WRCLI10__MAX_BW_MASK 0x001FE000L 9920 #define DAGB5_WRCLI10__MIN_BW_ENABLE_MASK 0x00200000L 9921 #define DAGB5_WRCLI10__MIN_BW_MASK 0x01C00000L 9922 #define DAGB5_WRCLI10__OSD_LIMITER_ENABLE_MASK 0x02000000L 9923 #define DAGB5_WRCLI10__MAX_OSD_MASK 0xFC000000L 9924 //DAGB5_WRCLI11 9925 #define DAGB5_WRCLI11__VIRT_CHAN__SHIFT 0x0 9926 #define DAGB5_WRCLI11__CHECK_TLB_CREDIT__SHIFT 0x3 9927 #define DAGB5_WRCLI11__URG_HIGH__SHIFT 0x4 9928 #define DAGB5_WRCLI11__URG_LOW__SHIFT 0x8 9929 #define DAGB5_WRCLI11__MAX_BW_ENABLE__SHIFT 0xc 9930 #define DAGB5_WRCLI11__MAX_BW__SHIFT 0xd 9931 #define DAGB5_WRCLI11__MIN_BW_ENABLE__SHIFT 0x15 9932 #define DAGB5_WRCLI11__MIN_BW__SHIFT 0x16 9933 #define DAGB5_WRCLI11__OSD_LIMITER_ENABLE__SHIFT 0x19 9934 #define DAGB5_WRCLI11__MAX_OSD__SHIFT 0x1a 9935 #define DAGB5_WRCLI11__VIRT_CHAN_MASK 0x00000007L 9936 #define DAGB5_WRCLI11__CHECK_TLB_CREDIT_MASK 0x00000008L 9937 #define DAGB5_WRCLI11__URG_HIGH_MASK 0x000000F0L 9938 #define DAGB5_WRCLI11__URG_LOW_MASK 0x00000F00L 9939 #define DAGB5_WRCLI11__MAX_BW_ENABLE_MASK 0x00001000L 9940 #define DAGB5_WRCLI11__MAX_BW_MASK 0x001FE000L 9941 #define DAGB5_WRCLI11__MIN_BW_ENABLE_MASK 0x00200000L 9942 #define DAGB5_WRCLI11__MIN_BW_MASK 0x01C00000L 9943 #define DAGB5_WRCLI11__OSD_LIMITER_ENABLE_MASK 0x02000000L 9944 #define DAGB5_WRCLI11__MAX_OSD_MASK 0xFC000000L 9945 //DAGB5_WRCLI12 9946 #define DAGB5_WRCLI12__VIRT_CHAN__SHIFT 0x0 9947 #define DAGB5_WRCLI12__CHECK_TLB_CREDIT__SHIFT 0x3 9948 #define DAGB5_WRCLI12__URG_HIGH__SHIFT 0x4 9949 #define DAGB5_WRCLI12__URG_LOW__SHIFT 0x8 9950 #define DAGB5_WRCLI12__MAX_BW_ENABLE__SHIFT 0xc 9951 #define DAGB5_WRCLI12__MAX_BW__SHIFT 0xd 9952 #define DAGB5_WRCLI12__MIN_BW_ENABLE__SHIFT 0x15 9953 #define DAGB5_WRCLI12__MIN_BW__SHIFT 0x16 9954 #define DAGB5_WRCLI12__OSD_LIMITER_ENABLE__SHIFT 0x19 9955 #define DAGB5_WRCLI12__MAX_OSD__SHIFT 0x1a 9956 #define DAGB5_WRCLI12__VIRT_CHAN_MASK 0x00000007L 9957 #define DAGB5_WRCLI12__CHECK_TLB_CREDIT_MASK 0x00000008L 9958 #define DAGB5_WRCLI12__URG_HIGH_MASK 0x000000F0L 9959 #define DAGB5_WRCLI12__URG_LOW_MASK 0x00000F00L 9960 #define DAGB5_WRCLI12__MAX_BW_ENABLE_MASK 0x00001000L 9961 #define DAGB5_WRCLI12__MAX_BW_MASK 0x001FE000L 9962 #define DAGB5_WRCLI12__MIN_BW_ENABLE_MASK 0x00200000L 9963 #define DAGB5_WRCLI12__MIN_BW_MASK 0x01C00000L 9964 #define DAGB5_WRCLI12__OSD_LIMITER_ENABLE_MASK 0x02000000L 9965 #define DAGB5_WRCLI12__MAX_OSD_MASK 0xFC000000L 9966 //DAGB5_WRCLI13 9967 #define DAGB5_WRCLI13__VIRT_CHAN__SHIFT 0x0 9968 #define DAGB5_WRCLI13__CHECK_TLB_CREDIT__SHIFT 0x3 9969 #define DAGB5_WRCLI13__URG_HIGH__SHIFT 0x4 9970 #define DAGB5_WRCLI13__URG_LOW__SHIFT 0x8 9971 #define DAGB5_WRCLI13__MAX_BW_ENABLE__SHIFT 0xc 9972 #define DAGB5_WRCLI13__MAX_BW__SHIFT 0xd 9973 #define DAGB5_WRCLI13__MIN_BW_ENABLE__SHIFT 0x15 9974 #define DAGB5_WRCLI13__MIN_BW__SHIFT 0x16 9975 #define DAGB5_WRCLI13__OSD_LIMITER_ENABLE__SHIFT 0x19 9976 #define DAGB5_WRCLI13__MAX_OSD__SHIFT 0x1a 9977 #define DAGB5_WRCLI13__VIRT_CHAN_MASK 0x00000007L 9978 #define DAGB5_WRCLI13__CHECK_TLB_CREDIT_MASK 0x00000008L 9979 #define DAGB5_WRCLI13__URG_HIGH_MASK 0x000000F0L 9980 #define DAGB5_WRCLI13__URG_LOW_MASK 0x00000F00L 9981 #define DAGB5_WRCLI13__MAX_BW_ENABLE_MASK 0x00001000L 9982 #define DAGB5_WRCLI13__MAX_BW_MASK 0x001FE000L 9983 #define DAGB5_WRCLI13__MIN_BW_ENABLE_MASK 0x00200000L 9984 #define DAGB5_WRCLI13__MIN_BW_MASK 0x01C00000L 9985 #define DAGB5_WRCLI13__OSD_LIMITER_ENABLE_MASK 0x02000000L 9986 #define DAGB5_WRCLI13__MAX_OSD_MASK 0xFC000000L 9987 //DAGB5_WRCLI14 9988 #define DAGB5_WRCLI14__VIRT_CHAN__SHIFT 0x0 9989 #define DAGB5_WRCLI14__CHECK_TLB_CREDIT__SHIFT 0x3 9990 #define DAGB5_WRCLI14__URG_HIGH__SHIFT 0x4 9991 #define DAGB5_WRCLI14__URG_LOW__SHIFT 0x8 9992 #define DAGB5_WRCLI14__MAX_BW_ENABLE__SHIFT 0xc 9993 #define DAGB5_WRCLI14__MAX_BW__SHIFT 0xd 9994 #define DAGB5_WRCLI14__MIN_BW_ENABLE__SHIFT 0x15 9995 #define DAGB5_WRCLI14__MIN_BW__SHIFT 0x16 9996 #define DAGB5_WRCLI14__OSD_LIMITER_ENABLE__SHIFT 0x19 9997 #define DAGB5_WRCLI14__MAX_OSD__SHIFT 0x1a 9998 #define DAGB5_WRCLI14__VIRT_CHAN_MASK 0x00000007L 9999 #define DAGB5_WRCLI14__CHECK_TLB_CREDIT_MASK 0x00000008L 10000 #define DAGB5_WRCLI14__URG_HIGH_MASK 0x000000F0L 10001 #define DAGB5_WRCLI14__URG_LOW_MASK 0x00000F00L 10002 #define DAGB5_WRCLI14__MAX_BW_ENABLE_MASK 0x00001000L 10003 #define DAGB5_WRCLI14__MAX_BW_MASK 0x001FE000L 10004 #define DAGB5_WRCLI14__MIN_BW_ENABLE_MASK 0x00200000L 10005 #define DAGB5_WRCLI14__MIN_BW_MASK 0x01C00000L 10006 #define DAGB5_WRCLI14__OSD_LIMITER_ENABLE_MASK 0x02000000L 10007 #define DAGB5_WRCLI14__MAX_OSD_MASK 0xFC000000L 10008 //DAGB5_WRCLI15 10009 #define DAGB5_WRCLI15__VIRT_CHAN__SHIFT 0x0 10010 #define DAGB5_WRCLI15__CHECK_TLB_CREDIT__SHIFT 0x3 10011 #define DAGB5_WRCLI15__URG_HIGH__SHIFT 0x4 10012 #define DAGB5_WRCLI15__URG_LOW__SHIFT 0x8 10013 #define DAGB5_WRCLI15__MAX_BW_ENABLE__SHIFT 0xc 10014 #define DAGB5_WRCLI15__MAX_BW__SHIFT 0xd 10015 #define DAGB5_WRCLI15__MIN_BW_ENABLE__SHIFT 0x15 10016 #define DAGB5_WRCLI15__MIN_BW__SHIFT 0x16 10017 #define DAGB5_WRCLI15__OSD_LIMITER_ENABLE__SHIFT 0x19 10018 #define DAGB5_WRCLI15__MAX_OSD__SHIFT 0x1a 10019 #define DAGB5_WRCLI15__VIRT_CHAN_MASK 0x00000007L 10020 #define DAGB5_WRCLI15__CHECK_TLB_CREDIT_MASK 0x00000008L 10021 #define DAGB5_WRCLI15__URG_HIGH_MASK 0x000000F0L 10022 #define DAGB5_WRCLI15__URG_LOW_MASK 0x00000F00L 10023 #define DAGB5_WRCLI15__MAX_BW_ENABLE_MASK 0x00001000L 10024 #define DAGB5_WRCLI15__MAX_BW_MASK 0x001FE000L 10025 #define DAGB5_WRCLI15__MIN_BW_ENABLE_MASK 0x00200000L 10026 #define DAGB5_WRCLI15__MIN_BW_MASK 0x01C00000L 10027 #define DAGB5_WRCLI15__OSD_LIMITER_ENABLE_MASK 0x02000000L 10028 #define DAGB5_WRCLI15__MAX_OSD_MASK 0xFC000000L 10029 //DAGB5_WR_CNTL 10030 #define DAGB5_WR_CNTL__SCLK_FREQ__SHIFT 0x0 10031 #define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW__SHIFT 0x4 10032 #define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW__SHIFT 0xa 10033 #define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE__SHIFT 0x10 10034 #define DAGB5_WR_CNTL__IO_LEVEL__SHIFT 0x11 10035 #define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC__SHIFT 0x14 10036 #define DAGB5_WR_CNTL__SHARE_VC_NUM__SHIFT 0x17 10037 #define DAGB5_WR_CNTL__FIX_JUMP__SHIFT 0x1a 10038 #define DAGB5_WR_CNTL__SCLK_FREQ_MASK 0x0000000FL 10039 #define DAGB5_WR_CNTL__CLI_MAX_BW_WINDOW_MASK 0x000003F0L 10040 #define DAGB5_WR_CNTL__VC_MAX_BW_WINDOW_MASK 0x0000FC00L 10041 #define DAGB5_WR_CNTL__IO_LEVEL_OVERRIDE_ENABLE_MASK 0x00010000L 10042 #define DAGB5_WR_CNTL__IO_LEVEL_MASK 0x000E0000L 10043 #define DAGB5_WR_CNTL__IO_LEVEL_COMPLY_VC_MASK 0x00700000L 10044 #define DAGB5_WR_CNTL__SHARE_VC_NUM_MASK 0x03800000L 10045 #define DAGB5_WR_CNTL__FIX_JUMP_MASK 0x04000000L 10046 //DAGB5_WR_GMI_CNTL 10047 #define DAGB5_WR_GMI_CNTL__EA_CREDIT__SHIFT 0x0 10048 #define DAGB5_WR_GMI_CNTL__LEVEL__SHIFT 0x6 10049 #define DAGB5_WR_GMI_CNTL__MAX_BURST__SHIFT 0x9 10050 #define DAGB5_WR_GMI_CNTL__LAZY_TIMER__SHIFT 0xd 10051 #define DAGB5_WR_GMI_CNTL__EA_CREDIT_MASK 0x0000003FL 10052 #define DAGB5_WR_GMI_CNTL__LEVEL_MASK 0x000001C0L 10053 #define DAGB5_WR_GMI_CNTL__MAX_BURST_MASK 0x00001E00L 10054 #define DAGB5_WR_GMI_CNTL__LAZY_TIMER_MASK 0x0001E000L 10055 //DAGB5_WR_ADDR_DAGB 10056 #define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE__SHIFT 0x0 10057 #define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 10058 #define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 10059 #define DAGB5_WR_ADDR_DAGB__WHOAMI__SHIFT 0x7 10060 #define DAGB5_WR_ADDR_DAGB__JUMP_MODE__SHIFT 0xd 10061 #define DAGB5_WR_ADDR_DAGB__DAGB_ENABLE_MASK 0x00000007L 10062 #define DAGB5_WR_ADDR_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 10063 #define DAGB5_WR_ADDR_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 10064 #define DAGB5_WR_ADDR_DAGB__WHOAMI_MASK 0x00001F80L 10065 #define DAGB5_WR_ADDR_DAGB__JUMP_MODE_MASK 0x00002000L 10066 //DAGB5_WR_OUTPUT_DAGB_MAX_BURST 10067 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0__SHIFT 0x0 10068 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1__SHIFT 0x4 10069 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2__SHIFT 0x8 10070 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3__SHIFT 0xc 10071 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4__SHIFT 0x10 10072 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5__SHIFT 0x14 10073 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6__SHIFT 0x18 10074 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7__SHIFT 0x1c 10075 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC0_MASK 0x0000000FL 10076 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC1_MASK 0x000000F0L 10077 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC2_MASK 0x00000F00L 10078 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC3_MASK 0x0000F000L 10079 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC4_MASK 0x000F0000L 10080 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC5_MASK 0x00F00000L 10081 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC6_MASK 0x0F000000L 10082 #define DAGB5_WR_OUTPUT_DAGB_MAX_BURST__VC7_MASK 0xF0000000L 10083 //DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER 10084 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0__SHIFT 0x0 10085 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1__SHIFT 0x4 10086 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2__SHIFT 0x8 10087 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3__SHIFT 0xc 10088 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4__SHIFT 0x10 10089 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5__SHIFT 0x14 10090 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6__SHIFT 0x18 10091 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7__SHIFT 0x1c 10092 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC0_MASK 0x0000000FL 10093 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC1_MASK 0x000000F0L 10094 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC2_MASK 0x00000F00L 10095 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC3_MASK 0x0000F000L 10096 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC4_MASK 0x000F0000L 10097 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC5_MASK 0x00F00000L 10098 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC6_MASK 0x0F000000L 10099 #define DAGB5_WR_OUTPUT_DAGB_LAZY_TIMER__VC7_MASK 0xF0000000L 10100 //DAGB5_WR_CGTT_CLK_CTRL 10101 #define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 10102 #define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 10103 #define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 10104 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 10105 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 10106 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 10107 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 10108 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 10109 #define DAGB5_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 10110 #define DAGB5_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 10111 #define DAGB5_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 10112 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 10113 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 10114 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 10115 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 10116 #define DAGB5_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 10117 //DAGB5_L1TLB_WR_CGTT_CLK_CTRL 10118 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 10119 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 10120 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 10121 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 10122 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 10123 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 10124 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 10125 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 10126 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 10127 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 10128 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 10129 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 10130 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 10131 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 10132 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 10133 #define DAGB5_L1TLB_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 10134 //DAGB5_ATCVM_WR_CGTT_CLK_CTRL 10135 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 10136 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 10137 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x16 10138 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 10139 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE__SHIFT 0x1c 10140 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ__SHIFT 0x1d 10141 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN__SHIFT 0x1e 10142 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER__SHIFT 0x1f 10143 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 10144 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 10145 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00400000L 10146 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 10147 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_WRITE_MASK 0x10000000L 10148 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_READ_MASK 0x20000000L 10149 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_RETURN_MASK 0x40000000L 10150 #define DAGB5_ATCVM_WR_CGTT_CLK_CTRL__LS_OVERRIDE_REGISTER_MASK 0x80000000L 10151 //DAGB5_WR_ADDR_DAGB_MAX_BURST0 10152 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 10153 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 10154 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 10155 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 10156 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 10157 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 10158 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 10159 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 10160 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 10161 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 10162 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 10163 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 10164 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 10165 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 10166 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 10167 #define DAGB5_WR_ADDR_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 10168 //DAGB5_WR_ADDR_DAGB_LAZY_TIMER0 10169 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 10170 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 10171 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 10172 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 10173 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 10174 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 10175 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 10176 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 10177 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 10178 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 10179 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 10180 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 10181 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 10182 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 10183 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 10184 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 10185 //DAGB5_WR_ADDR_DAGB_MAX_BURST1 10186 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 10187 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 10188 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 10189 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 10190 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 10191 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 10192 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 10193 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 10194 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 10195 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 10196 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 10197 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 10198 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 10199 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 10200 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 10201 #define DAGB5_WR_ADDR_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 10202 //DAGB5_WR_ADDR_DAGB_LAZY_TIMER1 10203 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 10204 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 10205 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 10206 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 10207 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 10208 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 10209 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 10210 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 10211 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 10212 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 10213 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 10214 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 10215 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 10216 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 10217 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 10218 #define DAGB5_WR_ADDR_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 10219 //DAGB5_WR_DATA_DAGB 10220 #define DAGB5_WR_DATA_DAGB__DAGB_ENABLE__SHIFT 0x0 10221 #define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD__SHIFT 0x3 10222 #define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT__SHIFT 0x6 10223 #define DAGB5_WR_DATA_DAGB__WHOAMI__SHIFT 0x7 10224 #define DAGB5_WR_DATA_DAGB__DAGB_ENABLE_MASK 0x00000007L 10225 #define DAGB5_WR_DATA_DAGB__ENABLE_JUMP_AHEAD_MASK 0x00000038L 10226 #define DAGB5_WR_DATA_DAGB__DISABLE_SELF_INIT_MASK 0x00000040L 10227 #define DAGB5_WR_DATA_DAGB__WHOAMI_MASK 0x00001F80L 10228 //DAGB5_WR_DATA_DAGB_MAX_BURST0 10229 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0__SHIFT 0x0 10230 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1__SHIFT 0x4 10231 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2__SHIFT 0x8 10232 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3__SHIFT 0xc 10233 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4__SHIFT 0x10 10234 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5__SHIFT 0x14 10235 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6__SHIFT 0x18 10236 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7__SHIFT 0x1c 10237 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT0_MASK 0x0000000FL 10238 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT1_MASK 0x000000F0L 10239 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT2_MASK 0x00000F00L 10240 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT3_MASK 0x0000F000L 10241 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT4_MASK 0x000F0000L 10242 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT5_MASK 0x00F00000L 10243 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT6_MASK 0x0F000000L 10244 #define DAGB5_WR_DATA_DAGB_MAX_BURST0__CLIENT7_MASK 0xF0000000L 10245 //DAGB5_WR_DATA_DAGB_LAZY_TIMER0 10246 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0__SHIFT 0x0 10247 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1__SHIFT 0x4 10248 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2__SHIFT 0x8 10249 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3__SHIFT 0xc 10250 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4__SHIFT 0x10 10251 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5__SHIFT 0x14 10252 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6__SHIFT 0x18 10253 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7__SHIFT 0x1c 10254 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT0_MASK 0x0000000FL 10255 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT1_MASK 0x000000F0L 10256 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT2_MASK 0x00000F00L 10257 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT3_MASK 0x0000F000L 10258 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT4_MASK 0x000F0000L 10259 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT5_MASK 0x00F00000L 10260 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT6_MASK 0x0F000000L 10261 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER0__CLIENT7_MASK 0xF0000000L 10262 //DAGB5_WR_DATA_DAGB_MAX_BURST1 10263 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8__SHIFT 0x0 10264 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9__SHIFT 0x4 10265 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10__SHIFT 0x8 10266 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11__SHIFT 0xc 10267 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12__SHIFT 0x10 10268 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13__SHIFT 0x14 10269 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14__SHIFT 0x18 10270 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15__SHIFT 0x1c 10271 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT8_MASK 0x0000000FL 10272 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT9_MASK 0x000000F0L 10273 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT10_MASK 0x00000F00L 10274 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT11_MASK 0x0000F000L 10275 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT12_MASK 0x000F0000L 10276 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT13_MASK 0x00F00000L 10277 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT14_MASK 0x0F000000L 10278 #define DAGB5_WR_DATA_DAGB_MAX_BURST1__CLIENT15_MASK 0xF0000000L 10279 //DAGB5_WR_DATA_DAGB_LAZY_TIMER1 10280 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8__SHIFT 0x0 10281 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9__SHIFT 0x4 10282 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10__SHIFT 0x8 10283 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11__SHIFT 0xc 10284 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12__SHIFT 0x10 10285 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13__SHIFT 0x14 10286 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14__SHIFT 0x18 10287 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15__SHIFT 0x1c 10288 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT8_MASK 0x0000000FL 10289 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT9_MASK 0x000000F0L 10290 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT10_MASK 0x00000F00L 10291 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT11_MASK 0x0000F000L 10292 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT12_MASK 0x000F0000L 10293 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT13_MASK 0x00F00000L 10294 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT14_MASK 0x0F000000L 10295 #define DAGB5_WR_DATA_DAGB_LAZY_TIMER1__CLIENT15_MASK 0xF0000000L 10296 //DAGB5_WR_VC0_CNTL 10297 #define DAGB5_WR_VC0_CNTL__STOR_CREDIT__SHIFT 0x0 10298 #define DAGB5_WR_VC0_CNTL__EA_CREDIT__SHIFT 0x5 10299 #define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10300 #define DAGB5_WR_VC0_CNTL__MAX_BW__SHIFT 0xc 10301 #define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10302 #define DAGB5_WR_VC0_CNTL__MIN_BW__SHIFT 0x15 10303 #define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10304 #define DAGB5_WR_VC0_CNTL__MAX_OSD__SHIFT 0x19 10305 #define DAGB5_WR_VC0_CNTL__STOR_CREDIT_MASK 0x0000001FL 10306 #define DAGB5_WR_VC0_CNTL__EA_CREDIT_MASK 0x000007E0L 10307 #define DAGB5_WR_VC0_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10308 #define DAGB5_WR_VC0_CNTL__MAX_BW_MASK 0x000FF000L 10309 #define DAGB5_WR_VC0_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10310 #define DAGB5_WR_VC0_CNTL__MIN_BW_MASK 0x00E00000L 10311 #define DAGB5_WR_VC0_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10312 #define DAGB5_WR_VC0_CNTL__MAX_OSD_MASK 0xFE000000L 10313 //DAGB5_WR_VC1_CNTL 10314 #define DAGB5_WR_VC1_CNTL__STOR_CREDIT__SHIFT 0x0 10315 #define DAGB5_WR_VC1_CNTL__EA_CREDIT__SHIFT 0x5 10316 #define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10317 #define DAGB5_WR_VC1_CNTL__MAX_BW__SHIFT 0xc 10318 #define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10319 #define DAGB5_WR_VC1_CNTL__MIN_BW__SHIFT 0x15 10320 #define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10321 #define DAGB5_WR_VC1_CNTL__MAX_OSD__SHIFT 0x19 10322 #define DAGB5_WR_VC1_CNTL__STOR_CREDIT_MASK 0x0000001FL 10323 #define DAGB5_WR_VC1_CNTL__EA_CREDIT_MASK 0x000007E0L 10324 #define DAGB5_WR_VC1_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10325 #define DAGB5_WR_VC1_CNTL__MAX_BW_MASK 0x000FF000L 10326 #define DAGB5_WR_VC1_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10327 #define DAGB5_WR_VC1_CNTL__MIN_BW_MASK 0x00E00000L 10328 #define DAGB5_WR_VC1_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10329 #define DAGB5_WR_VC1_CNTL__MAX_OSD_MASK 0xFE000000L 10330 //DAGB5_WR_VC2_CNTL 10331 #define DAGB5_WR_VC2_CNTL__STOR_CREDIT__SHIFT 0x0 10332 #define DAGB5_WR_VC2_CNTL__EA_CREDIT__SHIFT 0x5 10333 #define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10334 #define DAGB5_WR_VC2_CNTL__MAX_BW__SHIFT 0xc 10335 #define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10336 #define DAGB5_WR_VC2_CNTL__MIN_BW__SHIFT 0x15 10337 #define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10338 #define DAGB5_WR_VC2_CNTL__MAX_OSD__SHIFT 0x19 10339 #define DAGB5_WR_VC2_CNTL__STOR_CREDIT_MASK 0x0000001FL 10340 #define DAGB5_WR_VC2_CNTL__EA_CREDIT_MASK 0x000007E0L 10341 #define DAGB5_WR_VC2_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10342 #define DAGB5_WR_VC2_CNTL__MAX_BW_MASK 0x000FF000L 10343 #define DAGB5_WR_VC2_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10344 #define DAGB5_WR_VC2_CNTL__MIN_BW_MASK 0x00E00000L 10345 #define DAGB5_WR_VC2_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10346 #define DAGB5_WR_VC2_CNTL__MAX_OSD_MASK 0xFE000000L 10347 //DAGB5_WR_VC3_CNTL 10348 #define DAGB5_WR_VC3_CNTL__STOR_CREDIT__SHIFT 0x0 10349 #define DAGB5_WR_VC3_CNTL__EA_CREDIT__SHIFT 0x5 10350 #define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10351 #define DAGB5_WR_VC3_CNTL__MAX_BW__SHIFT 0xc 10352 #define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10353 #define DAGB5_WR_VC3_CNTL__MIN_BW__SHIFT 0x15 10354 #define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10355 #define DAGB5_WR_VC3_CNTL__MAX_OSD__SHIFT 0x19 10356 #define DAGB5_WR_VC3_CNTL__STOR_CREDIT_MASK 0x0000001FL 10357 #define DAGB5_WR_VC3_CNTL__EA_CREDIT_MASK 0x000007E0L 10358 #define DAGB5_WR_VC3_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10359 #define DAGB5_WR_VC3_CNTL__MAX_BW_MASK 0x000FF000L 10360 #define DAGB5_WR_VC3_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10361 #define DAGB5_WR_VC3_CNTL__MIN_BW_MASK 0x00E00000L 10362 #define DAGB5_WR_VC3_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10363 #define DAGB5_WR_VC3_CNTL__MAX_OSD_MASK 0xFE000000L 10364 //DAGB5_WR_VC4_CNTL 10365 #define DAGB5_WR_VC4_CNTL__STOR_CREDIT__SHIFT 0x0 10366 #define DAGB5_WR_VC4_CNTL__EA_CREDIT__SHIFT 0x5 10367 #define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10368 #define DAGB5_WR_VC4_CNTL__MAX_BW__SHIFT 0xc 10369 #define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10370 #define DAGB5_WR_VC4_CNTL__MIN_BW__SHIFT 0x15 10371 #define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10372 #define DAGB5_WR_VC4_CNTL__MAX_OSD__SHIFT 0x19 10373 #define DAGB5_WR_VC4_CNTL__STOR_CREDIT_MASK 0x0000001FL 10374 #define DAGB5_WR_VC4_CNTL__EA_CREDIT_MASK 0x000007E0L 10375 #define DAGB5_WR_VC4_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10376 #define DAGB5_WR_VC4_CNTL__MAX_BW_MASK 0x000FF000L 10377 #define DAGB5_WR_VC4_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10378 #define DAGB5_WR_VC4_CNTL__MIN_BW_MASK 0x00E00000L 10379 #define DAGB5_WR_VC4_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10380 #define DAGB5_WR_VC4_CNTL__MAX_OSD_MASK 0xFE000000L 10381 //DAGB5_WR_VC5_CNTL 10382 #define DAGB5_WR_VC5_CNTL__STOR_CREDIT__SHIFT 0x0 10383 #define DAGB5_WR_VC5_CNTL__EA_CREDIT__SHIFT 0x5 10384 #define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10385 #define DAGB5_WR_VC5_CNTL__MAX_BW__SHIFT 0xc 10386 #define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10387 #define DAGB5_WR_VC5_CNTL__MIN_BW__SHIFT 0x15 10388 #define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10389 #define DAGB5_WR_VC5_CNTL__MAX_OSD__SHIFT 0x19 10390 #define DAGB5_WR_VC5_CNTL__STOR_CREDIT_MASK 0x0000001FL 10391 #define DAGB5_WR_VC5_CNTL__EA_CREDIT_MASK 0x000007E0L 10392 #define DAGB5_WR_VC5_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10393 #define DAGB5_WR_VC5_CNTL__MAX_BW_MASK 0x000FF000L 10394 #define DAGB5_WR_VC5_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10395 #define DAGB5_WR_VC5_CNTL__MIN_BW_MASK 0x00E00000L 10396 #define DAGB5_WR_VC5_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10397 #define DAGB5_WR_VC5_CNTL__MAX_OSD_MASK 0xFE000000L 10398 //DAGB5_WR_VC6_CNTL 10399 #define DAGB5_WR_VC6_CNTL__STOR_CREDIT__SHIFT 0x0 10400 #define DAGB5_WR_VC6_CNTL__EA_CREDIT__SHIFT 0x5 10401 #define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10402 #define DAGB5_WR_VC6_CNTL__MAX_BW__SHIFT 0xc 10403 #define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10404 #define DAGB5_WR_VC6_CNTL__MIN_BW__SHIFT 0x15 10405 #define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10406 #define DAGB5_WR_VC6_CNTL__MAX_OSD__SHIFT 0x19 10407 #define DAGB5_WR_VC6_CNTL__STOR_CREDIT_MASK 0x0000001FL 10408 #define DAGB5_WR_VC6_CNTL__EA_CREDIT_MASK 0x000007E0L 10409 #define DAGB5_WR_VC6_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10410 #define DAGB5_WR_VC6_CNTL__MAX_BW_MASK 0x000FF000L 10411 #define DAGB5_WR_VC6_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10412 #define DAGB5_WR_VC6_CNTL__MIN_BW_MASK 0x00E00000L 10413 #define DAGB5_WR_VC6_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10414 #define DAGB5_WR_VC6_CNTL__MAX_OSD_MASK 0xFE000000L 10415 //DAGB5_WR_VC7_CNTL 10416 #define DAGB5_WR_VC7_CNTL__STOR_CREDIT__SHIFT 0x0 10417 #define DAGB5_WR_VC7_CNTL__EA_CREDIT__SHIFT 0x5 10418 #define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE__SHIFT 0xb 10419 #define DAGB5_WR_VC7_CNTL__MAX_BW__SHIFT 0xc 10420 #define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE__SHIFT 0x14 10421 #define DAGB5_WR_VC7_CNTL__MIN_BW__SHIFT 0x15 10422 #define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE__SHIFT 0x18 10423 #define DAGB5_WR_VC7_CNTL__MAX_OSD__SHIFT 0x19 10424 #define DAGB5_WR_VC7_CNTL__STOR_CREDIT_MASK 0x0000001FL 10425 #define DAGB5_WR_VC7_CNTL__EA_CREDIT_MASK 0x000007E0L 10426 #define DAGB5_WR_VC7_CNTL__MAX_BW_ENABLE_MASK 0x00000800L 10427 #define DAGB5_WR_VC7_CNTL__MAX_BW_MASK 0x000FF000L 10428 #define DAGB5_WR_VC7_CNTL__MIN_BW_ENABLE_MASK 0x00100000L 10429 #define DAGB5_WR_VC7_CNTL__MIN_BW_MASK 0x00E00000L 10430 #define DAGB5_WR_VC7_CNTL__OSD_LIMITER_ENABLE_MASK 0x01000000L 10431 #define DAGB5_WR_VC7_CNTL__MAX_OSD_MASK 0xFE000000L 10432 //DAGB5_WR_CNTL_MISC 10433 #define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT__SHIFT 0x0 10434 #define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT__SHIFT 0x6 10435 #define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT__SHIFT 0xd 10436 #define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE__SHIFT 0x13 10437 #define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE__SHIFT 0x14 10438 #define DAGB5_WR_CNTL_MISC__UTCL2_CID__SHIFT 0x15 10439 #define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS__SHIFT 0x1a 10440 #define DAGB5_WR_CNTL_MISC__STOR_POOL_CREDIT_MASK 0x0000003FL 10441 #define DAGB5_WR_CNTL_MISC__EA_POOL_CREDIT_MASK 0x00001FC0L 10442 #define DAGB5_WR_CNTL_MISC__IO_EA_CREDIT_MASK 0x0007E000L 10443 #define DAGB5_WR_CNTL_MISC__STOR_CC_LEGACY_MODE_MASK 0x00080000L 10444 #define DAGB5_WR_CNTL_MISC__EA_CC_LEGACY_MODE_MASK 0x00100000L 10445 #define DAGB5_WR_CNTL_MISC__UTCL2_CID_MASK 0x03E00000L 10446 #define DAGB5_WR_CNTL_MISC__RDRET_FIFO_CREDITS_MASK 0xFC000000L 10447 //DAGB5_WR_TLB_CREDIT 10448 #define DAGB5_WR_TLB_CREDIT__TLB0__SHIFT 0x0 10449 #define DAGB5_WR_TLB_CREDIT__TLB1__SHIFT 0x5 10450 #define DAGB5_WR_TLB_CREDIT__TLB2__SHIFT 0xa 10451 #define DAGB5_WR_TLB_CREDIT__TLB3__SHIFT 0xf 10452 #define DAGB5_WR_TLB_CREDIT__TLB4__SHIFT 0x14 10453 #define DAGB5_WR_TLB_CREDIT__TLB5__SHIFT 0x19 10454 #define DAGB5_WR_TLB_CREDIT__TLB0_MASK 0x0000001FL 10455 #define DAGB5_WR_TLB_CREDIT__TLB1_MASK 0x000003E0L 10456 #define DAGB5_WR_TLB_CREDIT__TLB2_MASK 0x00007C00L 10457 #define DAGB5_WR_TLB_CREDIT__TLB3_MASK 0x000F8000L 10458 #define DAGB5_WR_TLB_CREDIT__TLB4_MASK 0x01F00000L 10459 #define DAGB5_WR_TLB_CREDIT__TLB5_MASK 0x3E000000L 10460 //DAGB5_WR_DATA_CREDIT 10461 #define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS__SHIFT 0x0 10462 #define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS__SHIFT 0x8 10463 #define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS__SHIFT 0x10 10464 #define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS__SHIFT 0x18 10465 #define DAGB5_WR_DATA_CREDIT__DLOCK_VC_CREDITS_MASK 0x000000FFL 10466 #define DAGB5_WR_DATA_CREDIT__LARGE_BURST_CREDITS_MASK 0x0000FF00L 10467 #define DAGB5_WR_DATA_CREDIT__MIDDLE_BURST_CREDITS_MASK 0x00FF0000L 10468 #define DAGB5_WR_DATA_CREDIT__SMALL_BURST_CREDITS_MASK 0xFF000000L 10469 //DAGB5_WR_MISC_CREDIT 10470 #define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT__SHIFT 0x0 10471 #define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM__SHIFT 0x6 10472 #define DAGB5_WR_MISC_CREDIT__OSD_CREDIT__SHIFT 0x9 10473 #define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT__SHIFT 0x10 10474 #define DAGB5_WR_MISC_CREDIT__ATOMIC_CREDIT_MASK 0x0000003FL 10475 #define DAGB5_WR_MISC_CREDIT__DLOCK_VC_NUM_MASK 0x000001C0L 10476 #define DAGB5_WR_MISC_CREDIT__OSD_CREDIT_MASK 0x0000FE00L 10477 #define DAGB5_WR_MISC_CREDIT__OSD_DLOCK_CREDIT_MASK 0x007F0000L 10478 //DAGB5_WR_OSD_CREDIT_CNTL1 10479 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 10480 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x4 10481 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0x8 10482 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xc 10483 #define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT__SHIFT 0x10 10484 #define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT__SHIFT 0x14 10485 #define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x18 10486 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000000FL 10487 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000000F0L 10488 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00000F00L 10489 #define DAGB5_WR_OSD_CREDIT_CNTL1__VC3_CREDIT_MASK 0x0000F000L 10490 #define DAGB5_WR_OSD_CREDIT_CNTL1__IO_CREDIT_MASK 0x000F0000L 10491 #define DAGB5_WR_OSD_CREDIT_CNTL1__GMI_CREDIT_MASK 0x00F00000L 10492 #define DAGB5_WR_OSD_CREDIT_CNTL1__POOL_CREDIT_MASK 0x3F000000L 10493 //DAGB5_WR_OSD_CREDIT_CNTL2 10494 #define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN__SHIFT 0x0 10495 #define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY__SHIFT 0x4 10496 #define DAGB5_WR_OSD_CREDIT_CNTL2__CREDIT_MARGIN_MASK 0x0000000FL 10497 #define DAGB5_WR_OSD_CREDIT_CNTL2__ENABLE_LEGACY_MASK 0x00000010L 10498 //DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1 10499 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT__SHIFT 0x0 10500 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT__SHIFT 0x5 10501 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT__SHIFT 0xa 10502 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT__SHIFT 0xf 10503 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT__SHIFT 0x14 10504 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE__SHIFT 0x19 10505 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ__SHIFT 0x1a 10506 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0__SHIFT 0x1b 10507 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1__SHIFT 0x1c 10508 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2__SHIFT 0x1d 10509 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC0_CREDIT_MASK 0x0000001FL 10510 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC1_CREDIT_MASK 0x000003E0L 10511 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC2_CREDIT_MASK 0x00007C00L 10512 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC3_CREDIT_MASK 0x000F8000L 10513 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__POOL_CREDIT_MASK 0x01F00000L 10514 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__VC_MODE_MASK 0x02000000L 10515 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX_EQ_MASK 0x04000000L 10516 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX0_MASK 0x08000000L 10517 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX1_MASK 0x10000000L 10518 #define DAGB5_WR_ATOMIC_FIFO_CREDIT_CNTL1__FIX2_MASK 0x20000000L 10519 //DAGB5_WRCLI_GPU_SNOOP_OVERRIDE 10520 #define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE__SHIFT 0x0 10521 #define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE__ENABLE_MASK 0xFFFFFFFFL 10522 //DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE 10523 #define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE__SHIFT 0x0 10524 #define DAGB5_WRCLI_GPU_SNOOP_OVERRIDE_VALUE__ENABLE_MASK 0xFFFFFFFFL 10525 //DAGB5_WRCLI_ASK_PENDING 10526 #define DAGB5_WRCLI_ASK_PENDING__BUSY__SHIFT 0x0 10527 #define DAGB5_WRCLI_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 10528 //DAGB5_WRCLI_GO_PENDING 10529 #define DAGB5_WRCLI_GO_PENDING__BUSY__SHIFT 0x0 10530 #define DAGB5_WRCLI_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 10531 //DAGB5_WRCLI_GBLSEND_PENDING 10532 #define DAGB5_WRCLI_GBLSEND_PENDING__BUSY__SHIFT 0x0 10533 #define DAGB5_WRCLI_GBLSEND_PENDING__BUSY_MASK 0xFFFFFFFFL 10534 //DAGB5_WRCLI_TLB_PENDING 10535 #define DAGB5_WRCLI_TLB_PENDING__BUSY__SHIFT 0x0 10536 #define DAGB5_WRCLI_TLB_PENDING__BUSY_MASK 0xFFFFFFFFL 10537 //DAGB5_WRCLI_OARB_PENDING 10538 #define DAGB5_WRCLI_OARB_PENDING__BUSY__SHIFT 0x0 10539 #define DAGB5_WRCLI_OARB_PENDING__BUSY_MASK 0xFFFFFFFFL 10540 //DAGB5_WRCLI_OSD_PENDING 10541 #define DAGB5_WRCLI_OSD_PENDING__BUSY__SHIFT 0x0 10542 #define DAGB5_WRCLI_OSD_PENDING__BUSY_MASK 0xFFFFFFFFL 10543 //DAGB5_WRCLI_DBUS_ASK_PENDING 10544 #define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY__SHIFT 0x0 10545 #define DAGB5_WRCLI_DBUS_ASK_PENDING__BUSY_MASK 0xFFFFFFFFL 10546 //DAGB5_WRCLI_DBUS_GO_PENDING 10547 #define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY__SHIFT 0x0 10548 #define DAGB5_WRCLI_DBUS_GO_PENDING__BUSY_MASK 0xFFFFFFFFL 10549 //DAGB5_DAGB_DLY 10550 #define DAGB5_DAGB_DLY__DLY__SHIFT 0x0 10551 #define DAGB5_DAGB_DLY__CLI__SHIFT 0x8 10552 #define DAGB5_DAGB_DLY__POS__SHIFT 0x10 10553 #define DAGB5_DAGB_DLY__DLY_MASK 0x000000FFL 10554 #define DAGB5_DAGB_DLY__CLI_MASK 0x0000FF00L 10555 #define DAGB5_DAGB_DLY__POS_MASK 0x000F0000L 10556 //DAGB5_CNTL_MISC 10557 #define DAGB5_CNTL_MISC__EA_VC0_REMAP__SHIFT 0x0 10558 #define DAGB5_CNTL_MISC__EA_VC1_REMAP__SHIFT 0x3 10559 #define DAGB5_CNTL_MISC__EA_VC2_REMAP__SHIFT 0x6 10560 #define DAGB5_CNTL_MISC__EA_VC3_REMAP__SHIFT 0x9 10561 #define DAGB5_CNTL_MISC__EA_VC4_REMAP__SHIFT 0xc 10562 #define DAGB5_CNTL_MISC__EA_VC5_REMAP__SHIFT 0xf 10563 #define DAGB5_CNTL_MISC__EA_VC6_REMAP__SHIFT 0x12 10564 #define DAGB5_CNTL_MISC__EA_VC7_REMAP__SHIFT 0x15 10565 #define DAGB5_CNTL_MISC__BW_INIT_CYCLE__SHIFT 0x18 10566 #define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE__SHIFT 0x1e 10567 #define DAGB5_CNTL_MISC__EA_VC0_REMAP_MASK 0x00000007L 10568 #define DAGB5_CNTL_MISC__EA_VC1_REMAP_MASK 0x00000038L 10569 #define DAGB5_CNTL_MISC__EA_VC2_REMAP_MASK 0x000001C0L 10570 #define DAGB5_CNTL_MISC__EA_VC3_REMAP_MASK 0x00000E00L 10571 #define DAGB5_CNTL_MISC__EA_VC4_REMAP_MASK 0x00007000L 10572 #define DAGB5_CNTL_MISC__EA_VC5_REMAP_MASK 0x00038000L 10573 #define DAGB5_CNTL_MISC__EA_VC6_REMAP_MASK 0x001C0000L 10574 #define DAGB5_CNTL_MISC__EA_VC7_REMAP_MASK 0x00E00000L 10575 #define DAGB5_CNTL_MISC__BW_INIT_CYCLE_MASK 0x3F000000L 10576 #define DAGB5_CNTL_MISC__BW_RW_GAP_CYCLE_MASK 0xC0000000L 10577 //DAGB5_CNTL_MISC2 10578 #define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE__SHIFT 0x0 10579 #define DAGB5_CNTL_MISC2__URG_HALT_ENABLE__SHIFT 0x1 10580 #define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG__SHIFT 0x2 10581 #define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG__SHIFT 0x3 10582 #define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG__SHIFT 0x4 10583 #define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG__SHIFT 0x5 10584 #define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG__SHIFT 0x6 10585 #define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG__SHIFT 0x7 10586 #define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY__SHIFT 0x8 10587 #define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY__SHIFT 0x9 10588 #define DAGB5_CNTL_MISC2__SWAP_CTL__SHIFT 0xa 10589 #define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF__SHIFT 0xb 10590 #define DAGB5_CNTL_MISC2__HDP_CID__SHIFT 0xc 10591 #define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS__SHIFT 0x11 10592 #define DAGB5_CNTL_MISC2__URG_BOOST_ENABLE_MASK 0x00000001L 10593 #define DAGB5_CNTL_MISC2__URG_HALT_ENABLE_MASK 0x00000002L 10594 #define DAGB5_CNTL_MISC2__DISABLE_WRREQ_CG_MASK 0x00000004L 10595 #define DAGB5_CNTL_MISC2__DISABLE_WRRET_CG_MASK 0x00000008L 10596 #define DAGB5_CNTL_MISC2__DISABLE_RDREQ_CG_MASK 0x00000010L 10597 #define DAGB5_CNTL_MISC2__DISABLE_RDRET_CG_MASK 0x00000020L 10598 #define DAGB5_CNTL_MISC2__DISABLE_TLBWR_CG_MASK 0x00000040L 10599 #define DAGB5_CNTL_MISC2__DISABLE_TLBRD_CG_MASK 0x00000080L 10600 #define DAGB5_CNTL_MISC2__DISABLE_EAWRREQ_BUSY_MASK 0x00000100L 10601 #define DAGB5_CNTL_MISC2__DISABLE_EARDREQ_BUSY_MASK 0x00000200L 10602 #define DAGB5_CNTL_MISC2__SWAP_CTL_MASK 0x00000400L 10603 #define DAGB5_CNTL_MISC2__RDRET_FIFO_PERF_MASK 0x00000800L 10604 #define DAGB5_CNTL_MISC2__HDP_CID_MASK 0x0001F000L 10605 #define DAGB5_CNTL_MISC2__RDRET_FIFO_DLOCK_CREDITS_MASK 0x007E0000L 10606 //DAGB5_FATAL_ERROR_CNTL 10607 #define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM__SHIFT 0x0 10608 #define DAGB5_FATAL_ERROR_CNTL__FILTER_NUM_MASK 0x000003FFL 10609 //DAGB5_FATAL_ERROR_CLEAR 10610 #define DAGB5_FATAL_ERROR_CLEAR__CLEAR__SHIFT 0x0 10611 #define DAGB5_FATAL_ERROR_CLEAR__CLEAR_MASK 0x00000001L 10612 //DAGB5_FATAL_ERROR_STATUS0 10613 #define DAGB5_FATAL_ERROR_STATUS0__VALID__SHIFT 0x0 10614 #define DAGB5_FATAL_ERROR_STATUS0__CID__SHIFT 0x1 10615 #define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO__SHIFT 0x6 10616 #define DAGB5_FATAL_ERROR_STATUS0__VALID_MASK 0x00000001L 10617 #define DAGB5_FATAL_ERROR_STATUS0__CID_MASK 0x0000003EL 10618 #define DAGB5_FATAL_ERROR_STATUS0__ADDR_LO_MASK 0xFFFFFFC0L 10619 //DAGB5_FATAL_ERROR_STATUS1 10620 #define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI__SHIFT 0x0 10621 #define DAGB5_FATAL_ERROR_STATUS1__ADDR_HI_MASK 0x0001FFFFL 10622 //DAGB5_FATAL_ERROR_STATUS2 10623 #define DAGB5_FATAL_ERROR_STATUS2__TAG__SHIFT 0x0 10624 #define DAGB5_FATAL_ERROR_STATUS2__VFID__SHIFT 0x10 10625 #define DAGB5_FATAL_ERROR_STATUS2__VF__SHIFT 0x14 10626 #define DAGB5_FATAL_ERROR_STATUS2__SPACE__SHIFT 0x15 10627 #define DAGB5_FATAL_ERROR_STATUS2__IO__SHIFT 0x16 10628 #define DAGB5_FATAL_ERROR_STATUS2__SIZE__SHIFT 0x17 10629 #define DAGB5_FATAL_ERROR_STATUS2__FED__SHIFT 0x19 10630 #define DAGB5_FATAL_ERROR_STATUS2__TAG_MASK 0x0000FFFFL 10631 #define DAGB5_FATAL_ERROR_STATUS2__VFID_MASK 0x000F0000L 10632 #define DAGB5_FATAL_ERROR_STATUS2__VF_MASK 0x00100000L 10633 #define DAGB5_FATAL_ERROR_STATUS2__SPACE_MASK 0x00200000L 10634 #define DAGB5_FATAL_ERROR_STATUS2__IO_MASK 0x00400000L 10635 #define DAGB5_FATAL_ERROR_STATUS2__SIZE_MASK 0x00800000L 10636 #define DAGB5_FATAL_ERROR_STATUS2__FED_MASK 0x02000000L 10637 //DAGB5_FATAL_ERROR_STATUS3 10638 #define DAGB5_FATAL_ERROR_STATUS3__OP__SHIFT 0x6 10639 #define DAGB5_FATAL_ERROR_STATUS3__WRTMZ__SHIFT 0x10 10640 #define DAGB5_FATAL_ERROR_STATUS3__RDTMZ__SHIFT 0x11 10641 #define DAGB5_FATAL_ERROR_STATUS3__SNOOP__SHIFT 0x12 10642 #define DAGB5_FATAL_ERROR_STATUS3__INVAL__SHIFT 0x13 10643 #define DAGB5_FATAL_ERROR_STATUS3__NACK__SHIFT 0x14 10644 #define DAGB5_FATAL_ERROR_STATUS3__RO__SHIFT 0x16 10645 #define DAGB5_FATAL_ERROR_STATUS3__MEMLOG__SHIFT 0x17 10646 #define DAGB5_FATAL_ERROR_STATUS3__EOP__SHIFT 0x18 10647 #define DAGB5_FATAL_ERROR_STATUS3__OP_MASK 0x00001FC0L 10648 #define DAGB5_FATAL_ERROR_STATUS3__WRTMZ_MASK 0x00010000L 10649 #define DAGB5_FATAL_ERROR_STATUS3__RDTMZ_MASK 0x00020000L 10650 #define DAGB5_FATAL_ERROR_STATUS3__SNOOP_MASK 0x00040000L 10651 #define DAGB5_FATAL_ERROR_STATUS3__INVAL_MASK 0x00080000L 10652 #define DAGB5_FATAL_ERROR_STATUS3__NACK_MASK 0x00300000L 10653 #define DAGB5_FATAL_ERROR_STATUS3__RO_MASK 0x00400000L 10654 #define DAGB5_FATAL_ERROR_STATUS3__MEMLOG_MASK 0x00800000L 10655 #define DAGB5_FATAL_ERROR_STATUS3__EOP_MASK 0x01000000L 10656 //DAGB5_FIFO_EMPTY 10657 #define DAGB5_FIFO_EMPTY__EMPTY__SHIFT 0x0 10658 #define DAGB5_FIFO_EMPTY__EMPTY_MASK 0x00FFFFFFL 10659 //DAGB5_FIFO_FULL 10660 #define DAGB5_FIFO_FULL__FULL__SHIFT 0x0 10661 #define DAGB5_FIFO_FULL__FULL_MASK 0x007FFFFFL 10662 //DAGB5_WR_CREDITS_FULL 10663 #define DAGB5_WR_CREDITS_FULL__FULL__SHIFT 0x0 10664 #define DAGB5_WR_CREDITS_FULL__FULL_MASK 0x1FFFFFFFL 10665 //DAGB5_RD_CREDITS_FULL 10666 #define DAGB5_RD_CREDITS_FULL__FULL__SHIFT 0x0 10667 #define DAGB5_RD_CREDITS_FULL__FULL_MASK 0x0003FFFFL 10668 //DAGB5_PERFCOUNTER_LO 10669 #define DAGB5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 10670 #define DAGB5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 10671 //DAGB5_PERFCOUNTER_HI 10672 #define DAGB5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 10673 #define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 10674 #define DAGB5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 10675 #define DAGB5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 10676 //DAGB5_PERFCOUNTER0_CFG 10677 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 10678 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 10679 #define DAGB5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 10680 #define DAGB5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 10681 #define DAGB5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 10682 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 10683 #define DAGB5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 10684 #define DAGB5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 10685 #define DAGB5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 10686 #define DAGB5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 10687 //DAGB5_PERFCOUNTER1_CFG 10688 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 10689 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 10690 #define DAGB5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 10691 #define DAGB5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 10692 #define DAGB5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 10693 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 10694 #define DAGB5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 10695 #define DAGB5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 10696 #define DAGB5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 10697 #define DAGB5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 10698 //DAGB5_PERFCOUNTER2_CFG 10699 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 10700 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 10701 #define DAGB5_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 10702 #define DAGB5_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 10703 #define DAGB5_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 10704 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 10705 #define DAGB5_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 10706 #define DAGB5_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 10707 #define DAGB5_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 10708 #define DAGB5_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 10709 //DAGB5_PERFCOUNTER_RSLT_CNTL 10710 #define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 10711 #define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 10712 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 10713 #define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 10714 #define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 10715 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 10716 #define DAGB5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 10717 #define DAGB5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 10718 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 10719 #define DAGB5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 10720 #define DAGB5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 10721 #define DAGB5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 10722 //DAGB5_L1TLB_REG_RW 10723 #define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL__SHIFT 0x0 10724 #define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL__SHIFT 0x1 10725 #define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL__SHIFT 0x2 10726 #define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK__SHIFT 0x4 10727 #define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK__SHIFT 0x5 10728 #define DAGB5_L1TLB_REG_RW__RESERVE__SHIFT 0x6 10729 #define DAGB5_L1TLB_REG_RW__REG_WRITE_L1TLB_CTRL_MASK 0x00000001L 10730 #define DAGB5_L1TLB_REG_RW__REG_READ_L1TLB_CTRL_MASK 0x00000002L 10731 #define DAGB5_L1TLB_REG_RW__VMID_EXCEP_INT_CTRL_MASK 0x00000004L 10732 #define DAGB5_L1TLB_REG_RW__WDAT_PARITY_CHECK_MASK 0x00000010L 10733 #define DAGB5_L1TLB_REG_RW__DISABLE_RDRET_CHECK_MASK 0x00000020L 10734 #define DAGB5_L1TLB_REG_RW__RESERVE_MASK 0xFFFFFFC0L 10735 //DAGB5_RESERVE1 10736 #define DAGB5_RESERVE1__RESERVE__SHIFT 0x0 10737 #define DAGB5_RESERVE1__RESERVE_MASK 0xFFFFFFFFL 10738 //DAGB5_RESERVE2 10739 #define DAGB5_RESERVE2__RESERVE__SHIFT 0x0 10740 #define DAGB5_RESERVE2__RESERVE_MASK 0xFFFFFFFFL 10741 //DAGB5_RESERVE3 10742 #define DAGB5_RESERVE3__RESERVE__SHIFT 0x0 10743 #define DAGB5_RESERVE3__RESERVE_MASK 0xFFFFFFFFL 10744 //DAGB5_RESERVE4 10745 #define DAGB5_RESERVE4__RESERVE__SHIFT 0x0 10746 #define DAGB5_RESERVE4__RESERVE_MASK 0xFFFFFFFFL 10747 10748 10749 // addressBlock: mmhub_ea_mmeadec0 10750 //MMEA0_DRAM_RD_CLI2GRP_MAP0 10751 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 10752 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 10753 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 10754 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 10755 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 10756 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 10757 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 10758 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 10759 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 10760 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 10761 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 10762 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 10763 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 10764 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 10765 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 10766 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 10767 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 10768 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 10769 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 10770 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 10771 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 10772 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 10773 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 10774 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 10775 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 10776 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 10777 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 10778 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 10779 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 10780 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 10781 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 10782 #define MMEA0_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 10783 //MMEA0_DRAM_RD_CLI2GRP_MAP1 10784 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 10785 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 10786 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 10787 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 10788 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 10789 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 10790 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 10791 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 10792 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 10793 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 10794 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 10795 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 10796 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 10797 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 10798 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 10799 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 10800 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 10801 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 10802 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 10803 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 10804 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 10805 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 10806 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 10807 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 10808 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 10809 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 10810 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 10811 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 10812 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 10813 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 10814 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 10815 #define MMEA0_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 10816 //MMEA0_DRAM_WR_CLI2GRP_MAP0 10817 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 10818 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 10819 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 10820 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 10821 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 10822 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 10823 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 10824 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 10825 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 10826 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 10827 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 10828 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 10829 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 10830 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 10831 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 10832 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 10833 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 10834 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 10835 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 10836 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 10837 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 10838 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 10839 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 10840 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 10841 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 10842 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 10843 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 10844 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 10845 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 10846 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 10847 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 10848 #define MMEA0_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 10849 //MMEA0_DRAM_WR_CLI2GRP_MAP1 10850 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 10851 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 10852 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 10853 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 10854 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 10855 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 10856 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 10857 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 10858 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 10859 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 10860 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 10861 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 10862 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 10863 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 10864 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 10865 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 10866 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 10867 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 10868 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 10869 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 10870 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 10871 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 10872 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 10873 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 10874 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 10875 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 10876 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 10877 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 10878 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 10879 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 10880 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 10881 #define MMEA0_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 10882 //MMEA0_DRAM_RD_GRP2VC_MAP 10883 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 10884 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 10885 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 10886 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 10887 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 10888 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 10889 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 10890 #define MMEA0_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 10891 //MMEA0_DRAM_WR_GRP2VC_MAP 10892 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 10893 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 10894 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 10895 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 10896 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 10897 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 10898 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 10899 #define MMEA0_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 10900 //MMEA0_DRAM_RD_LAZY 10901 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 10902 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 10903 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 10904 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 10905 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 10906 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 10907 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 10908 #define MMEA0_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 10909 #define MMEA0_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 10910 #define MMEA0_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 10911 #define MMEA0_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 10912 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 10913 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 10914 #define MMEA0_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 10915 //MMEA0_DRAM_WR_LAZY 10916 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 10917 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 10918 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 10919 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 10920 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 10921 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 10922 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 10923 #define MMEA0_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 10924 #define MMEA0_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 10925 #define MMEA0_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 10926 #define MMEA0_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 10927 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 10928 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 10929 #define MMEA0_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 10930 //MMEA0_DRAM_RD_CAM_CNTL 10931 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 10932 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 10933 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 10934 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 10935 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 10936 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 10937 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 10938 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 10939 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 10940 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 10941 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 10942 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 10943 #define MMEA0_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 10944 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 10945 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 10946 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 10947 #define MMEA0_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 10948 #define MMEA0_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 10949 //MMEA0_DRAM_WR_CAM_CNTL 10950 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 10951 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 10952 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 10953 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 10954 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 10955 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 10956 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 10957 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 10958 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 10959 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 10960 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 10961 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 10962 #define MMEA0_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 10963 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 10964 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 10965 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 10966 #define MMEA0_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 10967 #define MMEA0_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 10968 //MMEA0_DRAM_PAGE_BURST 10969 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 10970 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 10971 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 10972 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 10973 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 10974 #define MMEA0_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 10975 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 10976 #define MMEA0_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 10977 //MMEA0_DRAM_RD_PRI_AGE 10978 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 10979 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 10980 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 10981 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 10982 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 10983 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 10984 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 10985 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 10986 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 10987 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 10988 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 10989 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 10990 #define MMEA0_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 10991 #define MMEA0_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 10992 #define MMEA0_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 10993 #define MMEA0_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 10994 //MMEA0_DRAM_WR_PRI_AGE 10995 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 10996 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 10997 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 10998 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 10999 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 11000 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 11001 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 11002 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 11003 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 11004 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 11005 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 11006 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 11007 #define MMEA0_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 11008 #define MMEA0_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 11009 #define MMEA0_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 11010 #define MMEA0_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 11011 //MMEA0_DRAM_RD_PRI_QUEUING 11012 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 11013 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 11014 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 11015 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 11016 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 11017 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 11018 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 11019 #define MMEA0_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 11020 //MMEA0_DRAM_WR_PRI_QUEUING 11021 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 11022 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 11023 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 11024 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 11025 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 11026 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 11027 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 11028 #define MMEA0_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 11029 //MMEA0_DRAM_RD_PRI_FIXED 11030 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 11031 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 11032 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 11033 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 11034 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 11035 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 11036 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 11037 #define MMEA0_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 11038 //MMEA0_DRAM_WR_PRI_FIXED 11039 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 11040 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 11041 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 11042 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 11043 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 11044 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 11045 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 11046 #define MMEA0_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 11047 //MMEA0_DRAM_RD_PRI_URGENCY 11048 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 11049 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 11050 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 11051 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 11052 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 11053 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 11054 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 11055 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 11056 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 11057 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 11058 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 11059 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 11060 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 11061 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 11062 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 11063 #define MMEA0_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 11064 //MMEA0_DRAM_WR_PRI_URGENCY 11065 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 11066 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 11067 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 11068 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 11069 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 11070 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 11071 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 11072 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 11073 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 11074 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 11075 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 11076 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 11077 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 11078 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 11079 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 11080 #define MMEA0_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 11081 //MMEA0_DRAM_RD_PRI_QUANT_PRI1 11082 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 11083 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 11084 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 11085 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 11086 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 11087 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 11088 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 11089 #define MMEA0_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 11090 //MMEA0_DRAM_RD_PRI_QUANT_PRI2 11091 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 11092 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 11093 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 11094 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 11095 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 11096 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 11097 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 11098 #define MMEA0_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 11099 //MMEA0_DRAM_RD_PRI_QUANT_PRI3 11100 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 11101 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 11102 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 11103 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 11104 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 11105 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 11106 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 11107 #define MMEA0_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 11108 //MMEA0_DRAM_WR_PRI_QUANT_PRI1 11109 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 11110 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 11111 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 11112 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 11113 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 11114 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 11115 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 11116 #define MMEA0_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 11117 //MMEA0_DRAM_WR_PRI_QUANT_PRI2 11118 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 11119 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 11120 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 11121 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 11122 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 11123 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 11124 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 11125 #define MMEA0_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 11126 //MMEA0_DRAM_WR_PRI_QUANT_PRI3 11127 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 11128 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 11129 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 11130 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 11131 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 11132 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 11133 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 11134 #define MMEA0_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 11135 //MMEA0_GMI_RD_CLI2GRP_MAP0 11136 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 11137 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 11138 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 11139 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 11140 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 11141 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 11142 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 11143 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 11144 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 11145 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 11146 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 11147 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 11148 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 11149 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 11150 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 11151 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 11152 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 11153 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 11154 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 11155 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 11156 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 11157 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 11158 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 11159 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 11160 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 11161 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 11162 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 11163 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 11164 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 11165 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 11166 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 11167 #define MMEA0_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 11168 //MMEA0_GMI_RD_CLI2GRP_MAP1 11169 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 11170 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 11171 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 11172 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 11173 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 11174 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 11175 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 11176 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 11177 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 11178 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 11179 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 11180 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 11181 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 11182 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 11183 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 11184 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 11185 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 11186 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 11187 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 11188 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 11189 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 11190 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 11191 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 11192 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 11193 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 11194 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 11195 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 11196 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 11197 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 11198 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 11199 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 11200 #define MMEA0_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 11201 //MMEA0_GMI_WR_CLI2GRP_MAP0 11202 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 11203 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 11204 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 11205 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 11206 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 11207 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 11208 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 11209 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 11210 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 11211 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 11212 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 11213 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 11214 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 11215 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 11216 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 11217 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 11218 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 11219 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 11220 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 11221 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 11222 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 11223 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 11224 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 11225 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 11226 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 11227 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 11228 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 11229 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 11230 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 11231 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 11232 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 11233 #define MMEA0_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 11234 //MMEA0_GMI_WR_CLI2GRP_MAP1 11235 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 11236 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 11237 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 11238 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 11239 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 11240 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 11241 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 11242 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 11243 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 11244 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 11245 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 11246 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 11247 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 11248 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 11249 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 11250 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 11251 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 11252 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 11253 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 11254 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 11255 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 11256 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 11257 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 11258 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 11259 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 11260 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 11261 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 11262 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 11263 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 11264 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 11265 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 11266 #define MMEA0_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 11267 //MMEA0_GMI_RD_GRP2VC_MAP 11268 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 11269 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 11270 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 11271 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 11272 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 11273 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 11274 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 11275 #define MMEA0_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 11276 //MMEA0_GMI_WR_GRP2VC_MAP 11277 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 11278 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 11279 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 11280 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 11281 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 11282 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 11283 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 11284 #define MMEA0_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 11285 //MMEA0_GMI_RD_LAZY 11286 #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 11287 #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 11288 #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 11289 #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 11290 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 11291 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 11292 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 11293 #define MMEA0_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 11294 #define MMEA0_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 11295 #define MMEA0_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 11296 #define MMEA0_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 11297 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 11298 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 11299 #define MMEA0_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 11300 //MMEA0_GMI_WR_LAZY 11301 #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 11302 #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 11303 #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 11304 #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 11305 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 11306 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 11307 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 11308 #define MMEA0_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 11309 #define MMEA0_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 11310 #define MMEA0_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 11311 #define MMEA0_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 11312 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 11313 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 11314 #define MMEA0_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 11315 //MMEA0_GMI_RD_CAM_CNTL 11316 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 11317 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 11318 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 11319 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 11320 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 11321 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 11322 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 11323 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 11324 #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 11325 #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 11326 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 11327 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 11328 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 11329 #define MMEA0_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 11330 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 11331 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 11332 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 11333 #define MMEA0_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 11334 #define MMEA0_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 11335 #define MMEA0_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 11336 //MMEA0_GMI_WR_CAM_CNTL 11337 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 11338 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 11339 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 11340 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 11341 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 11342 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 11343 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 11344 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 11345 #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 11346 #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 11347 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 11348 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 11349 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 11350 #define MMEA0_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 11351 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 11352 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 11353 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 11354 #define MMEA0_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 11355 #define MMEA0_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 11356 #define MMEA0_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 11357 //MMEA0_GMI_PAGE_BURST 11358 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 11359 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 11360 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 11361 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 11362 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 11363 #define MMEA0_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 11364 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 11365 #define MMEA0_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 11366 //MMEA0_GMI_RD_PRI_AGE 11367 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 11368 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 11369 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 11370 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 11371 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 11372 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 11373 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 11374 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 11375 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 11376 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 11377 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 11378 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 11379 #define MMEA0_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 11380 #define MMEA0_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 11381 #define MMEA0_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 11382 #define MMEA0_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 11383 //MMEA0_GMI_WR_PRI_AGE 11384 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 11385 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 11386 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 11387 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 11388 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 11389 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 11390 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 11391 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 11392 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 11393 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 11394 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 11395 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 11396 #define MMEA0_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 11397 #define MMEA0_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 11398 #define MMEA0_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 11399 #define MMEA0_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 11400 //MMEA0_GMI_RD_PRI_QUEUING 11401 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 11402 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 11403 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 11404 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 11405 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 11406 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 11407 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 11408 #define MMEA0_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 11409 //MMEA0_GMI_WR_PRI_QUEUING 11410 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 11411 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 11412 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 11413 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 11414 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 11415 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 11416 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 11417 #define MMEA0_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 11418 //MMEA0_GMI_RD_PRI_FIXED 11419 #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 11420 #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 11421 #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 11422 #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 11423 #define MMEA0_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 11424 #define MMEA0_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 11425 #define MMEA0_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 11426 #define MMEA0_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 11427 //MMEA0_GMI_WR_PRI_FIXED 11428 #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 11429 #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 11430 #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 11431 #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 11432 #define MMEA0_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 11433 #define MMEA0_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 11434 #define MMEA0_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 11435 #define MMEA0_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 11436 //MMEA0_GMI_RD_PRI_URGENCY 11437 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 11438 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 11439 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 11440 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 11441 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 11442 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 11443 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 11444 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 11445 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 11446 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 11447 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 11448 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 11449 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 11450 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 11451 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 11452 #define MMEA0_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 11453 //MMEA0_GMI_WR_PRI_URGENCY 11454 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 11455 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 11456 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 11457 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 11458 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 11459 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 11460 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 11461 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 11462 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 11463 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 11464 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 11465 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 11466 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 11467 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 11468 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 11469 #define MMEA0_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 11470 //MMEA0_GMI_RD_PRI_URGENCY_MASKING 11471 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 11472 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 11473 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 11474 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 11475 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 11476 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 11477 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 11478 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 11479 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 11480 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 11481 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 11482 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 11483 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 11484 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 11485 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 11486 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 11487 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 11488 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 11489 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 11490 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 11491 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 11492 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 11493 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 11494 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 11495 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 11496 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 11497 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 11498 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 11499 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 11500 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 11501 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 11502 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 11503 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 11504 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 11505 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 11506 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 11507 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 11508 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 11509 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 11510 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 11511 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 11512 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 11513 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 11514 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 11515 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 11516 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 11517 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 11518 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 11519 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 11520 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 11521 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 11522 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 11523 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 11524 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 11525 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 11526 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 11527 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 11528 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 11529 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 11530 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 11531 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 11532 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 11533 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 11534 #define MMEA0_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 11535 //MMEA0_GMI_WR_PRI_URGENCY_MASKING 11536 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 11537 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 11538 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 11539 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 11540 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 11541 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 11542 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 11543 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 11544 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 11545 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 11546 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 11547 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 11548 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 11549 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 11550 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 11551 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 11552 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 11553 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 11554 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 11555 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 11556 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 11557 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 11558 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 11559 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 11560 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 11561 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 11562 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 11563 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 11564 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 11565 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 11566 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 11567 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 11568 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 11569 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 11570 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 11571 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 11572 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 11573 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 11574 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 11575 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 11576 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 11577 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 11578 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 11579 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 11580 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 11581 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 11582 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 11583 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 11584 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 11585 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 11586 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 11587 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 11588 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 11589 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 11590 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 11591 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 11592 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 11593 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 11594 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 11595 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 11596 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 11597 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 11598 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 11599 #define MMEA0_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 11600 //MMEA0_GMI_RD_PRI_QUANT_PRI1 11601 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 11602 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 11603 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 11604 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 11605 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 11606 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 11607 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 11608 #define MMEA0_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 11609 //MMEA0_GMI_RD_PRI_QUANT_PRI2 11610 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 11611 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 11612 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 11613 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 11614 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 11615 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 11616 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 11617 #define MMEA0_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 11618 //MMEA0_GMI_RD_PRI_QUANT_PRI3 11619 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 11620 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 11621 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 11622 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 11623 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 11624 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 11625 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 11626 #define MMEA0_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 11627 //MMEA0_GMI_WR_PRI_QUANT_PRI1 11628 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 11629 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 11630 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 11631 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 11632 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 11633 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 11634 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 11635 #define MMEA0_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 11636 //MMEA0_GMI_WR_PRI_QUANT_PRI2 11637 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 11638 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 11639 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 11640 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 11641 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 11642 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 11643 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 11644 #define MMEA0_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 11645 //MMEA0_GMI_WR_PRI_QUANT_PRI3 11646 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 11647 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 11648 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 11649 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 11650 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 11651 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 11652 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 11653 #define MMEA0_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 11654 //MMEA0_ADDRNORM_BASE_ADDR0 11655 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 11656 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 11657 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 11658 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 11659 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 11660 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 11661 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 11662 #define MMEA0_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 11663 #define MMEA0_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 11664 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 11665 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 11666 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 11667 #define MMEA0_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 11668 #define MMEA0_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 11669 //MMEA0_ADDRNORM_LIMIT_ADDR0 11670 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 11671 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 11672 #define MMEA0_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 11673 #define MMEA0_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 11674 //MMEA0_ADDRNORM_BASE_ADDR1 11675 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 11676 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 11677 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 11678 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 11679 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 11680 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 11681 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 11682 #define MMEA0_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 11683 #define MMEA0_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 11684 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 11685 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 11686 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 11687 #define MMEA0_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 11688 #define MMEA0_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 11689 //MMEA0_ADDRNORM_LIMIT_ADDR1 11690 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 11691 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 11692 #define MMEA0_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 11693 #define MMEA0_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 11694 //MMEA0_ADDRNORM_OFFSET_ADDR1 11695 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 11696 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc 11697 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 11698 #define MMEA0_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L 11699 //MMEA0_ADDRNORM_BASE_ADDR2 11700 #define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 11701 #define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 11702 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 11703 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 11704 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 11705 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 11706 #define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 11707 #define MMEA0_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 11708 #define MMEA0_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 11709 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL 11710 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L 11711 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 11712 #define MMEA0_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 11713 #define MMEA0_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 11714 //MMEA0_ADDRNORM_LIMIT_ADDR2 11715 #define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 11716 #define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 11717 #define MMEA0_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 11718 #define MMEA0_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 11719 //MMEA0_ADDRNORM_BASE_ADDR3 11720 #define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 11721 #define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 11722 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 11723 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 11724 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 11725 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 11726 #define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 11727 #define MMEA0_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 11728 #define MMEA0_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 11729 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL 11730 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L 11731 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 11732 #define MMEA0_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 11733 #define MMEA0_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 11734 //MMEA0_ADDRNORM_LIMIT_ADDR3 11735 #define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 11736 #define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 11737 #define MMEA0_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 11738 #define MMEA0_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 11739 //MMEA0_ADDRNORM_OFFSET_ADDR3 11740 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 11741 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc 11742 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 11743 #define MMEA0_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L 11744 //MMEA0_ADDRNORM_MEGABASE_ADDR0 11745 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 11746 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 11747 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 11748 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 11749 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 11750 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 11751 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc 11752 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 11753 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 11754 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 11755 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 11756 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 11757 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 11758 #define MMEA0_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 11759 //MMEA0_ADDRNORM_MEGALIMIT_ADDR0 11760 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 11761 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 11762 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 11763 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 11764 //MMEA0_ADDRNORM_MEGABASE_ADDR1 11765 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 11766 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 11767 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 11768 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 11769 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 11770 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 11771 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc 11772 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 11773 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 11774 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 11775 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 11776 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 11777 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 11778 #define MMEA0_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 11779 //MMEA0_ADDRNORM_MEGALIMIT_ADDR1 11780 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 11781 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 11782 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 11783 #define MMEA0_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 11784 //MMEA0_ADDRNORMDRAM_HOLE_CNTL 11785 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 11786 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 11787 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 11788 #define MMEA0_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 11789 //MMEA0_ADDRNORMGMI_HOLE_CNTL 11790 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 11791 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 11792 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 11793 #define MMEA0_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 11794 //MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG 11795 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 11796 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 11797 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 11798 #define MMEA0_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 11799 //MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG 11800 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 11801 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 11802 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 11803 #define MMEA0_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 11804 //MMEA0_ADDRDEC_BANK_CFG 11805 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 11806 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 11807 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 11808 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 11809 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 11810 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 11811 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 11812 #define MMEA0_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 11813 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 11814 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 11815 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 11816 #define MMEA0_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 11817 //MMEA0_ADDRDEC_MISC_CFG 11818 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 11819 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 11820 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 11821 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 11822 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 11823 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 11824 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 11825 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 11826 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 11827 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 11828 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 11829 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 11830 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 11831 #define MMEA0_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 11832 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 11833 #define MMEA0_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 11834 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 11835 #define MMEA0_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 11836 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 11837 #define MMEA0_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 11838 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 11839 #define MMEA0_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 11840 //MMEA0_ADDRDECDRAM_HARVEST_ENABLE 11841 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 11842 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 11843 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 11844 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 11845 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 11846 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 11847 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 11848 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 11849 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 11850 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 11851 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 11852 #define MMEA0_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 11853 //MMEA0_ADDRDECGMI_HARVEST_ENABLE 11854 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 11855 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 11856 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 11857 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 11858 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 11859 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 11860 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 11861 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 11862 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 11863 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 11864 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 11865 #define MMEA0_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 11866 //MMEA0_ADDRDEC0_BASE_ADDR_CS0 11867 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 11868 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 11869 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 11870 #define MMEA0_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 11871 //MMEA0_ADDRDEC0_BASE_ADDR_CS1 11872 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 11873 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 11874 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 11875 #define MMEA0_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 11876 //MMEA0_ADDRDEC0_BASE_ADDR_CS2 11877 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 11878 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 11879 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 11880 #define MMEA0_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 11881 //MMEA0_ADDRDEC0_BASE_ADDR_CS3 11882 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 11883 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 11884 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 11885 #define MMEA0_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 11886 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS0 11887 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 11888 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 11889 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 11890 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 11891 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS1 11892 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 11893 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 11894 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 11895 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 11896 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS2 11897 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 11898 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 11899 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 11900 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 11901 //MMEA0_ADDRDEC0_BASE_ADDR_SECCS3 11902 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 11903 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 11904 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 11905 #define MMEA0_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 11906 //MMEA0_ADDRDEC0_ADDR_MASK_CS01 11907 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 11908 #define MMEA0_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 11909 //MMEA0_ADDRDEC0_ADDR_MASK_CS23 11910 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 11911 #define MMEA0_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 11912 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS01 11913 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 11914 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 11915 //MMEA0_ADDRDEC0_ADDR_MASK_SECCS23 11916 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 11917 #define MMEA0_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 11918 //MMEA0_ADDRDEC0_ADDR_CFG_CS01 11919 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 11920 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 11921 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 11922 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 11923 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 11924 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 11925 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 11926 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 11927 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 11928 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 11929 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 11930 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 11931 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 11932 #define MMEA0_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 11933 //MMEA0_ADDRDEC0_ADDR_CFG_CS23 11934 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 11935 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 11936 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 11937 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 11938 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 11939 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 11940 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 11941 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 11942 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 11943 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 11944 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 11945 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 11946 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 11947 #define MMEA0_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 11948 //MMEA0_ADDRDEC0_ADDR_SEL_CS01 11949 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 11950 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 11951 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 11952 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 11953 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 11954 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 11955 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 11956 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 11957 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 11958 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 11959 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 11960 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 11961 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 11962 #define MMEA0_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 11963 //MMEA0_ADDRDEC0_ADDR_SEL_CS23 11964 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 11965 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 11966 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 11967 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 11968 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 11969 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 11970 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 11971 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 11972 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 11973 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 11974 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 11975 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 11976 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 11977 #define MMEA0_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 11978 //MMEA0_ADDRDEC0_ADDR_SEL2_CS01 11979 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 11980 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 11981 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 11982 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 11983 //MMEA0_ADDRDEC0_ADDR_SEL2_CS23 11984 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 11985 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 11986 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 11987 #define MMEA0_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 11988 //MMEA0_ADDRDEC0_COL_SEL_LO_CS01 11989 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 11990 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 11991 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 11992 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 11993 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 11994 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 11995 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 11996 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 11997 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 11998 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 11999 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 12000 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 12001 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 12002 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 12003 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 12004 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 12005 //MMEA0_ADDRDEC0_COL_SEL_LO_CS23 12006 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 12007 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 12008 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 12009 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 12010 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 12011 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 12012 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 12013 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 12014 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 12015 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 12016 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 12017 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 12018 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 12019 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 12020 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 12021 #define MMEA0_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 12022 //MMEA0_ADDRDEC0_COL_SEL_HI_CS01 12023 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 12024 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 12025 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 12026 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 12027 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 12028 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 12029 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 12030 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 12031 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 12032 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 12033 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 12034 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 12035 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 12036 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 12037 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 12038 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 12039 //MMEA0_ADDRDEC0_COL_SEL_HI_CS23 12040 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 12041 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 12042 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 12043 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 12044 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 12045 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 12046 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 12047 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 12048 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 12049 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 12050 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 12051 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 12052 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 12053 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 12054 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 12055 #define MMEA0_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 12056 //MMEA0_ADDRDEC0_RM_SEL_CS01 12057 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 12058 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 12059 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 12060 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 12061 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12062 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12063 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 12064 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 12065 #define MMEA0_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 12066 #define MMEA0_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 12067 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12068 #define MMEA0_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12069 //MMEA0_ADDRDEC0_RM_SEL_CS23 12070 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 12071 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 12072 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 12073 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 12074 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12075 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12076 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 12077 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 12078 #define MMEA0_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 12079 #define MMEA0_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 12080 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12081 #define MMEA0_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12082 //MMEA0_ADDRDEC0_RM_SEL_SECCS01 12083 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 12084 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 12085 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 12086 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 12087 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12088 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12089 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 12090 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 12091 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 12092 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 12093 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12094 #define MMEA0_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12095 //MMEA0_ADDRDEC0_RM_SEL_SECCS23 12096 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 12097 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 12098 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 12099 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 12100 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12101 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12102 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 12103 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 12104 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 12105 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 12106 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12107 #define MMEA0_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12108 //MMEA0_ADDRDEC1_BASE_ADDR_CS0 12109 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 12110 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 12111 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 12112 #define MMEA0_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 12113 //MMEA0_ADDRDEC1_BASE_ADDR_CS1 12114 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 12115 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 12116 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 12117 #define MMEA0_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 12118 //MMEA0_ADDRDEC1_BASE_ADDR_CS2 12119 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 12120 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 12121 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 12122 #define MMEA0_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 12123 //MMEA0_ADDRDEC1_BASE_ADDR_CS3 12124 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 12125 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 12126 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 12127 #define MMEA0_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 12128 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS0 12129 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 12130 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 12131 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 12132 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 12133 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS1 12134 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 12135 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 12136 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 12137 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 12138 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS2 12139 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 12140 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 12141 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 12142 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 12143 //MMEA0_ADDRDEC1_BASE_ADDR_SECCS3 12144 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 12145 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 12146 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 12147 #define MMEA0_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 12148 //MMEA0_ADDRDEC1_ADDR_MASK_CS01 12149 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 12150 #define MMEA0_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 12151 //MMEA0_ADDRDEC1_ADDR_MASK_CS23 12152 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 12153 #define MMEA0_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 12154 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS01 12155 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 12156 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 12157 //MMEA0_ADDRDEC1_ADDR_MASK_SECCS23 12158 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 12159 #define MMEA0_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 12160 //MMEA0_ADDRDEC1_ADDR_CFG_CS01 12161 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 12162 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 12163 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 12164 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 12165 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 12166 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 12167 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 12168 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 12169 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 12170 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 12171 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 12172 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 12173 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 12174 #define MMEA0_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 12175 //MMEA0_ADDRDEC1_ADDR_CFG_CS23 12176 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 12177 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 12178 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 12179 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 12180 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 12181 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 12182 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 12183 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 12184 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 12185 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 12186 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 12187 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 12188 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 12189 #define MMEA0_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 12190 //MMEA0_ADDRDEC1_ADDR_SEL_CS01 12191 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 12192 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 12193 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 12194 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 12195 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 12196 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 12197 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 12198 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 12199 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 12200 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 12201 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 12202 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 12203 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 12204 #define MMEA0_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 12205 //MMEA0_ADDRDEC1_ADDR_SEL_CS23 12206 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 12207 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 12208 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 12209 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 12210 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 12211 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 12212 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 12213 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 12214 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 12215 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 12216 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 12217 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 12218 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 12219 #define MMEA0_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 12220 //MMEA0_ADDRDEC1_ADDR_SEL2_CS01 12221 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 12222 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 12223 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 12224 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 12225 //MMEA0_ADDRDEC1_ADDR_SEL2_CS23 12226 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 12227 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 12228 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 12229 #define MMEA0_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 12230 //MMEA0_ADDRDEC1_COL_SEL_LO_CS01 12231 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 12232 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 12233 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 12234 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 12235 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 12236 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 12237 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 12238 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 12239 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 12240 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 12241 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 12242 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 12243 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 12244 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 12245 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 12246 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 12247 //MMEA0_ADDRDEC1_COL_SEL_LO_CS23 12248 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 12249 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 12250 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 12251 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 12252 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 12253 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 12254 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 12255 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 12256 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 12257 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 12258 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 12259 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 12260 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 12261 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 12262 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 12263 #define MMEA0_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 12264 //MMEA0_ADDRDEC1_COL_SEL_HI_CS01 12265 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 12266 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 12267 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 12268 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 12269 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 12270 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 12271 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 12272 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 12273 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 12274 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 12275 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 12276 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 12277 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 12278 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 12279 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 12280 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 12281 //MMEA0_ADDRDEC1_COL_SEL_HI_CS23 12282 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 12283 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 12284 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 12285 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 12286 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 12287 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 12288 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 12289 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 12290 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 12291 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 12292 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 12293 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 12294 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 12295 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 12296 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 12297 #define MMEA0_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 12298 //MMEA0_ADDRDEC1_RM_SEL_CS01 12299 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 12300 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 12301 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 12302 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 12303 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12304 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12305 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 12306 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 12307 #define MMEA0_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 12308 #define MMEA0_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 12309 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12310 #define MMEA0_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12311 //MMEA0_ADDRDEC1_RM_SEL_CS23 12312 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 12313 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 12314 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 12315 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 12316 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12317 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12318 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 12319 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 12320 #define MMEA0_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 12321 #define MMEA0_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 12322 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12323 #define MMEA0_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12324 //MMEA0_ADDRDEC1_RM_SEL_SECCS01 12325 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 12326 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 12327 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 12328 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 12329 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12330 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12331 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 12332 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 12333 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 12334 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 12335 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12336 #define MMEA0_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12337 //MMEA0_ADDRDEC1_RM_SEL_SECCS23 12338 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 12339 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 12340 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 12341 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 12342 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12343 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12344 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 12345 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 12346 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 12347 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 12348 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12349 #define MMEA0_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12350 //MMEA0_ADDRDEC2_BASE_ADDR_CS0 12351 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 12352 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 12353 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 12354 #define MMEA0_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 12355 //MMEA0_ADDRDEC2_BASE_ADDR_CS1 12356 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 12357 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 12358 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 12359 #define MMEA0_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 12360 //MMEA0_ADDRDEC2_BASE_ADDR_CS2 12361 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 12362 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 12363 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 12364 #define MMEA0_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 12365 //MMEA0_ADDRDEC2_BASE_ADDR_CS3 12366 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 12367 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 12368 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 12369 #define MMEA0_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 12370 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS0 12371 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 12372 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 12373 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 12374 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 12375 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS1 12376 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 12377 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 12378 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 12379 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 12380 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS2 12381 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 12382 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 12383 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 12384 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 12385 //MMEA0_ADDRDEC2_BASE_ADDR_SECCS3 12386 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 12387 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 12388 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 12389 #define MMEA0_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 12390 //MMEA0_ADDRDEC2_ADDR_MASK_CS01 12391 #define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 12392 #define MMEA0_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 12393 //MMEA0_ADDRDEC2_ADDR_MASK_CS23 12394 #define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 12395 #define MMEA0_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 12396 //MMEA0_ADDRDEC2_ADDR_MASK_SECCS01 12397 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 12398 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 12399 //MMEA0_ADDRDEC2_ADDR_MASK_SECCS23 12400 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 12401 #define MMEA0_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 12402 //MMEA0_ADDRDEC2_ADDR_CFG_CS01 12403 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 12404 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 12405 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 12406 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 12407 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 12408 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 12409 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 12410 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 12411 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 12412 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 12413 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 12414 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 12415 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 12416 #define MMEA0_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 12417 //MMEA0_ADDRDEC2_ADDR_CFG_CS23 12418 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 12419 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 12420 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 12421 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 12422 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 12423 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 12424 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 12425 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 12426 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 12427 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 12428 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 12429 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 12430 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 12431 #define MMEA0_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 12432 //MMEA0_ADDRDEC2_ADDR_SEL_CS01 12433 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 12434 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 12435 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 12436 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 12437 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 12438 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 12439 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 12440 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 12441 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 12442 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 12443 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 12444 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 12445 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 12446 #define MMEA0_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 12447 //MMEA0_ADDRDEC2_ADDR_SEL_CS23 12448 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 12449 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 12450 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 12451 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 12452 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 12453 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 12454 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 12455 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 12456 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 12457 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 12458 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 12459 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 12460 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 12461 #define MMEA0_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 12462 //MMEA0_ADDRDEC2_ADDR_SEL2_CS01 12463 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 12464 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 12465 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 12466 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 12467 //MMEA0_ADDRDEC2_ADDR_SEL2_CS23 12468 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 12469 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 12470 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 12471 #define MMEA0_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 12472 //MMEA0_ADDRDEC2_COL_SEL_LO_CS01 12473 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 12474 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 12475 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 12476 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 12477 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 12478 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 12479 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 12480 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 12481 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 12482 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 12483 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 12484 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 12485 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 12486 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 12487 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 12488 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 12489 //MMEA0_ADDRDEC2_COL_SEL_LO_CS23 12490 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 12491 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 12492 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 12493 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 12494 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 12495 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 12496 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 12497 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 12498 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 12499 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 12500 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 12501 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 12502 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 12503 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 12504 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 12505 #define MMEA0_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 12506 //MMEA0_ADDRDEC2_COL_SEL_HI_CS01 12507 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 12508 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 12509 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 12510 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 12511 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 12512 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 12513 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 12514 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 12515 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 12516 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 12517 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 12518 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 12519 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 12520 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 12521 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 12522 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 12523 //MMEA0_ADDRDEC2_COL_SEL_HI_CS23 12524 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 12525 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 12526 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 12527 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 12528 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 12529 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 12530 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 12531 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 12532 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 12533 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 12534 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 12535 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 12536 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 12537 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 12538 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 12539 #define MMEA0_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 12540 //MMEA0_ADDRDEC2_RM_SEL_CS01 12541 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 12542 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 12543 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 12544 #define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 12545 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12546 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12547 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 12548 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 12549 #define MMEA0_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 12550 #define MMEA0_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 12551 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12552 #define MMEA0_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12553 //MMEA0_ADDRDEC2_RM_SEL_CS23 12554 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 12555 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 12556 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 12557 #define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 12558 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12559 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12560 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 12561 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 12562 #define MMEA0_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 12563 #define MMEA0_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 12564 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12565 #define MMEA0_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12566 //MMEA0_ADDRDEC2_RM_SEL_SECCS01 12567 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 12568 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 12569 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 12570 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 12571 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12572 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12573 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 12574 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 12575 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 12576 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 12577 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12578 #define MMEA0_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12579 //MMEA0_ADDRDEC2_RM_SEL_SECCS23 12580 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 12581 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 12582 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 12583 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 12584 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 12585 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 12586 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 12587 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 12588 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 12589 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 12590 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 12591 #define MMEA0_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 12592 //MMEA0_ADDRNORMDRAM_GLOBAL_CNTL 12593 //MMEA0_ADDRNORMGMI_GLOBAL_CNTL 12594 //MMEA0_ADDRNORM_MEGACONTROL_ADDR0 12595 #define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 12596 #define MMEA0_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 12597 //MMEA0_ADDRNORM_MEGACONTROL_ADDR1 12598 #define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 12599 #define MMEA0_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 12600 //MMEA0_ADDRNORMDRAM_MASKING 12601 #define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 12602 #define MMEA0_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 12603 //MMEA0_ADDRNORMGMI_MASKING 12604 #define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 12605 #define MMEA0_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 12606 //MMEA0_IO_RD_CLI2GRP_MAP0 12607 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 12608 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 12609 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 12610 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 12611 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 12612 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 12613 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 12614 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 12615 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 12616 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 12617 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 12618 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 12619 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 12620 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 12621 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 12622 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 12623 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 12624 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 12625 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 12626 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 12627 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 12628 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 12629 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 12630 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 12631 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 12632 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 12633 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 12634 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 12635 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 12636 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 12637 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 12638 #define MMEA0_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 12639 //MMEA0_IO_RD_CLI2GRP_MAP1 12640 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 12641 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 12642 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 12643 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 12644 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 12645 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 12646 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 12647 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 12648 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 12649 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 12650 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 12651 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 12652 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 12653 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 12654 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 12655 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 12656 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 12657 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 12658 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 12659 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 12660 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 12661 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 12662 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 12663 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 12664 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 12665 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 12666 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 12667 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 12668 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 12669 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 12670 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 12671 #define MMEA0_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 12672 //MMEA0_IO_WR_CLI2GRP_MAP0 12673 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 12674 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 12675 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 12676 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 12677 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 12678 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 12679 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 12680 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 12681 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 12682 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 12683 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 12684 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 12685 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 12686 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 12687 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 12688 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 12689 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 12690 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 12691 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 12692 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 12693 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 12694 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 12695 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 12696 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 12697 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 12698 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 12699 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 12700 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 12701 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 12702 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 12703 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 12704 #define MMEA0_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 12705 //MMEA0_IO_WR_CLI2GRP_MAP1 12706 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 12707 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 12708 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 12709 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 12710 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 12711 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 12712 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 12713 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 12714 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 12715 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 12716 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 12717 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 12718 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 12719 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 12720 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 12721 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 12722 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 12723 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 12724 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 12725 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 12726 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 12727 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 12728 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 12729 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 12730 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 12731 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 12732 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 12733 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 12734 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 12735 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 12736 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 12737 #define MMEA0_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 12738 //MMEA0_IO_RD_COMBINE_FLUSH 12739 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 12740 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 12741 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 12742 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 12743 #define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 12744 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 12745 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 12746 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 12747 #define MMEA0_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 12748 #define MMEA0_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 12749 //MMEA0_IO_WR_COMBINE_FLUSH 12750 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 12751 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 12752 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 12753 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 12754 #define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 12755 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 12756 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 12757 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 12758 #define MMEA0_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 12759 #define MMEA0_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 12760 //MMEA0_IO_GROUP_BURST 12761 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 12762 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 12763 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 12764 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 12765 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 12766 #define MMEA0_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 12767 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 12768 #define MMEA0_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 12769 //MMEA0_IO_RD_PRI_AGE 12770 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 12771 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 12772 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 12773 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 12774 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 12775 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 12776 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 12777 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 12778 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 12779 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 12780 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 12781 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 12782 #define MMEA0_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 12783 #define MMEA0_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 12784 #define MMEA0_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 12785 #define MMEA0_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 12786 //MMEA0_IO_WR_PRI_AGE 12787 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 12788 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 12789 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 12790 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 12791 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 12792 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 12793 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 12794 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 12795 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 12796 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 12797 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 12798 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 12799 #define MMEA0_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 12800 #define MMEA0_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 12801 #define MMEA0_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 12802 #define MMEA0_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 12803 //MMEA0_IO_RD_PRI_QUEUING 12804 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 12805 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 12806 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 12807 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 12808 #define MMEA0_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 12809 #define MMEA0_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 12810 #define MMEA0_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 12811 #define MMEA0_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 12812 //MMEA0_IO_WR_PRI_QUEUING 12813 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 12814 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 12815 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 12816 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 12817 #define MMEA0_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 12818 #define MMEA0_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 12819 #define MMEA0_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 12820 #define MMEA0_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 12821 //MMEA0_IO_RD_PRI_FIXED 12822 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 12823 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 12824 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 12825 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 12826 #define MMEA0_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 12827 #define MMEA0_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 12828 #define MMEA0_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 12829 #define MMEA0_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 12830 //MMEA0_IO_WR_PRI_FIXED 12831 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 12832 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 12833 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 12834 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 12835 #define MMEA0_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 12836 #define MMEA0_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 12837 #define MMEA0_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 12838 #define MMEA0_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 12839 //MMEA0_IO_RD_PRI_URGENCY 12840 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 12841 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 12842 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 12843 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 12844 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 12845 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 12846 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 12847 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 12848 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 12849 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 12850 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 12851 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 12852 #define MMEA0_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 12853 #define MMEA0_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 12854 #define MMEA0_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 12855 #define MMEA0_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 12856 //MMEA0_IO_WR_PRI_URGENCY 12857 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 12858 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 12859 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 12860 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 12861 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 12862 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 12863 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 12864 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 12865 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 12866 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 12867 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 12868 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 12869 #define MMEA0_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 12870 #define MMEA0_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 12871 #define MMEA0_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 12872 #define MMEA0_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 12873 //MMEA0_IO_RD_PRI_URGENCY_MASKING 12874 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 12875 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 12876 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 12877 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 12878 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 12879 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 12880 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 12881 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 12882 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 12883 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 12884 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 12885 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 12886 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 12887 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 12888 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 12889 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 12890 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 12891 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 12892 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 12893 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 12894 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 12895 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 12896 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 12897 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 12898 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 12899 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 12900 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 12901 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 12902 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 12903 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 12904 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 12905 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 12906 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 12907 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 12908 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 12909 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 12910 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 12911 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 12912 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 12913 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 12914 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 12915 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 12916 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 12917 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 12918 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 12919 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 12920 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 12921 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 12922 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 12923 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 12924 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 12925 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 12926 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 12927 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 12928 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 12929 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 12930 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 12931 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 12932 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 12933 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 12934 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 12935 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 12936 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 12937 #define MMEA0_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 12938 //MMEA0_IO_WR_PRI_URGENCY_MASKING 12939 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 12940 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 12941 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 12942 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 12943 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 12944 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 12945 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 12946 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 12947 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 12948 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 12949 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 12950 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 12951 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 12952 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 12953 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 12954 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 12955 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 12956 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 12957 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 12958 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 12959 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 12960 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 12961 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 12962 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 12963 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 12964 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 12965 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 12966 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 12967 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 12968 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 12969 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 12970 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 12971 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 12972 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 12973 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 12974 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 12975 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 12976 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 12977 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 12978 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 12979 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 12980 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 12981 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 12982 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 12983 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 12984 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 12985 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 12986 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 12987 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 12988 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 12989 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 12990 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 12991 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 12992 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 12993 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 12994 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 12995 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 12996 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 12997 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 12998 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 12999 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 13000 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 13001 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 13002 #define MMEA0_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 13003 //MMEA0_IO_RD_PRI_QUANT_PRI1 13004 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 13005 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 13006 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 13007 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 13008 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 13009 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 13010 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 13011 #define MMEA0_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 13012 //MMEA0_IO_RD_PRI_QUANT_PRI2 13013 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 13014 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 13015 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 13016 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 13017 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 13018 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 13019 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 13020 #define MMEA0_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 13021 //MMEA0_IO_RD_PRI_QUANT_PRI3 13022 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 13023 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 13024 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 13025 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 13026 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 13027 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 13028 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 13029 #define MMEA0_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 13030 //MMEA0_IO_WR_PRI_QUANT_PRI1 13031 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 13032 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 13033 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 13034 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 13035 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 13036 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 13037 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 13038 #define MMEA0_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 13039 //MMEA0_IO_WR_PRI_QUANT_PRI2 13040 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 13041 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 13042 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 13043 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 13044 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 13045 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 13046 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 13047 #define MMEA0_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 13048 //MMEA0_IO_WR_PRI_QUANT_PRI3 13049 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 13050 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 13051 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 13052 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 13053 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 13054 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 13055 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 13056 #define MMEA0_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 13057 //MMEA0_SDP_ARB_DRAM 13058 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 13059 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 13060 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 13061 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 13062 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 13063 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 13064 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 13065 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 13066 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 13067 #define MMEA0_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 13068 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 13069 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 13070 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 13071 #define MMEA0_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 13072 #define MMEA0_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 13073 #define MMEA0_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 13074 //MMEA0_SDP_ARB_GMI 13075 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 13076 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 13077 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 13078 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 13079 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 13080 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 13081 #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 13082 #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 13083 #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 13084 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 13085 #define MMEA0_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 13086 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 13087 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 13088 #define MMEA0_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 13089 #define MMEA0_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 13090 #define MMEA0_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 13091 #define MMEA0_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 13092 #define MMEA0_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 13093 //MMEA0_SDP_ARB_FINAL 13094 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 13095 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 13096 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 13097 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 13098 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 13099 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 13100 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 13101 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 13102 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 13103 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 13104 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 13105 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 13106 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 13107 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 13108 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 13109 #define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c 13110 #define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d 13111 #define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e 13112 #define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f 13113 #define MMEA0_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 13114 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 13115 #define MMEA0_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 13116 #define MMEA0_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 13117 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 13118 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 13119 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 13120 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 13121 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 13122 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 13123 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 13124 #define MMEA0_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 13125 #define MMEA0_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 13126 #define MMEA0_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 13127 #define MMEA0_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 13128 #define MMEA0_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L 13129 #define MMEA0_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L 13130 #define MMEA0_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L 13131 #define MMEA0_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L 13132 //MMEA0_SDP_DRAM_PRIORITY 13133 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 13134 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 13135 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 13136 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 13137 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 13138 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 13139 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 13140 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 13141 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 13142 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 13143 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 13144 #define MMEA0_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 13145 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 13146 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 13147 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 13148 #define MMEA0_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 13149 //MMEA0_SDP_GMI_PRIORITY 13150 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 13151 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 13152 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 13153 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 13154 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 13155 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 13156 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 13157 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 13158 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 13159 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 13160 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 13161 #define MMEA0_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 13162 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 13163 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 13164 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 13165 #define MMEA0_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 13166 //MMEA0_SDP_IO_PRIORITY 13167 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 13168 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 13169 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 13170 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 13171 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 13172 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 13173 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 13174 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 13175 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 13176 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 13177 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 13178 #define MMEA0_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 13179 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 13180 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 13181 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 13182 #define MMEA0_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 13183 //MMEA0_SDP_CREDITS 13184 #define MMEA0_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 13185 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 13186 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 13187 #define MMEA0_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 13188 #define MMEA0_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 13189 #define MMEA0_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 13190 //MMEA0_SDP_TAG_RESERVE0 13191 #define MMEA0_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 13192 #define MMEA0_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 13193 #define MMEA0_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 13194 #define MMEA0_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 13195 #define MMEA0_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 13196 #define MMEA0_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 13197 #define MMEA0_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 13198 #define MMEA0_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 13199 //MMEA0_SDP_TAG_RESERVE1 13200 #define MMEA0_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 13201 #define MMEA0_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 13202 #define MMEA0_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 13203 #define MMEA0_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 13204 #define MMEA0_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 13205 #define MMEA0_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 13206 #define MMEA0_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 13207 #define MMEA0_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 13208 //MMEA0_SDP_VCC_RESERVE0 13209 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 13210 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 13211 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 13212 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 13213 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 13214 #define MMEA0_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 13215 #define MMEA0_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 13216 #define MMEA0_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 13217 #define MMEA0_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 13218 #define MMEA0_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 13219 //MMEA0_SDP_VCC_RESERVE1 13220 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 13221 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 13222 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 13223 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 13224 #define MMEA0_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 13225 #define MMEA0_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 13226 #define MMEA0_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 13227 #define MMEA0_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 13228 //MMEA0_SDP_VCD_RESERVE0 13229 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 13230 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 13231 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 13232 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 13233 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 13234 #define MMEA0_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 13235 #define MMEA0_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 13236 #define MMEA0_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 13237 #define MMEA0_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 13238 #define MMEA0_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 13239 //MMEA0_SDP_VCD_RESERVE1 13240 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 13241 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 13242 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 13243 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 13244 #define MMEA0_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 13245 #define MMEA0_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 13246 #define MMEA0_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 13247 #define MMEA0_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 13248 //MMEA0_SDP_REQ_CNTL 13249 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 13250 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 13251 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 13252 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 13253 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 13254 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 13255 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 13256 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 13257 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 13258 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 13259 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 13260 #define MMEA0_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 13261 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 13262 #define MMEA0_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 13263 #define MMEA0_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 13264 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 13265 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 13266 #define MMEA0_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 13267 //MMEA0_MISC 13268 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 13269 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 13270 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 13271 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 13272 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 13273 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 13274 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 13275 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 13276 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 13277 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 13278 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 13279 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 13280 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 13281 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 13282 #define MMEA0_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 13283 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 13284 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 13285 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 13286 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 13287 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 13288 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 13289 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 13290 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 13291 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 13292 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 13293 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 13294 #define MMEA0_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 13295 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 13296 #define MMEA0_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 13297 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 13298 #define MMEA0_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 13299 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 13300 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 13301 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 13302 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 13303 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 13304 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 13305 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 13306 #define MMEA0_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 13307 #define MMEA0_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 13308 #define MMEA0_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 13309 #define MMEA0_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 13310 #define MMEA0_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 13311 #define MMEA0_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 13312 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 13313 #define MMEA0_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 13314 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 13315 #define MMEA0_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 13316 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 13317 #define MMEA0_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 13318 //MMEA0_LATENCY_SAMPLING 13319 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 13320 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 13321 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 13322 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 13323 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 13324 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 13325 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 13326 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 13327 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 13328 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 13329 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 13330 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 13331 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 13332 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 13333 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 13334 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 13335 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 13336 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 13337 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 13338 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 13339 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 13340 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 13341 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 13342 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 13343 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 13344 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 13345 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 13346 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 13347 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 13348 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 13349 #define MMEA0_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 13350 #define MMEA0_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 13351 //MMEA0_PERFCOUNTER_LO 13352 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 13353 #define MMEA0_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 13354 //MMEA0_PERFCOUNTER_HI 13355 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 13356 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 13357 #define MMEA0_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 13358 #define MMEA0_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 13359 //MMEA0_PERFCOUNTER0_CFG 13360 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 13361 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 13362 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 13363 #define MMEA0_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 13364 #define MMEA0_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 13365 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 13366 #define MMEA0_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 13367 #define MMEA0_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 13368 #define MMEA0_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 13369 #define MMEA0_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 13370 //MMEA0_PERFCOUNTER1_CFG 13371 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 13372 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 13373 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 13374 #define MMEA0_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 13375 #define MMEA0_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 13376 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 13377 #define MMEA0_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 13378 #define MMEA0_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 13379 #define MMEA0_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 13380 #define MMEA0_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 13381 //MMEA0_PERFCOUNTER_RSLT_CNTL 13382 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 13383 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 13384 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 13385 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 13386 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 13387 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 13388 #define MMEA0_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 13389 #define MMEA0_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 13390 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 13391 #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 13392 #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 13393 #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 13394 //MMEA0_EDC_CNT 13395 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 13396 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 13397 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 13398 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 13399 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 13400 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 13401 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 13402 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 13403 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 13404 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 13405 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 13406 #define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 13407 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 13408 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a 13409 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c 13410 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e 13411 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 13412 #define MMEA0_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 13413 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 13414 #define MMEA0_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 13415 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 13416 #define MMEA0_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 13417 #define MMEA0_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 13418 #define MMEA0_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 13419 #define MMEA0_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 13420 #define MMEA0_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 13421 #define MMEA0_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L 13422 #define MMEA0_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L 13423 #define MMEA0_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L 13424 #define MMEA0_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L 13425 #define MMEA0_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L 13426 #define MMEA0_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L 13427 //MMEA0_EDC_CNT2 13428 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 13429 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 13430 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 13431 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 13432 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 13433 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 13434 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 13435 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 13436 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 13437 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 13438 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 13439 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 13440 #define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 13441 #define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 13442 #define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 13443 #define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 13444 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 13445 #define MMEA0_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 13446 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 13447 #define MMEA0_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 13448 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 13449 #define MMEA0_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 13450 #define MMEA0_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 13451 #define MMEA0_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 13452 #define MMEA0_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 13453 #define MMEA0_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 13454 #define MMEA0_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 13455 #define MMEA0_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 13456 #define MMEA0_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 13457 #define MMEA0_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 13458 #define MMEA0_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 13459 #define MMEA0_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 13460 //MMEA0_DSM_CNTL 13461 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 13462 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 13463 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 13464 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 13465 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 13466 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 13467 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 13468 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 13469 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 13470 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 13471 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 13472 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 13473 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 13474 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 13475 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 13476 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 13477 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 13478 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 13479 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 13480 #define MMEA0_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 13481 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 13482 #define MMEA0_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 13483 #define MMEA0_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 13484 #define MMEA0_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 13485 #define MMEA0_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 13486 #define MMEA0_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 13487 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 13488 #define MMEA0_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 13489 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 13490 #define MMEA0_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 13491 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 13492 #define MMEA0_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 13493 //MMEA0_DSM_CNTLA 13494 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 13495 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 13496 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 13497 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 13498 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 13499 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 13500 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 13501 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 13502 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 13503 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 13504 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 13505 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 13506 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 13507 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 13508 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 13509 #define MMEA0_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 13510 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 13511 #define MMEA0_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 13512 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 13513 #define MMEA0_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 13514 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 13515 #define MMEA0_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 13516 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 13517 #define MMEA0_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 13518 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 13519 #define MMEA0_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 13520 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 13521 #define MMEA0_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 13522 //MMEA0_DSM_CNTLB 13523 //MMEA0_DSM_CNTL2 13524 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 13525 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 13526 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 13527 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 13528 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 13529 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 13530 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 13531 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 13532 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 13533 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 13534 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 13535 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 13536 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 13537 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 13538 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 13539 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 13540 #define MMEA0_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 13541 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 13542 #define MMEA0_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 13543 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 13544 #define MMEA0_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 13545 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 13546 #define MMEA0_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 13547 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 13548 #define MMEA0_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 13549 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 13550 #define MMEA0_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 13551 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 13552 #define MMEA0_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 13553 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 13554 #define MMEA0_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 13555 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 13556 #define MMEA0_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 13557 #define MMEA0_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 13558 //MMEA0_DSM_CNTL2A 13559 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 13560 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 13561 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 13562 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 13563 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 13564 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 13565 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 13566 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 13567 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 13568 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 13569 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 13570 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 13571 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 13572 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 13573 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 13574 #define MMEA0_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 13575 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 13576 #define MMEA0_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 13577 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 13578 #define MMEA0_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 13579 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 13580 #define MMEA0_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 13581 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 13582 #define MMEA0_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 13583 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 13584 #define MMEA0_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 13585 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 13586 #define MMEA0_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 13587 //MMEA0_DSM_CNTL2B 13588 //MMEA0_CGTT_CLK_CTRL 13589 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 13590 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 13591 #define MMEA0_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 13592 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 13593 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 13594 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 13595 #define MMEA0_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 13596 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 13597 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 13598 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 13599 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 13600 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 13601 #define MMEA0_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 13602 #define MMEA0_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 13603 #define MMEA0_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 13604 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 13605 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 13606 #define MMEA0_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 13607 #define MMEA0_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 13608 #define MMEA0_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 13609 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 13610 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 13611 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 13612 #define MMEA0_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 13613 //MMEA0_EDC_MODE 13614 #define MMEA0_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 13615 #define MMEA0_EDC_MODE__GATE_FUE__SHIFT 0x11 13616 #define MMEA0_EDC_MODE__DED_MODE__SHIFT 0x14 13617 #define MMEA0_EDC_MODE__PROP_FED__SHIFT 0x1d 13618 #define MMEA0_EDC_MODE__BYPASS__SHIFT 0x1f 13619 #define MMEA0_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 13620 #define MMEA0_EDC_MODE__GATE_FUE_MASK 0x00020000L 13621 #define MMEA0_EDC_MODE__DED_MODE_MASK 0x00300000L 13622 #define MMEA0_EDC_MODE__PROP_FED_MASK 0x20000000L 13623 #define MMEA0_EDC_MODE__BYPASS_MASK 0x80000000L 13624 //MMEA0_ERR_STATUS 13625 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 13626 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 13627 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 13628 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 13629 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 13630 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 13631 #define MMEA0_ERR_STATUS__FUE_FLAG__SHIFT 0xd 13632 #define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 13633 #define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 13634 #define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 13635 #define MMEA0_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 13636 #define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 13637 #define MMEA0_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 13638 #define MMEA0_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 13639 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 13640 #define MMEA0_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 13641 #define MMEA0_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 13642 #define MMEA0_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 13643 #define MMEA0_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 13644 #define MMEA0_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 13645 #define MMEA0_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 13646 #define MMEA0_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 13647 #define MMEA0_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 13648 #define MMEA0_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 13649 //MMEA0_MISC2 13650 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 13651 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 13652 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 13653 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 13654 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 13655 #define MMEA0_MISC2__RRET_SWAP_MODE__SHIFT 0xd 13656 #define MMEA0_MISC2__BLOCK_REQUESTS__SHIFT 0xe 13657 #define MMEA0_MISC2__REQUESTS_BLOCKED__SHIFT 0xf 13658 #define MMEA0_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 13659 #define MMEA0_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 13660 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 13661 #define MMEA0_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 13662 #define MMEA0_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 13663 #define MMEA0_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 13664 #define MMEA0_MISC2__BLOCK_REQUESTS_MASK 0x00004000L 13665 #define MMEA0_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L 13666 //MMEA0_ADDRDEC_SELECT 13667 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 13668 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 13669 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 13670 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 13671 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 13672 #define MMEA0_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 13673 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 13674 #define MMEA0_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 13675 //MMEA0_EDC_CNT3 13676 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 13677 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 13678 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 13679 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 13680 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 13681 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa 13682 #define MMEA0_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 13683 #define MMEA0_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 13684 #define MMEA0_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 13685 #define MMEA0_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 13686 #define MMEA0_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L 13687 #define MMEA0_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L 13688 //MMEA0_MISC_AON 13689 #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 13690 #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 13691 #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 13692 #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 13693 13694 13695 // addressBlock: mmhub_ea_mmeadec1 13696 //MMEA1_DRAM_RD_CLI2GRP_MAP0 13697 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 13698 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 13699 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 13700 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 13701 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 13702 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 13703 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 13704 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 13705 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 13706 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 13707 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 13708 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 13709 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 13710 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 13711 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 13712 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 13713 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 13714 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 13715 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 13716 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 13717 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 13718 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 13719 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 13720 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 13721 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 13722 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 13723 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 13724 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 13725 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 13726 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 13727 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 13728 #define MMEA1_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 13729 //MMEA1_DRAM_RD_CLI2GRP_MAP1 13730 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 13731 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 13732 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 13733 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 13734 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 13735 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 13736 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 13737 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 13738 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 13739 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 13740 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 13741 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 13742 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 13743 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 13744 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 13745 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 13746 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 13747 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 13748 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 13749 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 13750 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 13751 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 13752 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 13753 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 13754 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 13755 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 13756 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 13757 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 13758 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 13759 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 13760 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 13761 #define MMEA1_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 13762 //MMEA1_DRAM_WR_CLI2GRP_MAP0 13763 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 13764 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 13765 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 13766 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 13767 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 13768 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 13769 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 13770 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 13771 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 13772 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 13773 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 13774 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 13775 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 13776 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 13777 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 13778 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 13779 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 13780 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 13781 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 13782 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 13783 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 13784 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 13785 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 13786 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 13787 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 13788 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 13789 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 13790 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 13791 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 13792 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 13793 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 13794 #define MMEA1_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 13795 //MMEA1_DRAM_WR_CLI2GRP_MAP1 13796 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 13797 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 13798 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 13799 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 13800 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 13801 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 13802 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 13803 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 13804 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 13805 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 13806 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 13807 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 13808 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 13809 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 13810 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 13811 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 13812 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 13813 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 13814 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 13815 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 13816 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 13817 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 13818 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 13819 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 13820 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 13821 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 13822 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 13823 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 13824 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 13825 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 13826 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 13827 #define MMEA1_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 13828 //MMEA1_DRAM_RD_GRP2VC_MAP 13829 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 13830 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 13831 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 13832 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 13833 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 13834 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 13835 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 13836 #define MMEA1_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 13837 //MMEA1_DRAM_WR_GRP2VC_MAP 13838 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 13839 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 13840 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 13841 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 13842 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 13843 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 13844 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 13845 #define MMEA1_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 13846 //MMEA1_DRAM_RD_LAZY 13847 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 13848 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 13849 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 13850 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 13851 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 13852 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 13853 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 13854 #define MMEA1_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 13855 #define MMEA1_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 13856 #define MMEA1_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 13857 #define MMEA1_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 13858 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 13859 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 13860 #define MMEA1_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 13861 //MMEA1_DRAM_WR_LAZY 13862 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 13863 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 13864 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 13865 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 13866 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 13867 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 13868 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 13869 #define MMEA1_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 13870 #define MMEA1_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 13871 #define MMEA1_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 13872 #define MMEA1_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 13873 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 13874 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 13875 #define MMEA1_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 13876 //MMEA1_DRAM_RD_CAM_CNTL 13877 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 13878 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 13879 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 13880 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 13881 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 13882 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 13883 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 13884 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 13885 #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 13886 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 13887 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 13888 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 13889 #define MMEA1_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 13890 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 13891 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 13892 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 13893 #define MMEA1_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 13894 #define MMEA1_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 13895 //MMEA1_DRAM_WR_CAM_CNTL 13896 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 13897 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 13898 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 13899 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 13900 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 13901 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 13902 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 13903 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 13904 #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 13905 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 13906 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 13907 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 13908 #define MMEA1_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 13909 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 13910 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 13911 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 13912 #define MMEA1_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 13913 #define MMEA1_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 13914 //MMEA1_DRAM_PAGE_BURST 13915 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 13916 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 13917 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 13918 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 13919 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 13920 #define MMEA1_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 13921 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 13922 #define MMEA1_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 13923 //MMEA1_DRAM_RD_PRI_AGE 13924 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 13925 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 13926 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 13927 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 13928 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 13929 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 13930 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 13931 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 13932 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 13933 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 13934 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 13935 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 13936 #define MMEA1_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 13937 #define MMEA1_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 13938 #define MMEA1_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 13939 #define MMEA1_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 13940 //MMEA1_DRAM_WR_PRI_AGE 13941 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 13942 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 13943 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 13944 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 13945 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 13946 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 13947 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 13948 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 13949 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 13950 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 13951 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 13952 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 13953 #define MMEA1_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 13954 #define MMEA1_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 13955 #define MMEA1_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 13956 #define MMEA1_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 13957 //MMEA1_DRAM_RD_PRI_QUEUING 13958 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 13959 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 13960 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 13961 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 13962 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 13963 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 13964 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 13965 #define MMEA1_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 13966 //MMEA1_DRAM_WR_PRI_QUEUING 13967 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 13968 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 13969 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 13970 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 13971 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 13972 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 13973 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 13974 #define MMEA1_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 13975 //MMEA1_DRAM_RD_PRI_FIXED 13976 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 13977 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 13978 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 13979 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 13980 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 13981 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 13982 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 13983 #define MMEA1_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 13984 //MMEA1_DRAM_WR_PRI_FIXED 13985 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 13986 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 13987 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 13988 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 13989 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 13990 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 13991 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 13992 #define MMEA1_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 13993 //MMEA1_DRAM_RD_PRI_URGENCY 13994 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 13995 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 13996 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 13997 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 13998 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 13999 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 14000 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 14001 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 14002 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 14003 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 14004 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 14005 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 14006 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 14007 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 14008 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 14009 #define MMEA1_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 14010 //MMEA1_DRAM_WR_PRI_URGENCY 14011 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 14012 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 14013 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 14014 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 14015 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 14016 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 14017 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 14018 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 14019 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 14020 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 14021 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 14022 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 14023 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 14024 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 14025 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 14026 #define MMEA1_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 14027 //MMEA1_DRAM_RD_PRI_QUANT_PRI1 14028 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 14029 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 14030 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 14031 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 14032 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 14033 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 14034 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 14035 #define MMEA1_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 14036 //MMEA1_DRAM_RD_PRI_QUANT_PRI2 14037 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 14038 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 14039 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 14040 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 14041 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 14042 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 14043 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 14044 #define MMEA1_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 14045 //MMEA1_DRAM_RD_PRI_QUANT_PRI3 14046 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 14047 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 14048 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 14049 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 14050 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 14051 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 14052 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 14053 #define MMEA1_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 14054 //MMEA1_DRAM_WR_PRI_QUANT_PRI1 14055 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 14056 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 14057 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 14058 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 14059 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 14060 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 14061 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 14062 #define MMEA1_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 14063 //MMEA1_DRAM_WR_PRI_QUANT_PRI2 14064 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 14065 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 14066 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 14067 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 14068 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 14069 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 14070 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 14071 #define MMEA1_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 14072 //MMEA1_DRAM_WR_PRI_QUANT_PRI3 14073 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 14074 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 14075 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 14076 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 14077 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 14078 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 14079 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 14080 #define MMEA1_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 14081 //MMEA1_GMI_RD_CLI2GRP_MAP0 14082 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 14083 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 14084 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 14085 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 14086 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 14087 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 14088 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 14089 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 14090 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 14091 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 14092 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 14093 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 14094 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 14095 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 14096 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 14097 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 14098 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 14099 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 14100 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 14101 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 14102 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 14103 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 14104 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 14105 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 14106 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 14107 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 14108 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 14109 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 14110 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 14111 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 14112 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 14113 #define MMEA1_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 14114 //MMEA1_GMI_RD_CLI2GRP_MAP1 14115 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 14116 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 14117 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 14118 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 14119 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 14120 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 14121 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 14122 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 14123 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 14124 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 14125 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 14126 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 14127 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 14128 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 14129 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 14130 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 14131 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 14132 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 14133 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 14134 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 14135 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 14136 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 14137 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 14138 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 14139 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 14140 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 14141 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 14142 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 14143 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 14144 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 14145 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 14146 #define MMEA1_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 14147 //MMEA1_GMI_WR_CLI2GRP_MAP0 14148 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 14149 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 14150 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 14151 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 14152 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 14153 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 14154 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 14155 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 14156 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 14157 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 14158 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 14159 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 14160 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 14161 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 14162 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 14163 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 14164 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 14165 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 14166 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 14167 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 14168 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 14169 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 14170 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 14171 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 14172 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 14173 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 14174 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 14175 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 14176 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 14177 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 14178 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 14179 #define MMEA1_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 14180 //MMEA1_GMI_WR_CLI2GRP_MAP1 14181 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 14182 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 14183 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 14184 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 14185 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 14186 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 14187 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 14188 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 14189 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 14190 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 14191 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 14192 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 14193 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 14194 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 14195 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 14196 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 14197 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 14198 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 14199 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 14200 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 14201 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 14202 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 14203 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 14204 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 14205 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 14206 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 14207 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 14208 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 14209 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 14210 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 14211 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 14212 #define MMEA1_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 14213 //MMEA1_GMI_RD_GRP2VC_MAP 14214 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 14215 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 14216 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 14217 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 14218 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 14219 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 14220 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 14221 #define MMEA1_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 14222 //MMEA1_GMI_WR_GRP2VC_MAP 14223 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 14224 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 14225 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 14226 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 14227 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 14228 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 14229 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 14230 #define MMEA1_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 14231 //MMEA1_GMI_RD_LAZY 14232 #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 14233 #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 14234 #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 14235 #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 14236 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 14237 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 14238 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 14239 #define MMEA1_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 14240 #define MMEA1_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 14241 #define MMEA1_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 14242 #define MMEA1_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 14243 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 14244 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 14245 #define MMEA1_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 14246 //MMEA1_GMI_WR_LAZY 14247 #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 14248 #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 14249 #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 14250 #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 14251 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 14252 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 14253 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 14254 #define MMEA1_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 14255 #define MMEA1_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 14256 #define MMEA1_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 14257 #define MMEA1_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 14258 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 14259 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 14260 #define MMEA1_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 14261 //MMEA1_GMI_RD_CAM_CNTL 14262 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 14263 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 14264 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 14265 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 14266 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 14267 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 14268 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 14269 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 14270 #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 14271 #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 14272 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 14273 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 14274 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 14275 #define MMEA1_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 14276 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 14277 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 14278 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 14279 #define MMEA1_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 14280 #define MMEA1_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 14281 #define MMEA1_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 14282 //MMEA1_GMI_WR_CAM_CNTL 14283 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 14284 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 14285 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 14286 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 14287 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 14288 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 14289 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 14290 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 14291 #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 14292 #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 14293 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 14294 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 14295 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 14296 #define MMEA1_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 14297 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 14298 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 14299 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 14300 #define MMEA1_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 14301 #define MMEA1_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 14302 #define MMEA1_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 14303 //MMEA1_GMI_PAGE_BURST 14304 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 14305 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 14306 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 14307 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 14308 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 14309 #define MMEA1_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 14310 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 14311 #define MMEA1_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 14312 //MMEA1_GMI_RD_PRI_AGE 14313 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 14314 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 14315 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 14316 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 14317 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 14318 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 14319 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 14320 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 14321 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 14322 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 14323 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 14324 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 14325 #define MMEA1_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 14326 #define MMEA1_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 14327 #define MMEA1_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 14328 #define MMEA1_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 14329 //MMEA1_GMI_WR_PRI_AGE 14330 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 14331 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 14332 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 14333 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 14334 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 14335 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 14336 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 14337 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 14338 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 14339 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 14340 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 14341 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 14342 #define MMEA1_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 14343 #define MMEA1_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 14344 #define MMEA1_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 14345 #define MMEA1_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 14346 //MMEA1_GMI_RD_PRI_QUEUING 14347 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 14348 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 14349 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 14350 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 14351 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 14352 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 14353 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 14354 #define MMEA1_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 14355 //MMEA1_GMI_WR_PRI_QUEUING 14356 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 14357 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 14358 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 14359 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 14360 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 14361 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 14362 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 14363 #define MMEA1_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 14364 //MMEA1_GMI_RD_PRI_FIXED 14365 #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 14366 #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 14367 #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 14368 #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 14369 #define MMEA1_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 14370 #define MMEA1_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 14371 #define MMEA1_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 14372 #define MMEA1_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 14373 //MMEA1_GMI_WR_PRI_FIXED 14374 #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 14375 #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 14376 #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 14377 #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 14378 #define MMEA1_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 14379 #define MMEA1_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 14380 #define MMEA1_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 14381 #define MMEA1_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 14382 //MMEA1_GMI_RD_PRI_URGENCY 14383 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 14384 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 14385 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 14386 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 14387 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 14388 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 14389 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 14390 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 14391 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 14392 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 14393 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 14394 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 14395 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 14396 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 14397 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 14398 #define MMEA1_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 14399 //MMEA1_GMI_WR_PRI_URGENCY 14400 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 14401 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 14402 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 14403 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 14404 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 14405 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 14406 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 14407 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 14408 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 14409 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 14410 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 14411 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 14412 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 14413 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 14414 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 14415 #define MMEA1_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 14416 //MMEA1_GMI_RD_PRI_URGENCY_MASKING 14417 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 14418 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 14419 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 14420 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 14421 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 14422 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 14423 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 14424 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 14425 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 14426 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 14427 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 14428 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 14429 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 14430 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 14431 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 14432 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 14433 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 14434 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 14435 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 14436 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 14437 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 14438 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 14439 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 14440 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 14441 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 14442 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 14443 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 14444 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 14445 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 14446 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 14447 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 14448 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 14449 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 14450 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 14451 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 14452 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 14453 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 14454 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 14455 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 14456 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 14457 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 14458 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 14459 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 14460 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 14461 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 14462 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 14463 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 14464 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 14465 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 14466 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 14467 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 14468 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 14469 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 14470 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 14471 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 14472 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 14473 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 14474 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 14475 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 14476 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 14477 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 14478 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 14479 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 14480 #define MMEA1_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 14481 //MMEA1_GMI_WR_PRI_URGENCY_MASKING 14482 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 14483 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 14484 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 14485 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 14486 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 14487 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 14488 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 14489 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 14490 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 14491 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 14492 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 14493 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 14494 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 14495 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 14496 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 14497 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 14498 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 14499 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 14500 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 14501 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 14502 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 14503 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 14504 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 14505 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 14506 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 14507 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 14508 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 14509 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 14510 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 14511 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 14512 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 14513 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 14514 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 14515 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 14516 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 14517 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 14518 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 14519 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 14520 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 14521 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 14522 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 14523 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 14524 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 14525 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 14526 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 14527 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 14528 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 14529 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 14530 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 14531 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 14532 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 14533 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 14534 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 14535 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 14536 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 14537 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 14538 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 14539 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 14540 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 14541 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 14542 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 14543 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 14544 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 14545 #define MMEA1_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 14546 //MMEA1_GMI_RD_PRI_QUANT_PRI1 14547 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 14548 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 14549 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 14550 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 14551 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 14552 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 14553 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 14554 #define MMEA1_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 14555 //MMEA1_GMI_RD_PRI_QUANT_PRI2 14556 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 14557 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 14558 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 14559 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 14560 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 14561 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 14562 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 14563 #define MMEA1_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 14564 //MMEA1_GMI_RD_PRI_QUANT_PRI3 14565 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 14566 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 14567 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 14568 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 14569 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 14570 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 14571 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 14572 #define MMEA1_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 14573 //MMEA1_GMI_WR_PRI_QUANT_PRI1 14574 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 14575 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 14576 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 14577 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 14578 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 14579 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 14580 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 14581 #define MMEA1_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 14582 //MMEA1_GMI_WR_PRI_QUANT_PRI2 14583 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 14584 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 14585 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 14586 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 14587 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 14588 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 14589 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 14590 #define MMEA1_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 14591 //MMEA1_GMI_WR_PRI_QUANT_PRI3 14592 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 14593 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 14594 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 14595 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 14596 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 14597 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 14598 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 14599 #define MMEA1_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 14600 //MMEA1_ADDRNORM_BASE_ADDR0 14601 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 14602 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 14603 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 14604 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 14605 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 14606 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 14607 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 14608 #define MMEA1_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 14609 #define MMEA1_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 14610 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 14611 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 14612 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 14613 #define MMEA1_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 14614 #define MMEA1_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 14615 //MMEA1_ADDRNORM_LIMIT_ADDR0 14616 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 14617 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 14618 #define MMEA1_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 14619 #define MMEA1_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 14620 //MMEA1_ADDRNORM_BASE_ADDR1 14621 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 14622 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 14623 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 14624 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 14625 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 14626 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 14627 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 14628 #define MMEA1_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 14629 #define MMEA1_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 14630 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 14631 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 14632 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 14633 #define MMEA1_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 14634 #define MMEA1_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 14635 //MMEA1_ADDRNORM_LIMIT_ADDR1 14636 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 14637 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 14638 #define MMEA1_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 14639 #define MMEA1_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 14640 //MMEA1_ADDRNORM_OFFSET_ADDR1 14641 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 14642 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc 14643 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 14644 #define MMEA1_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L 14645 //MMEA1_ADDRNORM_BASE_ADDR2 14646 #define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 14647 #define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 14648 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 14649 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 14650 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 14651 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 14652 #define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 14653 #define MMEA1_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 14654 #define MMEA1_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 14655 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL 14656 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L 14657 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 14658 #define MMEA1_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 14659 #define MMEA1_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 14660 //MMEA1_ADDRNORM_LIMIT_ADDR2 14661 #define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 14662 #define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 14663 #define MMEA1_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 14664 #define MMEA1_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 14665 //MMEA1_ADDRNORM_BASE_ADDR3 14666 #define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 14667 #define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 14668 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 14669 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 14670 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 14671 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 14672 #define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 14673 #define MMEA1_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 14674 #define MMEA1_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 14675 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL 14676 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L 14677 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 14678 #define MMEA1_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 14679 #define MMEA1_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 14680 //MMEA1_ADDRNORM_LIMIT_ADDR3 14681 #define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 14682 #define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 14683 #define MMEA1_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 14684 #define MMEA1_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 14685 //MMEA1_ADDRNORM_OFFSET_ADDR3 14686 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 14687 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc 14688 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 14689 #define MMEA1_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L 14690 //MMEA1_ADDRNORM_MEGABASE_ADDR0 14691 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 14692 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 14693 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 14694 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 14695 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 14696 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 14697 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc 14698 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 14699 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 14700 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 14701 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 14702 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 14703 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 14704 #define MMEA1_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 14705 //MMEA1_ADDRNORM_MEGALIMIT_ADDR0 14706 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 14707 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 14708 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 14709 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 14710 //MMEA1_ADDRNORM_MEGABASE_ADDR1 14711 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 14712 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 14713 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 14714 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 14715 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 14716 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 14717 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc 14718 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 14719 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 14720 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 14721 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 14722 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 14723 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 14724 #define MMEA1_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 14725 //MMEA1_ADDRNORM_MEGALIMIT_ADDR1 14726 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 14727 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 14728 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 14729 #define MMEA1_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 14730 //MMEA1_ADDRNORMDRAM_HOLE_CNTL 14731 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 14732 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 14733 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 14734 #define MMEA1_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 14735 //MMEA1_ADDRNORMGMI_HOLE_CNTL 14736 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 14737 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 14738 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 14739 #define MMEA1_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 14740 //MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG 14741 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 14742 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 14743 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 14744 #define MMEA1_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 14745 //MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG 14746 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 14747 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 14748 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 14749 #define MMEA1_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 14750 //MMEA1_ADDRDEC_BANK_CFG 14751 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 14752 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 14753 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 14754 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 14755 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 14756 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 14757 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 14758 #define MMEA1_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 14759 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 14760 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 14761 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 14762 #define MMEA1_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 14763 //MMEA1_ADDRDEC_MISC_CFG 14764 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 14765 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 14766 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 14767 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 14768 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 14769 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 14770 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 14771 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 14772 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 14773 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 14774 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 14775 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 14776 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 14777 #define MMEA1_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 14778 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 14779 #define MMEA1_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 14780 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 14781 #define MMEA1_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 14782 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 14783 #define MMEA1_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 14784 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 14785 #define MMEA1_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 14786 //MMEA1_ADDRDECDRAM_HARVEST_ENABLE 14787 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 14788 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 14789 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 14790 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 14791 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 14792 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 14793 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 14794 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 14795 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 14796 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 14797 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 14798 #define MMEA1_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 14799 //MMEA1_ADDRDECGMI_HARVEST_ENABLE 14800 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 14801 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 14802 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 14803 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 14804 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 14805 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 14806 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 14807 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 14808 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 14809 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 14810 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 14811 #define MMEA1_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 14812 //MMEA1_ADDRDEC0_BASE_ADDR_CS0 14813 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 14814 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 14815 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 14816 #define MMEA1_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 14817 //MMEA1_ADDRDEC0_BASE_ADDR_CS1 14818 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 14819 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 14820 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 14821 #define MMEA1_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 14822 //MMEA1_ADDRDEC0_BASE_ADDR_CS2 14823 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 14824 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 14825 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 14826 #define MMEA1_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 14827 //MMEA1_ADDRDEC0_BASE_ADDR_CS3 14828 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 14829 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 14830 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 14831 #define MMEA1_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 14832 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS0 14833 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 14834 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 14835 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 14836 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 14837 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS1 14838 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 14839 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 14840 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 14841 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 14842 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS2 14843 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 14844 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 14845 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 14846 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 14847 //MMEA1_ADDRDEC0_BASE_ADDR_SECCS3 14848 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 14849 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 14850 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 14851 #define MMEA1_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 14852 //MMEA1_ADDRDEC0_ADDR_MASK_CS01 14853 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 14854 #define MMEA1_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 14855 //MMEA1_ADDRDEC0_ADDR_MASK_CS23 14856 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 14857 #define MMEA1_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 14858 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS01 14859 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 14860 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 14861 //MMEA1_ADDRDEC0_ADDR_MASK_SECCS23 14862 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 14863 #define MMEA1_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 14864 //MMEA1_ADDRDEC0_ADDR_CFG_CS01 14865 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 14866 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 14867 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 14868 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 14869 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 14870 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 14871 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 14872 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 14873 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 14874 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 14875 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 14876 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 14877 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 14878 #define MMEA1_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 14879 //MMEA1_ADDRDEC0_ADDR_CFG_CS23 14880 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 14881 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 14882 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 14883 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 14884 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 14885 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 14886 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 14887 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 14888 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 14889 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 14890 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 14891 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 14892 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 14893 #define MMEA1_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 14894 //MMEA1_ADDRDEC0_ADDR_SEL_CS01 14895 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 14896 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 14897 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 14898 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 14899 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 14900 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 14901 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 14902 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 14903 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 14904 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 14905 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 14906 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 14907 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 14908 #define MMEA1_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 14909 //MMEA1_ADDRDEC0_ADDR_SEL_CS23 14910 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 14911 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 14912 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 14913 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 14914 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 14915 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 14916 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 14917 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 14918 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 14919 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 14920 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 14921 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 14922 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 14923 #define MMEA1_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 14924 //MMEA1_ADDRDEC0_ADDR_SEL2_CS01 14925 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 14926 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 14927 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 14928 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 14929 //MMEA1_ADDRDEC0_ADDR_SEL2_CS23 14930 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 14931 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 14932 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 14933 #define MMEA1_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 14934 //MMEA1_ADDRDEC0_COL_SEL_LO_CS01 14935 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 14936 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 14937 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 14938 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 14939 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 14940 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 14941 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 14942 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 14943 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 14944 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 14945 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 14946 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 14947 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 14948 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 14949 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 14950 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 14951 //MMEA1_ADDRDEC0_COL_SEL_LO_CS23 14952 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 14953 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 14954 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 14955 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 14956 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 14957 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 14958 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 14959 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 14960 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 14961 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 14962 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 14963 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 14964 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 14965 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 14966 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 14967 #define MMEA1_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 14968 //MMEA1_ADDRDEC0_COL_SEL_HI_CS01 14969 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 14970 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 14971 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 14972 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 14973 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 14974 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 14975 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 14976 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 14977 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 14978 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 14979 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 14980 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 14981 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 14982 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 14983 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 14984 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 14985 //MMEA1_ADDRDEC0_COL_SEL_HI_CS23 14986 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 14987 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 14988 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 14989 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 14990 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 14991 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 14992 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 14993 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 14994 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 14995 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 14996 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 14997 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 14998 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 14999 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 15000 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 15001 #define MMEA1_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 15002 //MMEA1_ADDRDEC0_RM_SEL_CS01 15003 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 15004 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 15005 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 15006 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 15007 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15008 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15009 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 15010 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 15011 #define MMEA1_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 15012 #define MMEA1_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 15013 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15014 #define MMEA1_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15015 //MMEA1_ADDRDEC0_RM_SEL_CS23 15016 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 15017 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 15018 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 15019 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 15020 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15021 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15022 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 15023 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 15024 #define MMEA1_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 15025 #define MMEA1_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 15026 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15027 #define MMEA1_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15028 //MMEA1_ADDRDEC0_RM_SEL_SECCS01 15029 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 15030 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 15031 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 15032 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 15033 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15034 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15035 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 15036 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 15037 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 15038 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 15039 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15040 #define MMEA1_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15041 //MMEA1_ADDRDEC0_RM_SEL_SECCS23 15042 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 15043 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 15044 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 15045 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 15046 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15047 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15048 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 15049 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 15050 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 15051 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 15052 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15053 #define MMEA1_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15054 //MMEA1_ADDRDEC1_BASE_ADDR_CS0 15055 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 15056 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 15057 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 15058 #define MMEA1_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 15059 //MMEA1_ADDRDEC1_BASE_ADDR_CS1 15060 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 15061 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 15062 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 15063 #define MMEA1_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 15064 //MMEA1_ADDRDEC1_BASE_ADDR_CS2 15065 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 15066 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 15067 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 15068 #define MMEA1_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 15069 //MMEA1_ADDRDEC1_BASE_ADDR_CS3 15070 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 15071 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 15072 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 15073 #define MMEA1_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 15074 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS0 15075 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 15076 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 15077 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 15078 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 15079 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS1 15080 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 15081 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 15082 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 15083 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 15084 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS2 15085 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 15086 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 15087 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 15088 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 15089 //MMEA1_ADDRDEC1_BASE_ADDR_SECCS3 15090 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 15091 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 15092 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 15093 #define MMEA1_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 15094 //MMEA1_ADDRDEC1_ADDR_MASK_CS01 15095 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 15096 #define MMEA1_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 15097 //MMEA1_ADDRDEC1_ADDR_MASK_CS23 15098 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 15099 #define MMEA1_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 15100 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS01 15101 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 15102 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 15103 //MMEA1_ADDRDEC1_ADDR_MASK_SECCS23 15104 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 15105 #define MMEA1_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 15106 //MMEA1_ADDRDEC1_ADDR_CFG_CS01 15107 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 15108 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 15109 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 15110 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 15111 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 15112 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 15113 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 15114 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 15115 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 15116 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 15117 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 15118 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 15119 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 15120 #define MMEA1_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 15121 //MMEA1_ADDRDEC1_ADDR_CFG_CS23 15122 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 15123 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 15124 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 15125 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 15126 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 15127 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 15128 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 15129 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 15130 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 15131 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 15132 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 15133 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 15134 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 15135 #define MMEA1_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 15136 //MMEA1_ADDRDEC1_ADDR_SEL_CS01 15137 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 15138 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 15139 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 15140 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 15141 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 15142 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 15143 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 15144 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 15145 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 15146 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 15147 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 15148 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 15149 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 15150 #define MMEA1_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 15151 //MMEA1_ADDRDEC1_ADDR_SEL_CS23 15152 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 15153 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 15154 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 15155 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 15156 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 15157 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 15158 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 15159 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 15160 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 15161 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 15162 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 15163 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 15164 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 15165 #define MMEA1_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 15166 //MMEA1_ADDRDEC1_ADDR_SEL2_CS01 15167 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 15168 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 15169 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 15170 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 15171 //MMEA1_ADDRDEC1_ADDR_SEL2_CS23 15172 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 15173 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 15174 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 15175 #define MMEA1_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 15176 //MMEA1_ADDRDEC1_COL_SEL_LO_CS01 15177 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 15178 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 15179 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 15180 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 15181 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 15182 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 15183 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 15184 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 15185 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 15186 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 15187 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 15188 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 15189 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 15190 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 15191 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 15192 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 15193 //MMEA1_ADDRDEC1_COL_SEL_LO_CS23 15194 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 15195 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 15196 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 15197 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 15198 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 15199 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 15200 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 15201 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 15202 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 15203 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 15204 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 15205 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 15206 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 15207 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 15208 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 15209 #define MMEA1_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 15210 //MMEA1_ADDRDEC1_COL_SEL_HI_CS01 15211 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 15212 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 15213 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 15214 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 15215 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 15216 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 15217 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 15218 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 15219 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 15220 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 15221 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 15222 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 15223 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 15224 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 15225 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 15226 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 15227 //MMEA1_ADDRDEC1_COL_SEL_HI_CS23 15228 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 15229 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 15230 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 15231 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 15232 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 15233 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 15234 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 15235 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 15236 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 15237 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 15238 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 15239 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 15240 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 15241 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 15242 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 15243 #define MMEA1_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 15244 //MMEA1_ADDRDEC1_RM_SEL_CS01 15245 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 15246 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 15247 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 15248 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 15249 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15250 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15251 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 15252 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 15253 #define MMEA1_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 15254 #define MMEA1_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 15255 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15256 #define MMEA1_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15257 //MMEA1_ADDRDEC1_RM_SEL_CS23 15258 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 15259 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 15260 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 15261 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 15262 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15263 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15264 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 15265 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 15266 #define MMEA1_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 15267 #define MMEA1_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 15268 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15269 #define MMEA1_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15270 //MMEA1_ADDRDEC1_RM_SEL_SECCS01 15271 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 15272 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 15273 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 15274 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 15275 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15276 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15277 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 15278 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 15279 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 15280 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 15281 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15282 #define MMEA1_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15283 //MMEA1_ADDRDEC1_RM_SEL_SECCS23 15284 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 15285 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 15286 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 15287 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 15288 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15289 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15290 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 15291 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 15292 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 15293 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 15294 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15295 #define MMEA1_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15296 //MMEA1_ADDRDEC2_BASE_ADDR_CS0 15297 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 15298 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 15299 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 15300 #define MMEA1_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 15301 //MMEA1_ADDRDEC2_BASE_ADDR_CS1 15302 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 15303 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 15304 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 15305 #define MMEA1_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 15306 //MMEA1_ADDRDEC2_BASE_ADDR_CS2 15307 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 15308 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 15309 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 15310 #define MMEA1_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 15311 //MMEA1_ADDRDEC2_BASE_ADDR_CS3 15312 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 15313 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 15314 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 15315 #define MMEA1_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 15316 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS0 15317 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 15318 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 15319 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 15320 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 15321 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS1 15322 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 15323 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 15324 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 15325 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 15326 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS2 15327 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 15328 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 15329 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 15330 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 15331 //MMEA1_ADDRDEC2_BASE_ADDR_SECCS3 15332 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 15333 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 15334 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 15335 #define MMEA1_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 15336 //MMEA1_ADDRDEC2_ADDR_MASK_CS01 15337 #define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 15338 #define MMEA1_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 15339 //MMEA1_ADDRDEC2_ADDR_MASK_CS23 15340 #define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 15341 #define MMEA1_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 15342 //MMEA1_ADDRDEC2_ADDR_MASK_SECCS01 15343 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 15344 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 15345 //MMEA1_ADDRDEC2_ADDR_MASK_SECCS23 15346 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 15347 #define MMEA1_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 15348 //MMEA1_ADDRDEC2_ADDR_CFG_CS01 15349 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 15350 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 15351 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 15352 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 15353 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 15354 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 15355 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 15356 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 15357 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 15358 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 15359 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 15360 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 15361 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 15362 #define MMEA1_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 15363 //MMEA1_ADDRDEC2_ADDR_CFG_CS23 15364 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 15365 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 15366 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 15367 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 15368 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 15369 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 15370 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 15371 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 15372 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 15373 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 15374 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 15375 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 15376 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 15377 #define MMEA1_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 15378 //MMEA1_ADDRDEC2_ADDR_SEL_CS01 15379 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 15380 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 15381 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 15382 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 15383 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 15384 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 15385 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 15386 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 15387 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 15388 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 15389 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 15390 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 15391 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 15392 #define MMEA1_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 15393 //MMEA1_ADDRDEC2_ADDR_SEL_CS23 15394 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 15395 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 15396 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 15397 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 15398 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 15399 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 15400 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 15401 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 15402 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 15403 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 15404 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 15405 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 15406 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 15407 #define MMEA1_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 15408 //MMEA1_ADDRDEC2_ADDR_SEL2_CS01 15409 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 15410 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 15411 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 15412 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 15413 //MMEA1_ADDRDEC2_ADDR_SEL2_CS23 15414 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 15415 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 15416 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 15417 #define MMEA1_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 15418 //MMEA1_ADDRDEC2_COL_SEL_LO_CS01 15419 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 15420 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 15421 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 15422 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 15423 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 15424 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 15425 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 15426 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 15427 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 15428 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 15429 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 15430 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 15431 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 15432 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 15433 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 15434 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 15435 //MMEA1_ADDRDEC2_COL_SEL_LO_CS23 15436 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 15437 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 15438 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 15439 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 15440 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 15441 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 15442 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 15443 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 15444 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 15445 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 15446 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 15447 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 15448 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 15449 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 15450 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 15451 #define MMEA1_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 15452 //MMEA1_ADDRDEC2_COL_SEL_HI_CS01 15453 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 15454 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 15455 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 15456 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 15457 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 15458 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 15459 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 15460 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 15461 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 15462 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 15463 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 15464 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 15465 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 15466 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 15467 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 15468 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 15469 //MMEA1_ADDRDEC2_COL_SEL_HI_CS23 15470 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 15471 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 15472 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 15473 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 15474 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 15475 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 15476 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 15477 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 15478 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 15479 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 15480 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 15481 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 15482 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 15483 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 15484 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 15485 #define MMEA1_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 15486 //MMEA1_ADDRDEC2_RM_SEL_CS01 15487 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 15488 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 15489 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 15490 #define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 15491 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15492 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15493 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 15494 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 15495 #define MMEA1_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 15496 #define MMEA1_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 15497 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15498 #define MMEA1_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15499 //MMEA1_ADDRDEC2_RM_SEL_CS23 15500 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 15501 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 15502 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 15503 #define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 15504 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15505 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15506 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 15507 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 15508 #define MMEA1_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 15509 #define MMEA1_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 15510 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15511 #define MMEA1_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15512 //MMEA1_ADDRDEC2_RM_SEL_SECCS01 15513 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 15514 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 15515 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 15516 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 15517 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15518 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15519 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 15520 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 15521 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 15522 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 15523 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15524 #define MMEA1_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15525 //MMEA1_ADDRDEC2_RM_SEL_SECCS23 15526 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 15527 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 15528 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 15529 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 15530 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 15531 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 15532 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 15533 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 15534 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 15535 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 15536 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 15537 #define MMEA1_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 15538 //MMEA1_ADDRNORMDRAM_GLOBAL_CNTL 15539 //MMEA1_ADDRNORMGMI_GLOBAL_CNTL 15540 //MMEA1_ADDRNORM_MEGACONTROL_ADDR0 15541 #define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 15542 #define MMEA1_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 15543 //MMEA1_ADDRNORM_MEGACONTROL_ADDR1 15544 #define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 15545 #define MMEA1_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 15546 //MMEA1_ADDRNORMDRAM_MASKING 15547 #define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 15548 #define MMEA1_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 15549 //MMEA1_ADDRNORMGMI_MASKING 15550 #define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 15551 #define MMEA1_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 15552 //MMEA1_IO_RD_CLI2GRP_MAP0 15553 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 15554 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 15555 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 15556 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 15557 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 15558 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 15559 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 15560 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 15561 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 15562 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 15563 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 15564 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 15565 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 15566 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 15567 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 15568 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 15569 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 15570 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 15571 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 15572 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 15573 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 15574 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 15575 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 15576 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 15577 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 15578 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 15579 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 15580 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 15581 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 15582 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 15583 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 15584 #define MMEA1_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 15585 //MMEA1_IO_RD_CLI2GRP_MAP1 15586 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 15587 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 15588 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 15589 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 15590 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 15591 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 15592 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 15593 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 15594 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 15595 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 15596 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 15597 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 15598 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 15599 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 15600 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 15601 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 15602 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 15603 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 15604 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 15605 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 15606 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 15607 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 15608 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 15609 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 15610 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 15611 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 15612 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 15613 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 15614 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 15615 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 15616 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 15617 #define MMEA1_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 15618 //MMEA1_IO_WR_CLI2GRP_MAP0 15619 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 15620 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 15621 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 15622 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 15623 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 15624 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 15625 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 15626 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 15627 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 15628 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 15629 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 15630 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 15631 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 15632 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 15633 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 15634 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 15635 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 15636 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 15637 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 15638 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 15639 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 15640 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 15641 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 15642 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 15643 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 15644 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 15645 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 15646 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 15647 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 15648 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 15649 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 15650 #define MMEA1_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 15651 //MMEA1_IO_WR_CLI2GRP_MAP1 15652 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 15653 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 15654 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 15655 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 15656 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 15657 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 15658 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 15659 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 15660 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 15661 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 15662 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 15663 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 15664 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 15665 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 15666 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 15667 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 15668 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 15669 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 15670 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 15671 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 15672 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 15673 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 15674 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 15675 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 15676 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 15677 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 15678 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 15679 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 15680 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 15681 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 15682 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 15683 #define MMEA1_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 15684 //MMEA1_IO_RD_COMBINE_FLUSH 15685 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 15686 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 15687 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 15688 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 15689 #define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 15690 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 15691 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 15692 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 15693 #define MMEA1_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 15694 #define MMEA1_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 15695 //MMEA1_IO_WR_COMBINE_FLUSH 15696 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 15697 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 15698 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 15699 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 15700 #define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 15701 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 15702 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 15703 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 15704 #define MMEA1_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 15705 #define MMEA1_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 15706 //MMEA1_IO_GROUP_BURST 15707 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 15708 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 15709 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 15710 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 15711 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 15712 #define MMEA1_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 15713 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 15714 #define MMEA1_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 15715 //MMEA1_IO_RD_PRI_AGE 15716 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 15717 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 15718 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 15719 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 15720 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 15721 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 15722 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 15723 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 15724 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 15725 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 15726 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 15727 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 15728 #define MMEA1_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 15729 #define MMEA1_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 15730 #define MMEA1_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 15731 #define MMEA1_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 15732 //MMEA1_IO_WR_PRI_AGE 15733 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 15734 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 15735 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 15736 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 15737 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 15738 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 15739 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 15740 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 15741 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 15742 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 15743 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 15744 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 15745 #define MMEA1_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 15746 #define MMEA1_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 15747 #define MMEA1_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 15748 #define MMEA1_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 15749 //MMEA1_IO_RD_PRI_QUEUING 15750 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 15751 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 15752 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 15753 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 15754 #define MMEA1_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 15755 #define MMEA1_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 15756 #define MMEA1_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 15757 #define MMEA1_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 15758 //MMEA1_IO_WR_PRI_QUEUING 15759 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 15760 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 15761 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 15762 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 15763 #define MMEA1_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 15764 #define MMEA1_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 15765 #define MMEA1_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 15766 #define MMEA1_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 15767 //MMEA1_IO_RD_PRI_FIXED 15768 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 15769 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 15770 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 15771 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 15772 #define MMEA1_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 15773 #define MMEA1_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 15774 #define MMEA1_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 15775 #define MMEA1_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 15776 //MMEA1_IO_WR_PRI_FIXED 15777 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 15778 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 15779 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 15780 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 15781 #define MMEA1_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 15782 #define MMEA1_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 15783 #define MMEA1_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 15784 #define MMEA1_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 15785 //MMEA1_IO_RD_PRI_URGENCY 15786 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 15787 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 15788 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 15789 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 15790 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 15791 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 15792 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 15793 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 15794 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 15795 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 15796 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 15797 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 15798 #define MMEA1_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 15799 #define MMEA1_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 15800 #define MMEA1_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 15801 #define MMEA1_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 15802 //MMEA1_IO_WR_PRI_URGENCY 15803 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 15804 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 15805 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 15806 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 15807 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 15808 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 15809 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 15810 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 15811 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 15812 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 15813 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 15814 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 15815 #define MMEA1_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 15816 #define MMEA1_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 15817 #define MMEA1_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 15818 #define MMEA1_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 15819 //MMEA1_IO_RD_PRI_URGENCY_MASKING 15820 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 15821 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 15822 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 15823 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 15824 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 15825 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 15826 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 15827 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 15828 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 15829 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 15830 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 15831 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 15832 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 15833 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 15834 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 15835 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 15836 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 15837 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 15838 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 15839 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 15840 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 15841 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 15842 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 15843 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 15844 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 15845 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 15846 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 15847 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 15848 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 15849 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 15850 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 15851 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 15852 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 15853 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 15854 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 15855 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 15856 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 15857 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 15858 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 15859 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 15860 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 15861 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 15862 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 15863 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 15864 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 15865 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 15866 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 15867 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 15868 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 15869 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 15870 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 15871 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 15872 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 15873 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 15874 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 15875 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 15876 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 15877 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 15878 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 15879 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 15880 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 15881 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 15882 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 15883 #define MMEA1_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 15884 //MMEA1_IO_WR_PRI_URGENCY_MASKING 15885 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 15886 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 15887 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 15888 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 15889 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 15890 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 15891 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 15892 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 15893 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 15894 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 15895 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 15896 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 15897 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 15898 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 15899 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 15900 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 15901 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 15902 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 15903 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 15904 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 15905 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 15906 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 15907 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 15908 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 15909 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 15910 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 15911 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 15912 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 15913 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 15914 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 15915 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 15916 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 15917 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 15918 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 15919 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 15920 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 15921 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 15922 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 15923 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 15924 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 15925 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 15926 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 15927 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 15928 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 15929 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 15930 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 15931 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 15932 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 15933 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 15934 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 15935 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 15936 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 15937 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 15938 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 15939 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 15940 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 15941 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 15942 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 15943 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 15944 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 15945 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 15946 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 15947 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 15948 #define MMEA1_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 15949 //MMEA1_IO_RD_PRI_QUANT_PRI1 15950 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 15951 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 15952 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 15953 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 15954 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 15955 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 15956 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 15957 #define MMEA1_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 15958 //MMEA1_IO_RD_PRI_QUANT_PRI2 15959 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 15960 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 15961 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 15962 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 15963 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 15964 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 15965 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 15966 #define MMEA1_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 15967 //MMEA1_IO_RD_PRI_QUANT_PRI3 15968 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 15969 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 15970 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 15971 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 15972 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 15973 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 15974 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 15975 #define MMEA1_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 15976 //MMEA1_IO_WR_PRI_QUANT_PRI1 15977 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 15978 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 15979 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 15980 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 15981 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 15982 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 15983 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 15984 #define MMEA1_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 15985 //MMEA1_IO_WR_PRI_QUANT_PRI2 15986 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 15987 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 15988 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 15989 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 15990 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 15991 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 15992 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 15993 #define MMEA1_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 15994 //MMEA1_IO_WR_PRI_QUANT_PRI3 15995 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 15996 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 15997 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 15998 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 15999 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 16000 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 16001 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 16002 #define MMEA1_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 16003 //MMEA1_SDP_ARB_DRAM 16004 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 16005 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 16006 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 16007 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 16008 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 16009 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 16010 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 16011 #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 16012 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 16013 #define MMEA1_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 16014 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 16015 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 16016 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 16017 #define MMEA1_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 16018 #define MMEA1_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 16019 #define MMEA1_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 16020 //MMEA1_SDP_ARB_GMI 16021 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 16022 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 16023 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 16024 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 16025 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 16026 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 16027 #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 16028 #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 16029 #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 16030 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 16031 #define MMEA1_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 16032 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 16033 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 16034 #define MMEA1_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 16035 #define MMEA1_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 16036 #define MMEA1_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 16037 #define MMEA1_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 16038 #define MMEA1_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 16039 //MMEA1_SDP_ARB_FINAL 16040 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 16041 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 16042 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 16043 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 16044 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 16045 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 16046 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 16047 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 16048 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 16049 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 16050 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 16051 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 16052 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 16053 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 16054 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 16055 #define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c 16056 #define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d 16057 #define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e 16058 #define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f 16059 #define MMEA1_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 16060 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 16061 #define MMEA1_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 16062 #define MMEA1_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 16063 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 16064 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 16065 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 16066 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 16067 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 16068 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 16069 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 16070 #define MMEA1_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 16071 #define MMEA1_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 16072 #define MMEA1_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 16073 #define MMEA1_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 16074 #define MMEA1_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L 16075 #define MMEA1_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L 16076 #define MMEA1_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L 16077 #define MMEA1_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L 16078 //MMEA1_SDP_DRAM_PRIORITY 16079 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 16080 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 16081 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 16082 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 16083 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 16084 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 16085 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 16086 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 16087 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 16088 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 16089 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 16090 #define MMEA1_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 16091 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 16092 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 16093 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 16094 #define MMEA1_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 16095 //MMEA1_SDP_GMI_PRIORITY 16096 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 16097 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 16098 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 16099 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 16100 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 16101 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 16102 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 16103 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 16104 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 16105 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 16106 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 16107 #define MMEA1_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 16108 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 16109 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 16110 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 16111 #define MMEA1_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 16112 //MMEA1_SDP_IO_PRIORITY 16113 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 16114 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 16115 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 16116 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 16117 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 16118 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 16119 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 16120 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 16121 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 16122 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 16123 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 16124 #define MMEA1_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 16125 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 16126 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 16127 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 16128 #define MMEA1_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 16129 //MMEA1_SDP_CREDITS 16130 #define MMEA1_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 16131 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 16132 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 16133 #define MMEA1_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 16134 #define MMEA1_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 16135 #define MMEA1_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 16136 //MMEA1_SDP_TAG_RESERVE0 16137 #define MMEA1_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 16138 #define MMEA1_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 16139 #define MMEA1_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 16140 #define MMEA1_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 16141 #define MMEA1_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 16142 #define MMEA1_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 16143 #define MMEA1_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 16144 #define MMEA1_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 16145 //MMEA1_SDP_TAG_RESERVE1 16146 #define MMEA1_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 16147 #define MMEA1_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 16148 #define MMEA1_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 16149 #define MMEA1_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 16150 #define MMEA1_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 16151 #define MMEA1_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 16152 #define MMEA1_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 16153 #define MMEA1_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 16154 //MMEA1_SDP_VCC_RESERVE0 16155 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 16156 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 16157 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 16158 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 16159 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 16160 #define MMEA1_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 16161 #define MMEA1_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 16162 #define MMEA1_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 16163 #define MMEA1_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 16164 #define MMEA1_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 16165 //MMEA1_SDP_VCC_RESERVE1 16166 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 16167 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 16168 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 16169 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 16170 #define MMEA1_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 16171 #define MMEA1_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 16172 #define MMEA1_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 16173 #define MMEA1_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 16174 //MMEA1_SDP_VCD_RESERVE0 16175 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 16176 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 16177 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 16178 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 16179 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 16180 #define MMEA1_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 16181 #define MMEA1_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 16182 #define MMEA1_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 16183 #define MMEA1_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 16184 #define MMEA1_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 16185 //MMEA1_SDP_VCD_RESERVE1 16186 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 16187 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 16188 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 16189 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 16190 #define MMEA1_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 16191 #define MMEA1_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 16192 #define MMEA1_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 16193 #define MMEA1_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 16194 //MMEA1_SDP_REQ_CNTL 16195 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 16196 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 16197 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 16198 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 16199 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 16200 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 16201 #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 16202 #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 16203 #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 16204 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 16205 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 16206 #define MMEA1_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 16207 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 16208 #define MMEA1_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 16209 #define MMEA1_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 16210 #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 16211 #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 16212 #define MMEA1_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 16213 //MMEA1_MISC 16214 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 16215 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 16216 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 16217 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 16218 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 16219 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 16220 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 16221 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 16222 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 16223 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 16224 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 16225 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 16226 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 16227 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 16228 #define MMEA1_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 16229 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 16230 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 16231 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 16232 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 16233 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 16234 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 16235 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 16236 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 16237 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 16238 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 16239 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 16240 #define MMEA1_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 16241 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 16242 #define MMEA1_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 16243 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 16244 #define MMEA1_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 16245 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 16246 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 16247 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 16248 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 16249 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 16250 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 16251 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 16252 #define MMEA1_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 16253 #define MMEA1_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 16254 #define MMEA1_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 16255 #define MMEA1_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 16256 #define MMEA1_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 16257 #define MMEA1_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 16258 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 16259 #define MMEA1_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 16260 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 16261 #define MMEA1_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 16262 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 16263 #define MMEA1_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 16264 //MMEA1_LATENCY_SAMPLING 16265 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 16266 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 16267 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 16268 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 16269 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 16270 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 16271 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 16272 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 16273 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 16274 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 16275 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 16276 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 16277 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 16278 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 16279 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 16280 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 16281 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 16282 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 16283 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 16284 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 16285 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 16286 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 16287 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 16288 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 16289 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 16290 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 16291 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 16292 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 16293 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 16294 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 16295 #define MMEA1_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 16296 #define MMEA1_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 16297 //MMEA1_PERFCOUNTER_LO 16298 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 16299 #define MMEA1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 16300 //MMEA1_PERFCOUNTER_HI 16301 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 16302 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 16303 #define MMEA1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 16304 #define MMEA1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 16305 //MMEA1_PERFCOUNTER0_CFG 16306 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 16307 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 16308 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 16309 #define MMEA1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 16310 #define MMEA1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 16311 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 16312 #define MMEA1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 16313 #define MMEA1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 16314 #define MMEA1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 16315 #define MMEA1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 16316 //MMEA1_PERFCOUNTER1_CFG 16317 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 16318 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 16319 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 16320 #define MMEA1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 16321 #define MMEA1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 16322 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 16323 #define MMEA1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 16324 #define MMEA1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 16325 #define MMEA1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 16326 #define MMEA1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 16327 //MMEA1_PERFCOUNTER_RSLT_CNTL 16328 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 16329 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 16330 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 16331 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 16332 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 16333 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 16334 #define MMEA1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 16335 #define MMEA1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 16336 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 16337 #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 16338 #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 16339 #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 16340 //MMEA1_EDC_CNT 16341 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 16342 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 16343 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 16344 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 16345 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 16346 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 16347 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 16348 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 16349 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 16350 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 16351 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 16352 #define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 16353 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 16354 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a 16355 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c 16356 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e 16357 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 16358 #define MMEA1_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 16359 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 16360 #define MMEA1_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 16361 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 16362 #define MMEA1_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 16363 #define MMEA1_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 16364 #define MMEA1_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 16365 #define MMEA1_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 16366 #define MMEA1_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 16367 #define MMEA1_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L 16368 #define MMEA1_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L 16369 #define MMEA1_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L 16370 #define MMEA1_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L 16371 #define MMEA1_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L 16372 #define MMEA1_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L 16373 //MMEA1_EDC_CNT2 16374 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 16375 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 16376 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 16377 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 16378 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 16379 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 16380 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 16381 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 16382 #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 16383 #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 16384 #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 16385 #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 16386 #define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 16387 #define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 16388 #define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 16389 #define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 16390 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 16391 #define MMEA1_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 16392 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 16393 #define MMEA1_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 16394 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 16395 #define MMEA1_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 16396 #define MMEA1_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 16397 #define MMEA1_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 16398 #define MMEA1_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 16399 #define MMEA1_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 16400 #define MMEA1_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 16401 #define MMEA1_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 16402 #define MMEA1_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 16403 #define MMEA1_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 16404 #define MMEA1_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 16405 #define MMEA1_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 16406 //MMEA1_DSM_CNTL 16407 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 16408 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 16409 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 16410 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 16411 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 16412 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 16413 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 16414 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 16415 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 16416 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 16417 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 16418 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 16419 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 16420 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 16421 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 16422 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 16423 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 16424 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 16425 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 16426 #define MMEA1_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 16427 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 16428 #define MMEA1_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 16429 #define MMEA1_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 16430 #define MMEA1_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 16431 #define MMEA1_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 16432 #define MMEA1_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 16433 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 16434 #define MMEA1_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 16435 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 16436 #define MMEA1_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 16437 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 16438 #define MMEA1_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 16439 //MMEA1_DSM_CNTLA 16440 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 16441 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 16442 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 16443 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 16444 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 16445 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 16446 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 16447 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 16448 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 16449 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 16450 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 16451 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 16452 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 16453 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 16454 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 16455 #define MMEA1_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 16456 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 16457 #define MMEA1_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 16458 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 16459 #define MMEA1_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 16460 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 16461 #define MMEA1_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 16462 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 16463 #define MMEA1_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 16464 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 16465 #define MMEA1_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 16466 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 16467 #define MMEA1_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 16468 //MMEA1_DSM_CNTLB 16469 //MMEA1_DSM_CNTL2 16470 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 16471 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 16472 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 16473 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 16474 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 16475 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 16476 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 16477 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 16478 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 16479 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 16480 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 16481 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 16482 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 16483 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 16484 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 16485 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 16486 #define MMEA1_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 16487 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 16488 #define MMEA1_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 16489 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 16490 #define MMEA1_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 16491 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 16492 #define MMEA1_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 16493 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 16494 #define MMEA1_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 16495 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 16496 #define MMEA1_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 16497 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 16498 #define MMEA1_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 16499 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 16500 #define MMEA1_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 16501 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 16502 #define MMEA1_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 16503 #define MMEA1_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 16504 //MMEA1_DSM_CNTL2A 16505 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 16506 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 16507 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 16508 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 16509 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 16510 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 16511 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 16512 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 16513 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 16514 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 16515 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 16516 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 16517 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 16518 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 16519 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 16520 #define MMEA1_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 16521 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 16522 #define MMEA1_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 16523 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 16524 #define MMEA1_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 16525 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 16526 #define MMEA1_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 16527 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 16528 #define MMEA1_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 16529 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 16530 #define MMEA1_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 16531 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 16532 #define MMEA1_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 16533 //MMEA1_DSM_CNTL2B 16534 //MMEA1_CGTT_CLK_CTRL 16535 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 16536 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 16537 #define MMEA1_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 16538 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 16539 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 16540 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 16541 #define MMEA1_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 16542 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 16543 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 16544 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 16545 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 16546 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 16547 #define MMEA1_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 16548 #define MMEA1_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 16549 #define MMEA1_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 16550 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 16551 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 16552 #define MMEA1_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 16553 #define MMEA1_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 16554 #define MMEA1_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 16555 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 16556 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 16557 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 16558 #define MMEA1_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 16559 //MMEA1_EDC_MODE 16560 #define MMEA1_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 16561 #define MMEA1_EDC_MODE__GATE_FUE__SHIFT 0x11 16562 #define MMEA1_EDC_MODE__DED_MODE__SHIFT 0x14 16563 #define MMEA1_EDC_MODE__PROP_FED__SHIFT 0x1d 16564 #define MMEA1_EDC_MODE__BYPASS__SHIFT 0x1f 16565 #define MMEA1_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 16566 #define MMEA1_EDC_MODE__GATE_FUE_MASK 0x00020000L 16567 #define MMEA1_EDC_MODE__DED_MODE_MASK 0x00300000L 16568 #define MMEA1_EDC_MODE__PROP_FED_MASK 0x20000000L 16569 #define MMEA1_EDC_MODE__BYPASS_MASK 0x80000000L 16570 //MMEA1_ERR_STATUS 16571 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 16572 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 16573 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 16574 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 16575 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 16576 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 16577 #define MMEA1_ERR_STATUS__FUE_FLAG__SHIFT 0xd 16578 #define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 16579 #define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 16580 #define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 16581 #define MMEA1_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 16582 #define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 16583 #define MMEA1_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 16584 #define MMEA1_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 16585 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 16586 #define MMEA1_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 16587 #define MMEA1_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 16588 #define MMEA1_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 16589 #define MMEA1_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 16590 #define MMEA1_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 16591 #define MMEA1_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 16592 #define MMEA1_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 16593 #define MMEA1_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 16594 #define MMEA1_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 16595 //MMEA1_MISC2 16596 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 16597 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 16598 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 16599 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 16600 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 16601 #define MMEA1_MISC2__RRET_SWAP_MODE__SHIFT 0xd 16602 #define MMEA1_MISC2__BLOCK_REQUESTS__SHIFT 0xe 16603 #define MMEA1_MISC2__REQUESTS_BLOCKED__SHIFT 0xf 16604 #define MMEA1_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 16605 #define MMEA1_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 16606 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 16607 #define MMEA1_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 16608 #define MMEA1_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 16609 #define MMEA1_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 16610 #define MMEA1_MISC2__BLOCK_REQUESTS_MASK 0x00004000L 16611 #define MMEA1_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L 16612 //MMEA1_ADDRDEC_SELECT 16613 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 16614 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 16615 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 16616 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 16617 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 16618 #define MMEA1_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 16619 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 16620 #define MMEA1_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 16621 //MMEA1_EDC_CNT3 16622 #define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 16623 #define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 16624 #define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 16625 #define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 16626 #define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 16627 #define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa 16628 #define MMEA1_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 16629 #define MMEA1_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 16630 #define MMEA1_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 16631 #define MMEA1_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 16632 #define MMEA1_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L 16633 #define MMEA1_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L 16634 //MMEA1_MISC_AON 16635 #define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 16636 #define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 16637 #define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 16638 #define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 16639 16640 16641 // addressBlock: mmhub_ea_mmeadec2 16642 //MMEA2_DRAM_RD_CLI2GRP_MAP0 16643 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 16644 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 16645 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 16646 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 16647 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 16648 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 16649 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 16650 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 16651 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 16652 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 16653 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 16654 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 16655 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 16656 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 16657 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 16658 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 16659 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 16660 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 16661 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 16662 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 16663 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 16664 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 16665 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 16666 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 16667 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 16668 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 16669 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 16670 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 16671 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 16672 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 16673 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 16674 #define MMEA2_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 16675 //MMEA2_DRAM_RD_CLI2GRP_MAP1 16676 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 16677 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 16678 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 16679 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 16680 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 16681 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 16682 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 16683 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 16684 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 16685 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 16686 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 16687 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 16688 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 16689 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 16690 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 16691 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 16692 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 16693 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 16694 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 16695 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 16696 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 16697 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 16698 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 16699 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 16700 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 16701 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 16702 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 16703 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 16704 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 16705 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 16706 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 16707 #define MMEA2_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 16708 //MMEA2_DRAM_WR_CLI2GRP_MAP0 16709 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 16710 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 16711 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 16712 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 16713 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 16714 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 16715 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 16716 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 16717 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 16718 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 16719 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 16720 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 16721 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 16722 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 16723 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 16724 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 16725 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 16726 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 16727 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 16728 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 16729 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 16730 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 16731 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 16732 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 16733 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 16734 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 16735 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 16736 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 16737 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 16738 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 16739 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 16740 #define MMEA2_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 16741 //MMEA2_DRAM_WR_CLI2GRP_MAP1 16742 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 16743 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 16744 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 16745 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 16746 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 16747 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 16748 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 16749 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 16750 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 16751 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 16752 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 16753 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 16754 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 16755 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 16756 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 16757 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 16758 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 16759 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 16760 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 16761 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 16762 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 16763 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 16764 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 16765 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 16766 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 16767 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 16768 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 16769 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 16770 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 16771 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 16772 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 16773 #define MMEA2_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 16774 //MMEA2_DRAM_RD_GRP2VC_MAP 16775 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 16776 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 16777 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 16778 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 16779 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 16780 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 16781 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 16782 #define MMEA2_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 16783 //MMEA2_DRAM_WR_GRP2VC_MAP 16784 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 16785 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 16786 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 16787 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 16788 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 16789 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 16790 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 16791 #define MMEA2_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 16792 //MMEA2_DRAM_RD_LAZY 16793 #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 16794 #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 16795 #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 16796 #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 16797 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 16798 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 16799 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 16800 #define MMEA2_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 16801 #define MMEA2_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 16802 #define MMEA2_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 16803 #define MMEA2_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 16804 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 16805 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 16806 #define MMEA2_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 16807 //MMEA2_DRAM_WR_LAZY 16808 #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 16809 #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 16810 #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 16811 #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 16812 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 16813 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 16814 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 16815 #define MMEA2_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 16816 #define MMEA2_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 16817 #define MMEA2_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 16818 #define MMEA2_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 16819 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 16820 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 16821 #define MMEA2_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 16822 //MMEA2_DRAM_RD_CAM_CNTL 16823 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 16824 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 16825 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 16826 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 16827 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 16828 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 16829 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 16830 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 16831 #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 16832 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 16833 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 16834 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 16835 #define MMEA2_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 16836 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 16837 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 16838 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 16839 #define MMEA2_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 16840 #define MMEA2_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 16841 //MMEA2_DRAM_WR_CAM_CNTL 16842 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 16843 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 16844 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 16845 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 16846 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 16847 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 16848 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 16849 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 16850 #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 16851 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 16852 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 16853 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 16854 #define MMEA2_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 16855 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 16856 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 16857 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 16858 #define MMEA2_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 16859 #define MMEA2_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 16860 //MMEA2_DRAM_PAGE_BURST 16861 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 16862 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 16863 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 16864 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 16865 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 16866 #define MMEA2_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 16867 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 16868 #define MMEA2_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 16869 //MMEA2_DRAM_RD_PRI_AGE 16870 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 16871 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 16872 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 16873 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 16874 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 16875 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 16876 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 16877 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 16878 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 16879 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 16880 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 16881 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 16882 #define MMEA2_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 16883 #define MMEA2_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 16884 #define MMEA2_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 16885 #define MMEA2_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 16886 //MMEA2_DRAM_WR_PRI_AGE 16887 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 16888 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 16889 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 16890 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 16891 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 16892 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 16893 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 16894 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 16895 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 16896 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 16897 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 16898 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 16899 #define MMEA2_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 16900 #define MMEA2_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 16901 #define MMEA2_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 16902 #define MMEA2_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 16903 //MMEA2_DRAM_RD_PRI_QUEUING 16904 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 16905 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 16906 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 16907 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 16908 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 16909 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 16910 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 16911 #define MMEA2_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 16912 //MMEA2_DRAM_WR_PRI_QUEUING 16913 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 16914 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 16915 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 16916 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 16917 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 16918 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 16919 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 16920 #define MMEA2_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 16921 //MMEA2_DRAM_RD_PRI_FIXED 16922 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 16923 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 16924 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 16925 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 16926 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 16927 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 16928 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 16929 #define MMEA2_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 16930 //MMEA2_DRAM_WR_PRI_FIXED 16931 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 16932 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 16933 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 16934 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 16935 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 16936 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 16937 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 16938 #define MMEA2_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 16939 //MMEA2_DRAM_RD_PRI_URGENCY 16940 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 16941 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 16942 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 16943 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 16944 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 16945 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 16946 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 16947 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 16948 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 16949 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 16950 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 16951 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 16952 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 16953 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 16954 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 16955 #define MMEA2_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 16956 //MMEA2_DRAM_WR_PRI_URGENCY 16957 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 16958 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 16959 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 16960 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 16961 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 16962 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 16963 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 16964 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 16965 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 16966 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 16967 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 16968 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 16969 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 16970 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 16971 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 16972 #define MMEA2_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 16973 //MMEA2_DRAM_RD_PRI_QUANT_PRI1 16974 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 16975 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 16976 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 16977 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 16978 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 16979 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 16980 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 16981 #define MMEA2_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 16982 //MMEA2_DRAM_RD_PRI_QUANT_PRI2 16983 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 16984 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 16985 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 16986 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 16987 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 16988 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 16989 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 16990 #define MMEA2_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 16991 //MMEA2_DRAM_RD_PRI_QUANT_PRI3 16992 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 16993 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 16994 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 16995 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 16996 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 16997 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 16998 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 16999 #define MMEA2_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 17000 //MMEA2_DRAM_WR_PRI_QUANT_PRI1 17001 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 17002 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 17003 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 17004 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 17005 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 17006 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 17007 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 17008 #define MMEA2_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 17009 //MMEA2_DRAM_WR_PRI_QUANT_PRI2 17010 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 17011 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 17012 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 17013 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 17014 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 17015 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 17016 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 17017 #define MMEA2_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 17018 //MMEA2_DRAM_WR_PRI_QUANT_PRI3 17019 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 17020 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 17021 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 17022 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 17023 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 17024 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 17025 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 17026 #define MMEA2_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 17027 //MMEA2_GMI_RD_CLI2GRP_MAP0 17028 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 17029 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 17030 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 17031 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 17032 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 17033 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 17034 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 17035 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 17036 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 17037 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 17038 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 17039 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 17040 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 17041 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 17042 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 17043 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 17044 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 17045 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 17046 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 17047 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 17048 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 17049 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 17050 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 17051 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 17052 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 17053 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 17054 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 17055 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 17056 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 17057 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 17058 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 17059 #define MMEA2_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 17060 //MMEA2_GMI_RD_CLI2GRP_MAP1 17061 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 17062 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 17063 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 17064 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 17065 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 17066 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 17067 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 17068 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 17069 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 17070 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 17071 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 17072 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 17073 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 17074 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 17075 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 17076 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 17077 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 17078 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 17079 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 17080 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 17081 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 17082 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 17083 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 17084 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 17085 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 17086 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 17087 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 17088 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 17089 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 17090 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 17091 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 17092 #define MMEA2_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 17093 //MMEA2_GMI_WR_CLI2GRP_MAP0 17094 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 17095 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 17096 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 17097 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 17098 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 17099 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 17100 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 17101 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 17102 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 17103 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 17104 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 17105 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 17106 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 17107 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 17108 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 17109 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 17110 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 17111 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 17112 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 17113 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 17114 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 17115 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 17116 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 17117 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 17118 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 17119 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 17120 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 17121 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 17122 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 17123 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 17124 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 17125 #define MMEA2_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 17126 //MMEA2_GMI_WR_CLI2GRP_MAP1 17127 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 17128 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 17129 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 17130 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 17131 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 17132 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 17133 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 17134 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 17135 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 17136 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 17137 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 17138 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 17139 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 17140 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 17141 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 17142 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 17143 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 17144 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 17145 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 17146 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 17147 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 17148 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 17149 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 17150 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 17151 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 17152 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 17153 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 17154 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 17155 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 17156 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 17157 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 17158 #define MMEA2_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 17159 //MMEA2_GMI_RD_GRP2VC_MAP 17160 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 17161 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 17162 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 17163 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 17164 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 17165 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 17166 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 17167 #define MMEA2_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 17168 //MMEA2_GMI_WR_GRP2VC_MAP 17169 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 17170 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 17171 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 17172 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 17173 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 17174 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 17175 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 17176 #define MMEA2_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 17177 //MMEA2_GMI_RD_LAZY 17178 #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 17179 #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 17180 #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 17181 #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 17182 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 17183 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 17184 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 17185 #define MMEA2_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 17186 #define MMEA2_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 17187 #define MMEA2_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 17188 #define MMEA2_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 17189 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 17190 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 17191 #define MMEA2_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 17192 //MMEA2_GMI_WR_LAZY 17193 #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 17194 #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 17195 #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 17196 #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 17197 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 17198 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 17199 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 17200 #define MMEA2_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 17201 #define MMEA2_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 17202 #define MMEA2_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 17203 #define MMEA2_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 17204 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 17205 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 17206 #define MMEA2_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 17207 //MMEA2_GMI_RD_CAM_CNTL 17208 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 17209 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 17210 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 17211 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 17212 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 17213 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 17214 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 17215 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 17216 #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 17217 #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 17218 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 17219 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 17220 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 17221 #define MMEA2_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 17222 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 17223 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 17224 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 17225 #define MMEA2_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 17226 #define MMEA2_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 17227 #define MMEA2_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 17228 //MMEA2_GMI_WR_CAM_CNTL 17229 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 17230 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 17231 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 17232 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 17233 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 17234 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 17235 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 17236 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 17237 #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 17238 #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 17239 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 17240 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 17241 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 17242 #define MMEA2_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 17243 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 17244 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 17245 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 17246 #define MMEA2_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 17247 #define MMEA2_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 17248 #define MMEA2_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 17249 //MMEA2_GMI_PAGE_BURST 17250 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 17251 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 17252 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 17253 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 17254 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 17255 #define MMEA2_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 17256 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 17257 #define MMEA2_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 17258 //MMEA2_GMI_RD_PRI_AGE 17259 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 17260 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 17261 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 17262 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 17263 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 17264 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 17265 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 17266 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 17267 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 17268 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 17269 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 17270 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 17271 #define MMEA2_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 17272 #define MMEA2_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 17273 #define MMEA2_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 17274 #define MMEA2_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 17275 //MMEA2_GMI_WR_PRI_AGE 17276 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 17277 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 17278 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 17279 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 17280 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 17281 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 17282 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 17283 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 17284 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 17285 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 17286 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 17287 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 17288 #define MMEA2_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 17289 #define MMEA2_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 17290 #define MMEA2_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 17291 #define MMEA2_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 17292 //MMEA2_GMI_RD_PRI_QUEUING 17293 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 17294 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 17295 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 17296 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 17297 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 17298 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 17299 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 17300 #define MMEA2_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 17301 //MMEA2_GMI_WR_PRI_QUEUING 17302 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 17303 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 17304 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 17305 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 17306 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 17307 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 17308 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 17309 #define MMEA2_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 17310 //MMEA2_GMI_RD_PRI_FIXED 17311 #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 17312 #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 17313 #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 17314 #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 17315 #define MMEA2_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 17316 #define MMEA2_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 17317 #define MMEA2_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 17318 #define MMEA2_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 17319 //MMEA2_GMI_WR_PRI_FIXED 17320 #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 17321 #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 17322 #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 17323 #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 17324 #define MMEA2_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 17325 #define MMEA2_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 17326 #define MMEA2_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 17327 #define MMEA2_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 17328 //MMEA2_GMI_RD_PRI_URGENCY 17329 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 17330 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 17331 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 17332 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 17333 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 17334 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 17335 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 17336 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 17337 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 17338 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 17339 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 17340 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 17341 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 17342 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 17343 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 17344 #define MMEA2_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 17345 //MMEA2_GMI_WR_PRI_URGENCY 17346 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 17347 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 17348 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 17349 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 17350 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 17351 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 17352 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 17353 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 17354 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 17355 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 17356 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 17357 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 17358 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 17359 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 17360 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 17361 #define MMEA2_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 17362 //MMEA2_GMI_RD_PRI_URGENCY_MASKING 17363 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 17364 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 17365 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 17366 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 17367 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 17368 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 17369 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 17370 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 17371 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 17372 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 17373 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 17374 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 17375 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 17376 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 17377 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 17378 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 17379 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 17380 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 17381 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 17382 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 17383 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 17384 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 17385 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 17386 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 17387 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 17388 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 17389 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 17390 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 17391 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 17392 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 17393 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 17394 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 17395 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 17396 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 17397 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 17398 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 17399 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 17400 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 17401 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 17402 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 17403 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 17404 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 17405 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 17406 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 17407 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 17408 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 17409 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 17410 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 17411 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 17412 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 17413 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 17414 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 17415 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 17416 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 17417 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 17418 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 17419 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 17420 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 17421 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 17422 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 17423 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 17424 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 17425 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 17426 #define MMEA2_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 17427 //MMEA2_GMI_WR_PRI_URGENCY_MASKING 17428 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 17429 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 17430 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 17431 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 17432 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 17433 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 17434 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 17435 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 17436 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 17437 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 17438 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 17439 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 17440 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 17441 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 17442 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 17443 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 17444 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 17445 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 17446 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 17447 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 17448 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 17449 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 17450 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 17451 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 17452 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 17453 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 17454 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 17455 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 17456 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 17457 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 17458 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 17459 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 17460 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 17461 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 17462 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 17463 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 17464 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 17465 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 17466 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 17467 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 17468 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 17469 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 17470 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 17471 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 17472 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 17473 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 17474 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 17475 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 17476 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 17477 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 17478 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 17479 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 17480 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 17481 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 17482 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 17483 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 17484 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 17485 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 17486 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 17487 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 17488 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 17489 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 17490 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 17491 #define MMEA2_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 17492 //MMEA2_GMI_RD_PRI_QUANT_PRI1 17493 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 17494 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 17495 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 17496 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 17497 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 17498 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 17499 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 17500 #define MMEA2_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 17501 //MMEA2_GMI_RD_PRI_QUANT_PRI2 17502 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 17503 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 17504 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 17505 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 17506 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 17507 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 17508 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 17509 #define MMEA2_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 17510 //MMEA2_GMI_RD_PRI_QUANT_PRI3 17511 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 17512 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 17513 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 17514 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 17515 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 17516 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 17517 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 17518 #define MMEA2_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 17519 //MMEA2_GMI_WR_PRI_QUANT_PRI1 17520 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 17521 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 17522 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 17523 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 17524 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 17525 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 17526 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 17527 #define MMEA2_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 17528 //MMEA2_GMI_WR_PRI_QUANT_PRI2 17529 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 17530 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 17531 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 17532 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 17533 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 17534 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 17535 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 17536 #define MMEA2_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 17537 //MMEA2_GMI_WR_PRI_QUANT_PRI3 17538 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 17539 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 17540 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 17541 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 17542 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 17543 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 17544 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 17545 #define MMEA2_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 17546 //MMEA2_ADDRNORM_BASE_ADDR0 17547 #define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 17548 #define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 17549 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 17550 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 17551 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 17552 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 17553 #define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 17554 #define MMEA2_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 17555 #define MMEA2_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 17556 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 17557 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 17558 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 17559 #define MMEA2_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 17560 #define MMEA2_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 17561 //MMEA2_ADDRNORM_LIMIT_ADDR0 17562 #define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 17563 #define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 17564 #define MMEA2_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 17565 #define MMEA2_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 17566 //MMEA2_ADDRNORM_BASE_ADDR1 17567 #define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 17568 #define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 17569 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 17570 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 17571 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 17572 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 17573 #define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 17574 #define MMEA2_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 17575 #define MMEA2_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 17576 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 17577 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 17578 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 17579 #define MMEA2_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 17580 #define MMEA2_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 17581 //MMEA2_ADDRNORM_LIMIT_ADDR1 17582 #define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 17583 #define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 17584 #define MMEA2_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 17585 #define MMEA2_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 17586 //MMEA2_ADDRNORM_OFFSET_ADDR1 17587 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 17588 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc 17589 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 17590 #define MMEA2_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L 17591 //MMEA2_ADDRNORM_BASE_ADDR2 17592 #define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 17593 #define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 17594 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 17595 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 17596 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 17597 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 17598 #define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 17599 #define MMEA2_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 17600 #define MMEA2_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 17601 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL 17602 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L 17603 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 17604 #define MMEA2_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 17605 #define MMEA2_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 17606 //MMEA2_ADDRNORM_LIMIT_ADDR2 17607 #define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 17608 #define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 17609 #define MMEA2_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 17610 #define MMEA2_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 17611 //MMEA2_ADDRNORM_BASE_ADDR3 17612 #define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 17613 #define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 17614 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 17615 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 17616 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 17617 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 17618 #define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 17619 #define MMEA2_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 17620 #define MMEA2_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 17621 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL 17622 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L 17623 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 17624 #define MMEA2_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 17625 #define MMEA2_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 17626 //MMEA2_ADDRNORM_LIMIT_ADDR3 17627 #define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 17628 #define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 17629 #define MMEA2_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 17630 #define MMEA2_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 17631 //MMEA2_ADDRNORM_OFFSET_ADDR3 17632 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 17633 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc 17634 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 17635 #define MMEA2_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L 17636 //MMEA2_ADDRNORM_MEGABASE_ADDR0 17637 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 17638 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 17639 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 17640 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 17641 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 17642 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 17643 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc 17644 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 17645 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 17646 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 17647 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 17648 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 17649 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 17650 #define MMEA2_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 17651 //MMEA2_ADDRNORM_MEGALIMIT_ADDR0 17652 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 17653 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 17654 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 17655 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 17656 //MMEA2_ADDRNORM_MEGABASE_ADDR1 17657 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 17658 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 17659 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 17660 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 17661 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 17662 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 17663 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc 17664 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 17665 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 17666 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 17667 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 17668 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 17669 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 17670 #define MMEA2_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 17671 //MMEA2_ADDRNORM_MEGALIMIT_ADDR1 17672 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 17673 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 17674 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 17675 #define MMEA2_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 17676 //MMEA2_ADDRNORMDRAM_HOLE_CNTL 17677 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 17678 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 17679 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 17680 #define MMEA2_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 17681 //MMEA2_ADDRNORMGMI_HOLE_CNTL 17682 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 17683 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 17684 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 17685 #define MMEA2_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 17686 //MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG 17687 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 17688 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 17689 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 17690 #define MMEA2_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 17691 //MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG 17692 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 17693 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 17694 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 17695 #define MMEA2_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 17696 //MMEA2_ADDRDEC_BANK_CFG 17697 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 17698 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 17699 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 17700 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 17701 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 17702 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 17703 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 17704 #define MMEA2_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 17705 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 17706 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 17707 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 17708 #define MMEA2_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 17709 //MMEA2_ADDRDEC_MISC_CFG 17710 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 17711 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 17712 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 17713 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 17714 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 17715 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 17716 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 17717 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 17718 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 17719 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 17720 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 17721 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 17722 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 17723 #define MMEA2_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 17724 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 17725 #define MMEA2_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 17726 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 17727 #define MMEA2_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 17728 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 17729 #define MMEA2_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 17730 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 17731 #define MMEA2_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 17732 //MMEA2_ADDRDECDRAM_HARVEST_ENABLE 17733 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 17734 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 17735 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 17736 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 17737 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 17738 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 17739 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 17740 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 17741 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 17742 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 17743 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 17744 #define MMEA2_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 17745 //MMEA2_ADDRDECGMI_HARVEST_ENABLE 17746 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 17747 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 17748 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 17749 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 17750 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 17751 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 17752 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 17753 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 17754 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 17755 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 17756 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 17757 #define MMEA2_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 17758 //MMEA2_ADDRDEC0_BASE_ADDR_CS0 17759 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 17760 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 17761 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 17762 #define MMEA2_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 17763 //MMEA2_ADDRDEC0_BASE_ADDR_CS1 17764 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 17765 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 17766 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 17767 #define MMEA2_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 17768 //MMEA2_ADDRDEC0_BASE_ADDR_CS2 17769 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 17770 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 17771 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 17772 #define MMEA2_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 17773 //MMEA2_ADDRDEC0_BASE_ADDR_CS3 17774 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 17775 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 17776 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 17777 #define MMEA2_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 17778 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS0 17779 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 17780 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 17781 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 17782 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 17783 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS1 17784 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 17785 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 17786 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 17787 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 17788 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS2 17789 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 17790 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 17791 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 17792 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 17793 //MMEA2_ADDRDEC0_BASE_ADDR_SECCS3 17794 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 17795 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 17796 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 17797 #define MMEA2_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 17798 //MMEA2_ADDRDEC0_ADDR_MASK_CS01 17799 #define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 17800 #define MMEA2_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 17801 //MMEA2_ADDRDEC0_ADDR_MASK_CS23 17802 #define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 17803 #define MMEA2_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 17804 //MMEA2_ADDRDEC0_ADDR_MASK_SECCS01 17805 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 17806 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 17807 //MMEA2_ADDRDEC0_ADDR_MASK_SECCS23 17808 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 17809 #define MMEA2_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 17810 //MMEA2_ADDRDEC0_ADDR_CFG_CS01 17811 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 17812 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 17813 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 17814 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 17815 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 17816 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 17817 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 17818 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 17819 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 17820 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 17821 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 17822 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 17823 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 17824 #define MMEA2_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 17825 //MMEA2_ADDRDEC0_ADDR_CFG_CS23 17826 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 17827 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 17828 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 17829 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 17830 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 17831 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 17832 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 17833 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 17834 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 17835 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 17836 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 17837 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 17838 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 17839 #define MMEA2_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 17840 //MMEA2_ADDRDEC0_ADDR_SEL_CS01 17841 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 17842 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 17843 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 17844 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 17845 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 17846 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 17847 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 17848 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 17849 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 17850 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 17851 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 17852 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 17853 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 17854 #define MMEA2_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 17855 //MMEA2_ADDRDEC0_ADDR_SEL_CS23 17856 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 17857 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 17858 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 17859 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 17860 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 17861 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 17862 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 17863 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 17864 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 17865 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 17866 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 17867 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 17868 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 17869 #define MMEA2_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 17870 //MMEA2_ADDRDEC0_ADDR_SEL2_CS01 17871 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 17872 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 17873 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 17874 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 17875 //MMEA2_ADDRDEC0_ADDR_SEL2_CS23 17876 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 17877 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 17878 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 17879 #define MMEA2_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 17880 //MMEA2_ADDRDEC0_COL_SEL_LO_CS01 17881 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 17882 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 17883 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 17884 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 17885 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 17886 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 17887 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 17888 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 17889 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 17890 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 17891 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 17892 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 17893 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 17894 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 17895 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 17896 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 17897 //MMEA2_ADDRDEC0_COL_SEL_LO_CS23 17898 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 17899 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 17900 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 17901 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 17902 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 17903 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 17904 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 17905 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 17906 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 17907 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 17908 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 17909 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 17910 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 17911 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 17912 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 17913 #define MMEA2_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 17914 //MMEA2_ADDRDEC0_COL_SEL_HI_CS01 17915 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 17916 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 17917 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 17918 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 17919 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 17920 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 17921 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 17922 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 17923 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 17924 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 17925 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 17926 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 17927 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 17928 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 17929 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 17930 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 17931 //MMEA2_ADDRDEC0_COL_SEL_HI_CS23 17932 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 17933 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 17934 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 17935 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 17936 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 17937 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 17938 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 17939 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 17940 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 17941 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 17942 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 17943 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 17944 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 17945 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 17946 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 17947 #define MMEA2_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 17948 //MMEA2_ADDRDEC0_RM_SEL_CS01 17949 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 17950 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 17951 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 17952 #define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 17953 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 17954 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 17955 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 17956 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 17957 #define MMEA2_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 17958 #define MMEA2_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 17959 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 17960 #define MMEA2_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 17961 //MMEA2_ADDRDEC0_RM_SEL_CS23 17962 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 17963 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 17964 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 17965 #define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 17966 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 17967 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 17968 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 17969 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 17970 #define MMEA2_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 17971 #define MMEA2_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 17972 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 17973 #define MMEA2_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 17974 //MMEA2_ADDRDEC0_RM_SEL_SECCS01 17975 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 17976 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 17977 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 17978 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 17979 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 17980 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 17981 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 17982 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 17983 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 17984 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 17985 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 17986 #define MMEA2_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 17987 //MMEA2_ADDRDEC0_RM_SEL_SECCS23 17988 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 17989 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 17990 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 17991 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 17992 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 17993 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 17994 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 17995 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 17996 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 17997 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 17998 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 17999 #define MMEA2_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18000 //MMEA2_ADDRDEC1_BASE_ADDR_CS0 18001 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 18002 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 18003 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 18004 #define MMEA2_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 18005 //MMEA2_ADDRDEC1_BASE_ADDR_CS1 18006 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 18007 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 18008 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 18009 #define MMEA2_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 18010 //MMEA2_ADDRDEC1_BASE_ADDR_CS2 18011 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 18012 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 18013 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 18014 #define MMEA2_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 18015 //MMEA2_ADDRDEC1_BASE_ADDR_CS3 18016 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 18017 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 18018 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 18019 #define MMEA2_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 18020 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS0 18021 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 18022 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 18023 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 18024 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 18025 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS1 18026 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 18027 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 18028 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 18029 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 18030 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS2 18031 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 18032 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 18033 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 18034 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 18035 //MMEA2_ADDRDEC1_BASE_ADDR_SECCS3 18036 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 18037 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 18038 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 18039 #define MMEA2_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 18040 //MMEA2_ADDRDEC1_ADDR_MASK_CS01 18041 #define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 18042 #define MMEA2_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 18043 //MMEA2_ADDRDEC1_ADDR_MASK_CS23 18044 #define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 18045 #define MMEA2_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 18046 //MMEA2_ADDRDEC1_ADDR_MASK_SECCS01 18047 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 18048 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 18049 //MMEA2_ADDRDEC1_ADDR_MASK_SECCS23 18050 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 18051 #define MMEA2_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 18052 //MMEA2_ADDRDEC1_ADDR_CFG_CS01 18053 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 18054 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 18055 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 18056 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 18057 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 18058 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 18059 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 18060 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 18061 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 18062 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 18063 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 18064 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 18065 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 18066 #define MMEA2_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 18067 //MMEA2_ADDRDEC1_ADDR_CFG_CS23 18068 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 18069 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 18070 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 18071 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 18072 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 18073 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 18074 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 18075 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 18076 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 18077 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 18078 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 18079 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 18080 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 18081 #define MMEA2_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 18082 //MMEA2_ADDRDEC1_ADDR_SEL_CS01 18083 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 18084 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 18085 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 18086 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 18087 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 18088 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 18089 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 18090 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 18091 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 18092 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 18093 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 18094 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 18095 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 18096 #define MMEA2_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 18097 //MMEA2_ADDRDEC1_ADDR_SEL_CS23 18098 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 18099 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 18100 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 18101 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 18102 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 18103 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 18104 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 18105 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 18106 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 18107 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 18108 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 18109 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 18110 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 18111 #define MMEA2_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 18112 //MMEA2_ADDRDEC1_ADDR_SEL2_CS01 18113 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 18114 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 18115 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 18116 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 18117 //MMEA2_ADDRDEC1_ADDR_SEL2_CS23 18118 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 18119 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 18120 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 18121 #define MMEA2_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 18122 //MMEA2_ADDRDEC1_COL_SEL_LO_CS01 18123 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 18124 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 18125 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 18126 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 18127 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 18128 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 18129 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 18130 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 18131 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 18132 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 18133 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 18134 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 18135 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 18136 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 18137 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 18138 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 18139 //MMEA2_ADDRDEC1_COL_SEL_LO_CS23 18140 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 18141 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 18142 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 18143 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 18144 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 18145 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 18146 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 18147 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 18148 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 18149 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 18150 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 18151 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 18152 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 18153 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 18154 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 18155 #define MMEA2_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 18156 //MMEA2_ADDRDEC1_COL_SEL_HI_CS01 18157 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 18158 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 18159 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 18160 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 18161 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 18162 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 18163 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 18164 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 18165 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 18166 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 18167 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 18168 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 18169 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 18170 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 18171 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 18172 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 18173 //MMEA2_ADDRDEC1_COL_SEL_HI_CS23 18174 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 18175 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 18176 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 18177 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 18178 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 18179 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 18180 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 18181 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 18182 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 18183 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 18184 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 18185 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 18186 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 18187 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 18188 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 18189 #define MMEA2_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 18190 //MMEA2_ADDRDEC1_RM_SEL_CS01 18191 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 18192 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 18193 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 18194 #define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 18195 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18196 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18197 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 18198 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 18199 #define MMEA2_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 18200 #define MMEA2_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 18201 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18202 #define MMEA2_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18203 //MMEA2_ADDRDEC1_RM_SEL_CS23 18204 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 18205 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 18206 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 18207 #define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 18208 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18209 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18210 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 18211 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 18212 #define MMEA2_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 18213 #define MMEA2_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 18214 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18215 #define MMEA2_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18216 //MMEA2_ADDRDEC1_RM_SEL_SECCS01 18217 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 18218 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 18219 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 18220 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 18221 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18222 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18223 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 18224 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 18225 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 18226 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 18227 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18228 #define MMEA2_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18229 //MMEA2_ADDRDEC1_RM_SEL_SECCS23 18230 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 18231 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 18232 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 18233 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 18234 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18235 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18236 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 18237 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 18238 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 18239 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 18240 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18241 #define MMEA2_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18242 //MMEA2_ADDRDEC2_BASE_ADDR_CS0 18243 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 18244 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 18245 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 18246 #define MMEA2_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 18247 //MMEA2_ADDRDEC2_BASE_ADDR_CS1 18248 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 18249 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 18250 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 18251 #define MMEA2_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 18252 //MMEA2_ADDRDEC2_BASE_ADDR_CS2 18253 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 18254 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 18255 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 18256 #define MMEA2_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 18257 //MMEA2_ADDRDEC2_BASE_ADDR_CS3 18258 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 18259 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 18260 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 18261 #define MMEA2_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 18262 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS0 18263 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 18264 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 18265 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 18266 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 18267 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS1 18268 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 18269 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 18270 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 18271 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 18272 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS2 18273 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 18274 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 18275 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 18276 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 18277 //MMEA2_ADDRDEC2_BASE_ADDR_SECCS3 18278 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 18279 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 18280 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 18281 #define MMEA2_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 18282 //MMEA2_ADDRDEC2_ADDR_MASK_CS01 18283 #define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 18284 #define MMEA2_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 18285 //MMEA2_ADDRDEC2_ADDR_MASK_CS23 18286 #define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 18287 #define MMEA2_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 18288 //MMEA2_ADDRDEC2_ADDR_MASK_SECCS01 18289 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 18290 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 18291 //MMEA2_ADDRDEC2_ADDR_MASK_SECCS23 18292 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 18293 #define MMEA2_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 18294 //MMEA2_ADDRDEC2_ADDR_CFG_CS01 18295 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 18296 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 18297 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 18298 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 18299 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 18300 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 18301 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 18302 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 18303 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 18304 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 18305 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 18306 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 18307 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 18308 #define MMEA2_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 18309 //MMEA2_ADDRDEC2_ADDR_CFG_CS23 18310 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 18311 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 18312 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 18313 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 18314 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 18315 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 18316 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 18317 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 18318 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 18319 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 18320 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 18321 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 18322 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 18323 #define MMEA2_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 18324 //MMEA2_ADDRDEC2_ADDR_SEL_CS01 18325 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 18326 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 18327 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 18328 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 18329 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 18330 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 18331 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 18332 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 18333 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 18334 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 18335 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 18336 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 18337 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 18338 #define MMEA2_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 18339 //MMEA2_ADDRDEC2_ADDR_SEL_CS23 18340 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 18341 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 18342 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 18343 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 18344 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 18345 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 18346 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 18347 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 18348 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 18349 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 18350 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 18351 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 18352 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 18353 #define MMEA2_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 18354 //MMEA2_ADDRDEC2_ADDR_SEL2_CS01 18355 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 18356 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 18357 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 18358 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 18359 //MMEA2_ADDRDEC2_ADDR_SEL2_CS23 18360 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 18361 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 18362 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 18363 #define MMEA2_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 18364 //MMEA2_ADDRDEC2_COL_SEL_LO_CS01 18365 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 18366 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 18367 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 18368 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 18369 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 18370 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 18371 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 18372 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 18373 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 18374 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 18375 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 18376 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 18377 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 18378 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 18379 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 18380 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 18381 //MMEA2_ADDRDEC2_COL_SEL_LO_CS23 18382 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 18383 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 18384 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 18385 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 18386 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 18387 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 18388 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 18389 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 18390 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 18391 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 18392 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 18393 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 18394 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 18395 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 18396 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 18397 #define MMEA2_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 18398 //MMEA2_ADDRDEC2_COL_SEL_HI_CS01 18399 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 18400 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 18401 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 18402 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 18403 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 18404 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 18405 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 18406 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 18407 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 18408 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 18409 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 18410 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 18411 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 18412 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 18413 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 18414 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 18415 //MMEA2_ADDRDEC2_COL_SEL_HI_CS23 18416 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 18417 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 18418 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 18419 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 18420 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 18421 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 18422 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 18423 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 18424 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 18425 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 18426 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 18427 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 18428 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 18429 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 18430 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 18431 #define MMEA2_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 18432 //MMEA2_ADDRDEC2_RM_SEL_CS01 18433 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 18434 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 18435 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 18436 #define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 18437 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18438 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18439 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 18440 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 18441 #define MMEA2_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 18442 #define MMEA2_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 18443 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18444 #define MMEA2_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18445 //MMEA2_ADDRDEC2_RM_SEL_CS23 18446 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 18447 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 18448 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 18449 #define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 18450 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18451 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18452 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 18453 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 18454 #define MMEA2_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 18455 #define MMEA2_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 18456 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18457 #define MMEA2_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18458 //MMEA2_ADDRDEC2_RM_SEL_SECCS01 18459 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 18460 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 18461 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 18462 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 18463 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18464 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18465 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 18466 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 18467 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 18468 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 18469 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18470 #define MMEA2_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18471 //MMEA2_ADDRDEC2_RM_SEL_SECCS23 18472 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 18473 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 18474 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 18475 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 18476 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 18477 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 18478 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 18479 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 18480 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 18481 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 18482 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 18483 #define MMEA2_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 18484 //MMEA2_ADDRNORMDRAM_GLOBAL_CNTL 18485 //MMEA2_ADDRNORMGMI_GLOBAL_CNTL 18486 //MMEA2_ADDRNORM_MEGACONTROL_ADDR0 18487 #define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 18488 #define MMEA2_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 18489 //MMEA2_ADDRNORM_MEGACONTROL_ADDR1 18490 #define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 18491 #define MMEA2_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 18492 //MMEA2_ADDRNORMDRAM_MASKING 18493 #define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 18494 #define MMEA2_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 18495 //MMEA2_ADDRNORMGMI_MASKING 18496 #define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 18497 #define MMEA2_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 18498 //MMEA2_IO_RD_CLI2GRP_MAP0 18499 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 18500 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 18501 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 18502 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 18503 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 18504 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 18505 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 18506 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 18507 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 18508 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 18509 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 18510 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 18511 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 18512 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 18513 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 18514 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 18515 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 18516 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 18517 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 18518 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 18519 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 18520 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 18521 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 18522 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 18523 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 18524 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 18525 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 18526 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 18527 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 18528 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 18529 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 18530 #define MMEA2_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 18531 //MMEA2_IO_RD_CLI2GRP_MAP1 18532 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 18533 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 18534 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 18535 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 18536 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 18537 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 18538 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 18539 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 18540 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 18541 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 18542 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 18543 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 18544 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 18545 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 18546 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 18547 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 18548 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 18549 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 18550 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 18551 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 18552 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 18553 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 18554 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 18555 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 18556 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 18557 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 18558 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 18559 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 18560 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 18561 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 18562 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 18563 #define MMEA2_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 18564 //MMEA2_IO_WR_CLI2GRP_MAP0 18565 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 18566 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 18567 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 18568 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 18569 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 18570 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 18571 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 18572 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 18573 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 18574 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 18575 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 18576 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 18577 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 18578 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 18579 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 18580 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 18581 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 18582 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 18583 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 18584 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 18585 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 18586 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 18587 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 18588 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 18589 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 18590 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 18591 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 18592 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 18593 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 18594 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 18595 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 18596 #define MMEA2_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 18597 //MMEA2_IO_WR_CLI2GRP_MAP1 18598 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 18599 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 18600 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 18601 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 18602 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 18603 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 18604 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 18605 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 18606 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 18607 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 18608 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 18609 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 18610 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 18611 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 18612 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 18613 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 18614 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 18615 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 18616 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 18617 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 18618 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 18619 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 18620 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 18621 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 18622 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 18623 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 18624 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 18625 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 18626 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 18627 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 18628 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 18629 #define MMEA2_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 18630 //MMEA2_IO_RD_COMBINE_FLUSH 18631 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 18632 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 18633 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 18634 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 18635 #define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 18636 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 18637 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 18638 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 18639 #define MMEA2_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 18640 #define MMEA2_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 18641 //MMEA2_IO_WR_COMBINE_FLUSH 18642 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 18643 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 18644 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 18645 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 18646 #define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 18647 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 18648 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 18649 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 18650 #define MMEA2_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 18651 #define MMEA2_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 18652 //MMEA2_IO_GROUP_BURST 18653 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 18654 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 18655 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 18656 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 18657 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 18658 #define MMEA2_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 18659 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 18660 #define MMEA2_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 18661 //MMEA2_IO_RD_PRI_AGE 18662 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 18663 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 18664 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 18665 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 18666 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 18667 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 18668 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 18669 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 18670 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 18671 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 18672 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 18673 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 18674 #define MMEA2_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 18675 #define MMEA2_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 18676 #define MMEA2_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 18677 #define MMEA2_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 18678 //MMEA2_IO_WR_PRI_AGE 18679 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 18680 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 18681 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 18682 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 18683 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 18684 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 18685 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 18686 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 18687 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 18688 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 18689 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 18690 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 18691 #define MMEA2_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 18692 #define MMEA2_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 18693 #define MMEA2_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 18694 #define MMEA2_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 18695 //MMEA2_IO_RD_PRI_QUEUING 18696 #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 18697 #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 18698 #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 18699 #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 18700 #define MMEA2_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 18701 #define MMEA2_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 18702 #define MMEA2_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 18703 #define MMEA2_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 18704 //MMEA2_IO_WR_PRI_QUEUING 18705 #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 18706 #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 18707 #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 18708 #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 18709 #define MMEA2_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 18710 #define MMEA2_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 18711 #define MMEA2_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 18712 #define MMEA2_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 18713 //MMEA2_IO_RD_PRI_FIXED 18714 #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 18715 #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 18716 #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 18717 #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 18718 #define MMEA2_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 18719 #define MMEA2_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 18720 #define MMEA2_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 18721 #define MMEA2_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 18722 //MMEA2_IO_WR_PRI_FIXED 18723 #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 18724 #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 18725 #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 18726 #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 18727 #define MMEA2_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 18728 #define MMEA2_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 18729 #define MMEA2_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 18730 #define MMEA2_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 18731 //MMEA2_IO_RD_PRI_URGENCY 18732 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 18733 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 18734 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 18735 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 18736 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 18737 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 18738 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 18739 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 18740 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 18741 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 18742 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 18743 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 18744 #define MMEA2_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 18745 #define MMEA2_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 18746 #define MMEA2_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 18747 #define MMEA2_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 18748 //MMEA2_IO_WR_PRI_URGENCY 18749 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 18750 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 18751 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 18752 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 18753 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 18754 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 18755 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 18756 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 18757 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 18758 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 18759 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 18760 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 18761 #define MMEA2_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 18762 #define MMEA2_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 18763 #define MMEA2_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 18764 #define MMEA2_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 18765 //MMEA2_IO_RD_PRI_URGENCY_MASKING 18766 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 18767 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 18768 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 18769 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 18770 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 18771 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 18772 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 18773 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 18774 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 18775 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 18776 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 18777 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 18778 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 18779 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 18780 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 18781 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 18782 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 18783 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 18784 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 18785 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 18786 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 18787 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 18788 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 18789 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 18790 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 18791 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 18792 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 18793 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 18794 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 18795 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 18796 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 18797 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 18798 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 18799 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 18800 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 18801 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 18802 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 18803 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 18804 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 18805 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 18806 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 18807 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 18808 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 18809 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 18810 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 18811 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 18812 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 18813 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 18814 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 18815 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 18816 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 18817 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 18818 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 18819 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 18820 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 18821 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 18822 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 18823 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 18824 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 18825 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 18826 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 18827 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 18828 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 18829 #define MMEA2_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 18830 //MMEA2_IO_WR_PRI_URGENCY_MASKING 18831 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 18832 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 18833 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 18834 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 18835 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 18836 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 18837 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 18838 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 18839 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 18840 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 18841 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 18842 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 18843 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 18844 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 18845 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 18846 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 18847 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 18848 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 18849 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 18850 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 18851 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 18852 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 18853 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 18854 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 18855 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 18856 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 18857 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 18858 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 18859 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 18860 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 18861 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 18862 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 18863 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 18864 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 18865 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 18866 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 18867 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 18868 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 18869 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 18870 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 18871 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 18872 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 18873 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 18874 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 18875 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 18876 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 18877 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 18878 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 18879 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 18880 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 18881 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 18882 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 18883 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 18884 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 18885 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 18886 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 18887 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 18888 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 18889 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 18890 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 18891 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 18892 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 18893 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 18894 #define MMEA2_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 18895 //MMEA2_IO_RD_PRI_QUANT_PRI1 18896 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 18897 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 18898 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 18899 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 18900 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 18901 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 18902 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 18903 #define MMEA2_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 18904 //MMEA2_IO_RD_PRI_QUANT_PRI2 18905 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 18906 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 18907 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 18908 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 18909 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 18910 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 18911 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 18912 #define MMEA2_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 18913 //MMEA2_IO_RD_PRI_QUANT_PRI3 18914 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 18915 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 18916 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 18917 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 18918 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 18919 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 18920 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 18921 #define MMEA2_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 18922 //MMEA2_IO_WR_PRI_QUANT_PRI1 18923 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 18924 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 18925 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 18926 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 18927 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 18928 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 18929 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 18930 #define MMEA2_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 18931 //MMEA2_IO_WR_PRI_QUANT_PRI2 18932 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 18933 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 18934 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 18935 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 18936 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 18937 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 18938 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 18939 #define MMEA2_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 18940 //MMEA2_IO_WR_PRI_QUANT_PRI3 18941 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 18942 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 18943 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 18944 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 18945 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 18946 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 18947 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 18948 #define MMEA2_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 18949 //MMEA2_SDP_ARB_DRAM 18950 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 18951 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 18952 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 18953 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 18954 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 18955 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 18956 #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 18957 #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 18958 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 18959 #define MMEA2_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 18960 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 18961 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 18962 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 18963 #define MMEA2_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 18964 #define MMEA2_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 18965 #define MMEA2_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 18966 //MMEA2_SDP_ARB_GMI 18967 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 18968 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 18969 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 18970 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 18971 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 18972 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 18973 #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 18974 #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 18975 #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 18976 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 18977 #define MMEA2_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 18978 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 18979 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 18980 #define MMEA2_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 18981 #define MMEA2_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 18982 #define MMEA2_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 18983 #define MMEA2_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 18984 #define MMEA2_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 18985 //MMEA2_SDP_ARB_FINAL 18986 #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 18987 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 18988 #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 18989 #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 18990 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 18991 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 18992 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 18993 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 18994 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 18995 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 18996 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 18997 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 18998 #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 18999 #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 19000 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 19001 #define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c 19002 #define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d 19003 #define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e 19004 #define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f 19005 #define MMEA2_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 19006 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 19007 #define MMEA2_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 19008 #define MMEA2_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 19009 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 19010 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 19011 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 19012 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 19013 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 19014 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 19015 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 19016 #define MMEA2_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 19017 #define MMEA2_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 19018 #define MMEA2_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 19019 #define MMEA2_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 19020 #define MMEA2_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L 19021 #define MMEA2_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L 19022 #define MMEA2_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L 19023 #define MMEA2_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L 19024 //MMEA2_SDP_DRAM_PRIORITY 19025 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 19026 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 19027 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 19028 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 19029 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 19030 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 19031 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 19032 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 19033 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 19034 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 19035 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 19036 #define MMEA2_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 19037 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 19038 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 19039 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 19040 #define MMEA2_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 19041 //MMEA2_SDP_GMI_PRIORITY 19042 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 19043 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 19044 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 19045 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 19046 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 19047 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 19048 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 19049 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 19050 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 19051 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 19052 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 19053 #define MMEA2_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 19054 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 19055 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 19056 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 19057 #define MMEA2_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 19058 //MMEA2_SDP_IO_PRIORITY 19059 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 19060 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 19061 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 19062 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 19063 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 19064 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 19065 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 19066 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 19067 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 19068 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 19069 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 19070 #define MMEA2_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 19071 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 19072 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 19073 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 19074 #define MMEA2_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 19075 //MMEA2_SDP_CREDITS 19076 #define MMEA2_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 19077 #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 19078 #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 19079 #define MMEA2_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 19080 #define MMEA2_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 19081 #define MMEA2_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 19082 //MMEA2_SDP_TAG_RESERVE0 19083 #define MMEA2_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 19084 #define MMEA2_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 19085 #define MMEA2_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 19086 #define MMEA2_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 19087 #define MMEA2_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 19088 #define MMEA2_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 19089 #define MMEA2_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 19090 #define MMEA2_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 19091 //MMEA2_SDP_TAG_RESERVE1 19092 #define MMEA2_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 19093 #define MMEA2_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 19094 #define MMEA2_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 19095 #define MMEA2_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 19096 #define MMEA2_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 19097 #define MMEA2_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 19098 #define MMEA2_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 19099 #define MMEA2_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 19100 //MMEA2_SDP_VCC_RESERVE0 19101 #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 19102 #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 19103 #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 19104 #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 19105 #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 19106 #define MMEA2_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 19107 #define MMEA2_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 19108 #define MMEA2_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 19109 #define MMEA2_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 19110 #define MMEA2_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 19111 //MMEA2_SDP_VCC_RESERVE1 19112 #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 19113 #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 19114 #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 19115 #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 19116 #define MMEA2_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 19117 #define MMEA2_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 19118 #define MMEA2_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 19119 #define MMEA2_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 19120 //MMEA2_SDP_VCD_RESERVE0 19121 #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 19122 #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 19123 #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 19124 #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 19125 #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 19126 #define MMEA2_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 19127 #define MMEA2_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 19128 #define MMEA2_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 19129 #define MMEA2_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 19130 #define MMEA2_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 19131 //MMEA2_SDP_VCD_RESERVE1 19132 #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 19133 #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 19134 #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 19135 #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 19136 #define MMEA2_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 19137 #define MMEA2_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 19138 #define MMEA2_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 19139 #define MMEA2_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 19140 //MMEA2_SDP_REQ_CNTL 19141 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 19142 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 19143 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 19144 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 19145 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 19146 #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 19147 #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 19148 #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 19149 #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 19150 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 19151 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 19152 #define MMEA2_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 19153 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 19154 #define MMEA2_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 19155 #define MMEA2_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 19156 #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 19157 #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 19158 #define MMEA2_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 19159 //MMEA2_MISC 19160 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 19161 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 19162 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 19163 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 19164 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 19165 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 19166 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 19167 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 19168 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 19169 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 19170 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 19171 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 19172 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 19173 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 19174 #define MMEA2_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 19175 #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 19176 #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 19177 #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 19178 #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 19179 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 19180 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 19181 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 19182 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 19183 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 19184 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 19185 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 19186 #define MMEA2_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 19187 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 19188 #define MMEA2_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 19189 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 19190 #define MMEA2_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 19191 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 19192 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 19193 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 19194 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 19195 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 19196 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 19197 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 19198 #define MMEA2_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 19199 #define MMEA2_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 19200 #define MMEA2_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 19201 #define MMEA2_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 19202 #define MMEA2_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 19203 #define MMEA2_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 19204 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 19205 #define MMEA2_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 19206 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 19207 #define MMEA2_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 19208 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 19209 #define MMEA2_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 19210 //MMEA2_LATENCY_SAMPLING 19211 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 19212 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 19213 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 19214 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 19215 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 19216 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 19217 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 19218 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 19219 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 19220 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 19221 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 19222 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 19223 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 19224 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 19225 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 19226 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 19227 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 19228 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 19229 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 19230 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 19231 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 19232 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 19233 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 19234 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 19235 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 19236 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 19237 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 19238 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 19239 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 19240 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 19241 #define MMEA2_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 19242 #define MMEA2_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 19243 //MMEA2_PERFCOUNTER_LO 19244 #define MMEA2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 19245 #define MMEA2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 19246 //MMEA2_PERFCOUNTER_HI 19247 #define MMEA2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 19248 #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 19249 #define MMEA2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 19250 #define MMEA2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 19251 //MMEA2_PERFCOUNTER0_CFG 19252 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 19253 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 19254 #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 19255 #define MMEA2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 19256 #define MMEA2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 19257 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 19258 #define MMEA2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 19259 #define MMEA2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 19260 #define MMEA2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 19261 #define MMEA2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 19262 //MMEA2_PERFCOUNTER1_CFG 19263 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 19264 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 19265 #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 19266 #define MMEA2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 19267 #define MMEA2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 19268 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 19269 #define MMEA2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 19270 #define MMEA2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 19271 #define MMEA2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 19272 #define MMEA2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 19273 //MMEA2_PERFCOUNTER_RSLT_CNTL 19274 #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 19275 #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 19276 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 19277 #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 19278 #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 19279 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 19280 #define MMEA2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 19281 #define MMEA2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 19282 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 19283 #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 19284 #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 19285 #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 19286 //MMEA2_EDC_CNT 19287 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 19288 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 19289 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 19290 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 19291 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 19292 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 19293 #define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 19294 #define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 19295 #define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 19296 #define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 19297 #define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 19298 #define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 19299 #define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 19300 #define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a 19301 #define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c 19302 #define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e 19303 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 19304 #define MMEA2_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 19305 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 19306 #define MMEA2_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 19307 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 19308 #define MMEA2_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 19309 #define MMEA2_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 19310 #define MMEA2_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 19311 #define MMEA2_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 19312 #define MMEA2_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 19313 #define MMEA2_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L 19314 #define MMEA2_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L 19315 #define MMEA2_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L 19316 #define MMEA2_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L 19317 #define MMEA2_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L 19318 #define MMEA2_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L 19319 //MMEA2_EDC_CNT2 19320 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 19321 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 19322 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 19323 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 19324 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 19325 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 19326 #define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 19327 #define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 19328 #define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 19329 #define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 19330 #define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 19331 #define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 19332 #define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 19333 #define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 19334 #define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 19335 #define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 19336 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 19337 #define MMEA2_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 19338 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 19339 #define MMEA2_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 19340 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 19341 #define MMEA2_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 19342 #define MMEA2_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 19343 #define MMEA2_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 19344 #define MMEA2_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 19345 #define MMEA2_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 19346 #define MMEA2_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 19347 #define MMEA2_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 19348 #define MMEA2_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 19349 #define MMEA2_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 19350 #define MMEA2_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 19351 #define MMEA2_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 19352 //MMEA2_DSM_CNTL 19353 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 19354 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 19355 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 19356 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 19357 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 19358 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 19359 #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 19360 #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 19361 #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 19362 #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 19363 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 19364 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 19365 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 19366 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 19367 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 19368 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 19369 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 19370 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 19371 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 19372 #define MMEA2_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 19373 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 19374 #define MMEA2_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 19375 #define MMEA2_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 19376 #define MMEA2_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 19377 #define MMEA2_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 19378 #define MMEA2_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 19379 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 19380 #define MMEA2_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 19381 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 19382 #define MMEA2_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 19383 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 19384 #define MMEA2_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 19385 //MMEA2_DSM_CNTLA 19386 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 19387 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 19388 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 19389 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 19390 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 19391 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 19392 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 19393 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 19394 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 19395 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 19396 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 19397 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 19398 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 19399 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 19400 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 19401 #define MMEA2_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 19402 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 19403 #define MMEA2_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 19404 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 19405 #define MMEA2_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 19406 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 19407 #define MMEA2_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 19408 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 19409 #define MMEA2_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 19410 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 19411 #define MMEA2_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 19412 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 19413 #define MMEA2_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 19414 //MMEA2_DSM_CNTLB 19415 //MMEA2_DSM_CNTL2 19416 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 19417 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 19418 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 19419 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 19420 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 19421 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 19422 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 19423 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 19424 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 19425 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 19426 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 19427 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 19428 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 19429 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 19430 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 19431 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 19432 #define MMEA2_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 19433 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 19434 #define MMEA2_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 19435 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 19436 #define MMEA2_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 19437 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 19438 #define MMEA2_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 19439 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 19440 #define MMEA2_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 19441 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 19442 #define MMEA2_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 19443 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 19444 #define MMEA2_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 19445 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 19446 #define MMEA2_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 19447 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 19448 #define MMEA2_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 19449 #define MMEA2_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 19450 //MMEA2_DSM_CNTL2A 19451 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 19452 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 19453 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 19454 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 19455 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 19456 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 19457 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 19458 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 19459 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 19460 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 19461 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 19462 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 19463 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 19464 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 19465 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 19466 #define MMEA2_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 19467 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 19468 #define MMEA2_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 19469 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 19470 #define MMEA2_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 19471 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 19472 #define MMEA2_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 19473 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 19474 #define MMEA2_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 19475 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 19476 #define MMEA2_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 19477 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 19478 #define MMEA2_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 19479 //MMEA2_DSM_CNTL2B 19480 //MMEA2_CGTT_CLK_CTRL 19481 #define MMEA2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 19482 #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 19483 #define MMEA2_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 19484 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 19485 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 19486 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 19487 #define MMEA2_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 19488 #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 19489 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 19490 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 19491 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 19492 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 19493 #define MMEA2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 19494 #define MMEA2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 19495 #define MMEA2_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 19496 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 19497 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 19498 #define MMEA2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 19499 #define MMEA2_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 19500 #define MMEA2_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 19501 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 19502 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 19503 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 19504 #define MMEA2_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 19505 //MMEA2_EDC_MODE 19506 #define MMEA2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 19507 #define MMEA2_EDC_MODE__GATE_FUE__SHIFT 0x11 19508 #define MMEA2_EDC_MODE__DED_MODE__SHIFT 0x14 19509 #define MMEA2_EDC_MODE__PROP_FED__SHIFT 0x1d 19510 #define MMEA2_EDC_MODE__BYPASS__SHIFT 0x1f 19511 #define MMEA2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 19512 #define MMEA2_EDC_MODE__GATE_FUE_MASK 0x00020000L 19513 #define MMEA2_EDC_MODE__DED_MODE_MASK 0x00300000L 19514 #define MMEA2_EDC_MODE__PROP_FED_MASK 0x20000000L 19515 #define MMEA2_EDC_MODE__BYPASS_MASK 0x80000000L 19516 //MMEA2_ERR_STATUS 19517 #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 19518 #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 19519 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 19520 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 19521 #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 19522 #define MMEA2_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 19523 #define MMEA2_ERR_STATUS__FUE_FLAG__SHIFT 0xd 19524 #define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 19525 #define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 19526 #define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 19527 #define MMEA2_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 19528 #define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 19529 #define MMEA2_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 19530 #define MMEA2_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 19531 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 19532 #define MMEA2_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 19533 #define MMEA2_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 19534 #define MMEA2_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 19535 #define MMEA2_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 19536 #define MMEA2_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 19537 #define MMEA2_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 19538 #define MMEA2_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 19539 #define MMEA2_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 19540 #define MMEA2_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 19541 //MMEA2_MISC2 19542 #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 19543 #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 19544 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 19545 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 19546 #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 19547 #define MMEA2_MISC2__RRET_SWAP_MODE__SHIFT 0xd 19548 #define MMEA2_MISC2__BLOCK_REQUESTS__SHIFT 0xe 19549 #define MMEA2_MISC2__REQUESTS_BLOCKED__SHIFT 0xf 19550 #define MMEA2_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 19551 #define MMEA2_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 19552 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 19553 #define MMEA2_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 19554 #define MMEA2_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 19555 #define MMEA2_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 19556 #define MMEA2_MISC2__BLOCK_REQUESTS_MASK 0x00004000L 19557 #define MMEA2_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L 19558 //MMEA2_ADDRDEC_SELECT 19559 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 19560 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 19561 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 19562 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 19563 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 19564 #define MMEA2_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 19565 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 19566 #define MMEA2_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 19567 //MMEA2_EDC_CNT3 19568 #define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 19569 #define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 19570 #define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 19571 #define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 19572 #define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 19573 #define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa 19574 #define MMEA2_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 19575 #define MMEA2_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 19576 #define MMEA2_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 19577 #define MMEA2_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 19578 #define MMEA2_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L 19579 #define MMEA2_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L 19580 //MMEA2_MISC_AON 19581 #define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 19582 #define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 19583 #define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 19584 #define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 19585 19586 19587 // addressBlock: mmhub_ea_mmeadec3 19588 //MMEA3_DRAM_RD_CLI2GRP_MAP0 19589 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 19590 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 19591 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 19592 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 19593 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 19594 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 19595 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 19596 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 19597 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 19598 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 19599 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 19600 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 19601 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 19602 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 19603 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 19604 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 19605 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 19606 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 19607 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 19608 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 19609 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 19610 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 19611 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 19612 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 19613 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 19614 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 19615 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 19616 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 19617 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 19618 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 19619 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 19620 #define MMEA3_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 19621 //MMEA3_DRAM_RD_CLI2GRP_MAP1 19622 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 19623 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 19624 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 19625 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 19626 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 19627 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 19628 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 19629 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 19630 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 19631 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 19632 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 19633 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 19634 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 19635 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 19636 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 19637 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 19638 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 19639 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 19640 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 19641 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 19642 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 19643 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 19644 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 19645 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 19646 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 19647 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 19648 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 19649 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 19650 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 19651 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 19652 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 19653 #define MMEA3_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 19654 //MMEA3_DRAM_WR_CLI2GRP_MAP0 19655 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 19656 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 19657 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 19658 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 19659 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 19660 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 19661 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 19662 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 19663 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 19664 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 19665 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 19666 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 19667 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 19668 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 19669 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 19670 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 19671 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 19672 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 19673 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 19674 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 19675 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 19676 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 19677 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 19678 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 19679 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 19680 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 19681 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 19682 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 19683 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 19684 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 19685 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 19686 #define MMEA3_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 19687 //MMEA3_DRAM_WR_CLI2GRP_MAP1 19688 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 19689 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 19690 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 19691 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 19692 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 19693 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 19694 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 19695 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 19696 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 19697 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 19698 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 19699 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 19700 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 19701 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 19702 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 19703 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 19704 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 19705 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 19706 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 19707 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 19708 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 19709 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 19710 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 19711 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 19712 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 19713 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 19714 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 19715 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 19716 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 19717 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 19718 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 19719 #define MMEA3_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 19720 //MMEA3_DRAM_RD_GRP2VC_MAP 19721 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 19722 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 19723 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 19724 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 19725 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 19726 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 19727 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 19728 #define MMEA3_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 19729 //MMEA3_DRAM_WR_GRP2VC_MAP 19730 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 19731 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 19732 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 19733 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 19734 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 19735 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 19736 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 19737 #define MMEA3_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 19738 //MMEA3_DRAM_RD_LAZY 19739 #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 19740 #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 19741 #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 19742 #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 19743 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 19744 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 19745 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 19746 #define MMEA3_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 19747 #define MMEA3_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 19748 #define MMEA3_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 19749 #define MMEA3_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 19750 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 19751 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 19752 #define MMEA3_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 19753 //MMEA3_DRAM_WR_LAZY 19754 #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 19755 #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 19756 #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 19757 #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 19758 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 19759 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 19760 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 19761 #define MMEA3_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 19762 #define MMEA3_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 19763 #define MMEA3_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 19764 #define MMEA3_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 19765 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 19766 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 19767 #define MMEA3_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 19768 //MMEA3_DRAM_RD_CAM_CNTL 19769 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 19770 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 19771 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 19772 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 19773 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 19774 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 19775 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 19776 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 19777 #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 19778 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 19779 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 19780 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 19781 #define MMEA3_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 19782 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 19783 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 19784 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 19785 #define MMEA3_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 19786 #define MMEA3_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 19787 //MMEA3_DRAM_WR_CAM_CNTL 19788 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 19789 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 19790 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 19791 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 19792 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 19793 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 19794 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 19795 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 19796 #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 19797 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 19798 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 19799 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 19800 #define MMEA3_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 19801 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 19802 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 19803 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 19804 #define MMEA3_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 19805 #define MMEA3_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 19806 //MMEA3_DRAM_PAGE_BURST 19807 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 19808 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 19809 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 19810 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 19811 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 19812 #define MMEA3_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 19813 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 19814 #define MMEA3_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 19815 //MMEA3_DRAM_RD_PRI_AGE 19816 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 19817 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 19818 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 19819 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 19820 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 19821 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 19822 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 19823 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 19824 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 19825 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 19826 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 19827 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 19828 #define MMEA3_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 19829 #define MMEA3_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 19830 #define MMEA3_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 19831 #define MMEA3_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 19832 //MMEA3_DRAM_WR_PRI_AGE 19833 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 19834 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 19835 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 19836 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 19837 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 19838 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 19839 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 19840 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 19841 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 19842 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 19843 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 19844 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 19845 #define MMEA3_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 19846 #define MMEA3_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 19847 #define MMEA3_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 19848 #define MMEA3_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 19849 //MMEA3_DRAM_RD_PRI_QUEUING 19850 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 19851 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 19852 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 19853 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 19854 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 19855 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 19856 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 19857 #define MMEA3_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 19858 //MMEA3_DRAM_WR_PRI_QUEUING 19859 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 19860 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 19861 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 19862 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 19863 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 19864 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 19865 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 19866 #define MMEA3_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 19867 //MMEA3_DRAM_RD_PRI_FIXED 19868 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 19869 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 19870 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 19871 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 19872 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 19873 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 19874 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 19875 #define MMEA3_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 19876 //MMEA3_DRAM_WR_PRI_FIXED 19877 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 19878 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 19879 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 19880 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 19881 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 19882 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 19883 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 19884 #define MMEA3_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 19885 //MMEA3_DRAM_RD_PRI_URGENCY 19886 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 19887 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 19888 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 19889 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 19890 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 19891 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 19892 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 19893 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 19894 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 19895 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 19896 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 19897 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 19898 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 19899 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 19900 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 19901 #define MMEA3_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 19902 //MMEA3_DRAM_WR_PRI_URGENCY 19903 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 19904 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 19905 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 19906 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 19907 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 19908 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 19909 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 19910 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 19911 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 19912 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 19913 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 19914 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 19915 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 19916 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 19917 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 19918 #define MMEA3_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 19919 //MMEA3_DRAM_RD_PRI_QUANT_PRI1 19920 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 19921 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 19922 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 19923 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 19924 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 19925 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 19926 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 19927 #define MMEA3_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 19928 //MMEA3_DRAM_RD_PRI_QUANT_PRI2 19929 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 19930 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 19931 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 19932 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 19933 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 19934 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 19935 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 19936 #define MMEA3_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 19937 //MMEA3_DRAM_RD_PRI_QUANT_PRI3 19938 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 19939 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 19940 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 19941 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 19942 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 19943 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 19944 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 19945 #define MMEA3_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 19946 //MMEA3_DRAM_WR_PRI_QUANT_PRI1 19947 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 19948 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 19949 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 19950 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 19951 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 19952 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 19953 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 19954 #define MMEA3_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 19955 //MMEA3_DRAM_WR_PRI_QUANT_PRI2 19956 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 19957 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 19958 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 19959 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 19960 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 19961 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 19962 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 19963 #define MMEA3_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 19964 //MMEA3_DRAM_WR_PRI_QUANT_PRI3 19965 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 19966 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 19967 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 19968 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 19969 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 19970 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 19971 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 19972 #define MMEA3_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 19973 //MMEA3_GMI_RD_CLI2GRP_MAP0 19974 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 19975 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 19976 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 19977 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 19978 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 19979 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 19980 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 19981 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 19982 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 19983 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 19984 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 19985 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 19986 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 19987 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 19988 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 19989 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 19990 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 19991 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 19992 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 19993 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 19994 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 19995 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 19996 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 19997 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 19998 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 19999 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 20000 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 20001 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 20002 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 20003 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 20004 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 20005 #define MMEA3_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 20006 //MMEA3_GMI_RD_CLI2GRP_MAP1 20007 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 20008 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 20009 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 20010 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 20011 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 20012 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 20013 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 20014 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 20015 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 20016 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 20017 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 20018 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 20019 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 20020 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 20021 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 20022 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 20023 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 20024 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 20025 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 20026 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 20027 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 20028 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 20029 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 20030 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 20031 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 20032 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 20033 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 20034 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 20035 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 20036 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 20037 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 20038 #define MMEA3_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 20039 //MMEA3_GMI_WR_CLI2GRP_MAP0 20040 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 20041 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 20042 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 20043 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 20044 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 20045 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 20046 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 20047 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 20048 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 20049 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 20050 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 20051 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 20052 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 20053 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 20054 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 20055 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 20056 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 20057 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 20058 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 20059 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 20060 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 20061 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 20062 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 20063 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 20064 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 20065 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 20066 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 20067 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 20068 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 20069 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 20070 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 20071 #define MMEA3_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 20072 //MMEA3_GMI_WR_CLI2GRP_MAP1 20073 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 20074 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 20075 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 20076 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 20077 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 20078 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 20079 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 20080 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 20081 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 20082 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 20083 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 20084 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 20085 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 20086 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 20087 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 20088 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 20089 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 20090 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 20091 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 20092 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 20093 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 20094 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 20095 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 20096 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 20097 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 20098 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 20099 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 20100 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 20101 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 20102 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 20103 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 20104 #define MMEA3_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 20105 //MMEA3_GMI_RD_GRP2VC_MAP 20106 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 20107 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 20108 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 20109 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 20110 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 20111 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 20112 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 20113 #define MMEA3_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 20114 //MMEA3_GMI_WR_GRP2VC_MAP 20115 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 20116 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 20117 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 20118 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 20119 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 20120 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 20121 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 20122 #define MMEA3_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 20123 //MMEA3_GMI_RD_LAZY 20124 #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 20125 #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 20126 #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 20127 #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 20128 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 20129 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 20130 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 20131 #define MMEA3_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 20132 #define MMEA3_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 20133 #define MMEA3_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 20134 #define MMEA3_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 20135 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 20136 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 20137 #define MMEA3_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 20138 //MMEA3_GMI_WR_LAZY 20139 #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 20140 #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 20141 #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 20142 #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 20143 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 20144 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 20145 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 20146 #define MMEA3_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 20147 #define MMEA3_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 20148 #define MMEA3_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 20149 #define MMEA3_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 20150 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 20151 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 20152 #define MMEA3_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 20153 //MMEA3_GMI_RD_CAM_CNTL 20154 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 20155 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 20156 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 20157 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 20158 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 20159 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 20160 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 20161 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 20162 #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 20163 #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 20164 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 20165 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 20166 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 20167 #define MMEA3_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 20168 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 20169 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 20170 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 20171 #define MMEA3_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 20172 #define MMEA3_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 20173 #define MMEA3_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 20174 //MMEA3_GMI_WR_CAM_CNTL 20175 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 20176 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 20177 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 20178 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 20179 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 20180 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 20181 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 20182 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 20183 #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 20184 #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 20185 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 20186 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 20187 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 20188 #define MMEA3_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 20189 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 20190 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 20191 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 20192 #define MMEA3_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 20193 #define MMEA3_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 20194 #define MMEA3_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 20195 //MMEA3_GMI_PAGE_BURST 20196 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 20197 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 20198 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 20199 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 20200 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 20201 #define MMEA3_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 20202 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 20203 #define MMEA3_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 20204 //MMEA3_GMI_RD_PRI_AGE 20205 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 20206 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 20207 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 20208 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 20209 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 20210 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 20211 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 20212 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 20213 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 20214 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 20215 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 20216 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 20217 #define MMEA3_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 20218 #define MMEA3_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 20219 #define MMEA3_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 20220 #define MMEA3_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 20221 //MMEA3_GMI_WR_PRI_AGE 20222 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 20223 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 20224 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 20225 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 20226 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 20227 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 20228 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 20229 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 20230 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 20231 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 20232 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 20233 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 20234 #define MMEA3_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 20235 #define MMEA3_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 20236 #define MMEA3_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 20237 #define MMEA3_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 20238 //MMEA3_GMI_RD_PRI_QUEUING 20239 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 20240 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 20241 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 20242 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 20243 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 20244 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 20245 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 20246 #define MMEA3_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 20247 //MMEA3_GMI_WR_PRI_QUEUING 20248 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 20249 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 20250 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 20251 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 20252 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 20253 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 20254 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 20255 #define MMEA3_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 20256 //MMEA3_GMI_RD_PRI_FIXED 20257 #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 20258 #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 20259 #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 20260 #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 20261 #define MMEA3_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 20262 #define MMEA3_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 20263 #define MMEA3_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 20264 #define MMEA3_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 20265 //MMEA3_GMI_WR_PRI_FIXED 20266 #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 20267 #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 20268 #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 20269 #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 20270 #define MMEA3_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 20271 #define MMEA3_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 20272 #define MMEA3_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 20273 #define MMEA3_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 20274 //MMEA3_GMI_RD_PRI_URGENCY 20275 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 20276 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 20277 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 20278 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 20279 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 20280 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 20281 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 20282 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 20283 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 20284 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 20285 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 20286 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 20287 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 20288 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 20289 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 20290 #define MMEA3_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 20291 //MMEA3_GMI_WR_PRI_URGENCY 20292 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 20293 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 20294 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 20295 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 20296 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 20297 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 20298 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 20299 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 20300 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 20301 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 20302 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 20303 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 20304 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 20305 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 20306 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 20307 #define MMEA3_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 20308 //MMEA3_GMI_RD_PRI_URGENCY_MASKING 20309 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 20310 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 20311 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 20312 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 20313 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 20314 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 20315 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 20316 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 20317 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 20318 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 20319 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 20320 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 20321 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 20322 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 20323 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 20324 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 20325 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 20326 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 20327 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 20328 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 20329 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 20330 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 20331 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 20332 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 20333 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 20334 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 20335 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 20336 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 20337 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 20338 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 20339 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 20340 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 20341 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 20342 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 20343 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 20344 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 20345 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 20346 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 20347 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 20348 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 20349 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 20350 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 20351 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 20352 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 20353 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 20354 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 20355 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 20356 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 20357 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 20358 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 20359 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 20360 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 20361 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 20362 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 20363 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 20364 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 20365 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 20366 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 20367 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 20368 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 20369 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 20370 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 20371 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 20372 #define MMEA3_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 20373 //MMEA3_GMI_WR_PRI_URGENCY_MASKING 20374 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 20375 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 20376 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 20377 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 20378 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 20379 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 20380 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 20381 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 20382 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 20383 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 20384 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 20385 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 20386 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 20387 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 20388 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 20389 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 20390 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 20391 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 20392 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 20393 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 20394 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 20395 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 20396 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 20397 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 20398 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 20399 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 20400 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 20401 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 20402 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 20403 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 20404 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 20405 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 20406 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 20407 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 20408 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 20409 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 20410 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 20411 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 20412 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 20413 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 20414 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 20415 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 20416 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 20417 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 20418 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 20419 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 20420 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 20421 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 20422 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 20423 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 20424 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 20425 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 20426 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 20427 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 20428 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 20429 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 20430 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 20431 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 20432 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 20433 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 20434 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 20435 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 20436 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 20437 #define MMEA3_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 20438 //MMEA3_GMI_RD_PRI_QUANT_PRI1 20439 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 20440 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 20441 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 20442 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 20443 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 20444 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 20445 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 20446 #define MMEA3_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 20447 //MMEA3_GMI_RD_PRI_QUANT_PRI2 20448 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 20449 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 20450 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 20451 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 20452 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 20453 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 20454 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 20455 #define MMEA3_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 20456 //MMEA3_GMI_RD_PRI_QUANT_PRI3 20457 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 20458 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 20459 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 20460 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 20461 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 20462 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 20463 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 20464 #define MMEA3_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 20465 //MMEA3_GMI_WR_PRI_QUANT_PRI1 20466 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 20467 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 20468 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 20469 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 20470 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 20471 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 20472 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 20473 #define MMEA3_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 20474 //MMEA3_GMI_WR_PRI_QUANT_PRI2 20475 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 20476 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 20477 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 20478 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 20479 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 20480 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 20481 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 20482 #define MMEA3_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 20483 //MMEA3_GMI_WR_PRI_QUANT_PRI3 20484 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 20485 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 20486 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 20487 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 20488 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 20489 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 20490 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 20491 #define MMEA3_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 20492 //MMEA3_ADDRNORM_BASE_ADDR0 20493 #define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 20494 #define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 20495 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 20496 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 20497 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 20498 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 20499 #define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 20500 #define MMEA3_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 20501 #define MMEA3_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 20502 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 20503 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 20504 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 20505 #define MMEA3_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 20506 #define MMEA3_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 20507 //MMEA3_ADDRNORM_LIMIT_ADDR0 20508 #define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 20509 #define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 20510 #define MMEA3_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 20511 #define MMEA3_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 20512 //MMEA3_ADDRNORM_BASE_ADDR1 20513 #define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 20514 #define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 20515 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 20516 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 20517 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 20518 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 20519 #define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 20520 #define MMEA3_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 20521 #define MMEA3_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 20522 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 20523 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 20524 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 20525 #define MMEA3_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 20526 #define MMEA3_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 20527 //MMEA3_ADDRNORM_LIMIT_ADDR1 20528 #define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 20529 #define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 20530 #define MMEA3_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 20531 #define MMEA3_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 20532 //MMEA3_ADDRNORM_OFFSET_ADDR1 20533 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 20534 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc 20535 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 20536 #define MMEA3_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L 20537 //MMEA3_ADDRNORM_BASE_ADDR2 20538 #define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 20539 #define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 20540 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 20541 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 20542 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 20543 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 20544 #define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 20545 #define MMEA3_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 20546 #define MMEA3_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 20547 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL 20548 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L 20549 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 20550 #define MMEA3_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 20551 #define MMEA3_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 20552 //MMEA3_ADDRNORM_LIMIT_ADDR2 20553 #define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 20554 #define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 20555 #define MMEA3_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 20556 #define MMEA3_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 20557 //MMEA3_ADDRNORM_BASE_ADDR3 20558 #define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 20559 #define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 20560 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 20561 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 20562 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 20563 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 20564 #define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 20565 #define MMEA3_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 20566 #define MMEA3_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 20567 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL 20568 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L 20569 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 20570 #define MMEA3_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 20571 #define MMEA3_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 20572 //MMEA3_ADDRNORM_LIMIT_ADDR3 20573 #define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 20574 #define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 20575 #define MMEA3_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 20576 #define MMEA3_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 20577 //MMEA3_ADDRNORM_OFFSET_ADDR3 20578 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 20579 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc 20580 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 20581 #define MMEA3_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L 20582 //MMEA3_ADDRNORM_MEGABASE_ADDR0 20583 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 20584 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 20585 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 20586 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 20587 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 20588 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 20589 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc 20590 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 20591 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 20592 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 20593 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 20594 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 20595 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 20596 #define MMEA3_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 20597 //MMEA3_ADDRNORM_MEGALIMIT_ADDR0 20598 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 20599 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 20600 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 20601 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 20602 //MMEA3_ADDRNORM_MEGABASE_ADDR1 20603 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 20604 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 20605 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 20606 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 20607 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 20608 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 20609 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc 20610 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 20611 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 20612 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 20613 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 20614 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 20615 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 20616 #define MMEA3_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 20617 //MMEA3_ADDRNORM_MEGALIMIT_ADDR1 20618 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 20619 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 20620 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 20621 #define MMEA3_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 20622 //MMEA3_ADDRNORMDRAM_HOLE_CNTL 20623 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 20624 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 20625 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 20626 #define MMEA3_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 20627 //MMEA3_ADDRNORMGMI_HOLE_CNTL 20628 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 20629 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 20630 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 20631 #define MMEA3_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 20632 //MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG 20633 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 20634 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 20635 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 20636 #define MMEA3_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 20637 //MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG 20638 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 20639 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 20640 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 20641 #define MMEA3_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 20642 //MMEA3_ADDRDEC_BANK_CFG 20643 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 20644 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 20645 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 20646 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 20647 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 20648 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 20649 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 20650 #define MMEA3_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 20651 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 20652 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 20653 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 20654 #define MMEA3_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 20655 //MMEA3_ADDRDEC_MISC_CFG 20656 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 20657 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 20658 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 20659 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 20660 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 20661 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 20662 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 20663 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 20664 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 20665 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 20666 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 20667 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 20668 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 20669 #define MMEA3_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 20670 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 20671 #define MMEA3_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 20672 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 20673 #define MMEA3_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 20674 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 20675 #define MMEA3_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 20676 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 20677 #define MMEA3_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 20678 //MMEA3_ADDRDECDRAM_HARVEST_ENABLE 20679 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 20680 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 20681 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 20682 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 20683 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 20684 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 20685 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 20686 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 20687 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 20688 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 20689 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 20690 #define MMEA3_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 20691 //MMEA3_ADDRDECGMI_HARVEST_ENABLE 20692 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 20693 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 20694 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 20695 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 20696 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 20697 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 20698 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 20699 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 20700 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 20701 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 20702 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 20703 #define MMEA3_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 20704 //MMEA3_ADDRDEC0_BASE_ADDR_CS0 20705 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 20706 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 20707 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 20708 #define MMEA3_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 20709 //MMEA3_ADDRDEC0_BASE_ADDR_CS1 20710 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 20711 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 20712 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 20713 #define MMEA3_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 20714 //MMEA3_ADDRDEC0_BASE_ADDR_CS2 20715 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 20716 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 20717 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 20718 #define MMEA3_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 20719 //MMEA3_ADDRDEC0_BASE_ADDR_CS3 20720 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 20721 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 20722 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 20723 #define MMEA3_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 20724 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS0 20725 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 20726 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 20727 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 20728 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 20729 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS1 20730 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 20731 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 20732 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 20733 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 20734 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS2 20735 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 20736 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 20737 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 20738 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 20739 //MMEA3_ADDRDEC0_BASE_ADDR_SECCS3 20740 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 20741 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 20742 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 20743 #define MMEA3_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 20744 //MMEA3_ADDRDEC0_ADDR_MASK_CS01 20745 #define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 20746 #define MMEA3_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 20747 //MMEA3_ADDRDEC0_ADDR_MASK_CS23 20748 #define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 20749 #define MMEA3_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 20750 //MMEA3_ADDRDEC0_ADDR_MASK_SECCS01 20751 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 20752 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 20753 //MMEA3_ADDRDEC0_ADDR_MASK_SECCS23 20754 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 20755 #define MMEA3_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 20756 //MMEA3_ADDRDEC0_ADDR_CFG_CS01 20757 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 20758 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 20759 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 20760 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 20761 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 20762 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 20763 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 20764 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 20765 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 20766 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 20767 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 20768 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 20769 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 20770 #define MMEA3_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 20771 //MMEA3_ADDRDEC0_ADDR_CFG_CS23 20772 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 20773 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 20774 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 20775 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 20776 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 20777 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 20778 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 20779 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 20780 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 20781 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 20782 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 20783 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 20784 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 20785 #define MMEA3_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 20786 //MMEA3_ADDRDEC0_ADDR_SEL_CS01 20787 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 20788 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 20789 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 20790 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 20791 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 20792 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 20793 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 20794 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 20795 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 20796 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 20797 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 20798 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 20799 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 20800 #define MMEA3_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 20801 //MMEA3_ADDRDEC0_ADDR_SEL_CS23 20802 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 20803 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 20804 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 20805 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 20806 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 20807 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 20808 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 20809 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 20810 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 20811 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 20812 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 20813 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 20814 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 20815 #define MMEA3_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 20816 //MMEA3_ADDRDEC0_ADDR_SEL2_CS01 20817 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 20818 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 20819 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 20820 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 20821 //MMEA3_ADDRDEC0_ADDR_SEL2_CS23 20822 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 20823 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 20824 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 20825 #define MMEA3_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 20826 //MMEA3_ADDRDEC0_COL_SEL_LO_CS01 20827 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 20828 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 20829 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 20830 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 20831 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 20832 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 20833 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 20834 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 20835 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 20836 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 20837 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 20838 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 20839 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 20840 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 20841 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 20842 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 20843 //MMEA3_ADDRDEC0_COL_SEL_LO_CS23 20844 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 20845 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 20846 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 20847 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 20848 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 20849 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 20850 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 20851 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 20852 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 20853 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 20854 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 20855 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 20856 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 20857 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 20858 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 20859 #define MMEA3_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 20860 //MMEA3_ADDRDEC0_COL_SEL_HI_CS01 20861 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 20862 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 20863 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 20864 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 20865 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 20866 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 20867 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 20868 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 20869 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 20870 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 20871 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 20872 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 20873 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 20874 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 20875 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 20876 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 20877 //MMEA3_ADDRDEC0_COL_SEL_HI_CS23 20878 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 20879 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 20880 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 20881 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 20882 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 20883 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 20884 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 20885 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 20886 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 20887 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 20888 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 20889 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 20890 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 20891 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 20892 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 20893 #define MMEA3_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 20894 //MMEA3_ADDRDEC0_RM_SEL_CS01 20895 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 20896 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 20897 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 20898 #define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 20899 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 20900 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 20901 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 20902 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 20903 #define MMEA3_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 20904 #define MMEA3_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 20905 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 20906 #define MMEA3_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 20907 //MMEA3_ADDRDEC0_RM_SEL_CS23 20908 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 20909 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 20910 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 20911 #define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 20912 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 20913 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 20914 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 20915 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 20916 #define MMEA3_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 20917 #define MMEA3_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 20918 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 20919 #define MMEA3_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 20920 //MMEA3_ADDRDEC0_RM_SEL_SECCS01 20921 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 20922 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 20923 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 20924 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 20925 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 20926 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 20927 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 20928 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 20929 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 20930 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 20931 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 20932 #define MMEA3_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 20933 //MMEA3_ADDRDEC0_RM_SEL_SECCS23 20934 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 20935 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 20936 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 20937 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 20938 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 20939 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 20940 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 20941 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 20942 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 20943 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 20944 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 20945 #define MMEA3_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 20946 //MMEA3_ADDRDEC1_BASE_ADDR_CS0 20947 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 20948 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 20949 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 20950 #define MMEA3_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 20951 //MMEA3_ADDRDEC1_BASE_ADDR_CS1 20952 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 20953 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 20954 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 20955 #define MMEA3_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 20956 //MMEA3_ADDRDEC1_BASE_ADDR_CS2 20957 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 20958 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 20959 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 20960 #define MMEA3_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 20961 //MMEA3_ADDRDEC1_BASE_ADDR_CS3 20962 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 20963 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 20964 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 20965 #define MMEA3_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 20966 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS0 20967 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 20968 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 20969 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 20970 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 20971 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS1 20972 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 20973 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 20974 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 20975 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 20976 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS2 20977 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 20978 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 20979 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 20980 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 20981 //MMEA3_ADDRDEC1_BASE_ADDR_SECCS3 20982 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 20983 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 20984 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 20985 #define MMEA3_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 20986 //MMEA3_ADDRDEC1_ADDR_MASK_CS01 20987 #define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 20988 #define MMEA3_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 20989 //MMEA3_ADDRDEC1_ADDR_MASK_CS23 20990 #define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 20991 #define MMEA3_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 20992 //MMEA3_ADDRDEC1_ADDR_MASK_SECCS01 20993 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 20994 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 20995 //MMEA3_ADDRDEC1_ADDR_MASK_SECCS23 20996 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 20997 #define MMEA3_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 20998 //MMEA3_ADDRDEC1_ADDR_CFG_CS01 20999 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 21000 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 21001 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 21002 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 21003 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 21004 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 21005 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 21006 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 21007 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 21008 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 21009 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 21010 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 21011 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 21012 #define MMEA3_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 21013 //MMEA3_ADDRDEC1_ADDR_CFG_CS23 21014 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 21015 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 21016 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 21017 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 21018 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 21019 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 21020 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 21021 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 21022 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 21023 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 21024 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 21025 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 21026 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 21027 #define MMEA3_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 21028 //MMEA3_ADDRDEC1_ADDR_SEL_CS01 21029 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 21030 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 21031 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 21032 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 21033 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 21034 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 21035 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 21036 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 21037 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 21038 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 21039 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 21040 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 21041 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 21042 #define MMEA3_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 21043 //MMEA3_ADDRDEC1_ADDR_SEL_CS23 21044 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 21045 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 21046 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 21047 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 21048 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 21049 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 21050 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 21051 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 21052 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 21053 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 21054 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 21055 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 21056 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 21057 #define MMEA3_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 21058 //MMEA3_ADDRDEC1_ADDR_SEL2_CS01 21059 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 21060 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 21061 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 21062 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 21063 //MMEA3_ADDRDEC1_ADDR_SEL2_CS23 21064 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 21065 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 21066 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 21067 #define MMEA3_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 21068 //MMEA3_ADDRDEC1_COL_SEL_LO_CS01 21069 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 21070 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 21071 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 21072 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 21073 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 21074 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 21075 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 21076 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 21077 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 21078 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 21079 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 21080 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 21081 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 21082 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 21083 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 21084 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 21085 //MMEA3_ADDRDEC1_COL_SEL_LO_CS23 21086 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 21087 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 21088 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 21089 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 21090 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 21091 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 21092 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 21093 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 21094 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 21095 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 21096 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 21097 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 21098 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 21099 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 21100 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 21101 #define MMEA3_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 21102 //MMEA3_ADDRDEC1_COL_SEL_HI_CS01 21103 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 21104 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 21105 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 21106 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 21107 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 21108 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 21109 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 21110 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 21111 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 21112 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 21113 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 21114 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 21115 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 21116 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 21117 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 21118 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 21119 //MMEA3_ADDRDEC1_COL_SEL_HI_CS23 21120 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 21121 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 21122 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 21123 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 21124 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 21125 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 21126 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 21127 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 21128 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 21129 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 21130 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 21131 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 21132 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 21133 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 21134 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 21135 #define MMEA3_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 21136 //MMEA3_ADDRDEC1_RM_SEL_CS01 21137 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 21138 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 21139 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 21140 #define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 21141 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21142 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21143 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 21144 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 21145 #define MMEA3_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 21146 #define MMEA3_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 21147 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21148 #define MMEA3_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21149 //MMEA3_ADDRDEC1_RM_SEL_CS23 21150 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 21151 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 21152 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 21153 #define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 21154 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21155 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21156 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 21157 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 21158 #define MMEA3_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 21159 #define MMEA3_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 21160 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21161 #define MMEA3_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21162 //MMEA3_ADDRDEC1_RM_SEL_SECCS01 21163 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 21164 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 21165 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 21166 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 21167 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21168 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21169 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 21170 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 21171 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 21172 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 21173 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21174 #define MMEA3_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21175 //MMEA3_ADDRDEC1_RM_SEL_SECCS23 21176 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 21177 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 21178 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 21179 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 21180 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21181 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21182 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 21183 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 21184 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 21185 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 21186 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21187 #define MMEA3_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21188 //MMEA3_ADDRDEC2_BASE_ADDR_CS0 21189 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 21190 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 21191 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 21192 #define MMEA3_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 21193 //MMEA3_ADDRDEC2_BASE_ADDR_CS1 21194 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 21195 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 21196 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 21197 #define MMEA3_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 21198 //MMEA3_ADDRDEC2_BASE_ADDR_CS2 21199 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 21200 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 21201 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 21202 #define MMEA3_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 21203 //MMEA3_ADDRDEC2_BASE_ADDR_CS3 21204 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 21205 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 21206 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 21207 #define MMEA3_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 21208 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS0 21209 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 21210 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 21211 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 21212 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 21213 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS1 21214 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 21215 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 21216 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 21217 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 21218 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS2 21219 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 21220 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 21221 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 21222 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 21223 //MMEA3_ADDRDEC2_BASE_ADDR_SECCS3 21224 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 21225 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 21226 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 21227 #define MMEA3_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 21228 //MMEA3_ADDRDEC2_ADDR_MASK_CS01 21229 #define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 21230 #define MMEA3_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 21231 //MMEA3_ADDRDEC2_ADDR_MASK_CS23 21232 #define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 21233 #define MMEA3_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 21234 //MMEA3_ADDRDEC2_ADDR_MASK_SECCS01 21235 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 21236 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 21237 //MMEA3_ADDRDEC2_ADDR_MASK_SECCS23 21238 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 21239 #define MMEA3_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 21240 //MMEA3_ADDRDEC2_ADDR_CFG_CS01 21241 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 21242 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 21243 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 21244 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 21245 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 21246 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 21247 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 21248 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 21249 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 21250 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 21251 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 21252 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 21253 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 21254 #define MMEA3_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 21255 //MMEA3_ADDRDEC2_ADDR_CFG_CS23 21256 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 21257 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 21258 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 21259 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 21260 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 21261 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 21262 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 21263 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 21264 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 21265 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 21266 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 21267 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 21268 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 21269 #define MMEA3_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 21270 //MMEA3_ADDRDEC2_ADDR_SEL_CS01 21271 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 21272 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 21273 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 21274 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 21275 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 21276 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 21277 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 21278 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 21279 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 21280 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 21281 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 21282 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 21283 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 21284 #define MMEA3_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 21285 //MMEA3_ADDRDEC2_ADDR_SEL_CS23 21286 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 21287 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 21288 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 21289 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 21290 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 21291 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 21292 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 21293 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 21294 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 21295 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 21296 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 21297 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 21298 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 21299 #define MMEA3_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 21300 //MMEA3_ADDRDEC2_ADDR_SEL2_CS01 21301 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 21302 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 21303 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 21304 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 21305 //MMEA3_ADDRDEC2_ADDR_SEL2_CS23 21306 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 21307 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 21308 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 21309 #define MMEA3_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 21310 //MMEA3_ADDRDEC2_COL_SEL_LO_CS01 21311 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 21312 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 21313 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 21314 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 21315 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 21316 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 21317 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 21318 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 21319 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 21320 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 21321 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 21322 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 21323 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 21324 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 21325 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 21326 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 21327 //MMEA3_ADDRDEC2_COL_SEL_LO_CS23 21328 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 21329 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 21330 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 21331 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 21332 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 21333 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 21334 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 21335 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 21336 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 21337 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 21338 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 21339 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 21340 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 21341 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 21342 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 21343 #define MMEA3_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 21344 //MMEA3_ADDRDEC2_COL_SEL_HI_CS01 21345 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 21346 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 21347 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 21348 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 21349 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 21350 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 21351 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 21352 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 21353 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 21354 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 21355 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 21356 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 21357 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 21358 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 21359 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 21360 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 21361 //MMEA3_ADDRDEC2_COL_SEL_HI_CS23 21362 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 21363 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 21364 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 21365 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 21366 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 21367 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 21368 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 21369 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 21370 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 21371 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 21372 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 21373 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 21374 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 21375 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 21376 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 21377 #define MMEA3_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 21378 //MMEA3_ADDRDEC2_RM_SEL_CS01 21379 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 21380 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 21381 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 21382 #define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 21383 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21384 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21385 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 21386 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 21387 #define MMEA3_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 21388 #define MMEA3_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 21389 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21390 #define MMEA3_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21391 //MMEA3_ADDRDEC2_RM_SEL_CS23 21392 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 21393 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 21394 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 21395 #define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 21396 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21397 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21398 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 21399 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 21400 #define MMEA3_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 21401 #define MMEA3_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 21402 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21403 #define MMEA3_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21404 //MMEA3_ADDRDEC2_RM_SEL_SECCS01 21405 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 21406 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 21407 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 21408 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 21409 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21410 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21411 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 21412 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 21413 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 21414 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 21415 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21416 #define MMEA3_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21417 //MMEA3_ADDRDEC2_RM_SEL_SECCS23 21418 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 21419 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 21420 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 21421 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 21422 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 21423 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 21424 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 21425 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 21426 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 21427 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 21428 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 21429 #define MMEA3_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 21430 //MMEA3_ADDRNORMDRAM_GLOBAL_CNTL 21431 //MMEA3_ADDRNORMGMI_GLOBAL_CNTL 21432 //MMEA3_ADDRNORM_MEGACONTROL_ADDR0 21433 #define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 21434 #define MMEA3_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 21435 //MMEA3_ADDRNORM_MEGACONTROL_ADDR1 21436 #define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 21437 #define MMEA3_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 21438 //MMEA3_ADDRNORMDRAM_MASKING 21439 #define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 21440 #define MMEA3_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 21441 //MMEA3_ADDRNORMGMI_MASKING 21442 #define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 21443 #define MMEA3_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 21444 //MMEA3_IO_RD_CLI2GRP_MAP0 21445 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 21446 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 21447 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 21448 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 21449 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 21450 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 21451 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 21452 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 21453 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 21454 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 21455 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 21456 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 21457 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 21458 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 21459 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 21460 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 21461 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 21462 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 21463 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 21464 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 21465 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 21466 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 21467 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 21468 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 21469 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 21470 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 21471 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 21472 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 21473 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 21474 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 21475 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 21476 #define MMEA3_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 21477 //MMEA3_IO_RD_CLI2GRP_MAP1 21478 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 21479 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 21480 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 21481 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 21482 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 21483 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 21484 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 21485 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 21486 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 21487 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 21488 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 21489 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 21490 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 21491 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 21492 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 21493 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 21494 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 21495 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 21496 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 21497 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 21498 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 21499 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 21500 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 21501 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 21502 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 21503 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 21504 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 21505 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 21506 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 21507 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 21508 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 21509 #define MMEA3_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 21510 //MMEA3_IO_WR_CLI2GRP_MAP0 21511 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 21512 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 21513 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 21514 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 21515 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 21516 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 21517 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 21518 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 21519 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 21520 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 21521 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 21522 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 21523 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 21524 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 21525 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 21526 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 21527 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 21528 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 21529 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 21530 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 21531 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 21532 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 21533 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 21534 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 21535 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 21536 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 21537 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 21538 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 21539 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 21540 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 21541 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 21542 #define MMEA3_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 21543 //MMEA3_IO_WR_CLI2GRP_MAP1 21544 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 21545 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 21546 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 21547 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 21548 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 21549 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 21550 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 21551 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 21552 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 21553 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 21554 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 21555 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 21556 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 21557 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 21558 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 21559 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 21560 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 21561 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 21562 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 21563 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 21564 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 21565 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 21566 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 21567 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 21568 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 21569 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 21570 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 21571 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 21572 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 21573 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 21574 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 21575 #define MMEA3_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 21576 //MMEA3_IO_RD_COMBINE_FLUSH 21577 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 21578 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 21579 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 21580 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 21581 #define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 21582 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 21583 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 21584 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 21585 #define MMEA3_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 21586 #define MMEA3_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 21587 //MMEA3_IO_WR_COMBINE_FLUSH 21588 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 21589 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 21590 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 21591 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 21592 #define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 21593 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 21594 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 21595 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 21596 #define MMEA3_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 21597 #define MMEA3_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 21598 //MMEA3_IO_GROUP_BURST 21599 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 21600 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 21601 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 21602 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 21603 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 21604 #define MMEA3_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 21605 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 21606 #define MMEA3_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 21607 //MMEA3_IO_RD_PRI_AGE 21608 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 21609 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 21610 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 21611 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 21612 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 21613 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 21614 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 21615 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 21616 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 21617 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 21618 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 21619 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 21620 #define MMEA3_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 21621 #define MMEA3_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 21622 #define MMEA3_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 21623 #define MMEA3_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 21624 //MMEA3_IO_WR_PRI_AGE 21625 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 21626 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 21627 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 21628 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 21629 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 21630 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 21631 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 21632 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 21633 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 21634 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 21635 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 21636 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 21637 #define MMEA3_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 21638 #define MMEA3_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 21639 #define MMEA3_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 21640 #define MMEA3_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 21641 //MMEA3_IO_RD_PRI_QUEUING 21642 #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 21643 #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 21644 #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 21645 #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 21646 #define MMEA3_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 21647 #define MMEA3_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 21648 #define MMEA3_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 21649 #define MMEA3_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 21650 //MMEA3_IO_WR_PRI_QUEUING 21651 #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 21652 #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 21653 #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 21654 #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 21655 #define MMEA3_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 21656 #define MMEA3_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 21657 #define MMEA3_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 21658 #define MMEA3_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 21659 //MMEA3_IO_RD_PRI_FIXED 21660 #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 21661 #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 21662 #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 21663 #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 21664 #define MMEA3_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 21665 #define MMEA3_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 21666 #define MMEA3_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 21667 #define MMEA3_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 21668 //MMEA3_IO_WR_PRI_FIXED 21669 #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 21670 #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 21671 #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 21672 #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 21673 #define MMEA3_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 21674 #define MMEA3_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 21675 #define MMEA3_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 21676 #define MMEA3_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 21677 //MMEA3_IO_RD_PRI_URGENCY 21678 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 21679 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 21680 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 21681 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 21682 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 21683 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 21684 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 21685 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 21686 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 21687 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 21688 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 21689 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 21690 #define MMEA3_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 21691 #define MMEA3_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 21692 #define MMEA3_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 21693 #define MMEA3_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 21694 //MMEA3_IO_WR_PRI_URGENCY 21695 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 21696 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 21697 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 21698 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 21699 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 21700 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 21701 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 21702 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 21703 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 21704 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 21705 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 21706 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 21707 #define MMEA3_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 21708 #define MMEA3_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 21709 #define MMEA3_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 21710 #define MMEA3_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 21711 //MMEA3_IO_RD_PRI_URGENCY_MASKING 21712 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 21713 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 21714 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 21715 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 21716 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 21717 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 21718 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 21719 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 21720 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 21721 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 21722 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 21723 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 21724 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 21725 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 21726 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 21727 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 21728 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 21729 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 21730 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 21731 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 21732 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 21733 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 21734 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 21735 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 21736 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 21737 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 21738 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 21739 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 21740 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 21741 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 21742 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 21743 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 21744 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 21745 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 21746 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 21747 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 21748 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 21749 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 21750 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 21751 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 21752 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 21753 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 21754 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 21755 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 21756 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 21757 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 21758 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 21759 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 21760 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 21761 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 21762 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 21763 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 21764 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 21765 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 21766 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 21767 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 21768 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 21769 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 21770 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 21771 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 21772 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 21773 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 21774 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 21775 #define MMEA3_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 21776 //MMEA3_IO_WR_PRI_URGENCY_MASKING 21777 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 21778 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 21779 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 21780 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 21781 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 21782 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 21783 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 21784 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 21785 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 21786 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 21787 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 21788 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 21789 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 21790 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 21791 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 21792 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 21793 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 21794 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 21795 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 21796 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 21797 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 21798 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 21799 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 21800 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 21801 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 21802 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 21803 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 21804 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 21805 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 21806 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 21807 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 21808 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 21809 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 21810 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 21811 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 21812 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 21813 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 21814 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 21815 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 21816 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 21817 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 21818 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 21819 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 21820 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 21821 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 21822 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 21823 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 21824 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 21825 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 21826 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 21827 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 21828 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 21829 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 21830 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 21831 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 21832 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 21833 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 21834 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 21835 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 21836 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 21837 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 21838 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 21839 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 21840 #define MMEA3_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 21841 //MMEA3_IO_RD_PRI_QUANT_PRI1 21842 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 21843 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 21844 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 21845 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 21846 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 21847 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 21848 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 21849 #define MMEA3_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 21850 //MMEA3_IO_RD_PRI_QUANT_PRI2 21851 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 21852 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 21853 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 21854 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 21855 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 21856 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 21857 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 21858 #define MMEA3_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 21859 //MMEA3_IO_RD_PRI_QUANT_PRI3 21860 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 21861 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 21862 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 21863 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 21864 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 21865 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 21866 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 21867 #define MMEA3_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 21868 //MMEA3_IO_WR_PRI_QUANT_PRI1 21869 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 21870 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 21871 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 21872 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 21873 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 21874 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 21875 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 21876 #define MMEA3_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 21877 //MMEA3_IO_WR_PRI_QUANT_PRI2 21878 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 21879 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 21880 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 21881 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 21882 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 21883 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 21884 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 21885 #define MMEA3_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 21886 //MMEA3_IO_WR_PRI_QUANT_PRI3 21887 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 21888 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 21889 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 21890 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 21891 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 21892 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 21893 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 21894 #define MMEA3_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 21895 //MMEA3_SDP_ARB_DRAM 21896 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 21897 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 21898 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 21899 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 21900 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 21901 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 21902 #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 21903 #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 21904 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 21905 #define MMEA3_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 21906 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 21907 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 21908 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 21909 #define MMEA3_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 21910 #define MMEA3_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 21911 #define MMEA3_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 21912 //MMEA3_SDP_ARB_GMI 21913 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 21914 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 21915 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 21916 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 21917 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 21918 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 21919 #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 21920 #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 21921 #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 21922 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 21923 #define MMEA3_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 21924 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 21925 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 21926 #define MMEA3_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 21927 #define MMEA3_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 21928 #define MMEA3_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 21929 #define MMEA3_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 21930 #define MMEA3_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 21931 //MMEA3_SDP_ARB_FINAL 21932 #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 21933 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 21934 #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 21935 #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 21936 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 21937 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 21938 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 21939 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 21940 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 21941 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 21942 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 21943 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 21944 #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 21945 #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 21946 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 21947 #define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c 21948 #define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d 21949 #define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e 21950 #define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f 21951 #define MMEA3_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 21952 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 21953 #define MMEA3_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 21954 #define MMEA3_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 21955 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 21956 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 21957 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 21958 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 21959 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 21960 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 21961 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 21962 #define MMEA3_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 21963 #define MMEA3_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 21964 #define MMEA3_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 21965 #define MMEA3_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 21966 #define MMEA3_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L 21967 #define MMEA3_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L 21968 #define MMEA3_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L 21969 #define MMEA3_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L 21970 //MMEA3_SDP_DRAM_PRIORITY 21971 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 21972 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 21973 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 21974 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 21975 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 21976 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 21977 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 21978 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 21979 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 21980 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 21981 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 21982 #define MMEA3_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 21983 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 21984 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 21985 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 21986 #define MMEA3_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 21987 //MMEA3_SDP_GMI_PRIORITY 21988 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 21989 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 21990 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 21991 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 21992 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 21993 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 21994 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 21995 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 21996 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 21997 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 21998 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 21999 #define MMEA3_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 22000 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 22001 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 22002 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 22003 #define MMEA3_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 22004 //MMEA3_SDP_IO_PRIORITY 22005 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 22006 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 22007 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 22008 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 22009 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 22010 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 22011 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 22012 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 22013 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 22014 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 22015 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 22016 #define MMEA3_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 22017 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 22018 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 22019 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 22020 #define MMEA3_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 22021 //MMEA3_SDP_CREDITS 22022 #define MMEA3_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 22023 #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 22024 #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 22025 #define MMEA3_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 22026 #define MMEA3_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 22027 #define MMEA3_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 22028 //MMEA3_SDP_TAG_RESERVE0 22029 #define MMEA3_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 22030 #define MMEA3_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 22031 #define MMEA3_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 22032 #define MMEA3_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 22033 #define MMEA3_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 22034 #define MMEA3_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 22035 #define MMEA3_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 22036 #define MMEA3_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 22037 //MMEA3_SDP_TAG_RESERVE1 22038 #define MMEA3_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 22039 #define MMEA3_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 22040 #define MMEA3_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 22041 #define MMEA3_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 22042 #define MMEA3_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 22043 #define MMEA3_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 22044 #define MMEA3_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 22045 #define MMEA3_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 22046 //MMEA3_SDP_VCC_RESERVE0 22047 #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 22048 #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 22049 #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 22050 #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 22051 #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 22052 #define MMEA3_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 22053 #define MMEA3_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 22054 #define MMEA3_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 22055 #define MMEA3_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 22056 #define MMEA3_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 22057 //MMEA3_SDP_VCC_RESERVE1 22058 #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 22059 #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 22060 #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 22061 #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 22062 #define MMEA3_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 22063 #define MMEA3_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 22064 #define MMEA3_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 22065 #define MMEA3_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 22066 //MMEA3_SDP_VCD_RESERVE0 22067 #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 22068 #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 22069 #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 22070 #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 22071 #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 22072 #define MMEA3_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 22073 #define MMEA3_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 22074 #define MMEA3_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 22075 #define MMEA3_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 22076 #define MMEA3_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 22077 //MMEA3_SDP_VCD_RESERVE1 22078 #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 22079 #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 22080 #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 22081 #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 22082 #define MMEA3_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 22083 #define MMEA3_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 22084 #define MMEA3_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 22085 #define MMEA3_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 22086 //MMEA3_SDP_REQ_CNTL 22087 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 22088 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 22089 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 22090 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 22091 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 22092 #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 22093 #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 22094 #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 22095 #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 22096 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 22097 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 22098 #define MMEA3_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 22099 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 22100 #define MMEA3_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 22101 #define MMEA3_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 22102 #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 22103 #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 22104 #define MMEA3_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 22105 //MMEA3_MISC 22106 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 22107 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 22108 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 22109 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 22110 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 22111 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 22112 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 22113 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 22114 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 22115 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 22116 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 22117 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 22118 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 22119 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 22120 #define MMEA3_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 22121 #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 22122 #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 22123 #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 22124 #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 22125 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 22126 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 22127 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 22128 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 22129 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 22130 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 22131 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 22132 #define MMEA3_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 22133 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 22134 #define MMEA3_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 22135 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 22136 #define MMEA3_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 22137 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 22138 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 22139 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 22140 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 22141 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 22142 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 22143 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 22144 #define MMEA3_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 22145 #define MMEA3_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 22146 #define MMEA3_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 22147 #define MMEA3_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 22148 #define MMEA3_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 22149 #define MMEA3_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 22150 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 22151 #define MMEA3_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 22152 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 22153 #define MMEA3_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 22154 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 22155 #define MMEA3_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 22156 //MMEA3_LATENCY_SAMPLING 22157 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 22158 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 22159 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 22160 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 22161 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 22162 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 22163 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 22164 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 22165 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 22166 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 22167 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 22168 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 22169 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 22170 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 22171 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 22172 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 22173 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 22174 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 22175 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 22176 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 22177 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 22178 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 22179 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 22180 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 22181 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 22182 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 22183 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 22184 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 22185 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 22186 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 22187 #define MMEA3_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 22188 #define MMEA3_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 22189 //MMEA3_PERFCOUNTER_LO 22190 #define MMEA3_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 22191 #define MMEA3_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 22192 //MMEA3_PERFCOUNTER_HI 22193 #define MMEA3_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 22194 #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 22195 #define MMEA3_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 22196 #define MMEA3_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 22197 //MMEA3_PERFCOUNTER0_CFG 22198 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 22199 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 22200 #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 22201 #define MMEA3_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 22202 #define MMEA3_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 22203 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 22204 #define MMEA3_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 22205 #define MMEA3_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 22206 #define MMEA3_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 22207 #define MMEA3_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 22208 //MMEA3_PERFCOUNTER1_CFG 22209 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 22210 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 22211 #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 22212 #define MMEA3_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 22213 #define MMEA3_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 22214 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 22215 #define MMEA3_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 22216 #define MMEA3_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 22217 #define MMEA3_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 22218 #define MMEA3_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 22219 //MMEA3_PERFCOUNTER_RSLT_CNTL 22220 #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 22221 #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 22222 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 22223 #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 22224 #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 22225 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 22226 #define MMEA3_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 22227 #define MMEA3_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 22228 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 22229 #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 22230 #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 22231 #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 22232 //MMEA3_EDC_CNT 22233 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 22234 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 22235 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 22236 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 22237 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 22238 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 22239 #define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 22240 #define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 22241 #define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 22242 #define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 22243 #define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 22244 #define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 22245 #define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 22246 #define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a 22247 #define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c 22248 #define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e 22249 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 22250 #define MMEA3_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 22251 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 22252 #define MMEA3_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 22253 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 22254 #define MMEA3_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 22255 #define MMEA3_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 22256 #define MMEA3_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 22257 #define MMEA3_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 22258 #define MMEA3_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 22259 #define MMEA3_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L 22260 #define MMEA3_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L 22261 #define MMEA3_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L 22262 #define MMEA3_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L 22263 #define MMEA3_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L 22264 #define MMEA3_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L 22265 //MMEA3_EDC_CNT2 22266 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 22267 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 22268 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 22269 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 22270 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 22271 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 22272 #define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 22273 #define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 22274 #define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 22275 #define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 22276 #define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 22277 #define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 22278 #define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 22279 #define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 22280 #define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 22281 #define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 22282 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 22283 #define MMEA3_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 22284 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 22285 #define MMEA3_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 22286 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 22287 #define MMEA3_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 22288 #define MMEA3_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 22289 #define MMEA3_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 22290 #define MMEA3_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 22291 #define MMEA3_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 22292 #define MMEA3_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 22293 #define MMEA3_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 22294 #define MMEA3_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 22295 #define MMEA3_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 22296 #define MMEA3_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 22297 #define MMEA3_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 22298 //MMEA3_DSM_CNTL 22299 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 22300 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 22301 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 22302 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 22303 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 22304 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 22305 #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 22306 #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 22307 #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 22308 #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 22309 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 22310 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 22311 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 22312 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 22313 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 22314 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 22315 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 22316 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 22317 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 22318 #define MMEA3_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 22319 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 22320 #define MMEA3_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 22321 #define MMEA3_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 22322 #define MMEA3_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 22323 #define MMEA3_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 22324 #define MMEA3_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 22325 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 22326 #define MMEA3_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 22327 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 22328 #define MMEA3_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 22329 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 22330 #define MMEA3_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 22331 //MMEA3_DSM_CNTLA 22332 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 22333 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 22334 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 22335 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 22336 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 22337 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 22338 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 22339 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 22340 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 22341 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 22342 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 22343 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 22344 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 22345 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 22346 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 22347 #define MMEA3_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 22348 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 22349 #define MMEA3_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 22350 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 22351 #define MMEA3_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 22352 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 22353 #define MMEA3_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 22354 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 22355 #define MMEA3_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 22356 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 22357 #define MMEA3_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 22358 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 22359 #define MMEA3_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 22360 //MMEA3_DSM_CNTLB 22361 //MMEA3_DSM_CNTL2 22362 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 22363 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 22364 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 22365 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 22366 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 22367 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 22368 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 22369 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 22370 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 22371 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 22372 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 22373 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 22374 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 22375 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 22376 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 22377 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 22378 #define MMEA3_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 22379 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 22380 #define MMEA3_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 22381 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 22382 #define MMEA3_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 22383 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 22384 #define MMEA3_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 22385 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 22386 #define MMEA3_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 22387 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 22388 #define MMEA3_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 22389 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 22390 #define MMEA3_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 22391 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 22392 #define MMEA3_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 22393 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 22394 #define MMEA3_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 22395 #define MMEA3_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 22396 //MMEA3_DSM_CNTL2A 22397 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 22398 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 22399 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 22400 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 22401 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 22402 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 22403 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 22404 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 22405 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 22406 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 22407 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 22408 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 22409 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 22410 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 22411 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 22412 #define MMEA3_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 22413 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 22414 #define MMEA3_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 22415 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 22416 #define MMEA3_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 22417 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 22418 #define MMEA3_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 22419 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 22420 #define MMEA3_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 22421 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 22422 #define MMEA3_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 22423 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 22424 #define MMEA3_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 22425 //MMEA3_DSM_CNTL2B 22426 //MMEA3_CGTT_CLK_CTRL 22427 #define MMEA3_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 22428 #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 22429 #define MMEA3_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 22430 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 22431 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 22432 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 22433 #define MMEA3_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 22434 #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 22435 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 22436 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 22437 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 22438 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 22439 #define MMEA3_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 22440 #define MMEA3_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 22441 #define MMEA3_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 22442 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 22443 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 22444 #define MMEA3_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 22445 #define MMEA3_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 22446 #define MMEA3_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 22447 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 22448 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 22449 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 22450 #define MMEA3_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 22451 //MMEA3_EDC_MODE 22452 #define MMEA3_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 22453 #define MMEA3_EDC_MODE__GATE_FUE__SHIFT 0x11 22454 #define MMEA3_EDC_MODE__DED_MODE__SHIFT 0x14 22455 #define MMEA3_EDC_MODE__PROP_FED__SHIFT 0x1d 22456 #define MMEA3_EDC_MODE__BYPASS__SHIFT 0x1f 22457 #define MMEA3_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 22458 #define MMEA3_EDC_MODE__GATE_FUE_MASK 0x00020000L 22459 #define MMEA3_EDC_MODE__DED_MODE_MASK 0x00300000L 22460 #define MMEA3_EDC_MODE__PROP_FED_MASK 0x20000000L 22461 #define MMEA3_EDC_MODE__BYPASS_MASK 0x80000000L 22462 //MMEA3_ERR_STATUS 22463 #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 22464 #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 22465 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 22466 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 22467 #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 22468 #define MMEA3_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 22469 #define MMEA3_ERR_STATUS__FUE_FLAG__SHIFT 0xd 22470 #define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 22471 #define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 22472 #define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 22473 #define MMEA3_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 22474 #define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 22475 #define MMEA3_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 22476 #define MMEA3_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 22477 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 22478 #define MMEA3_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 22479 #define MMEA3_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 22480 #define MMEA3_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 22481 #define MMEA3_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 22482 #define MMEA3_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 22483 #define MMEA3_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 22484 #define MMEA3_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 22485 #define MMEA3_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 22486 #define MMEA3_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 22487 //MMEA3_MISC2 22488 #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 22489 #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 22490 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 22491 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 22492 #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 22493 #define MMEA3_MISC2__RRET_SWAP_MODE__SHIFT 0xd 22494 #define MMEA3_MISC2__BLOCK_REQUESTS__SHIFT 0xe 22495 #define MMEA3_MISC2__REQUESTS_BLOCKED__SHIFT 0xf 22496 #define MMEA3_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 22497 #define MMEA3_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 22498 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 22499 #define MMEA3_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 22500 #define MMEA3_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 22501 #define MMEA3_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 22502 #define MMEA3_MISC2__BLOCK_REQUESTS_MASK 0x00004000L 22503 #define MMEA3_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L 22504 //MMEA3_ADDRDEC_SELECT 22505 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 22506 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 22507 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 22508 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 22509 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 22510 #define MMEA3_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 22511 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 22512 #define MMEA3_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 22513 //MMEA3_EDC_CNT3 22514 #define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 22515 #define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 22516 #define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 22517 #define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 22518 #define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 22519 #define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa 22520 #define MMEA3_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 22521 #define MMEA3_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 22522 #define MMEA3_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 22523 #define MMEA3_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 22524 #define MMEA3_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L 22525 #define MMEA3_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L 22526 //MMEA3_MISC_AON 22527 #define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 22528 #define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 22529 #define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 22530 #define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 22531 22532 22533 // addressBlock: mmhub_ea_mmeadec4 22534 //MMEA4_DRAM_RD_CLI2GRP_MAP0 22535 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 22536 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 22537 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 22538 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 22539 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 22540 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 22541 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 22542 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 22543 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 22544 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 22545 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 22546 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 22547 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 22548 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 22549 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 22550 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 22551 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 22552 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 22553 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 22554 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 22555 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 22556 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 22557 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 22558 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 22559 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 22560 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 22561 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 22562 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 22563 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 22564 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 22565 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 22566 #define MMEA4_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 22567 //MMEA4_DRAM_RD_CLI2GRP_MAP1 22568 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 22569 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 22570 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 22571 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 22572 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 22573 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 22574 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 22575 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 22576 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 22577 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 22578 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 22579 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 22580 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 22581 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 22582 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 22583 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 22584 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 22585 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 22586 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 22587 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 22588 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 22589 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 22590 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 22591 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 22592 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 22593 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 22594 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 22595 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 22596 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 22597 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 22598 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 22599 #define MMEA4_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 22600 //MMEA4_DRAM_WR_CLI2GRP_MAP0 22601 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 22602 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 22603 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 22604 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 22605 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 22606 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 22607 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 22608 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 22609 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 22610 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 22611 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 22612 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 22613 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 22614 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 22615 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 22616 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 22617 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 22618 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 22619 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 22620 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 22621 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 22622 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 22623 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 22624 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 22625 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 22626 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 22627 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 22628 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 22629 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 22630 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 22631 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 22632 #define MMEA4_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 22633 //MMEA4_DRAM_WR_CLI2GRP_MAP1 22634 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 22635 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 22636 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 22637 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 22638 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 22639 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 22640 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 22641 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 22642 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 22643 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 22644 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 22645 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 22646 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 22647 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 22648 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 22649 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 22650 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 22651 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 22652 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 22653 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 22654 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 22655 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 22656 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 22657 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 22658 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 22659 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 22660 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 22661 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 22662 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 22663 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 22664 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 22665 #define MMEA4_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 22666 //MMEA4_DRAM_RD_GRP2VC_MAP 22667 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 22668 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 22669 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 22670 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 22671 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 22672 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 22673 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 22674 #define MMEA4_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 22675 //MMEA4_DRAM_WR_GRP2VC_MAP 22676 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 22677 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 22678 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 22679 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 22680 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 22681 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 22682 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 22683 #define MMEA4_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 22684 //MMEA4_DRAM_RD_LAZY 22685 #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 22686 #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 22687 #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 22688 #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 22689 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 22690 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 22691 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 22692 #define MMEA4_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 22693 #define MMEA4_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 22694 #define MMEA4_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 22695 #define MMEA4_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 22696 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 22697 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 22698 #define MMEA4_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 22699 //MMEA4_DRAM_WR_LAZY 22700 #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 22701 #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 22702 #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 22703 #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 22704 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 22705 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 22706 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 22707 #define MMEA4_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 22708 #define MMEA4_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 22709 #define MMEA4_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 22710 #define MMEA4_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 22711 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 22712 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 22713 #define MMEA4_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 22714 //MMEA4_DRAM_RD_CAM_CNTL 22715 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 22716 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 22717 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 22718 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 22719 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 22720 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 22721 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 22722 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 22723 #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 22724 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 22725 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 22726 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 22727 #define MMEA4_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 22728 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 22729 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 22730 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 22731 #define MMEA4_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 22732 #define MMEA4_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 22733 //MMEA4_DRAM_WR_CAM_CNTL 22734 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 22735 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 22736 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 22737 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 22738 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 22739 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 22740 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 22741 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 22742 #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 22743 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 22744 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 22745 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 22746 #define MMEA4_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 22747 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 22748 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 22749 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 22750 #define MMEA4_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 22751 #define MMEA4_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 22752 //MMEA4_DRAM_PAGE_BURST 22753 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 22754 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 22755 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 22756 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 22757 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 22758 #define MMEA4_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 22759 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 22760 #define MMEA4_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 22761 //MMEA4_DRAM_RD_PRI_AGE 22762 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 22763 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 22764 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 22765 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 22766 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 22767 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 22768 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 22769 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 22770 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 22771 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 22772 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 22773 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 22774 #define MMEA4_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 22775 #define MMEA4_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 22776 #define MMEA4_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 22777 #define MMEA4_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 22778 //MMEA4_DRAM_WR_PRI_AGE 22779 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 22780 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 22781 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 22782 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 22783 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 22784 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 22785 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 22786 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 22787 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 22788 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 22789 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 22790 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 22791 #define MMEA4_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 22792 #define MMEA4_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 22793 #define MMEA4_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 22794 #define MMEA4_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 22795 //MMEA4_DRAM_RD_PRI_QUEUING 22796 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 22797 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 22798 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 22799 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 22800 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 22801 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 22802 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 22803 #define MMEA4_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 22804 //MMEA4_DRAM_WR_PRI_QUEUING 22805 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 22806 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 22807 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 22808 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 22809 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 22810 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 22811 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 22812 #define MMEA4_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 22813 //MMEA4_DRAM_RD_PRI_FIXED 22814 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 22815 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 22816 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 22817 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 22818 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 22819 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 22820 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 22821 #define MMEA4_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 22822 //MMEA4_DRAM_WR_PRI_FIXED 22823 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 22824 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 22825 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 22826 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 22827 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 22828 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 22829 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 22830 #define MMEA4_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 22831 //MMEA4_DRAM_RD_PRI_URGENCY 22832 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 22833 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 22834 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 22835 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 22836 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 22837 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 22838 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 22839 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 22840 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 22841 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 22842 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 22843 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 22844 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 22845 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 22846 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 22847 #define MMEA4_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 22848 //MMEA4_DRAM_WR_PRI_URGENCY 22849 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 22850 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 22851 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 22852 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 22853 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 22854 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 22855 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 22856 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 22857 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 22858 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 22859 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 22860 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 22861 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 22862 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 22863 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 22864 #define MMEA4_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 22865 //MMEA4_DRAM_RD_PRI_QUANT_PRI1 22866 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 22867 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 22868 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 22869 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 22870 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 22871 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 22872 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 22873 #define MMEA4_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 22874 //MMEA4_DRAM_RD_PRI_QUANT_PRI2 22875 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 22876 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 22877 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 22878 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 22879 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 22880 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 22881 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 22882 #define MMEA4_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 22883 //MMEA4_DRAM_RD_PRI_QUANT_PRI3 22884 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 22885 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 22886 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 22887 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 22888 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 22889 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 22890 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 22891 #define MMEA4_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 22892 //MMEA4_DRAM_WR_PRI_QUANT_PRI1 22893 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 22894 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 22895 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 22896 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 22897 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 22898 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 22899 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 22900 #define MMEA4_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 22901 //MMEA4_DRAM_WR_PRI_QUANT_PRI2 22902 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 22903 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 22904 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 22905 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 22906 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 22907 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 22908 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 22909 #define MMEA4_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 22910 //MMEA4_DRAM_WR_PRI_QUANT_PRI3 22911 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 22912 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 22913 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 22914 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 22915 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 22916 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 22917 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 22918 #define MMEA4_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 22919 //MMEA4_GMI_RD_CLI2GRP_MAP0 22920 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 22921 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 22922 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 22923 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 22924 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 22925 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 22926 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 22927 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 22928 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 22929 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 22930 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 22931 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 22932 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 22933 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 22934 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 22935 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 22936 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 22937 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 22938 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 22939 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 22940 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 22941 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 22942 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 22943 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 22944 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 22945 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 22946 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 22947 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 22948 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 22949 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 22950 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 22951 #define MMEA4_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 22952 //MMEA4_GMI_RD_CLI2GRP_MAP1 22953 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 22954 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 22955 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 22956 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 22957 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 22958 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 22959 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 22960 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 22961 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 22962 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 22963 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 22964 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 22965 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 22966 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 22967 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 22968 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 22969 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 22970 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 22971 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 22972 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 22973 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 22974 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 22975 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 22976 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 22977 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 22978 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 22979 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 22980 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 22981 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 22982 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 22983 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 22984 #define MMEA4_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 22985 //MMEA4_GMI_WR_CLI2GRP_MAP0 22986 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 22987 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 22988 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 22989 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 22990 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 22991 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 22992 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 22993 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 22994 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 22995 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 22996 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 22997 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 22998 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 22999 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 23000 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 23001 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 23002 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 23003 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 23004 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 23005 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 23006 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 23007 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 23008 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 23009 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 23010 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 23011 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 23012 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 23013 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 23014 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 23015 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 23016 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 23017 #define MMEA4_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 23018 //MMEA4_GMI_WR_CLI2GRP_MAP1 23019 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 23020 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 23021 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 23022 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 23023 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 23024 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 23025 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 23026 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 23027 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 23028 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 23029 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 23030 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 23031 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 23032 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 23033 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 23034 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 23035 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 23036 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 23037 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 23038 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 23039 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 23040 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 23041 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 23042 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 23043 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 23044 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 23045 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 23046 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 23047 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 23048 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 23049 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 23050 #define MMEA4_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 23051 //MMEA4_GMI_RD_GRP2VC_MAP 23052 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 23053 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 23054 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 23055 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 23056 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 23057 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 23058 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 23059 #define MMEA4_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 23060 //MMEA4_GMI_WR_GRP2VC_MAP 23061 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 23062 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 23063 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 23064 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 23065 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 23066 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 23067 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 23068 #define MMEA4_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 23069 //MMEA4_GMI_RD_LAZY 23070 #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 23071 #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 23072 #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 23073 #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 23074 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 23075 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 23076 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 23077 #define MMEA4_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 23078 #define MMEA4_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 23079 #define MMEA4_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 23080 #define MMEA4_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 23081 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 23082 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 23083 #define MMEA4_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 23084 //MMEA4_GMI_WR_LAZY 23085 #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 23086 #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 23087 #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 23088 #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 23089 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 23090 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 23091 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 23092 #define MMEA4_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 23093 #define MMEA4_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 23094 #define MMEA4_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 23095 #define MMEA4_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 23096 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 23097 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 23098 #define MMEA4_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 23099 //MMEA4_GMI_RD_CAM_CNTL 23100 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 23101 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 23102 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 23103 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 23104 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 23105 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 23106 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 23107 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 23108 #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 23109 #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 23110 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 23111 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 23112 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 23113 #define MMEA4_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 23114 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 23115 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 23116 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 23117 #define MMEA4_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 23118 #define MMEA4_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 23119 #define MMEA4_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 23120 //MMEA4_GMI_WR_CAM_CNTL 23121 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 23122 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 23123 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 23124 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 23125 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 23126 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 23127 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 23128 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 23129 #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 23130 #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 23131 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 23132 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 23133 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 23134 #define MMEA4_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 23135 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 23136 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 23137 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 23138 #define MMEA4_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 23139 #define MMEA4_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 23140 #define MMEA4_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 23141 //MMEA4_GMI_PAGE_BURST 23142 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 23143 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 23144 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 23145 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 23146 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 23147 #define MMEA4_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 23148 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 23149 #define MMEA4_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 23150 //MMEA4_GMI_RD_PRI_AGE 23151 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 23152 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 23153 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 23154 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 23155 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 23156 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 23157 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 23158 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 23159 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 23160 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 23161 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 23162 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 23163 #define MMEA4_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 23164 #define MMEA4_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 23165 #define MMEA4_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 23166 #define MMEA4_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 23167 //MMEA4_GMI_WR_PRI_AGE 23168 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 23169 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 23170 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 23171 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 23172 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 23173 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 23174 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 23175 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 23176 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 23177 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 23178 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 23179 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 23180 #define MMEA4_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 23181 #define MMEA4_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 23182 #define MMEA4_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 23183 #define MMEA4_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 23184 //MMEA4_GMI_RD_PRI_QUEUING 23185 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 23186 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 23187 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 23188 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 23189 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 23190 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 23191 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 23192 #define MMEA4_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 23193 //MMEA4_GMI_WR_PRI_QUEUING 23194 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 23195 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 23196 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 23197 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 23198 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 23199 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 23200 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 23201 #define MMEA4_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 23202 //MMEA4_GMI_RD_PRI_FIXED 23203 #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 23204 #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 23205 #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 23206 #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 23207 #define MMEA4_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 23208 #define MMEA4_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 23209 #define MMEA4_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 23210 #define MMEA4_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 23211 //MMEA4_GMI_WR_PRI_FIXED 23212 #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 23213 #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 23214 #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 23215 #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 23216 #define MMEA4_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 23217 #define MMEA4_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 23218 #define MMEA4_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 23219 #define MMEA4_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 23220 //MMEA4_GMI_RD_PRI_URGENCY 23221 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 23222 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 23223 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 23224 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 23225 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 23226 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 23227 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 23228 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 23229 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 23230 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 23231 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 23232 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 23233 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 23234 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 23235 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 23236 #define MMEA4_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 23237 //MMEA4_GMI_WR_PRI_URGENCY 23238 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 23239 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 23240 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 23241 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 23242 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 23243 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 23244 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 23245 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 23246 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 23247 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 23248 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 23249 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 23250 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 23251 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 23252 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 23253 #define MMEA4_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 23254 //MMEA4_GMI_RD_PRI_URGENCY_MASKING 23255 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 23256 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 23257 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 23258 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 23259 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 23260 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 23261 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 23262 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 23263 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 23264 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 23265 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 23266 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 23267 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 23268 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 23269 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 23270 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 23271 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 23272 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 23273 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 23274 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 23275 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 23276 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 23277 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 23278 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 23279 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 23280 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 23281 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 23282 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 23283 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 23284 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 23285 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 23286 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 23287 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 23288 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 23289 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 23290 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 23291 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 23292 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 23293 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 23294 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 23295 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 23296 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 23297 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 23298 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 23299 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 23300 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 23301 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 23302 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 23303 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 23304 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 23305 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 23306 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 23307 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 23308 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 23309 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 23310 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 23311 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 23312 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 23313 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 23314 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 23315 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 23316 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 23317 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 23318 #define MMEA4_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 23319 //MMEA4_GMI_WR_PRI_URGENCY_MASKING 23320 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 23321 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 23322 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 23323 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 23324 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 23325 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 23326 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 23327 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 23328 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 23329 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 23330 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 23331 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 23332 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 23333 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 23334 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 23335 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 23336 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 23337 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 23338 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 23339 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 23340 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 23341 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 23342 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 23343 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 23344 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 23345 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 23346 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 23347 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 23348 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 23349 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 23350 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 23351 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 23352 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 23353 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 23354 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 23355 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 23356 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 23357 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 23358 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 23359 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 23360 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 23361 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 23362 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 23363 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 23364 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 23365 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 23366 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 23367 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 23368 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 23369 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 23370 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 23371 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 23372 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 23373 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 23374 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 23375 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 23376 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 23377 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 23378 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 23379 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 23380 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 23381 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 23382 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 23383 #define MMEA4_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 23384 //MMEA4_GMI_RD_PRI_QUANT_PRI1 23385 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 23386 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 23387 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 23388 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 23389 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 23390 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 23391 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 23392 #define MMEA4_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 23393 //MMEA4_GMI_RD_PRI_QUANT_PRI2 23394 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 23395 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 23396 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 23397 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 23398 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 23399 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 23400 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 23401 #define MMEA4_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 23402 //MMEA4_GMI_RD_PRI_QUANT_PRI3 23403 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 23404 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 23405 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 23406 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 23407 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 23408 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 23409 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 23410 #define MMEA4_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 23411 //MMEA4_GMI_WR_PRI_QUANT_PRI1 23412 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 23413 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 23414 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 23415 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 23416 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 23417 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 23418 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 23419 #define MMEA4_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 23420 //MMEA4_GMI_WR_PRI_QUANT_PRI2 23421 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 23422 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 23423 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 23424 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 23425 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 23426 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 23427 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 23428 #define MMEA4_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 23429 //MMEA4_GMI_WR_PRI_QUANT_PRI3 23430 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 23431 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 23432 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 23433 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 23434 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 23435 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 23436 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 23437 #define MMEA4_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 23438 //MMEA4_ADDRNORM_BASE_ADDR0 23439 #define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 23440 #define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 23441 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 23442 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 23443 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 23444 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 23445 #define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 23446 #define MMEA4_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 23447 #define MMEA4_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 23448 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 23449 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 23450 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 23451 #define MMEA4_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 23452 #define MMEA4_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 23453 //MMEA4_ADDRNORM_LIMIT_ADDR0 23454 #define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 23455 #define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 23456 #define MMEA4_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 23457 #define MMEA4_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 23458 //MMEA4_ADDRNORM_BASE_ADDR1 23459 #define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 23460 #define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 23461 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 23462 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 23463 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 23464 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 23465 #define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 23466 #define MMEA4_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 23467 #define MMEA4_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 23468 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 23469 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 23470 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 23471 #define MMEA4_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 23472 #define MMEA4_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 23473 //MMEA4_ADDRNORM_LIMIT_ADDR1 23474 #define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 23475 #define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 23476 #define MMEA4_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 23477 #define MMEA4_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 23478 //MMEA4_ADDRNORM_OFFSET_ADDR1 23479 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 23480 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc 23481 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 23482 #define MMEA4_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L 23483 //MMEA4_ADDRNORM_BASE_ADDR2 23484 #define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 23485 #define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 23486 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 23487 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 23488 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 23489 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 23490 #define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 23491 #define MMEA4_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 23492 #define MMEA4_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 23493 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL 23494 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L 23495 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 23496 #define MMEA4_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 23497 #define MMEA4_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 23498 //MMEA4_ADDRNORM_LIMIT_ADDR2 23499 #define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 23500 #define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 23501 #define MMEA4_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 23502 #define MMEA4_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 23503 //MMEA4_ADDRNORM_BASE_ADDR3 23504 #define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 23505 #define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 23506 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 23507 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 23508 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 23509 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 23510 #define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 23511 #define MMEA4_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 23512 #define MMEA4_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 23513 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL 23514 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L 23515 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 23516 #define MMEA4_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 23517 #define MMEA4_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 23518 //MMEA4_ADDRNORM_LIMIT_ADDR3 23519 #define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 23520 #define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 23521 #define MMEA4_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 23522 #define MMEA4_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 23523 //MMEA4_ADDRNORM_OFFSET_ADDR3 23524 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 23525 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc 23526 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 23527 #define MMEA4_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L 23528 //MMEA4_ADDRNORM_MEGABASE_ADDR0 23529 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 23530 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 23531 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 23532 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 23533 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 23534 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 23535 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc 23536 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 23537 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 23538 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 23539 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 23540 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 23541 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 23542 #define MMEA4_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 23543 //MMEA4_ADDRNORM_MEGALIMIT_ADDR0 23544 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 23545 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 23546 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 23547 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 23548 //MMEA4_ADDRNORM_MEGABASE_ADDR1 23549 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 23550 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 23551 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 23552 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 23553 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 23554 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 23555 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc 23556 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 23557 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 23558 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 23559 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 23560 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 23561 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 23562 #define MMEA4_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 23563 //MMEA4_ADDRNORM_MEGALIMIT_ADDR1 23564 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 23565 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 23566 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 23567 #define MMEA4_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 23568 //MMEA4_ADDRNORMDRAM_HOLE_CNTL 23569 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 23570 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 23571 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 23572 #define MMEA4_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 23573 //MMEA4_ADDRNORMGMI_HOLE_CNTL 23574 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 23575 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 23576 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 23577 #define MMEA4_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 23578 //MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG 23579 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 23580 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 23581 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 23582 #define MMEA4_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 23583 //MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG 23584 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 23585 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 23586 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 23587 #define MMEA4_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 23588 //MMEA4_ADDRDEC_BANK_CFG 23589 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 23590 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 23591 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 23592 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 23593 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 23594 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 23595 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 23596 #define MMEA4_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 23597 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 23598 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 23599 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 23600 #define MMEA4_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 23601 //MMEA4_ADDRDEC_MISC_CFG 23602 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 23603 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 23604 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 23605 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 23606 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 23607 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 23608 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 23609 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 23610 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 23611 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 23612 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 23613 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 23614 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 23615 #define MMEA4_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 23616 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 23617 #define MMEA4_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 23618 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 23619 #define MMEA4_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 23620 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 23621 #define MMEA4_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 23622 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 23623 #define MMEA4_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 23624 //MMEA4_ADDRDECDRAM_HARVEST_ENABLE 23625 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 23626 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 23627 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 23628 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 23629 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 23630 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 23631 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 23632 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 23633 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 23634 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 23635 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 23636 #define MMEA4_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 23637 //MMEA4_ADDRDECGMI_HARVEST_ENABLE 23638 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 23639 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 23640 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 23641 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 23642 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 23643 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 23644 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 23645 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 23646 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 23647 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 23648 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 23649 #define MMEA4_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 23650 //MMEA4_ADDRDEC0_BASE_ADDR_CS0 23651 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 23652 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 23653 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 23654 #define MMEA4_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 23655 //MMEA4_ADDRDEC0_BASE_ADDR_CS1 23656 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 23657 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 23658 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 23659 #define MMEA4_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 23660 //MMEA4_ADDRDEC0_BASE_ADDR_CS2 23661 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 23662 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 23663 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 23664 #define MMEA4_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 23665 //MMEA4_ADDRDEC0_BASE_ADDR_CS3 23666 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 23667 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 23668 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 23669 #define MMEA4_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 23670 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS0 23671 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 23672 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 23673 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 23674 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 23675 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS1 23676 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 23677 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 23678 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 23679 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 23680 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS2 23681 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 23682 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 23683 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 23684 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 23685 //MMEA4_ADDRDEC0_BASE_ADDR_SECCS3 23686 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 23687 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 23688 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 23689 #define MMEA4_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 23690 //MMEA4_ADDRDEC0_ADDR_MASK_CS01 23691 #define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 23692 #define MMEA4_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 23693 //MMEA4_ADDRDEC0_ADDR_MASK_CS23 23694 #define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 23695 #define MMEA4_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 23696 //MMEA4_ADDRDEC0_ADDR_MASK_SECCS01 23697 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 23698 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 23699 //MMEA4_ADDRDEC0_ADDR_MASK_SECCS23 23700 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 23701 #define MMEA4_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 23702 //MMEA4_ADDRDEC0_ADDR_CFG_CS01 23703 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 23704 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 23705 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 23706 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 23707 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 23708 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 23709 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 23710 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 23711 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 23712 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 23713 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 23714 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 23715 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 23716 #define MMEA4_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 23717 //MMEA4_ADDRDEC0_ADDR_CFG_CS23 23718 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 23719 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 23720 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 23721 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 23722 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 23723 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 23724 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 23725 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 23726 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 23727 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 23728 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 23729 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 23730 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 23731 #define MMEA4_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 23732 //MMEA4_ADDRDEC0_ADDR_SEL_CS01 23733 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 23734 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 23735 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 23736 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 23737 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 23738 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 23739 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 23740 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 23741 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 23742 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 23743 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 23744 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 23745 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 23746 #define MMEA4_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 23747 //MMEA4_ADDRDEC0_ADDR_SEL_CS23 23748 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 23749 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 23750 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 23751 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 23752 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 23753 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 23754 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 23755 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 23756 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 23757 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 23758 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 23759 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 23760 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 23761 #define MMEA4_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 23762 //MMEA4_ADDRDEC0_ADDR_SEL2_CS01 23763 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 23764 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 23765 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 23766 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 23767 //MMEA4_ADDRDEC0_ADDR_SEL2_CS23 23768 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 23769 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 23770 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 23771 #define MMEA4_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 23772 //MMEA4_ADDRDEC0_COL_SEL_LO_CS01 23773 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 23774 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 23775 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 23776 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 23777 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 23778 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 23779 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 23780 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 23781 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 23782 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 23783 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 23784 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 23785 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 23786 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 23787 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 23788 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 23789 //MMEA4_ADDRDEC0_COL_SEL_LO_CS23 23790 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 23791 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 23792 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 23793 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 23794 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 23795 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 23796 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 23797 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 23798 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 23799 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 23800 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 23801 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 23802 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 23803 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 23804 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 23805 #define MMEA4_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 23806 //MMEA4_ADDRDEC0_COL_SEL_HI_CS01 23807 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 23808 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 23809 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 23810 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 23811 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 23812 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 23813 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 23814 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 23815 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 23816 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 23817 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 23818 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 23819 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 23820 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 23821 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 23822 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 23823 //MMEA4_ADDRDEC0_COL_SEL_HI_CS23 23824 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 23825 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 23826 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 23827 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 23828 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 23829 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 23830 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 23831 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 23832 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 23833 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 23834 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 23835 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 23836 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 23837 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 23838 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 23839 #define MMEA4_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 23840 //MMEA4_ADDRDEC0_RM_SEL_CS01 23841 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 23842 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 23843 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 23844 #define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 23845 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 23846 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 23847 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 23848 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 23849 #define MMEA4_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 23850 #define MMEA4_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 23851 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 23852 #define MMEA4_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 23853 //MMEA4_ADDRDEC0_RM_SEL_CS23 23854 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 23855 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 23856 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 23857 #define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 23858 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 23859 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 23860 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 23861 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 23862 #define MMEA4_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 23863 #define MMEA4_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 23864 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 23865 #define MMEA4_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 23866 //MMEA4_ADDRDEC0_RM_SEL_SECCS01 23867 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 23868 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 23869 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 23870 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 23871 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 23872 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 23873 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 23874 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 23875 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 23876 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 23877 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 23878 #define MMEA4_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 23879 //MMEA4_ADDRDEC0_RM_SEL_SECCS23 23880 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 23881 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 23882 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 23883 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 23884 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 23885 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 23886 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 23887 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 23888 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 23889 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 23890 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 23891 #define MMEA4_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 23892 //MMEA4_ADDRDEC1_BASE_ADDR_CS0 23893 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 23894 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 23895 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 23896 #define MMEA4_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 23897 //MMEA4_ADDRDEC1_BASE_ADDR_CS1 23898 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 23899 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 23900 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 23901 #define MMEA4_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 23902 //MMEA4_ADDRDEC1_BASE_ADDR_CS2 23903 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 23904 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 23905 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 23906 #define MMEA4_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 23907 //MMEA4_ADDRDEC1_BASE_ADDR_CS3 23908 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 23909 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 23910 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 23911 #define MMEA4_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 23912 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS0 23913 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 23914 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 23915 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 23916 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 23917 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS1 23918 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 23919 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 23920 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 23921 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 23922 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS2 23923 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 23924 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 23925 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 23926 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 23927 //MMEA4_ADDRDEC1_BASE_ADDR_SECCS3 23928 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 23929 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 23930 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 23931 #define MMEA4_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 23932 //MMEA4_ADDRDEC1_ADDR_MASK_CS01 23933 #define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 23934 #define MMEA4_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 23935 //MMEA4_ADDRDEC1_ADDR_MASK_CS23 23936 #define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 23937 #define MMEA4_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 23938 //MMEA4_ADDRDEC1_ADDR_MASK_SECCS01 23939 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 23940 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 23941 //MMEA4_ADDRDEC1_ADDR_MASK_SECCS23 23942 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 23943 #define MMEA4_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 23944 //MMEA4_ADDRDEC1_ADDR_CFG_CS01 23945 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 23946 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 23947 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 23948 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 23949 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 23950 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 23951 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 23952 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 23953 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 23954 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 23955 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 23956 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 23957 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 23958 #define MMEA4_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 23959 //MMEA4_ADDRDEC1_ADDR_CFG_CS23 23960 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 23961 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 23962 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 23963 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 23964 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 23965 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 23966 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 23967 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 23968 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 23969 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 23970 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 23971 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 23972 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 23973 #define MMEA4_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 23974 //MMEA4_ADDRDEC1_ADDR_SEL_CS01 23975 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 23976 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 23977 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 23978 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 23979 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 23980 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 23981 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 23982 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 23983 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 23984 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 23985 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 23986 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 23987 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 23988 #define MMEA4_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 23989 //MMEA4_ADDRDEC1_ADDR_SEL_CS23 23990 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 23991 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 23992 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 23993 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 23994 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 23995 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 23996 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 23997 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 23998 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 23999 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 24000 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 24001 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 24002 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 24003 #define MMEA4_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 24004 //MMEA4_ADDRDEC1_ADDR_SEL2_CS01 24005 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 24006 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 24007 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 24008 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 24009 //MMEA4_ADDRDEC1_ADDR_SEL2_CS23 24010 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 24011 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 24012 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 24013 #define MMEA4_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 24014 //MMEA4_ADDRDEC1_COL_SEL_LO_CS01 24015 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 24016 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 24017 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 24018 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 24019 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 24020 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 24021 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 24022 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 24023 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 24024 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 24025 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 24026 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 24027 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 24028 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 24029 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 24030 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 24031 //MMEA4_ADDRDEC1_COL_SEL_LO_CS23 24032 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 24033 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 24034 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 24035 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 24036 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 24037 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 24038 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 24039 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 24040 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 24041 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 24042 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 24043 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 24044 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 24045 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 24046 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 24047 #define MMEA4_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 24048 //MMEA4_ADDRDEC1_COL_SEL_HI_CS01 24049 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 24050 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 24051 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 24052 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 24053 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 24054 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 24055 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 24056 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 24057 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 24058 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 24059 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 24060 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 24061 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 24062 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 24063 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 24064 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 24065 //MMEA4_ADDRDEC1_COL_SEL_HI_CS23 24066 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 24067 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 24068 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 24069 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 24070 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 24071 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 24072 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 24073 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 24074 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 24075 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 24076 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 24077 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 24078 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 24079 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 24080 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 24081 #define MMEA4_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 24082 //MMEA4_ADDRDEC1_RM_SEL_CS01 24083 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 24084 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 24085 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 24086 #define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 24087 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24088 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24089 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 24090 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 24091 #define MMEA4_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 24092 #define MMEA4_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 24093 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24094 #define MMEA4_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24095 //MMEA4_ADDRDEC1_RM_SEL_CS23 24096 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 24097 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 24098 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 24099 #define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 24100 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24101 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24102 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 24103 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 24104 #define MMEA4_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 24105 #define MMEA4_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 24106 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24107 #define MMEA4_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24108 //MMEA4_ADDRDEC1_RM_SEL_SECCS01 24109 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 24110 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 24111 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 24112 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 24113 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24114 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24115 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 24116 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 24117 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 24118 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 24119 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24120 #define MMEA4_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24121 //MMEA4_ADDRDEC1_RM_SEL_SECCS23 24122 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 24123 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 24124 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 24125 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 24126 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24127 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24128 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 24129 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 24130 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 24131 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 24132 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24133 #define MMEA4_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24134 //MMEA4_ADDRDEC2_BASE_ADDR_CS0 24135 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 24136 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 24137 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 24138 #define MMEA4_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 24139 //MMEA4_ADDRDEC2_BASE_ADDR_CS1 24140 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 24141 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 24142 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 24143 #define MMEA4_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 24144 //MMEA4_ADDRDEC2_BASE_ADDR_CS2 24145 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 24146 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 24147 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 24148 #define MMEA4_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 24149 //MMEA4_ADDRDEC2_BASE_ADDR_CS3 24150 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 24151 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 24152 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 24153 #define MMEA4_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 24154 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS0 24155 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 24156 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 24157 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 24158 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 24159 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS1 24160 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 24161 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 24162 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 24163 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 24164 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS2 24165 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 24166 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 24167 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 24168 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 24169 //MMEA4_ADDRDEC2_BASE_ADDR_SECCS3 24170 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 24171 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 24172 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 24173 #define MMEA4_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 24174 //MMEA4_ADDRDEC2_ADDR_MASK_CS01 24175 #define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 24176 #define MMEA4_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 24177 //MMEA4_ADDRDEC2_ADDR_MASK_CS23 24178 #define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 24179 #define MMEA4_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 24180 //MMEA4_ADDRDEC2_ADDR_MASK_SECCS01 24181 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 24182 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 24183 //MMEA4_ADDRDEC2_ADDR_MASK_SECCS23 24184 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 24185 #define MMEA4_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 24186 //MMEA4_ADDRDEC2_ADDR_CFG_CS01 24187 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 24188 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 24189 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 24190 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 24191 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 24192 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 24193 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 24194 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 24195 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 24196 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 24197 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 24198 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 24199 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 24200 #define MMEA4_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 24201 //MMEA4_ADDRDEC2_ADDR_CFG_CS23 24202 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 24203 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 24204 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 24205 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 24206 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 24207 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 24208 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 24209 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 24210 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 24211 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 24212 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 24213 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 24214 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 24215 #define MMEA4_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 24216 //MMEA4_ADDRDEC2_ADDR_SEL_CS01 24217 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 24218 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 24219 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 24220 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 24221 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 24222 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 24223 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 24224 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 24225 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 24226 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 24227 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 24228 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 24229 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 24230 #define MMEA4_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 24231 //MMEA4_ADDRDEC2_ADDR_SEL_CS23 24232 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 24233 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 24234 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 24235 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 24236 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 24237 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 24238 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 24239 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 24240 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 24241 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 24242 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 24243 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 24244 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 24245 #define MMEA4_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 24246 //MMEA4_ADDRDEC2_ADDR_SEL2_CS01 24247 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 24248 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 24249 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 24250 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 24251 //MMEA4_ADDRDEC2_ADDR_SEL2_CS23 24252 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 24253 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 24254 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 24255 #define MMEA4_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 24256 //MMEA4_ADDRDEC2_COL_SEL_LO_CS01 24257 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 24258 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 24259 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 24260 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 24261 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 24262 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 24263 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 24264 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 24265 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 24266 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 24267 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 24268 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 24269 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 24270 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 24271 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 24272 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 24273 //MMEA4_ADDRDEC2_COL_SEL_LO_CS23 24274 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 24275 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 24276 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 24277 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 24278 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 24279 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 24280 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 24281 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 24282 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 24283 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 24284 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 24285 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 24286 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 24287 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 24288 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 24289 #define MMEA4_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 24290 //MMEA4_ADDRDEC2_COL_SEL_HI_CS01 24291 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 24292 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 24293 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 24294 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 24295 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 24296 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 24297 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 24298 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 24299 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 24300 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 24301 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 24302 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 24303 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 24304 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 24305 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 24306 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 24307 //MMEA4_ADDRDEC2_COL_SEL_HI_CS23 24308 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 24309 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 24310 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 24311 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 24312 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 24313 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 24314 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 24315 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 24316 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 24317 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 24318 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 24319 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 24320 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 24321 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 24322 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 24323 #define MMEA4_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 24324 //MMEA4_ADDRDEC2_RM_SEL_CS01 24325 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 24326 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 24327 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 24328 #define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 24329 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24330 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24331 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 24332 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 24333 #define MMEA4_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 24334 #define MMEA4_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 24335 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24336 #define MMEA4_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24337 //MMEA4_ADDRDEC2_RM_SEL_CS23 24338 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 24339 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 24340 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 24341 #define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 24342 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24343 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24344 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 24345 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 24346 #define MMEA4_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 24347 #define MMEA4_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 24348 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24349 #define MMEA4_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24350 //MMEA4_ADDRDEC2_RM_SEL_SECCS01 24351 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 24352 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 24353 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 24354 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 24355 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24356 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24357 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 24358 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 24359 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 24360 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 24361 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24362 #define MMEA4_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24363 //MMEA4_ADDRDEC2_RM_SEL_SECCS23 24364 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 24365 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 24366 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 24367 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 24368 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 24369 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 24370 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 24371 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 24372 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 24373 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 24374 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 24375 #define MMEA4_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 24376 //MMEA4_ADDRNORMDRAM_GLOBAL_CNTL 24377 //MMEA4_ADDRNORMGMI_GLOBAL_CNTL 24378 //MMEA4_ADDRNORM_MEGACONTROL_ADDR0 24379 #define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 24380 #define MMEA4_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 24381 //MMEA4_ADDRNORM_MEGACONTROL_ADDR1 24382 #define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 24383 #define MMEA4_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 24384 //MMEA4_ADDRNORMDRAM_MASKING 24385 #define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 24386 #define MMEA4_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 24387 //MMEA4_ADDRNORMGMI_MASKING 24388 #define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 24389 #define MMEA4_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 24390 //MMEA4_IO_RD_CLI2GRP_MAP0 24391 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 24392 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 24393 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 24394 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 24395 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 24396 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 24397 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 24398 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 24399 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 24400 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 24401 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 24402 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 24403 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 24404 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 24405 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 24406 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 24407 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 24408 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 24409 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 24410 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 24411 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 24412 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 24413 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 24414 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 24415 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 24416 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 24417 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 24418 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 24419 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 24420 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 24421 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 24422 #define MMEA4_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 24423 //MMEA4_IO_RD_CLI2GRP_MAP1 24424 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 24425 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 24426 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 24427 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 24428 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 24429 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 24430 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 24431 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 24432 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 24433 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 24434 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 24435 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 24436 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 24437 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 24438 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 24439 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 24440 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 24441 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 24442 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 24443 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 24444 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 24445 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 24446 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 24447 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 24448 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 24449 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 24450 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 24451 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 24452 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 24453 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 24454 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 24455 #define MMEA4_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 24456 //MMEA4_IO_WR_CLI2GRP_MAP0 24457 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 24458 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 24459 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 24460 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 24461 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 24462 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 24463 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 24464 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 24465 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 24466 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 24467 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 24468 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 24469 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 24470 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 24471 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 24472 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 24473 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 24474 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 24475 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 24476 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 24477 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 24478 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 24479 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 24480 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 24481 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 24482 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 24483 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 24484 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 24485 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 24486 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 24487 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 24488 #define MMEA4_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 24489 //MMEA4_IO_WR_CLI2GRP_MAP1 24490 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 24491 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 24492 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 24493 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 24494 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 24495 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 24496 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 24497 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 24498 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 24499 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 24500 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 24501 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 24502 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 24503 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 24504 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 24505 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 24506 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 24507 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 24508 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 24509 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 24510 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 24511 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 24512 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 24513 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 24514 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 24515 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 24516 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 24517 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 24518 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 24519 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 24520 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 24521 #define MMEA4_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 24522 //MMEA4_IO_RD_COMBINE_FLUSH 24523 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 24524 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 24525 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 24526 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 24527 #define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 24528 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 24529 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 24530 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 24531 #define MMEA4_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 24532 #define MMEA4_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 24533 //MMEA4_IO_WR_COMBINE_FLUSH 24534 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 24535 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 24536 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 24537 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 24538 #define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 24539 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 24540 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 24541 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 24542 #define MMEA4_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 24543 #define MMEA4_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 24544 //MMEA4_IO_GROUP_BURST 24545 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 24546 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 24547 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 24548 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 24549 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 24550 #define MMEA4_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 24551 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 24552 #define MMEA4_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 24553 //MMEA4_IO_RD_PRI_AGE 24554 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 24555 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 24556 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 24557 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 24558 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 24559 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 24560 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 24561 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 24562 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 24563 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 24564 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 24565 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 24566 #define MMEA4_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 24567 #define MMEA4_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 24568 #define MMEA4_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 24569 #define MMEA4_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 24570 //MMEA4_IO_WR_PRI_AGE 24571 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 24572 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 24573 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 24574 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 24575 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 24576 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 24577 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 24578 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 24579 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 24580 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 24581 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 24582 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 24583 #define MMEA4_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 24584 #define MMEA4_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 24585 #define MMEA4_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 24586 #define MMEA4_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 24587 //MMEA4_IO_RD_PRI_QUEUING 24588 #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 24589 #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 24590 #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 24591 #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 24592 #define MMEA4_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 24593 #define MMEA4_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 24594 #define MMEA4_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 24595 #define MMEA4_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 24596 //MMEA4_IO_WR_PRI_QUEUING 24597 #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 24598 #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 24599 #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 24600 #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 24601 #define MMEA4_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 24602 #define MMEA4_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 24603 #define MMEA4_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 24604 #define MMEA4_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 24605 //MMEA4_IO_RD_PRI_FIXED 24606 #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 24607 #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 24608 #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 24609 #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 24610 #define MMEA4_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 24611 #define MMEA4_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 24612 #define MMEA4_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 24613 #define MMEA4_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 24614 //MMEA4_IO_WR_PRI_FIXED 24615 #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 24616 #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 24617 #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 24618 #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 24619 #define MMEA4_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 24620 #define MMEA4_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 24621 #define MMEA4_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 24622 #define MMEA4_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 24623 //MMEA4_IO_RD_PRI_URGENCY 24624 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 24625 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 24626 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 24627 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 24628 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 24629 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 24630 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 24631 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 24632 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 24633 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 24634 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 24635 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 24636 #define MMEA4_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 24637 #define MMEA4_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 24638 #define MMEA4_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 24639 #define MMEA4_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 24640 //MMEA4_IO_WR_PRI_URGENCY 24641 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 24642 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 24643 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 24644 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 24645 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 24646 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 24647 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 24648 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 24649 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 24650 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 24651 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 24652 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 24653 #define MMEA4_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 24654 #define MMEA4_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 24655 #define MMEA4_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 24656 #define MMEA4_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 24657 //MMEA4_IO_RD_PRI_URGENCY_MASKING 24658 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 24659 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 24660 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 24661 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 24662 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 24663 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 24664 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 24665 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 24666 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 24667 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 24668 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 24669 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 24670 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 24671 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 24672 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 24673 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 24674 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 24675 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 24676 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 24677 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 24678 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 24679 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 24680 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 24681 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 24682 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 24683 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 24684 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 24685 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 24686 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 24687 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 24688 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 24689 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 24690 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 24691 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 24692 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 24693 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 24694 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 24695 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 24696 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 24697 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 24698 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 24699 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 24700 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 24701 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 24702 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 24703 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 24704 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 24705 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 24706 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 24707 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 24708 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 24709 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 24710 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 24711 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 24712 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 24713 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 24714 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 24715 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 24716 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 24717 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 24718 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 24719 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 24720 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 24721 #define MMEA4_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 24722 //MMEA4_IO_WR_PRI_URGENCY_MASKING 24723 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 24724 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 24725 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 24726 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 24727 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 24728 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 24729 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 24730 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 24731 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 24732 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 24733 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 24734 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 24735 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 24736 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 24737 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 24738 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 24739 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 24740 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 24741 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 24742 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 24743 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 24744 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 24745 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 24746 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 24747 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 24748 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 24749 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 24750 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 24751 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 24752 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 24753 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 24754 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 24755 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 24756 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 24757 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 24758 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 24759 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 24760 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 24761 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 24762 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 24763 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 24764 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 24765 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 24766 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 24767 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 24768 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 24769 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 24770 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 24771 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 24772 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 24773 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 24774 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 24775 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 24776 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 24777 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 24778 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 24779 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 24780 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 24781 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 24782 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 24783 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 24784 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 24785 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 24786 #define MMEA4_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 24787 //MMEA4_IO_RD_PRI_QUANT_PRI1 24788 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 24789 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 24790 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 24791 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 24792 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 24793 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 24794 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 24795 #define MMEA4_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 24796 //MMEA4_IO_RD_PRI_QUANT_PRI2 24797 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 24798 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 24799 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 24800 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 24801 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 24802 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 24803 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 24804 #define MMEA4_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 24805 //MMEA4_IO_RD_PRI_QUANT_PRI3 24806 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 24807 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 24808 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 24809 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 24810 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 24811 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 24812 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 24813 #define MMEA4_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 24814 //MMEA4_IO_WR_PRI_QUANT_PRI1 24815 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 24816 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 24817 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 24818 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 24819 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 24820 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 24821 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 24822 #define MMEA4_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 24823 //MMEA4_IO_WR_PRI_QUANT_PRI2 24824 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 24825 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 24826 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 24827 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 24828 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 24829 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 24830 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 24831 #define MMEA4_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 24832 //MMEA4_IO_WR_PRI_QUANT_PRI3 24833 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 24834 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 24835 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 24836 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 24837 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 24838 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 24839 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 24840 #define MMEA4_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 24841 //MMEA4_SDP_ARB_DRAM 24842 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 24843 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 24844 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 24845 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 24846 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 24847 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 24848 #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 24849 #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 24850 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 24851 #define MMEA4_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 24852 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 24853 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 24854 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 24855 #define MMEA4_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 24856 #define MMEA4_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 24857 #define MMEA4_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 24858 //MMEA4_SDP_ARB_GMI 24859 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 24860 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 24861 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 24862 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 24863 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 24864 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 24865 #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 24866 #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 24867 #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 24868 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 24869 #define MMEA4_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 24870 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 24871 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 24872 #define MMEA4_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 24873 #define MMEA4_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 24874 #define MMEA4_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 24875 #define MMEA4_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 24876 #define MMEA4_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 24877 //MMEA4_SDP_ARB_FINAL 24878 #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 24879 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 24880 #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 24881 #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 24882 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 24883 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 24884 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 24885 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 24886 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 24887 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 24888 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 24889 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 24890 #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 24891 #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 24892 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 24893 #define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c 24894 #define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d 24895 #define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e 24896 #define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f 24897 #define MMEA4_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 24898 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 24899 #define MMEA4_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 24900 #define MMEA4_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 24901 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 24902 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 24903 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 24904 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 24905 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 24906 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 24907 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 24908 #define MMEA4_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 24909 #define MMEA4_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 24910 #define MMEA4_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 24911 #define MMEA4_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 24912 #define MMEA4_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L 24913 #define MMEA4_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L 24914 #define MMEA4_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L 24915 #define MMEA4_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L 24916 //MMEA4_SDP_DRAM_PRIORITY 24917 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 24918 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 24919 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 24920 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 24921 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 24922 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 24923 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 24924 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 24925 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 24926 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 24927 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 24928 #define MMEA4_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 24929 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 24930 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 24931 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 24932 #define MMEA4_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 24933 //MMEA4_SDP_GMI_PRIORITY 24934 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 24935 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 24936 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 24937 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 24938 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 24939 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 24940 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 24941 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 24942 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 24943 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 24944 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 24945 #define MMEA4_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 24946 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 24947 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 24948 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 24949 #define MMEA4_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 24950 //MMEA4_SDP_IO_PRIORITY 24951 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 24952 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 24953 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 24954 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 24955 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 24956 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 24957 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 24958 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 24959 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 24960 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 24961 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 24962 #define MMEA4_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 24963 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 24964 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 24965 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 24966 #define MMEA4_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 24967 //MMEA4_SDP_CREDITS 24968 #define MMEA4_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 24969 #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 24970 #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 24971 #define MMEA4_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 24972 #define MMEA4_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 24973 #define MMEA4_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 24974 //MMEA4_SDP_TAG_RESERVE0 24975 #define MMEA4_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 24976 #define MMEA4_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 24977 #define MMEA4_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 24978 #define MMEA4_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 24979 #define MMEA4_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 24980 #define MMEA4_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 24981 #define MMEA4_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 24982 #define MMEA4_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 24983 //MMEA4_SDP_TAG_RESERVE1 24984 #define MMEA4_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 24985 #define MMEA4_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 24986 #define MMEA4_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 24987 #define MMEA4_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 24988 #define MMEA4_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 24989 #define MMEA4_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 24990 #define MMEA4_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 24991 #define MMEA4_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 24992 //MMEA4_SDP_VCC_RESERVE0 24993 #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 24994 #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 24995 #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 24996 #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 24997 #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 24998 #define MMEA4_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 24999 #define MMEA4_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 25000 #define MMEA4_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 25001 #define MMEA4_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 25002 #define MMEA4_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 25003 //MMEA4_SDP_VCC_RESERVE1 25004 #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 25005 #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 25006 #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 25007 #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 25008 #define MMEA4_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 25009 #define MMEA4_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 25010 #define MMEA4_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 25011 #define MMEA4_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 25012 //MMEA4_SDP_VCD_RESERVE0 25013 #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 25014 #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 25015 #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 25016 #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 25017 #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 25018 #define MMEA4_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 25019 #define MMEA4_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 25020 #define MMEA4_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 25021 #define MMEA4_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 25022 #define MMEA4_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 25023 //MMEA4_SDP_VCD_RESERVE1 25024 #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 25025 #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 25026 #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 25027 #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 25028 #define MMEA4_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 25029 #define MMEA4_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 25030 #define MMEA4_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 25031 #define MMEA4_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 25032 //MMEA4_SDP_REQ_CNTL 25033 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 25034 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 25035 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 25036 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 25037 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 25038 #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 25039 #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 25040 #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 25041 #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 25042 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 25043 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 25044 #define MMEA4_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 25045 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 25046 #define MMEA4_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 25047 #define MMEA4_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 25048 #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 25049 #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 25050 #define MMEA4_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 25051 //MMEA4_MISC 25052 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 25053 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 25054 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 25055 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 25056 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 25057 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 25058 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 25059 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 25060 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 25061 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 25062 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 25063 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 25064 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 25065 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 25066 #define MMEA4_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 25067 #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 25068 #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 25069 #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 25070 #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 25071 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 25072 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 25073 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 25074 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 25075 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 25076 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 25077 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 25078 #define MMEA4_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 25079 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 25080 #define MMEA4_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 25081 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 25082 #define MMEA4_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 25083 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 25084 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 25085 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 25086 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 25087 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 25088 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 25089 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 25090 #define MMEA4_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 25091 #define MMEA4_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 25092 #define MMEA4_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 25093 #define MMEA4_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 25094 #define MMEA4_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 25095 #define MMEA4_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 25096 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 25097 #define MMEA4_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 25098 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 25099 #define MMEA4_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 25100 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 25101 #define MMEA4_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 25102 //MMEA4_LATENCY_SAMPLING 25103 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 25104 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 25105 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 25106 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 25107 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 25108 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 25109 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 25110 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 25111 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 25112 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 25113 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 25114 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 25115 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 25116 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 25117 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 25118 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 25119 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 25120 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 25121 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 25122 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 25123 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 25124 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 25125 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 25126 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 25127 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 25128 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 25129 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 25130 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 25131 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 25132 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 25133 #define MMEA4_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 25134 #define MMEA4_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 25135 //MMEA4_PERFCOUNTER_LO 25136 #define MMEA4_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 25137 #define MMEA4_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 25138 //MMEA4_PERFCOUNTER_HI 25139 #define MMEA4_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 25140 #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 25141 #define MMEA4_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 25142 #define MMEA4_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 25143 //MMEA4_PERFCOUNTER0_CFG 25144 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 25145 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 25146 #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 25147 #define MMEA4_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 25148 #define MMEA4_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 25149 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 25150 #define MMEA4_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 25151 #define MMEA4_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 25152 #define MMEA4_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 25153 #define MMEA4_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 25154 //MMEA4_PERFCOUNTER1_CFG 25155 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 25156 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 25157 #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 25158 #define MMEA4_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 25159 #define MMEA4_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 25160 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 25161 #define MMEA4_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 25162 #define MMEA4_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 25163 #define MMEA4_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 25164 #define MMEA4_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 25165 //MMEA4_PERFCOUNTER_RSLT_CNTL 25166 #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 25167 #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 25168 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 25169 #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 25170 #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 25171 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 25172 #define MMEA4_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 25173 #define MMEA4_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 25174 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 25175 #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 25176 #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 25177 #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 25178 //MMEA4_EDC_CNT 25179 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 25180 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 25181 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 25182 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 25183 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 25184 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 25185 #define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 25186 #define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 25187 #define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 25188 #define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 25189 #define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 25190 #define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 25191 #define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 25192 #define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a 25193 #define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c 25194 #define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e 25195 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 25196 #define MMEA4_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 25197 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 25198 #define MMEA4_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 25199 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 25200 #define MMEA4_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 25201 #define MMEA4_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 25202 #define MMEA4_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 25203 #define MMEA4_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 25204 #define MMEA4_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 25205 #define MMEA4_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L 25206 #define MMEA4_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L 25207 #define MMEA4_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L 25208 #define MMEA4_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L 25209 #define MMEA4_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L 25210 #define MMEA4_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L 25211 //MMEA4_EDC_CNT2 25212 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 25213 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 25214 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 25215 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 25216 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 25217 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 25218 #define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 25219 #define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 25220 #define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 25221 #define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 25222 #define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 25223 #define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 25224 #define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 25225 #define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 25226 #define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 25227 #define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 25228 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 25229 #define MMEA4_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 25230 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 25231 #define MMEA4_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 25232 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 25233 #define MMEA4_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 25234 #define MMEA4_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 25235 #define MMEA4_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 25236 #define MMEA4_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 25237 #define MMEA4_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 25238 #define MMEA4_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 25239 #define MMEA4_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 25240 #define MMEA4_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 25241 #define MMEA4_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 25242 #define MMEA4_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 25243 #define MMEA4_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 25244 //MMEA4_DSM_CNTL 25245 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 25246 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 25247 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 25248 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 25249 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 25250 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 25251 #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 25252 #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 25253 #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 25254 #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 25255 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 25256 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 25257 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 25258 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 25259 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 25260 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 25261 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 25262 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 25263 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 25264 #define MMEA4_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 25265 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 25266 #define MMEA4_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 25267 #define MMEA4_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 25268 #define MMEA4_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 25269 #define MMEA4_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 25270 #define MMEA4_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 25271 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 25272 #define MMEA4_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 25273 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 25274 #define MMEA4_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 25275 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 25276 #define MMEA4_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 25277 //MMEA4_DSM_CNTLA 25278 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 25279 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 25280 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 25281 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 25282 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 25283 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 25284 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 25285 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 25286 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 25287 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 25288 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 25289 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 25290 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 25291 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 25292 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 25293 #define MMEA4_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 25294 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 25295 #define MMEA4_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 25296 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 25297 #define MMEA4_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 25298 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 25299 #define MMEA4_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 25300 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 25301 #define MMEA4_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 25302 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 25303 #define MMEA4_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 25304 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 25305 #define MMEA4_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 25306 //MMEA4_DSM_CNTLB 25307 //MMEA4_DSM_CNTL2 25308 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 25309 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 25310 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 25311 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 25312 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 25313 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 25314 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 25315 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 25316 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 25317 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 25318 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 25319 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 25320 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 25321 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 25322 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 25323 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 25324 #define MMEA4_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 25325 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 25326 #define MMEA4_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 25327 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 25328 #define MMEA4_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 25329 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 25330 #define MMEA4_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 25331 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 25332 #define MMEA4_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 25333 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 25334 #define MMEA4_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 25335 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 25336 #define MMEA4_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 25337 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 25338 #define MMEA4_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 25339 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 25340 #define MMEA4_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 25341 #define MMEA4_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 25342 //MMEA4_DSM_CNTL2A 25343 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 25344 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 25345 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 25346 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 25347 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 25348 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 25349 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 25350 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 25351 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 25352 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 25353 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 25354 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 25355 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 25356 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 25357 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 25358 #define MMEA4_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 25359 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 25360 #define MMEA4_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 25361 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 25362 #define MMEA4_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 25363 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 25364 #define MMEA4_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 25365 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 25366 #define MMEA4_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 25367 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 25368 #define MMEA4_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 25369 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 25370 #define MMEA4_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 25371 //MMEA4_DSM_CNTL2B 25372 //MMEA4_CGTT_CLK_CTRL 25373 #define MMEA4_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 25374 #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 25375 #define MMEA4_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 25376 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 25377 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 25378 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 25379 #define MMEA4_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 25380 #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 25381 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 25382 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 25383 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 25384 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 25385 #define MMEA4_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 25386 #define MMEA4_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 25387 #define MMEA4_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 25388 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 25389 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 25390 #define MMEA4_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 25391 #define MMEA4_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 25392 #define MMEA4_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 25393 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 25394 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 25395 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 25396 #define MMEA4_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 25397 //MMEA4_EDC_MODE 25398 #define MMEA4_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 25399 #define MMEA4_EDC_MODE__GATE_FUE__SHIFT 0x11 25400 #define MMEA4_EDC_MODE__DED_MODE__SHIFT 0x14 25401 #define MMEA4_EDC_MODE__PROP_FED__SHIFT 0x1d 25402 #define MMEA4_EDC_MODE__BYPASS__SHIFT 0x1f 25403 #define MMEA4_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 25404 #define MMEA4_EDC_MODE__GATE_FUE_MASK 0x00020000L 25405 #define MMEA4_EDC_MODE__DED_MODE_MASK 0x00300000L 25406 #define MMEA4_EDC_MODE__PROP_FED_MASK 0x20000000L 25407 #define MMEA4_EDC_MODE__BYPASS_MASK 0x80000000L 25408 //MMEA4_ERR_STATUS 25409 #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 25410 #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 25411 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 25412 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 25413 #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 25414 #define MMEA4_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 25415 #define MMEA4_ERR_STATUS__FUE_FLAG__SHIFT 0xd 25416 #define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 25417 #define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 25418 #define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 25419 #define MMEA4_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 25420 #define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 25421 #define MMEA4_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 25422 #define MMEA4_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 25423 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 25424 #define MMEA4_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 25425 #define MMEA4_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 25426 #define MMEA4_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 25427 #define MMEA4_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 25428 #define MMEA4_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 25429 #define MMEA4_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 25430 #define MMEA4_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 25431 #define MMEA4_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 25432 #define MMEA4_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 25433 //MMEA4_MISC2 25434 #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 25435 #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 25436 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 25437 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 25438 #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 25439 #define MMEA4_MISC2__RRET_SWAP_MODE__SHIFT 0xd 25440 #define MMEA4_MISC2__BLOCK_REQUESTS__SHIFT 0xe 25441 #define MMEA4_MISC2__REQUESTS_BLOCKED__SHIFT 0xf 25442 #define MMEA4_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 25443 #define MMEA4_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 25444 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 25445 #define MMEA4_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 25446 #define MMEA4_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 25447 #define MMEA4_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 25448 #define MMEA4_MISC2__BLOCK_REQUESTS_MASK 0x00004000L 25449 #define MMEA4_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L 25450 //MMEA4_ADDRDEC_SELECT 25451 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 25452 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 25453 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 25454 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 25455 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 25456 #define MMEA4_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 25457 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 25458 #define MMEA4_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 25459 //MMEA4_EDC_CNT3 25460 #define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 25461 #define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 25462 #define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 25463 #define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 25464 #define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 25465 #define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa 25466 #define MMEA4_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 25467 #define MMEA4_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 25468 #define MMEA4_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 25469 #define MMEA4_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 25470 #define MMEA4_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L 25471 #define MMEA4_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L 25472 //MMEA4_MISC_AON 25473 #define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 25474 #define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 25475 #define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 25476 #define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 25477 25478 25479 // addressBlock: mmhub_ea_mmeadec5 25480 //MMEA5_DRAM_RD_CLI2GRP_MAP0 25481 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 25482 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 25483 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 25484 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 25485 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 25486 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 25487 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 25488 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 25489 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 25490 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 25491 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 25492 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 25493 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 25494 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 25495 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 25496 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 25497 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 25498 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 25499 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 25500 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 25501 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 25502 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 25503 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 25504 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 25505 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 25506 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 25507 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 25508 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 25509 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 25510 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 25511 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 25512 #define MMEA5_DRAM_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 25513 //MMEA5_DRAM_RD_CLI2GRP_MAP1 25514 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 25515 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 25516 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 25517 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 25518 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 25519 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 25520 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 25521 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 25522 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 25523 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 25524 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 25525 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 25526 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 25527 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 25528 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 25529 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 25530 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 25531 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 25532 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 25533 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 25534 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 25535 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 25536 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 25537 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 25538 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 25539 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 25540 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 25541 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 25542 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 25543 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 25544 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 25545 #define MMEA5_DRAM_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 25546 //MMEA5_DRAM_WR_CLI2GRP_MAP0 25547 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 25548 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 25549 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 25550 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 25551 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 25552 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 25553 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 25554 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 25555 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 25556 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 25557 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 25558 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 25559 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 25560 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 25561 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 25562 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 25563 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 25564 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 25565 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 25566 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 25567 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 25568 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 25569 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 25570 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 25571 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 25572 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 25573 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 25574 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 25575 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 25576 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 25577 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 25578 #define MMEA5_DRAM_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 25579 //MMEA5_DRAM_WR_CLI2GRP_MAP1 25580 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 25581 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 25582 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 25583 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 25584 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 25585 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 25586 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 25587 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 25588 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 25589 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 25590 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 25591 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 25592 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 25593 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 25594 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 25595 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 25596 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 25597 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 25598 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 25599 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 25600 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 25601 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 25602 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 25603 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 25604 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 25605 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 25606 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 25607 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 25608 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 25609 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 25610 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 25611 #define MMEA5_DRAM_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 25612 //MMEA5_DRAM_RD_GRP2VC_MAP 25613 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 25614 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 25615 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 25616 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 25617 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 25618 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 25619 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 25620 #define MMEA5_DRAM_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 25621 //MMEA5_DRAM_WR_GRP2VC_MAP 25622 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 25623 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 25624 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 25625 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 25626 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 25627 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 25628 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 25629 #define MMEA5_DRAM_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 25630 //MMEA5_DRAM_RD_LAZY 25631 #define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 25632 #define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 25633 #define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 25634 #define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 25635 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 25636 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 25637 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 25638 #define MMEA5_DRAM_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 25639 #define MMEA5_DRAM_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 25640 #define MMEA5_DRAM_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 25641 #define MMEA5_DRAM_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 25642 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 25643 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 25644 #define MMEA5_DRAM_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 25645 //MMEA5_DRAM_WR_LAZY 25646 #define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 25647 #define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 25648 #define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 25649 #define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 25650 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 25651 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 25652 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 25653 #define MMEA5_DRAM_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 25654 #define MMEA5_DRAM_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 25655 #define MMEA5_DRAM_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 25656 #define MMEA5_DRAM_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 25657 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 25658 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 25659 #define MMEA5_DRAM_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 25660 //MMEA5_DRAM_RD_CAM_CNTL 25661 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 25662 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 25663 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 25664 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 25665 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 25666 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 25667 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 25668 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 25669 #define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 25670 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 25671 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 25672 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 25673 #define MMEA5_DRAM_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 25674 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 25675 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 25676 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 25677 #define MMEA5_DRAM_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 25678 #define MMEA5_DRAM_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 25679 //MMEA5_DRAM_WR_CAM_CNTL 25680 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 25681 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 25682 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 25683 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 25684 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 25685 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 25686 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 25687 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 25688 #define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 25689 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 25690 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 25691 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 25692 #define MMEA5_DRAM_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 25693 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 25694 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 25695 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 25696 #define MMEA5_DRAM_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 25697 #define MMEA5_DRAM_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 25698 //MMEA5_DRAM_PAGE_BURST 25699 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 25700 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 25701 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 25702 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 25703 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 25704 #define MMEA5_DRAM_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 25705 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 25706 #define MMEA5_DRAM_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 25707 //MMEA5_DRAM_RD_PRI_AGE 25708 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 25709 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 25710 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 25711 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 25712 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 25713 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 25714 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 25715 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 25716 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 25717 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 25718 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 25719 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 25720 #define MMEA5_DRAM_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 25721 #define MMEA5_DRAM_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 25722 #define MMEA5_DRAM_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 25723 #define MMEA5_DRAM_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 25724 //MMEA5_DRAM_WR_PRI_AGE 25725 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 25726 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 25727 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 25728 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 25729 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 25730 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 25731 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 25732 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 25733 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 25734 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 25735 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 25736 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 25737 #define MMEA5_DRAM_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 25738 #define MMEA5_DRAM_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 25739 #define MMEA5_DRAM_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 25740 #define MMEA5_DRAM_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 25741 //MMEA5_DRAM_RD_PRI_QUEUING 25742 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 25743 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 25744 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 25745 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 25746 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 25747 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 25748 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 25749 #define MMEA5_DRAM_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 25750 //MMEA5_DRAM_WR_PRI_QUEUING 25751 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 25752 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 25753 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 25754 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 25755 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 25756 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 25757 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 25758 #define MMEA5_DRAM_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 25759 //MMEA5_DRAM_RD_PRI_FIXED 25760 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 25761 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 25762 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 25763 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 25764 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 25765 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 25766 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 25767 #define MMEA5_DRAM_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 25768 //MMEA5_DRAM_WR_PRI_FIXED 25769 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 25770 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 25771 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 25772 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 25773 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 25774 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 25775 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 25776 #define MMEA5_DRAM_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 25777 //MMEA5_DRAM_RD_PRI_URGENCY 25778 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 25779 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 25780 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 25781 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 25782 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 25783 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 25784 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 25785 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 25786 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 25787 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 25788 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 25789 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 25790 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 25791 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 25792 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 25793 #define MMEA5_DRAM_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 25794 //MMEA5_DRAM_WR_PRI_URGENCY 25795 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 25796 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 25797 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 25798 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 25799 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 25800 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 25801 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 25802 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 25803 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 25804 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 25805 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 25806 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 25807 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 25808 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 25809 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 25810 #define MMEA5_DRAM_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 25811 //MMEA5_DRAM_RD_PRI_QUANT_PRI1 25812 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 25813 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 25814 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 25815 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 25816 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 25817 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 25818 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 25819 #define MMEA5_DRAM_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 25820 //MMEA5_DRAM_RD_PRI_QUANT_PRI2 25821 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 25822 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 25823 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 25824 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 25825 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 25826 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 25827 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 25828 #define MMEA5_DRAM_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 25829 //MMEA5_DRAM_RD_PRI_QUANT_PRI3 25830 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 25831 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 25832 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 25833 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 25834 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 25835 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 25836 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 25837 #define MMEA5_DRAM_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 25838 //MMEA5_DRAM_WR_PRI_QUANT_PRI1 25839 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 25840 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 25841 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 25842 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 25843 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 25844 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 25845 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 25846 #define MMEA5_DRAM_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 25847 //MMEA5_DRAM_WR_PRI_QUANT_PRI2 25848 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 25849 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 25850 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 25851 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 25852 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 25853 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 25854 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 25855 #define MMEA5_DRAM_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 25856 //MMEA5_DRAM_WR_PRI_QUANT_PRI3 25857 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 25858 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 25859 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 25860 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 25861 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 25862 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 25863 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 25864 #define MMEA5_DRAM_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 25865 //MMEA5_GMI_RD_CLI2GRP_MAP0 25866 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 25867 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 25868 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 25869 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 25870 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 25871 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 25872 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 25873 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 25874 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 25875 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 25876 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 25877 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 25878 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 25879 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 25880 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 25881 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 25882 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 25883 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 25884 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 25885 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 25886 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 25887 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 25888 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 25889 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 25890 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 25891 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 25892 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 25893 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 25894 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 25895 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 25896 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 25897 #define MMEA5_GMI_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 25898 //MMEA5_GMI_RD_CLI2GRP_MAP1 25899 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 25900 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 25901 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 25902 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 25903 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 25904 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 25905 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 25906 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 25907 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 25908 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 25909 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 25910 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 25911 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 25912 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 25913 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 25914 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 25915 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 25916 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 25917 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 25918 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 25919 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 25920 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 25921 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 25922 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 25923 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 25924 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 25925 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 25926 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 25927 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 25928 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 25929 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 25930 #define MMEA5_GMI_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 25931 //MMEA5_GMI_WR_CLI2GRP_MAP0 25932 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 25933 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 25934 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 25935 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 25936 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 25937 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 25938 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 25939 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 25940 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 25941 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 25942 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 25943 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 25944 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 25945 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 25946 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 25947 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 25948 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 25949 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 25950 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 25951 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 25952 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 25953 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 25954 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 25955 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 25956 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 25957 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 25958 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 25959 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 25960 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 25961 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 25962 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 25963 #define MMEA5_GMI_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 25964 //MMEA5_GMI_WR_CLI2GRP_MAP1 25965 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 25966 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 25967 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 25968 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 25969 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 25970 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 25971 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 25972 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 25973 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 25974 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 25975 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 25976 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 25977 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 25978 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 25979 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 25980 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 25981 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 25982 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 25983 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 25984 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 25985 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 25986 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 25987 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 25988 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 25989 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 25990 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 25991 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 25992 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 25993 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 25994 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 25995 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 25996 #define MMEA5_GMI_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 25997 //MMEA5_GMI_RD_GRP2VC_MAP 25998 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 25999 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 26000 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 26001 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 26002 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 26003 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 26004 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 26005 #define MMEA5_GMI_RD_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 26006 //MMEA5_GMI_WR_GRP2VC_MAP 26007 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC__SHIFT 0x0 26008 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC__SHIFT 0x3 26009 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC__SHIFT 0x6 26010 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC__SHIFT 0x9 26011 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP0_VC_MASK 0x00000007L 26012 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP1_VC_MASK 0x00000038L 26013 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP2_VC_MASK 0x000001C0L 26014 #define MMEA5_GMI_WR_GRP2VC_MAP__GROUP3_VC_MASK 0x00000E00L 26015 //MMEA5_GMI_RD_LAZY 26016 #define MMEA5_GMI_RD_LAZY__GROUP0_DELAY__SHIFT 0x0 26017 #define MMEA5_GMI_RD_LAZY__GROUP1_DELAY__SHIFT 0x3 26018 #define MMEA5_GMI_RD_LAZY__GROUP2_DELAY__SHIFT 0x6 26019 #define MMEA5_GMI_RD_LAZY__GROUP3_DELAY__SHIFT 0x9 26020 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 26021 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 26022 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 26023 #define MMEA5_GMI_RD_LAZY__GROUP0_DELAY_MASK 0x00000007L 26024 #define MMEA5_GMI_RD_LAZY__GROUP1_DELAY_MASK 0x00000038L 26025 #define MMEA5_GMI_RD_LAZY__GROUP2_DELAY_MASK 0x000001C0L 26026 #define MMEA5_GMI_RD_LAZY__GROUP3_DELAY_MASK 0x00000E00L 26027 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 26028 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 26029 #define MMEA5_GMI_RD_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 26030 //MMEA5_GMI_WR_LAZY 26031 #define MMEA5_GMI_WR_LAZY__GROUP0_DELAY__SHIFT 0x0 26032 #define MMEA5_GMI_WR_LAZY__GROUP1_DELAY__SHIFT 0x3 26033 #define MMEA5_GMI_WR_LAZY__GROUP2_DELAY__SHIFT 0x6 26034 #define MMEA5_GMI_WR_LAZY__GROUP3_DELAY__SHIFT 0x9 26035 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH__SHIFT 0xc 26036 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT__SHIFT 0x14 26037 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX__SHIFT 0x1b 26038 #define MMEA5_GMI_WR_LAZY__GROUP0_DELAY_MASK 0x00000007L 26039 #define MMEA5_GMI_WR_LAZY__GROUP1_DELAY_MASK 0x00000038L 26040 #define MMEA5_GMI_WR_LAZY__GROUP2_DELAY_MASK 0x000001C0L 26041 #define MMEA5_GMI_WR_LAZY__GROUP3_DELAY_MASK 0x00000E00L 26042 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_THRESH_MASK 0x0003F000L 26043 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_TIMEOUT_MASK 0x07F00000L 26044 #define MMEA5_GMI_WR_LAZY__REQ_ACCUM_IDLEMAX_MASK 0x78000000L 26045 //MMEA5_GMI_RD_CAM_CNTL 26046 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 26047 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 26048 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 26049 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 26050 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 26051 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 26052 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 26053 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 26054 #define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 26055 #define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 26056 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 26057 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 26058 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 26059 #define MMEA5_GMI_RD_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 26060 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 26061 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 26062 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 26063 #define MMEA5_GMI_RD_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 26064 #define MMEA5_GMI_RD_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 26065 #define MMEA5_GMI_RD_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 26066 //MMEA5_GMI_WR_CAM_CNTL 26067 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0__SHIFT 0x0 26068 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1__SHIFT 0x4 26069 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2__SHIFT 0x8 26070 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3__SHIFT 0xc 26071 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0__SHIFT 0x10 26072 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1__SHIFT 0x13 26073 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2__SHIFT 0x16 26074 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3__SHIFT 0x19 26075 #define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN__SHIFT 0x1c 26076 #define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING__SHIFT 0x1d 26077 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP0_MASK 0x0000000FL 26078 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP1_MASK 0x000000F0L 26079 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP2_MASK 0x00000F00L 26080 #define MMEA5_GMI_WR_CAM_CNTL__DEPTH_GROUP3_MASK 0x0000F000L 26081 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP0_MASK 0x00070000L 26082 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP1_MASK 0x00380000L 26083 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP2_MASK 0x01C00000L 26084 #define MMEA5_GMI_WR_CAM_CNTL__REORDER_LIMIT_GROUP3_MASK 0x0E000000L 26085 #define MMEA5_GMI_WR_CAM_CNTL__REFILL_CHAIN_MASK 0x10000000L 26086 #define MMEA5_GMI_WR_CAM_CNTL__PAGEBASED_CHAINING_MASK 0x20000000L 26087 //MMEA5_GMI_PAGE_BURST 26088 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO__SHIFT 0x0 26089 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI__SHIFT 0x8 26090 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO__SHIFT 0x10 26091 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI__SHIFT 0x18 26092 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_LO_MASK 0x000000FFL 26093 #define MMEA5_GMI_PAGE_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 26094 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 26095 #define MMEA5_GMI_PAGE_BURST__WR_LIMIT_HI_MASK 0xFF000000L 26096 //MMEA5_GMI_RD_PRI_AGE 26097 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 26098 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 26099 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 26100 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 26101 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 26102 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 26103 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 26104 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 26105 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 26106 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 26107 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 26108 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 26109 #define MMEA5_GMI_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 26110 #define MMEA5_GMI_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 26111 #define MMEA5_GMI_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 26112 #define MMEA5_GMI_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 26113 //MMEA5_GMI_WR_PRI_AGE 26114 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 26115 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 26116 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 26117 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 26118 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 26119 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 26120 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 26121 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 26122 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 26123 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 26124 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 26125 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 26126 #define MMEA5_GMI_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 26127 #define MMEA5_GMI_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 26128 #define MMEA5_GMI_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 26129 #define MMEA5_GMI_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 26130 //MMEA5_GMI_RD_PRI_QUEUING 26131 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 26132 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 26133 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 26134 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 26135 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 26136 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 26137 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 26138 #define MMEA5_GMI_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 26139 //MMEA5_GMI_WR_PRI_QUEUING 26140 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 26141 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 26142 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 26143 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 26144 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 26145 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 26146 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 26147 #define MMEA5_GMI_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 26148 //MMEA5_GMI_RD_PRI_FIXED 26149 #define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 26150 #define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 26151 #define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 26152 #define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 26153 #define MMEA5_GMI_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 26154 #define MMEA5_GMI_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 26155 #define MMEA5_GMI_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 26156 #define MMEA5_GMI_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 26157 //MMEA5_GMI_WR_PRI_FIXED 26158 #define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 26159 #define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 26160 #define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 26161 #define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 26162 #define MMEA5_GMI_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 26163 #define MMEA5_GMI_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 26164 #define MMEA5_GMI_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 26165 #define MMEA5_GMI_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 26166 //MMEA5_GMI_RD_PRI_URGENCY 26167 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 26168 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 26169 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 26170 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 26171 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 26172 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 26173 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 26174 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 26175 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 26176 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 26177 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 26178 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 26179 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 26180 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 26181 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 26182 #define MMEA5_GMI_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 26183 //MMEA5_GMI_WR_PRI_URGENCY 26184 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 26185 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 26186 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 26187 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 26188 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 26189 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 26190 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 26191 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 26192 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 26193 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 26194 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 26195 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 26196 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 26197 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 26198 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 26199 #define MMEA5_GMI_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 26200 //MMEA5_GMI_RD_PRI_URGENCY_MASKING 26201 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 26202 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 26203 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 26204 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 26205 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 26206 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 26207 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 26208 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 26209 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 26210 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 26211 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 26212 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 26213 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 26214 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 26215 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 26216 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 26217 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 26218 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 26219 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 26220 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 26221 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 26222 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 26223 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 26224 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 26225 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 26226 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 26227 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 26228 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 26229 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 26230 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 26231 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 26232 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 26233 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 26234 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 26235 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 26236 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 26237 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 26238 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 26239 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 26240 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 26241 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 26242 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 26243 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 26244 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 26245 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 26246 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 26247 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 26248 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 26249 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 26250 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 26251 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 26252 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 26253 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 26254 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 26255 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 26256 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 26257 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 26258 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 26259 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 26260 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 26261 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 26262 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 26263 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 26264 #define MMEA5_GMI_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 26265 //MMEA5_GMI_WR_PRI_URGENCY_MASKING 26266 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 26267 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 26268 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 26269 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 26270 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 26271 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 26272 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 26273 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 26274 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 26275 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 26276 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 26277 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 26278 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 26279 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 26280 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 26281 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 26282 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 26283 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 26284 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 26285 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 26286 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 26287 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 26288 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 26289 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 26290 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 26291 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 26292 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 26293 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 26294 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 26295 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 26296 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 26297 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 26298 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 26299 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 26300 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 26301 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 26302 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 26303 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 26304 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 26305 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 26306 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 26307 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 26308 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 26309 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 26310 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 26311 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 26312 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 26313 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 26314 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 26315 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 26316 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 26317 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 26318 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 26319 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 26320 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 26321 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 26322 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 26323 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 26324 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 26325 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 26326 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 26327 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 26328 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 26329 #define MMEA5_GMI_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 26330 //MMEA5_GMI_RD_PRI_QUANT_PRI1 26331 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 26332 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 26333 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 26334 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 26335 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 26336 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 26337 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 26338 #define MMEA5_GMI_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 26339 //MMEA5_GMI_RD_PRI_QUANT_PRI2 26340 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 26341 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 26342 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 26343 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 26344 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 26345 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 26346 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 26347 #define MMEA5_GMI_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 26348 //MMEA5_GMI_RD_PRI_QUANT_PRI3 26349 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 26350 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 26351 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 26352 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 26353 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 26354 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 26355 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 26356 #define MMEA5_GMI_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 26357 //MMEA5_GMI_WR_PRI_QUANT_PRI1 26358 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 26359 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 26360 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 26361 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 26362 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 26363 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 26364 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 26365 #define MMEA5_GMI_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 26366 //MMEA5_GMI_WR_PRI_QUANT_PRI2 26367 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 26368 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 26369 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 26370 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 26371 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 26372 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 26373 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 26374 #define MMEA5_GMI_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 26375 //MMEA5_GMI_WR_PRI_QUANT_PRI3 26376 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 26377 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 26378 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 26379 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 26380 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 26381 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 26382 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 26383 #define MMEA5_GMI_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 26384 //MMEA5_ADDRNORM_BASE_ADDR0 26385 #define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 26386 #define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 26387 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 26388 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 26389 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 26390 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 26391 #define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR__SHIFT 0xc 26392 #define MMEA5_ADDRNORM_BASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 26393 #define MMEA5_ADDRNORM_BASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 26394 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 26395 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 26396 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 26397 #define MMEA5_ADDRNORM_BASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 26398 #define MMEA5_ADDRNORM_BASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 26399 //MMEA5_ADDRNORM_LIMIT_ADDR0 26400 #define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 26401 #define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 26402 #define MMEA5_ADDRNORM_LIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 26403 #define MMEA5_ADDRNORM_LIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 26404 //MMEA5_ADDRNORM_BASE_ADDR1 26405 #define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 26406 #define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 26407 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 26408 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 26409 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 26410 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 26411 #define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR__SHIFT 0xc 26412 #define MMEA5_ADDRNORM_BASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 26413 #define MMEA5_ADDRNORM_BASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 26414 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 26415 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 26416 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 26417 #define MMEA5_ADDRNORM_BASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 26418 #define MMEA5_ADDRNORM_BASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 26419 //MMEA5_ADDRNORM_LIMIT_ADDR1 26420 #define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 26421 #define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 26422 #define MMEA5_ADDRNORM_LIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 26423 #define MMEA5_ADDRNORM_LIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 26424 //MMEA5_ADDRNORM_OFFSET_ADDR1 26425 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN__SHIFT 0x0 26426 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET__SHIFT 0xc 26427 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_EN_MASK 0x00000001L 26428 #define MMEA5_ADDRNORM_OFFSET_ADDR1__HI_ADDR_OFFSET_MASK 0x00FFF000L 26429 //MMEA5_ADDRNORM_BASE_ADDR2 26430 #define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL__SHIFT 0x0 26431 #define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN__SHIFT 0x1 26432 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN__SHIFT 0x2 26433 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES__SHIFT 0x7 26434 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS__SHIFT 0x8 26435 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL__SHIFT 0x9 26436 #define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR__SHIFT 0xc 26437 #define MMEA5_ADDRNORM_BASE_ADDR2__ADDR_RNG_VAL_MASK 0x00000001L 26438 #define MMEA5_ADDRNORM_BASE_ADDR2__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 26439 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_CHAN_MASK 0x0000007CL 26440 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_DIES_MASK 0x00000080L 26441 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_NUM_SOCKETS_MASK 0x00000100L 26442 #define MMEA5_ADDRNORM_BASE_ADDR2__INTLV_ADDR_SEL_MASK 0x00000E00L 26443 #define MMEA5_ADDRNORM_BASE_ADDR2__BASE_ADDR_MASK 0xFFFFF000L 26444 //MMEA5_ADDRNORM_LIMIT_ADDR2 26445 #define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID__SHIFT 0x0 26446 #define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR__SHIFT 0xc 26447 #define MMEA5_ADDRNORM_LIMIT_ADDR2__DST_FABRIC_ID_MASK 0x0000001FL 26448 #define MMEA5_ADDRNORM_LIMIT_ADDR2__LIMIT_ADDR_MASK 0xFFFFF000L 26449 //MMEA5_ADDRNORM_BASE_ADDR3 26450 #define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL__SHIFT 0x0 26451 #define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN__SHIFT 0x1 26452 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN__SHIFT 0x2 26453 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES__SHIFT 0x7 26454 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS__SHIFT 0x8 26455 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL__SHIFT 0x9 26456 #define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR__SHIFT 0xc 26457 #define MMEA5_ADDRNORM_BASE_ADDR3__ADDR_RNG_VAL_MASK 0x00000001L 26458 #define MMEA5_ADDRNORM_BASE_ADDR3__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 26459 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_CHAN_MASK 0x0000007CL 26460 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_DIES_MASK 0x00000080L 26461 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_NUM_SOCKETS_MASK 0x00000100L 26462 #define MMEA5_ADDRNORM_BASE_ADDR3__INTLV_ADDR_SEL_MASK 0x00000E00L 26463 #define MMEA5_ADDRNORM_BASE_ADDR3__BASE_ADDR_MASK 0xFFFFF000L 26464 //MMEA5_ADDRNORM_LIMIT_ADDR3 26465 #define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID__SHIFT 0x0 26466 #define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR__SHIFT 0xc 26467 #define MMEA5_ADDRNORM_LIMIT_ADDR3__DST_FABRIC_ID_MASK 0x0000001FL 26468 #define MMEA5_ADDRNORM_LIMIT_ADDR3__LIMIT_ADDR_MASK 0xFFFFF000L 26469 //MMEA5_ADDRNORM_OFFSET_ADDR3 26470 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN__SHIFT 0x0 26471 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET__SHIFT 0xc 26472 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_EN_MASK 0x00000001L 26473 #define MMEA5_ADDRNORM_OFFSET_ADDR3__HI_ADDR_OFFSET_MASK 0x00FFF000L 26474 //MMEA5_ADDRNORM_MEGABASE_ADDR0 26475 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL__SHIFT 0x0 26476 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN__SHIFT 0x1 26477 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN__SHIFT 0x2 26478 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES__SHIFT 0x7 26479 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS__SHIFT 0x8 26480 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL__SHIFT 0x9 26481 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR__SHIFT 0xc 26482 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__ADDR_RNG_VAL_MASK 0x00000001L 26483 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 26484 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_CHAN_MASK 0x0000007CL 26485 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_DIES_MASK 0x00000080L 26486 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_NUM_SOCKETS_MASK 0x00000100L 26487 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__INTLV_ADDR_SEL_MASK 0x00000E00L 26488 #define MMEA5_ADDRNORM_MEGABASE_ADDR0__BASE_ADDR_MASK 0xFFFFF000L 26489 //MMEA5_ADDRNORM_MEGALIMIT_ADDR0 26490 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID__SHIFT 0x0 26491 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR__SHIFT 0xc 26492 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__DST_FABRIC_ID_MASK 0x0000001FL 26493 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR0__LIMIT_ADDR_MASK 0xFFFFF000L 26494 //MMEA5_ADDRNORM_MEGABASE_ADDR1 26495 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL__SHIFT 0x0 26496 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN__SHIFT 0x1 26497 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN__SHIFT 0x2 26498 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES__SHIFT 0x7 26499 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS__SHIFT 0x8 26500 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL__SHIFT 0x9 26501 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR__SHIFT 0xc 26502 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__ADDR_RNG_VAL_MASK 0x00000001L 26503 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__LGCY_MMIO_HOLE_EN_MASK 0x00000002L 26504 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_CHAN_MASK 0x0000007CL 26505 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_DIES_MASK 0x00000080L 26506 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_NUM_SOCKETS_MASK 0x00000100L 26507 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__INTLV_ADDR_SEL_MASK 0x00000E00L 26508 #define MMEA5_ADDRNORM_MEGABASE_ADDR1__BASE_ADDR_MASK 0xFFFFF000L 26509 //MMEA5_ADDRNORM_MEGALIMIT_ADDR1 26510 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID__SHIFT 0x0 26511 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR__SHIFT 0xc 26512 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__DST_FABRIC_ID_MASK 0x0000001FL 26513 #define MMEA5_ADDRNORM_MEGALIMIT_ADDR1__LIMIT_ADDR_MASK 0xFFFFF000L 26514 //MMEA5_ADDRNORMDRAM_HOLE_CNTL 26515 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 26516 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 26517 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 26518 #define MMEA5_ADDRNORMDRAM_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 26519 //MMEA5_ADDRNORMGMI_HOLE_CNTL 26520 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID__SHIFT 0x0 26521 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET__SHIFT 0x7 26522 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_VALID_MASK 0x00000001L 26523 #define MMEA5_ADDRNORMGMI_HOLE_CNTL__DRAM_HOLE_OFFSET_MASK 0x0000FF80L 26524 //MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG 26525 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0__SHIFT 0x0 26526 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1__SHIFT 0x6 26527 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE0_MASK 0x0000003FL 26528 #define MMEA5_ADDRNORMDRAM_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE1_MASK 0x00000FC0L 26529 //MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG 26530 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2__SHIFT 0x0 26531 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3__SHIFT 0x6 26532 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE2_MASK 0x0000003FL 26533 #define MMEA5_ADDRNORMGMI_NP2_CHANNEL_CFG__LOG2_ADDR64K_SPACE3_MASK 0x00000FC0L 26534 //MMEA5_ADDRDEC_BANK_CFG 26535 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM__SHIFT 0x0 26536 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI__SHIFT 0x6 26537 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM__SHIFT 0xc 26538 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI__SHIFT 0xf 26539 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM__SHIFT 0x12 26540 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI__SHIFT 0x13 26541 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_DRAM_MASK 0x0000003FL 26542 #define MMEA5_ADDRDEC_BANK_CFG__BANK_MASK_GMI_MASK 0x00000FC0L 26543 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_DRAM_MASK 0x00007000L 26544 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_SEL_GMI_MASK 0x00038000L 26545 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_DRAM_MASK 0x00040000L 26546 #define MMEA5_ADDRDEC_BANK_CFG__BANKGROUP_INTERLEAVE_GMI_MASK 0x00080000L 26547 //MMEA5_ADDRDEC_MISC_CFG 26548 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0__SHIFT 0x0 26549 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1__SHIFT 0x1 26550 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2__SHIFT 0x2 26551 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM__SHIFT 0x8 26552 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI__SHIFT 0x9 26553 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM__SHIFT 0xc 26554 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI__SHIFT 0x11 26555 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM__SHIFT 0x16 26556 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI__SHIFT 0x18 26557 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM__SHIFT 0x1a 26558 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI__SHIFT 0x1d 26559 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN0_MASK 0x00000001L 26560 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN1_MASK 0x00000002L 26561 #define MMEA5_ADDRDEC_MISC_CFG__VCM_EN2_MASK 0x00000004L 26562 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_DRAM_MASK 0x00000100L 26563 #define MMEA5_ADDRDEC_MISC_CFG__PCH_MASK_GMI_MASK 0x00000200L 26564 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_DRAM_MASK 0x0001F000L 26565 #define MMEA5_ADDRDEC_MISC_CFG__CH_MASK_GMI_MASK 0x003E0000L 26566 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_DRAM_MASK 0x00C00000L 26567 #define MMEA5_ADDRDEC_MISC_CFG__CS_MASK_GMI_MASK 0x03000000L 26568 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_DRAM_MASK 0x1C000000L 26569 #define MMEA5_ADDRDEC_MISC_CFG__RM_MASK_GMI_MASK 0xE0000000L 26570 //MMEA5_ADDRDECDRAM_HARVEST_ENABLE 26571 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 26572 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 26573 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 26574 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 26575 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 26576 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 26577 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 26578 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 26579 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 26580 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 26581 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 26582 #define MMEA5_ADDRDECDRAM_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 26583 //MMEA5_ADDRDECGMI_HARVEST_ENABLE 26584 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN__SHIFT 0x0 26585 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL__SHIFT 0x1 26586 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN__SHIFT 0x2 26587 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL__SHIFT 0x3 26588 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN__SHIFT 0x4 26589 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL__SHIFT 0x5 26590 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_EN_MASK 0x00000001L 26591 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B3_VAL_MASK 0x00000002L 26592 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_EN_MASK 0x00000004L 26593 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B4_VAL_MASK 0x00000008L 26594 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_EN_MASK 0x00000010L 26595 #define MMEA5_ADDRDECGMI_HARVEST_ENABLE__FORCE_B5_VAL_MASK 0x00000020L 26596 //MMEA5_ADDRDEC0_BASE_ADDR_CS0 26597 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 26598 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 26599 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 26600 #define MMEA5_ADDRDEC0_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 26601 //MMEA5_ADDRDEC0_BASE_ADDR_CS1 26602 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 26603 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 26604 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 26605 #define MMEA5_ADDRDEC0_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 26606 //MMEA5_ADDRDEC0_BASE_ADDR_CS2 26607 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 26608 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 26609 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 26610 #define MMEA5_ADDRDEC0_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 26611 //MMEA5_ADDRDEC0_BASE_ADDR_CS3 26612 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 26613 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 26614 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 26615 #define MMEA5_ADDRDEC0_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 26616 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS0 26617 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 26618 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 26619 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 26620 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 26621 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS1 26622 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 26623 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 26624 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 26625 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 26626 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS2 26627 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 26628 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 26629 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 26630 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 26631 //MMEA5_ADDRDEC0_BASE_ADDR_SECCS3 26632 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 26633 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 26634 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 26635 #define MMEA5_ADDRDEC0_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 26636 //MMEA5_ADDRDEC0_ADDR_MASK_CS01 26637 #define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 26638 #define MMEA5_ADDRDEC0_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 26639 //MMEA5_ADDRDEC0_ADDR_MASK_CS23 26640 #define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 26641 #define MMEA5_ADDRDEC0_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 26642 //MMEA5_ADDRDEC0_ADDR_MASK_SECCS01 26643 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 26644 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 26645 //MMEA5_ADDRDEC0_ADDR_MASK_SECCS23 26646 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 26647 #define MMEA5_ADDRDEC0_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 26648 //MMEA5_ADDRDEC0_ADDR_CFG_CS01 26649 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 26650 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 26651 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 26652 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 26653 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 26654 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 26655 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 26656 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 26657 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 26658 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 26659 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 26660 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 26661 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 26662 #define MMEA5_ADDRDEC0_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 26663 //MMEA5_ADDRDEC0_ADDR_CFG_CS23 26664 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 26665 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 26666 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 26667 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 26668 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 26669 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 26670 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 26671 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 26672 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 26673 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 26674 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 26675 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 26676 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 26677 #define MMEA5_ADDRDEC0_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 26678 //MMEA5_ADDRDEC0_ADDR_SEL_CS01 26679 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0__SHIFT 0x0 26680 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1__SHIFT 0x4 26681 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2__SHIFT 0x8 26682 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3__SHIFT 0xc 26683 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4__SHIFT 0x10 26684 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 26685 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 26686 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 26687 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 26688 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 26689 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 26690 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 26691 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 26692 #define MMEA5_ADDRDEC0_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 26693 //MMEA5_ADDRDEC0_ADDR_SEL_CS23 26694 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0__SHIFT 0x0 26695 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1__SHIFT 0x4 26696 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2__SHIFT 0x8 26697 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3__SHIFT 0xc 26698 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4__SHIFT 0x10 26699 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 26700 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 26701 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 26702 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 26703 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 26704 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 26705 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 26706 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 26707 #define MMEA5_ADDRDEC0_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 26708 //MMEA5_ADDRDEC0_ADDR_SEL2_CS01 26709 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 26710 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 26711 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 26712 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 26713 //MMEA5_ADDRDEC0_ADDR_SEL2_CS23 26714 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 26715 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 26716 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 26717 #define MMEA5_ADDRDEC0_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 26718 //MMEA5_ADDRDEC0_COL_SEL_LO_CS01 26719 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0__SHIFT 0x0 26720 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1__SHIFT 0x4 26721 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2__SHIFT 0x8 26722 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3__SHIFT 0xc 26723 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4__SHIFT 0x10 26724 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5__SHIFT 0x14 26725 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6__SHIFT 0x18 26726 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 26727 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 26728 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 26729 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 26730 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 26731 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 26732 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 26733 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 26734 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 26735 //MMEA5_ADDRDEC0_COL_SEL_LO_CS23 26736 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0__SHIFT 0x0 26737 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1__SHIFT 0x4 26738 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2__SHIFT 0x8 26739 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3__SHIFT 0xc 26740 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4__SHIFT 0x10 26741 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5__SHIFT 0x14 26742 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6__SHIFT 0x18 26743 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 26744 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 26745 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 26746 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 26747 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 26748 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 26749 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 26750 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 26751 #define MMEA5_ADDRDEC0_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 26752 //MMEA5_ADDRDEC0_COL_SEL_HI_CS01 26753 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8__SHIFT 0x0 26754 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9__SHIFT 0x4 26755 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10__SHIFT 0x8 26756 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11__SHIFT 0xc 26757 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12__SHIFT 0x10 26758 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13__SHIFT 0x14 26759 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14__SHIFT 0x18 26760 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 26761 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 26762 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 26763 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 26764 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 26765 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 26766 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 26767 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 26768 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 26769 //MMEA5_ADDRDEC0_COL_SEL_HI_CS23 26770 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8__SHIFT 0x0 26771 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9__SHIFT 0x4 26772 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10__SHIFT 0x8 26773 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11__SHIFT 0xc 26774 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12__SHIFT 0x10 26775 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13__SHIFT 0x14 26776 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14__SHIFT 0x18 26777 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 26778 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 26779 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 26780 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 26781 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 26782 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 26783 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 26784 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 26785 #define MMEA5_ADDRDEC0_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 26786 //MMEA5_ADDRDEC0_RM_SEL_CS01 26787 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0__SHIFT 0x0 26788 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1__SHIFT 0x4 26789 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2__SHIFT 0x8 26790 #define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 26791 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 26792 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 26793 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM0_MASK 0x0000000FL 26794 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM1_MASK 0x000000F0L 26795 #define MMEA5_ADDRDEC0_RM_SEL_CS01__RM2_MASK 0x00000F00L 26796 #define MMEA5_ADDRDEC0_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 26797 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 26798 #define MMEA5_ADDRDEC0_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 26799 //MMEA5_ADDRDEC0_RM_SEL_CS23 26800 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0__SHIFT 0x0 26801 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1__SHIFT 0x4 26802 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2__SHIFT 0x8 26803 #define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 26804 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 26805 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 26806 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM0_MASK 0x0000000FL 26807 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM1_MASK 0x000000F0L 26808 #define MMEA5_ADDRDEC0_RM_SEL_CS23__RM2_MASK 0x00000F00L 26809 #define MMEA5_ADDRDEC0_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 26810 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 26811 #define MMEA5_ADDRDEC0_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 26812 //MMEA5_ADDRDEC0_RM_SEL_SECCS01 26813 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0__SHIFT 0x0 26814 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1__SHIFT 0x4 26815 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2__SHIFT 0x8 26816 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 26817 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 26818 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 26819 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 26820 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 26821 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 26822 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 26823 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 26824 #define MMEA5_ADDRDEC0_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 26825 //MMEA5_ADDRDEC0_RM_SEL_SECCS23 26826 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0__SHIFT 0x0 26827 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1__SHIFT 0x4 26828 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2__SHIFT 0x8 26829 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 26830 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 26831 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 26832 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 26833 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 26834 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 26835 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 26836 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 26837 #define MMEA5_ADDRDEC0_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 26838 //MMEA5_ADDRDEC1_BASE_ADDR_CS0 26839 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 26840 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 26841 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 26842 #define MMEA5_ADDRDEC1_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 26843 //MMEA5_ADDRDEC1_BASE_ADDR_CS1 26844 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 26845 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 26846 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 26847 #define MMEA5_ADDRDEC1_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 26848 //MMEA5_ADDRDEC1_BASE_ADDR_CS2 26849 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 26850 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 26851 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 26852 #define MMEA5_ADDRDEC1_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 26853 //MMEA5_ADDRDEC1_BASE_ADDR_CS3 26854 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 26855 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 26856 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 26857 #define MMEA5_ADDRDEC1_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 26858 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS0 26859 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 26860 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 26861 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 26862 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 26863 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS1 26864 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 26865 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 26866 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 26867 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 26868 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS2 26869 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 26870 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 26871 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 26872 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 26873 //MMEA5_ADDRDEC1_BASE_ADDR_SECCS3 26874 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 26875 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 26876 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 26877 #define MMEA5_ADDRDEC1_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 26878 //MMEA5_ADDRDEC1_ADDR_MASK_CS01 26879 #define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 26880 #define MMEA5_ADDRDEC1_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 26881 //MMEA5_ADDRDEC1_ADDR_MASK_CS23 26882 #define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 26883 #define MMEA5_ADDRDEC1_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 26884 //MMEA5_ADDRDEC1_ADDR_MASK_SECCS01 26885 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 26886 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 26887 //MMEA5_ADDRDEC1_ADDR_MASK_SECCS23 26888 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 26889 #define MMEA5_ADDRDEC1_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 26890 //MMEA5_ADDRDEC1_ADDR_CFG_CS01 26891 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 26892 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 26893 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 26894 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 26895 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 26896 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 26897 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 26898 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 26899 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 26900 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 26901 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 26902 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 26903 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 26904 #define MMEA5_ADDRDEC1_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 26905 //MMEA5_ADDRDEC1_ADDR_CFG_CS23 26906 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 26907 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 26908 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 26909 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 26910 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 26911 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 26912 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 26913 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 26914 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 26915 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 26916 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 26917 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 26918 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 26919 #define MMEA5_ADDRDEC1_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 26920 //MMEA5_ADDRDEC1_ADDR_SEL_CS01 26921 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0__SHIFT 0x0 26922 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1__SHIFT 0x4 26923 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2__SHIFT 0x8 26924 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3__SHIFT 0xc 26925 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4__SHIFT 0x10 26926 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 26927 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 26928 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 26929 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 26930 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 26931 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 26932 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 26933 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 26934 #define MMEA5_ADDRDEC1_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 26935 //MMEA5_ADDRDEC1_ADDR_SEL_CS23 26936 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0__SHIFT 0x0 26937 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1__SHIFT 0x4 26938 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2__SHIFT 0x8 26939 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3__SHIFT 0xc 26940 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4__SHIFT 0x10 26941 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 26942 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 26943 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 26944 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 26945 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 26946 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 26947 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 26948 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 26949 #define MMEA5_ADDRDEC1_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 26950 //MMEA5_ADDRDEC1_ADDR_SEL2_CS01 26951 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 26952 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 26953 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 26954 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 26955 //MMEA5_ADDRDEC1_ADDR_SEL2_CS23 26956 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 26957 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 26958 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 26959 #define MMEA5_ADDRDEC1_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 26960 //MMEA5_ADDRDEC1_COL_SEL_LO_CS01 26961 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0__SHIFT 0x0 26962 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1__SHIFT 0x4 26963 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2__SHIFT 0x8 26964 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3__SHIFT 0xc 26965 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4__SHIFT 0x10 26966 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5__SHIFT 0x14 26967 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6__SHIFT 0x18 26968 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 26969 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 26970 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 26971 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 26972 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 26973 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 26974 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 26975 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 26976 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 26977 //MMEA5_ADDRDEC1_COL_SEL_LO_CS23 26978 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0__SHIFT 0x0 26979 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1__SHIFT 0x4 26980 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2__SHIFT 0x8 26981 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3__SHIFT 0xc 26982 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4__SHIFT 0x10 26983 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5__SHIFT 0x14 26984 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6__SHIFT 0x18 26985 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 26986 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 26987 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 26988 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 26989 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 26990 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 26991 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 26992 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 26993 #define MMEA5_ADDRDEC1_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 26994 //MMEA5_ADDRDEC1_COL_SEL_HI_CS01 26995 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8__SHIFT 0x0 26996 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9__SHIFT 0x4 26997 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10__SHIFT 0x8 26998 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11__SHIFT 0xc 26999 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12__SHIFT 0x10 27000 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13__SHIFT 0x14 27001 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14__SHIFT 0x18 27002 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 27003 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 27004 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 27005 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 27006 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 27007 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 27008 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 27009 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 27010 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 27011 //MMEA5_ADDRDEC1_COL_SEL_HI_CS23 27012 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8__SHIFT 0x0 27013 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9__SHIFT 0x4 27014 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10__SHIFT 0x8 27015 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11__SHIFT 0xc 27016 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12__SHIFT 0x10 27017 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13__SHIFT 0x14 27018 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14__SHIFT 0x18 27019 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 27020 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 27021 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 27022 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 27023 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 27024 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 27025 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 27026 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 27027 #define MMEA5_ADDRDEC1_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 27028 //MMEA5_ADDRDEC1_RM_SEL_CS01 27029 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0__SHIFT 0x0 27030 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1__SHIFT 0x4 27031 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2__SHIFT 0x8 27032 #define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 27033 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27034 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27035 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM0_MASK 0x0000000FL 27036 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM1_MASK 0x000000F0L 27037 #define MMEA5_ADDRDEC1_RM_SEL_CS01__RM2_MASK 0x00000F00L 27038 #define MMEA5_ADDRDEC1_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 27039 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27040 #define MMEA5_ADDRDEC1_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27041 //MMEA5_ADDRDEC1_RM_SEL_CS23 27042 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0__SHIFT 0x0 27043 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1__SHIFT 0x4 27044 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2__SHIFT 0x8 27045 #define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 27046 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27047 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27048 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM0_MASK 0x0000000FL 27049 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM1_MASK 0x000000F0L 27050 #define MMEA5_ADDRDEC1_RM_SEL_CS23__RM2_MASK 0x00000F00L 27051 #define MMEA5_ADDRDEC1_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 27052 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27053 #define MMEA5_ADDRDEC1_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27054 //MMEA5_ADDRDEC1_RM_SEL_SECCS01 27055 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0__SHIFT 0x0 27056 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1__SHIFT 0x4 27057 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2__SHIFT 0x8 27058 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 27059 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27060 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27061 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 27062 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 27063 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 27064 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 27065 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27066 #define MMEA5_ADDRDEC1_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27067 //MMEA5_ADDRDEC1_RM_SEL_SECCS23 27068 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0__SHIFT 0x0 27069 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1__SHIFT 0x4 27070 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2__SHIFT 0x8 27071 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 27072 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27073 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27074 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 27075 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 27076 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 27077 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 27078 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27079 #define MMEA5_ADDRDEC1_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27080 //MMEA5_ADDRDEC2_BASE_ADDR_CS0 27081 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN__SHIFT 0x0 27082 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR__SHIFT 0x1 27083 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__CS_EN_MASK 0x00000001L 27084 #define MMEA5_ADDRDEC2_BASE_ADDR_CS0__BASE_ADDR_MASK 0xFFFFFFFEL 27085 //MMEA5_ADDRDEC2_BASE_ADDR_CS1 27086 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN__SHIFT 0x0 27087 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR__SHIFT 0x1 27088 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__CS_EN_MASK 0x00000001L 27089 #define MMEA5_ADDRDEC2_BASE_ADDR_CS1__BASE_ADDR_MASK 0xFFFFFFFEL 27090 //MMEA5_ADDRDEC2_BASE_ADDR_CS2 27091 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN__SHIFT 0x0 27092 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR__SHIFT 0x1 27093 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__CS_EN_MASK 0x00000001L 27094 #define MMEA5_ADDRDEC2_BASE_ADDR_CS2__BASE_ADDR_MASK 0xFFFFFFFEL 27095 //MMEA5_ADDRDEC2_BASE_ADDR_CS3 27096 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN__SHIFT 0x0 27097 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR__SHIFT 0x1 27098 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__CS_EN_MASK 0x00000001L 27099 #define MMEA5_ADDRDEC2_BASE_ADDR_CS3__BASE_ADDR_MASK 0xFFFFFFFEL 27100 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS0 27101 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN__SHIFT 0x0 27102 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR__SHIFT 0x1 27103 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__CS_EN_MASK 0x00000001L 27104 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS0__BASE_ADDR_MASK 0xFFFFFFFEL 27105 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS1 27106 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN__SHIFT 0x0 27107 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR__SHIFT 0x1 27108 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__CS_EN_MASK 0x00000001L 27109 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS1__BASE_ADDR_MASK 0xFFFFFFFEL 27110 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS2 27111 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN__SHIFT 0x0 27112 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR__SHIFT 0x1 27113 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__CS_EN_MASK 0x00000001L 27114 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS2__BASE_ADDR_MASK 0xFFFFFFFEL 27115 //MMEA5_ADDRDEC2_BASE_ADDR_SECCS3 27116 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN__SHIFT 0x0 27117 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR__SHIFT 0x1 27118 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__CS_EN_MASK 0x00000001L 27119 #define MMEA5_ADDRDEC2_BASE_ADDR_SECCS3__BASE_ADDR_MASK 0xFFFFFFFEL 27120 //MMEA5_ADDRDEC2_ADDR_MASK_CS01 27121 #define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK__SHIFT 0x1 27122 #define MMEA5_ADDRDEC2_ADDR_MASK_CS01__ADDR_MASK_MASK 0xFFFFFFFEL 27123 //MMEA5_ADDRDEC2_ADDR_MASK_CS23 27124 #define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK__SHIFT 0x1 27125 #define MMEA5_ADDRDEC2_ADDR_MASK_CS23__ADDR_MASK_MASK 0xFFFFFFFEL 27126 //MMEA5_ADDRDEC2_ADDR_MASK_SECCS01 27127 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK__SHIFT 0x1 27128 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS01__ADDR_MASK_MASK 0xFFFFFFFEL 27129 //MMEA5_ADDRDEC2_ADDR_MASK_SECCS23 27130 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK__SHIFT 0x1 27131 #define MMEA5_ADDRDEC2_ADDR_MASK_SECCS23__ADDR_MASK_MASK 0xFFFFFFFEL 27132 //MMEA5_ADDRDEC2_ADDR_CFG_CS01 27133 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS__SHIFT 0x1 27134 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM__SHIFT 0x4 27135 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO__SHIFT 0x8 27136 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI__SHIFT 0xc 27137 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL__SHIFT 0x10 27138 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS__SHIFT 0x14 27139 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN__SHIFT 0x1f 27140 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANK_GROUPS_MASK 0x0000000EL 27141 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_RM_MASK 0x00000030L 27142 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_LO_MASK 0x00000F00L 27143 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_ROW_HI_MASK 0x0000F000L 27144 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_COL_MASK 0x000F0000L 27145 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__NUM_BANKS_MASK 0x00300000L 27146 #define MMEA5_ADDRDEC2_ADDR_CFG_CS01__HI_COL_EN_MASK 0x80000000L 27147 //MMEA5_ADDRDEC2_ADDR_CFG_CS23 27148 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS__SHIFT 0x1 27149 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM__SHIFT 0x4 27150 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO__SHIFT 0x8 27151 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI__SHIFT 0xc 27152 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL__SHIFT 0x10 27153 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS__SHIFT 0x14 27154 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN__SHIFT 0x1f 27155 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANK_GROUPS_MASK 0x0000000EL 27156 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_RM_MASK 0x00000030L 27157 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_LO_MASK 0x00000F00L 27158 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_ROW_HI_MASK 0x0000F000L 27159 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_COL_MASK 0x000F0000L 27160 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__NUM_BANKS_MASK 0x00300000L 27161 #define MMEA5_ADDRDEC2_ADDR_CFG_CS23__HI_COL_EN_MASK 0x80000000L 27162 //MMEA5_ADDRDEC2_ADDR_SEL_CS01 27163 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0__SHIFT 0x0 27164 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1__SHIFT 0x4 27165 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2__SHIFT 0x8 27166 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3__SHIFT 0xc 27167 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4__SHIFT 0x10 27168 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO__SHIFT 0x18 27169 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI__SHIFT 0x1c 27170 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK0_MASK 0x0000000FL 27171 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK1_MASK 0x000000F0L 27172 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK2_MASK 0x00000F00L 27173 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK3_MASK 0x0000F000L 27174 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__BANK4_MASK 0x001F0000L 27175 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_LO_MASK 0x0F000000L 27176 #define MMEA5_ADDRDEC2_ADDR_SEL_CS01__ROW_HI_MASK 0xF0000000L 27177 //MMEA5_ADDRDEC2_ADDR_SEL_CS23 27178 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0__SHIFT 0x0 27179 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1__SHIFT 0x4 27180 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2__SHIFT 0x8 27181 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3__SHIFT 0xc 27182 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4__SHIFT 0x10 27183 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO__SHIFT 0x18 27184 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI__SHIFT 0x1c 27185 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK0_MASK 0x0000000FL 27186 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK1_MASK 0x000000F0L 27187 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK2_MASK 0x00000F00L 27188 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK3_MASK 0x0000F000L 27189 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__BANK4_MASK 0x001F0000L 27190 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_LO_MASK 0x0F000000L 27191 #define MMEA5_ADDRDEC2_ADDR_SEL_CS23__ROW_HI_MASK 0xF0000000L 27192 //MMEA5_ADDRDEC2_ADDR_SEL2_CS01 27193 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5__SHIFT 0x0 27194 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT__SHIFT 0xc 27195 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__BANK5_MASK 0x0000001FL 27196 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS01__CHAN_BIT_MASK 0x0000F000L 27197 //MMEA5_ADDRDEC2_ADDR_SEL2_CS23 27198 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5__SHIFT 0x0 27199 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT__SHIFT 0xc 27200 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__BANK5_MASK 0x0000001FL 27201 #define MMEA5_ADDRDEC2_ADDR_SEL2_CS23__CHAN_BIT_MASK 0x0000F000L 27202 //MMEA5_ADDRDEC2_COL_SEL_LO_CS01 27203 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0__SHIFT 0x0 27204 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1__SHIFT 0x4 27205 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2__SHIFT 0x8 27206 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3__SHIFT 0xc 27207 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4__SHIFT 0x10 27208 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5__SHIFT 0x14 27209 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6__SHIFT 0x18 27210 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7__SHIFT 0x1c 27211 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL0_MASK 0x0000000FL 27212 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL1_MASK 0x000000F0L 27213 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL2_MASK 0x00000F00L 27214 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL3_MASK 0x0000F000L 27215 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL4_MASK 0x000F0000L 27216 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL5_MASK 0x00F00000L 27217 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL6_MASK 0x0F000000L 27218 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS01__COL7_MASK 0xF0000000L 27219 //MMEA5_ADDRDEC2_COL_SEL_LO_CS23 27220 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0__SHIFT 0x0 27221 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1__SHIFT 0x4 27222 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2__SHIFT 0x8 27223 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3__SHIFT 0xc 27224 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4__SHIFT 0x10 27225 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5__SHIFT 0x14 27226 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6__SHIFT 0x18 27227 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7__SHIFT 0x1c 27228 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL0_MASK 0x0000000FL 27229 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL1_MASK 0x000000F0L 27230 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL2_MASK 0x00000F00L 27231 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL3_MASK 0x0000F000L 27232 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL4_MASK 0x000F0000L 27233 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL5_MASK 0x00F00000L 27234 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL6_MASK 0x0F000000L 27235 #define MMEA5_ADDRDEC2_COL_SEL_LO_CS23__COL7_MASK 0xF0000000L 27236 //MMEA5_ADDRDEC2_COL_SEL_HI_CS01 27237 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8__SHIFT 0x0 27238 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9__SHIFT 0x4 27239 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10__SHIFT 0x8 27240 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11__SHIFT 0xc 27241 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12__SHIFT 0x10 27242 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13__SHIFT 0x14 27243 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14__SHIFT 0x18 27244 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15__SHIFT 0x1c 27245 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL8_MASK 0x0000000FL 27246 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL9_MASK 0x000000F0L 27247 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL10_MASK 0x00000F00L 27248 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL11_MASK 0x0000F000L 27249 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL12_MASK 0x000F0000L 27250 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL13_MASK 0x00F00000L 27251 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL14_MASK 0x0F000000L 27252 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS01__COL15_MASK 0xF0000000L 27253 //MMEA5_ADDRDEC2_COL_SEL_HI_CS23 27254 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8__SHIFT 0x0 27255 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9__SHIFT 0x4 27256 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10__SHIFT 0x8 27257 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11__SHIFT 0xc 27258 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12__SHIFT 0x10 27259 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13__SHIFT 0x14 27260 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14__SHIFT 0x18 27261 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15__SHIFT 0x1c 27262 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL8_MASK 0x0000000FL 27263 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL9_MASK 0x000000F0L 27264 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL10_MASK 0x00000F00L 27265 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL11_MASK 0x0000F000L 27266 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL12_MASK 0x000F0000L 27267 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL13_MASK 0x00F00000L 27268 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL14_MASK 0x0F000000L 27269 #define MMEA5_ADDRDEC2_COL_SEL_HI_CS23__COL15_MASK 0xF0000000L 27270 //MMEA5_ADDRDEC2_RM_SEL_CS01 27271 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0__SHIFT 0x0 27272 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1__SHIFT 0x4 27273 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2__SHIFT 0x8 27274 #define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT__SHIFT 0xc 27275 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27276 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27277 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM0_MASK 0x0000000FL 27278 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM1_MASK 0x000000F0L 27279 #define MMEA5_ADDRDEC2_RM_SEL_CS01__RM2_MASK 0x00000F00L 27280 #define MMEA5_ADDRDEC2_RM_SEL_CS01__CHAN_BIT_MASK 0x0000F000L 27281 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27282 #define MMEA5_ADDRDEC2_RM_SEL_CS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27283 //MMEA5_ADDRDEC2_RM_SEL_CS23 27284 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0__SHIFT 0x0 27285 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1__SHIFT 0x4 27286 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2__SHIFT 0x8 27287 #define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT__SHIFT 0xc 27288 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27289 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27290 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM0_MASK 0x0000000FL 27291 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM1_MASK 0x000000F0L 27292 #define MMEA5_ADDRDEC2_RM_SEL_CS23__RM2_MASK 0x00000F00L 27293 #define MMEA5_ADDRDEC2_RM_SEL_CS23__CHAN_BIT_MASK 0x0000F000L 27294 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27295 #define MMEA5_ADDRDEC2_RM_SEL_CS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27296 //MMEA5_ADDRDEC2_RM_SEL_SECCS01 27297 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0__SHIFT 0x0 27298 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1__SHIFT 0x4 27299 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2__SHIFT 0x8 27300 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT__SHIFT 0xc 27301 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27302 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27303 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM0_MASK 0x0000000FL 27304 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM1_MASK 0x000000F0L 27305 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__RM2_MASK 0x00000F00L 27306 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__CHAN_BIT_MASK 0x0000F000L 27307 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27308 #define MMEA5_ADDRDEC2_RM_SEL_SECCS01__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27309 //MMEA5_ADDRDEC2_RM_SEL_SECCS23 27310 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0__SHIFT 0x0 27311 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1__SHIFT 0x4 27312 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2__SHIFT 0x8 27313 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT__SHIFT 0xc 27314 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN__SHIFT 0x10 27315 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD__SHIFT 0x12 27316 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM0_MASK 0x0000000FL 27317 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM1_MASK 0x000000F0L 27318 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__RM2_MASK 0x00000F00L 27319 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__CHAN_BIT_MASK 0x0000F000L 27320 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_EVEN_MASK 0x00030000L 27321 #define MMEA5_ADDRDEC2_RM_SEL_SECCS23__INVERT_ROW_MSBS_ODD_MASK 0x000C0000L 27322 //MMEA5_ADDRNORMDRAM_GLOBAL_CNTL 27323 //MMEA5_ADDRNORMGMI_GLOBAL_CNTL 27324 //MMEA5_ADDRNORM_MEGACONTROL_ADDR0 27325 #define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 27326 #define MMEA5_ADDRNORM_MEGACONTROL_ADDR0__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 27327 //MMEA5_ADDRNORM_MEGACONTROL_ADDR1 27328 #define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE__SHIFT 0x0 27329 #define MMEA5_ADDRNORM_MEGACONTROL_ADDR1__LOG2_DIE_ADDR64K_SPACE_MASK 0x0000003FL 27330 //MMEA5_ADDRNORMDRAM_MASKING 27331 #define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK__SHIFT 0x0 27332 #define MMEA5_ADDRNORMDRAM_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 27333 //MMEA5_ADDRNORMGMI_MASKING 27334 #define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK__SHIFT 0x0 27335 #define MMEA5_ADDRNORMGMI_MASKING__ADDRHI_MASK_MASK 0x00000FFFL 27336 //MMEA5_IO_RD_CLI2GRP_MAP0 27337 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 27338 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 27339 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 27340 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 27341 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 27342 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 27343 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 27344 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 27345 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 27346 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 27347 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 27348 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 27349 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 27350 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 27351 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 27352 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 27353 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 27354 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 27355 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 27356 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 27357 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 27358 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 27359 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 27360 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 27361 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 27362 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 27363 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 27364 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 27365 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 27366 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 27367 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 27368 #define MMEA5_IO_RD_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 27369 //MMEA5_IO_RD_CLI2GRP_MAP1 27370 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 27371 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 27372 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 27373 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 27374 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 27375 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 27376 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 27377 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 27378 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 27379 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 27380 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 27381 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 27382 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 27383 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 27384 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 27385 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 27386 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 27387 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 27388 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 27389 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 27390 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 27391 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 27392 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 27393 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 27394 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 27395 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 27396 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 27397 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 27398 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 27399 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 27400 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 27401 #define MMEA5_IO_RD_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 27402 //MMEA5_IO_WR_CLI2GRP_MAP0 27403 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP__SHIFT 0x0 27404 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP__SHIFT 0x2 27405 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP__SHIFT 0x4 27406 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP__SHIFT 0x6 27407 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP__SHIFT 0x8 27408 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP__SHIFT 0xa 27409 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP__SHIFT 0xc 27410 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP__SHIFT 0xe 27411 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP__SHIFT 0x10 27412 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP__SHIFT 0x12 27413 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP__SHIFT 0x14 27414 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP__SHIFT 0x16 27415 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP__SHIFT 0x18 27416 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP__SHIFT 0x1a 27417 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP__SHIFT 0x1c 27418 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP__SHIFT 0x1e 27419 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID0_GROUP_MASK 0x00000003L 27420 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID1_GROUP_MASK 0x0000000CL 27421 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID2_GROUP_MASK 0x00000030L 27422 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID3_GROUP_MASK 0x000000C0L 27423 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID4_GROUP_MASK 0x00000300L 27424 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID5_GROUP_MASK 0x00000C00L 27425 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID6_GROUP_MASK 0x00003000L 27426 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID7_GROUP_MASK 0x0000C000L 27427 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID8_GROUP_MASK 0x00030000L 27428 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID9_GROUP_MASK 0x000C0000L 27429 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID10_GROUP_MASK 0x00300000L 27430 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID11_GROUP_MASK 0x00C00000L 27431 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID12_GROUP_MASK 0x03000000L 27432 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID13_GROUP_MASK 0x0C000000L 27433 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID14_GROUP_MASK 0x30000000L 27434 #define MMEA5_IO_WR_CLI2GRP_MAP0__CID15_GROUP_MASK 0xC0000000L 27435 //MMEA5_IO_WR_CLI2GRP_MAP1 27436 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP__SHIFT 0x0 27437 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP__SHIFT 0x2 27438 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP__SHIFT 0x4 27439 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP__SHIFT 0x6 27440 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP__SHIFT 0x8 27441 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP__SHIFT 0xa 27442 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP__SHIFT 0xc 27443 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP__SHIFT 0xe 27444 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP__SHIFT 0x10 27445 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP__SHIFT 0x12 27446 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP__SHIFT 0x14 27447 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP__SHIFT 0x16 27448 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP__SHIFT 0x18 27449 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP__SHIFT 0x1a 27450 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP__SHIFT 0x1c 27451 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP__SHIFT 0x1e 27452 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID16_GROUP_MASK 0x00000003L 27453 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID17_GROUP_MASK 0x0000000CL 27454 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID18_GROUP_MASK 0x00000030L 27455 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID19_GROUP_MASK 0x000000C0L 27456 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID20_GROUP_MASK 0x00000300L 27457 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID21_GROUP_MASK 0x00000C00L 27458 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID22_GROUP_MASK 0x00003000L 27459 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID23_GROUP_MASK 0x0000C000L 27460 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID24_GROUP_MASK 0x00030000L 27461 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID25_GROUP_MASK 0x000C0000L 27462 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID26_GROUP_MASK 0x00300000L 27463 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID27_GROUP_MASK 0x00C00000L 27464 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID28_GROUP_MASK 0x03000000L 27465 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID29_GROUP_MASK 0x0C000000L 27466 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID30_GROUP_MASK 0x30000000L 27467 #define MMEA5_IO_WR_CLI2GRP_MAP1__CID31_GROUP_MASK 0xC0000000L 27468 //MMEA5_IO_RD_COMBINE_FLUSH 27469 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 27470 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 27471 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 27472 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 27473 #define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 27474 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 27475 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 27476 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 27477 #define MMEA5_IO_RD_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 27478 #define MMEA5_IO_RD_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 27479 //MMEA5_IO_WR_COMBINE_FLUSH 27480 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER__SHIFT 0x0 27481 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER__SHIFT 0x4 27482 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER__SHIFT 0x8 27483 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER__SHIFT 0xc 27484 #define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE__SHIFT 0x10 27485 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP0_TIMER_MASK 0x0000000FL 27486 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP1_TIMER_MASK 0x000000F0L 27487 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP2_TIMER_MASK 0x00000F00L 27488 #define MMEA5_IO_WR_COMBINE_FLUSH__GROUP3_TIMER_MASK 0x0000F000L 27489 #define MMEA5_IO_WR_COMBINE_FLUSH__COMB_MODE_MASK 0x00030000L 27490 //MMEA5_IO_GROUP_BURST 27491 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO__SHIFT 0x0 27492 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI__SHIFT 0x8 27493 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO__SHIFT 0x10 27494 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI__SHIFT 0x18 27495 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_LO_MASK 0x000000FFL 27496 #define MMEA5_IO_GROUP_BURST__RD_LIMIT_HI_MASK 0x0000FF00L 27497 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_LO_MASK 0x00FF0000L 27498 #define MMEA5_IO_GROUP_BURST__WR_LIMIT_HI_MASK 0xFF000000L 27499 //MMEA5_IO_RD_PRI_AGE 27500 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 27501 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 27502 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 27503 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 27504 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 27505 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 27506 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 27507 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 27508 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 27509 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 27510 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 27511 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 27512 #define MMEA5_IO_RD_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 27513 #define MMEA5_IO_RD_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 27514 #define MMEA5_IO_RD_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 27515 #define MMEA5_IO_RD_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 27516 //MMEA5_IO_WR_PRI_AGE 27517 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE__SHIFT 0x0 27518 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE__SHIFT 0x3 27519 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE__SHIFT 0x6 27520 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE__SHIFT 0x9 27521 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT__SHIFT 0xc 27522 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT__SHIFT 0xf 27523 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT__SHIFT 0x12 27524 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT__SHIFT 0x15 27525 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGING_RATE_MASK 0x00000007L 27526 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGING_RATE_MASK 0x00000038L 27527 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGING_RATE_MASK 0x000001C0L 27528 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGING_RATE_MASK 0x00000E00L 27529 #define MMEA5_IO_WR_PRI_AGE__GROUP0_AGE_COEFFICIENT_MASK 0x00007000L 27530 #define MMEA5_IO_WR_PRI_AGE__GROUP1_AGE_COEFFICIENT_MASK 0x00038000L 27531 #define MMEA5_IO_WR_PRI_AGE__GROUP2_AGE_COEFFICIENT_MASK 0x001C0000L 27532 #define MMEA5_IO_WR_PRI_AGE__GROUP3_AGE_COEFFICIENT_MASK 0x00E00000L 27533 //MMEA5_IO_RD_PRI_QUEUING 27534 #define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 27535 #define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 27536 #define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 27537 #define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 27538 #define MMEA5_IO_RD_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 27539 #define MMEA5_IO_RD_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 27540 #define MMEA5_IO_RD_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 27541 #define MMEA5_IO_RD_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 27542 //MMEA5_IO_WR_PRI_QUEUING 27543 #define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT__SHIFT 0x0 27544 #define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT__SHIFT 0x3 27545 #define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT__SHIFT 0x6 27546 #define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT__SHIFT 0x9 27547 #define MMEA5_IO_WR_PRI_QUEUING__GROUP0_QUEUING_COEFFICIENT_MASK 0x00000007L 27548 #define MMEA5_IO_WR_PRI_QUEUING__GROUP1_QUEUING_COEFFICIENT_MASK 0x00000038L 27549 #define MMEA5_IO_WR_PRI_QUEUING__GROUP2_QUEUING_COEFFICIENT_MASK 0x000001C0L 27550 #define MMEA5_IO_WR_PRI_QUEUING__GROUP3_QUEUING_COEFFICIENT_MASK 0x00000E00L 27551 //MMEA5_IO_RD_PRI_FIXED 27552 #define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 27553 #define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 27554 #define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 27555 #define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 27556 #define MMEA5_IO_RD_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 27557 #define MMEA5_IO_RD_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 27558 #define MMEA5_IO_RD_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 27559 #define MMEA5_IO_RD_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 27560 //MMEA5_IO_WR_PRI_FIXED 27561 #define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT__SHIFT 0x0 27562 #define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT__SHIFT 0x3 27563 #define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT__SHIFT 0x6 27564 #define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT__SHIFT 0x9 27565 #define MMEA5_IO_WR_PRI_FIXED__GROUP0_FIXED_COEFFICIENT_MASK 0x00000007L 27566 #define MMEA5_IO_WR_PRI_FIXED__GROUP1_FIXED_COEFFICIENT_MASK 0x00000038L 27567 #define MMEA5_IO_WR_PRI_FIXED__GROUP2_FIXED_COEFFICIENT_MASK 0x000001C0L 27568 #define MMEA5_IO_WR_PRI_FIXED__GROUP3_FIXED_COEFFICIENT_MASK 0x00000E00L 27569 //MMEA5_IO_RD_PRI_URGENCY 27570 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 27571 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 27572 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 27573 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 27574 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 27575 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 27576 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 27577 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 27578 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 27579 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 27580 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 27581 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 27582 #define MMEA5_IO_RD_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 27583 #define MMEA5_IO_RD_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 27584 #define MMEA5_IO_RD_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 27585 #define MMEA5_IO_RD_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 27586 //MMEA5_IO_WR_PRI_URGENCY 27587 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT__SHIFT 0x0 27588 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT__SHIFT 0x3 27589 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT__SHIFT 0x6 27590 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT__SHIFT 0x9 27591 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE__SHIFT 0xc 27592 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE__SHIFT 0xd 27593 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE__SHIFT 0xe 27594 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE__SHIFT 0xf 27595 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_COEFFICIENT_MASK 0x00000007L 27596 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_COEFFICIENT_MASK 0x00000038L 27597 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_COEFFICIENT_MASK 0x000001C0L 27598 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_COEFFICIENT_MASK 0x00000E00L 27599 #define MMEA5_IO_WR_PRI_URGENCY__GROUP0_URGENCY_MODE_MASK 0x00001000L 27600 #define MMEA5_IO_WR_PRI_URGENCY__GROUP1_URGENCY_MODE_MASK 0x00002000L 27601 #define MMEA5_IO_WR_PRI_URGENCY__GROUP2_URGENCY_MODE_MASK 0x00004000L 27602 #define MMEA5_IO_WR_PRI_URGENCY__GROUP3_URGENCY_MODE_MASK 0x00008000L 27603 //MMEA5_IO_RD_PRI_URGENCY_MASKING 27604 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 27605 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 27606 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 27607 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 27608 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 27609 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 27610 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 27611 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 27612 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 27613 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 27614 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 27615 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 27616 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 27617 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 27618 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 27619 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 27620 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 27621 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 27622 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 27623 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 27624 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 27625 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 27626 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 27627 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 27628 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 27629 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 27630 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 27631 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 27632 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 27633 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 27634 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 27635 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 27636 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 27637 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 27638 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 27639 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 27640 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 27641 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 27642 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 27643 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 27644 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 27645 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 27646 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 27647 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 27648 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 27649 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 27650 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 27651 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 27652 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 27653 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 27654 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 27655 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 27656 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 27657 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 27658 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 27659 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 27660 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 27661 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 27662 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 27663 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 27664 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 27665 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 27666 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 27667 #define MMEA5_IO_RD_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 27668 //MMEA5_IO_WR_PRI_URGENCY_MASKING 27669 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK__SHIFT 0x0 27670 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK__SHIFT 0x1 27671 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK__SHIFT 0x2 27672 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK__SHIFT 0x3 27673 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK__SHIFT 0x4 27674 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK__SHIFT 0x5 27675 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK__SHIFT 0x6 27676 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK__SHIFT 0x7 27677 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK__SHIFT 0x8 27678 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK__SHIFT 0x9 27679 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK__SHIFT 0xa 27680 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK__SHIFT 0xb 27681 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK__SHIFT 0xc 27682 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK__SHIFT 0xd 27683 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK__SHIFT 0xe 27684 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK__SHIFT 0xf 27685 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK__SHIFT 0x10 27686 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK__SHIFT 0x11 27687 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK__SHIFT 0x12 27688 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK__SHIFT 0x13 27689 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK__SHIFT 0x14 27690 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK__SHIFT 0x15 27691 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK__SHIFT 0x16 27692 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK__SHIFT 0x17 27693 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK__SHIFT 0x18 27694 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK__SHIFT 0x19 27695 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK__SHIFT 0x1a 27696 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK__SHIFT 0x1b 27697 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK__SHIFT 0x1c 27698 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK__SHIFT 0x1d 27699 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK__SHIFT 0x1e 27700 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK__SHIFT 0x1f 27701 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID0_MASK_MASK 0x00000001L 27702 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID1_MASK_MASK 0x00000002L 27703 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID2_MASK_MASK 0x00000004L 27704 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID3_MASK_MASK 0x00000008L 27705 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID4_MASK_MASK 0x00000010L 27706 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID5_MASK_MASK 0x00000020L 27707 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID6_MASK_MASK 0x00000040L 27708 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID7_MASK_MASK 0x00000080L 27709 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID8_MASK_MASK 0x00000100L 27710 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID9_MASK_MASK 0x00000200L 27711 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID10_MASK_MASK 0x00000400L 27712 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID11_MASK_MASK 0x00000800L 27713 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID12_MASK_MASK 0x00001000L 27714 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID13_MASK_MASK 0x00002000L 27715 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID14_MASK_MASK 0x00004000L 27716 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID15_MASK_MASK 0x00008000L 27717 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID16_MASK_MASK 0x00010000L 27718 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID17_MASK_MASK 0x00020000L 27719 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID18_MASK_MASK 0x00040000L 27720 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID19_MASK_MASK 0x00080000L 27721 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID20_MASK_MASK 0x00100000L 27722 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID21_MASK_MASK 0x00200000L 27723 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID22_MASK_MASK 0x00400000L 27724 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID23_MASK_MASK 0x00800000L 27725 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID24_MASK_MASK 0x01000000L 27726 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID25_MASK_MASK 0x02000000L 27727 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID26_MASK_MASK 0x04000000L 27728 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID27_MASK_MASK 0x08000000L 27729 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID28_MASK_MASK 0x10000000L 27730 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID29_MASK_MASK 0x20000000L 27731 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID30_MASK_MASK 0x40000000L 27732 #define MMEA5_IO_WR_PRI_URGENCY_MASKING__CID31_MASK_MASK 0x80000000L 27733 //MMEA5_IO_RD_PRI_QUANT_PRI1 27734 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 27735 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 27736 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 27737 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 27738 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 27739 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 27740 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 27741 #define MMEA5_IO_RD_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 27742 //MMEA5_IO_RD_PRI_QUANT_PRI2 27743 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 27744 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 27745 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 27746 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 27747 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 27748 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 27749 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 27750 #define MMEA5_IO_RD_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 27751 //MMEA5_IO_RD_PRI_QUANT_PRI3 27752 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 27753 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 27754 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 27755 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 27756 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 27757 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 27758 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 27759 #define MMEA5_IO_RD_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 27760 //MMEA5_IO_WR_PRI_QUANT_PRI1 27761 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD__SHIFT 0x0 27762 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD__SHIFT 0x8 27763 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD__SHIFT 0x10 27764 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD__SHIFT 0x18 27765 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP0_THRESHOLD_MASK 0x000000FFL 27766 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP1_THRESHOLD_MASK 0x0000FF00L 27767 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP2_THRESHOLD_MASK 0x00FF0000L 27768 #define MMEA5_IO_WR_PRI_QUANT_PRI1__GROUP3_THRESHOLD_MASK 0xFF000000L 27769 //MMEA5_IO_WR_PRI_QUANT_PRI2 27770 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD__SHIFT 0x0 27771 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD__SHIFT 0x8 27772 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD__SHIFT 0x10 27773 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD__SHIFT 0x18 27774 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP0_THRESHOLD_MASK 0x000000FFL 27775 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP1_THRESHOLD_MASK 0x0000FF00L 27776 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP2_THRESHOLD_MASK 0x00FF0000L 27777 #define MMEA5_IO_WR_PRI_QUANT_PRI2__GROUP3_THRESHOLD_MASK 0xFF000000L 27778 //MMEA5_IO_WR_PRI_QUANT_PRI3 27779 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD__SHIFT 0x0 27780 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD__SHIFT 0x8 27781 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD__SHIFT 0x10 27782 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD__SHIFT 0x18 27783 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP0_THRESHOLD_MASK 0x000000FFL 27784 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP1_THRESHOLD_MASK 0x0000FF00L 27785 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP2_THRESHOLD_MASK 0x00FF0000L 27786 #define MMEA5_IO_WR_PRI_QUANT_PRI3__GROUP3_THRESHOLD_MASK 0xFF000000L 27787 //MMEA5_SDP_ARB_DRAM 27788 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 27789 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 27790 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI__SHIFT 0x10 27791 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI__SHIFT 0x11 27792 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES__SHIFT 0x12 27793 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES__SHIFT 0x13 27794 #define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE__SHIFT 0x14 27795 #define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 27796 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 27797 #define MMEA5_SDP_ARB_DRAM__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 27798 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 27799 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 27800 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2RD_ON_RES_MASK 0x00040000L 27801 #define MMEA5_SDP_ARB_DRAM__EARLY_SW2WR_ON_RES_MASK 0x00080000L 27802 #define MMEA5_SDP_ARB_DRAM__EOB_ON_EXPIRE_MASK 0x00100000L 27803 #define MMEA5_SDP_ARB_DRAM__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 27804 //MMEA5_SDP_ARB_GMI 27805 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL__SHIFT 0x0 27806 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA__SHIFT 0x8 27807 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI__SHIFT 0x10 27808 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI__SHIFT 0x11 27809 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES__SHIFT 0x12 27810 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES__SHIFT 0x13 27811 #define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE__SHIFT 0x14 27812 #define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE__SHIFT 0x15 27813 #define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING__SHIFT 0x16 27814 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_CYCL_MASK 0x0000007FL 27815 #define MMEA5_SDP_ARB_GMI__RDWR_BURST_LIMIT_DATA_MASK 0x00007F00L 27816 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_PRI_MASK 0x00010000L 27817 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_PRI_MASK 0x00020000L 27818 #define MMEA5_SDP_ARB_GMI__EARLY_SW2RD_ON_RES_MASK 0x00040000L 27819 #define MMEA5_SDP_ARB_GMI__EARLY_SW2WR_ON_RES_MASK 0x00080000L 27820 #define MMEA5_SDP_ARB_GMI__EOB_ON_EXPIRE_MASK 0x00100000L 27821 #define MMEA5_SDP_ARB_GMI__DECOUPLE_RDWR_BNKSTATE_MASK 0x00200000L 27822 #define MMEA5_SDP_ARB_GMI__ALLOW_CHAIN_BREAKING_MASK 0x00400000L 27823 //MMEA5_SDP_ARB_FINAL 27824 #define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT__SHIFT 0x0 27825 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT__SHIFT 0x5 27826 #define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT__SHIFT 0xa 27827 #define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER__SHIFT 0xf 27828 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC0__SHIFT 0x11 27829 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC1__SHIFT 0x12 27830 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC2__SHIFT 0x13 27831 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC3__SHIFT 0x14 27832 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC4__SHIFT 0x15 27833 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC5__SHIFT 0x16 27834 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC6__SHIFT 0x17 27835 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC7__SHIFT 0x18 27836 #define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR__SHIFT 0x19 27837 #define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR__SHIFT 0x1a 27838 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH__SHIFT 0x1b 27839 #define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE__SHIFT 0x1c 27840 #define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE__SHIFT 0x1d 27841 #define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE__SHIFT 0x1e 27842 #define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE__SHIFT 0x1f 27843 #define MMEA5_SDP_ARB_FINAL__DRAM_BURST_LIMIT_MASK 0x0000001FL 27844 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_LIMIT_MASK 0x000003E0L 27845 #define MMEA5_SDP_ARB_FINAL__IO_BURST_LIMIT_MASK 0x00007C00L 27846 #define MMEA5_SDP_ARB_FINAL__BURST_LIMIT_MULTIPLIER_MASK 0x00018000L 27847 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC0_MASK 0x00020000L 27848 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC1_MASK 0x00040000L 27849 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC2_MASK 0x00080000L 27850 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC3_MASK 0x00100000L 27851 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC4_MASK 0x00200000L 27852 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC5_MASK 0x00400000L 27853 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC6_MASK 0x00800000L 27854 #define MMEA5_SDP_ARB_FINAL__RDONLY_VC7_MASK 0x01000000L 27855 #define MMEA5_SDP_ARB_FINAL__ERREVENT_ON_ERROR_MASK 0x02000000L 27856 #define MMEA5_SDP_ARB_FINAL__HALTREQ_ON_ERROR_MASK 0x04000000L 27857 #define MMEA5_SDP_ARB_FINAL__GMI_BURST_STRETCH_MASK 0x08000000L 27858 #define MMEA5_SDP_ARB_FINAL__DRAM_RD_THROTTLE_MASK 0x10000000L 27859 #define MMEA5_SDP_ARB_FINAL__DRAM_WR_THROTTLE_MASK 0x20000000L 27860 #define MMEA5_SDP_ARB_FINAL__GMI_RD_THROTTLE_MASK 0x40000000L 27861 #define MMEA5_SDP_ARB_FINAL__GMI_WR_THROTTLE_MASK 0x80000000L 27862 //MMEA5_SDP_DRAM_PRIORITY 27863 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 27864 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 27865 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 27866 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 27867 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 27868 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 27869 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 27870 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 27871 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 27872 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 27873 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 27874 #define MMEA5_SDP_DRAM_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 27875 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 27876 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 27877 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 27878 #define MMEA5_SDP_DRAM_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 27879 //MMEA5_SDP_GMI_PRIORITY 27880 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 27881 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 27882 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 27883 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 27884 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 27885 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 27886 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 27887 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 27888 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 27889 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 27890 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 27891 #define MMEA5_SDP_GMI_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 27892 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 27893 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 27894 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 27895 #define MMEA5_SDP_GMI_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 27896 //MMEA5_SDP_IO_PRIORITY 27897 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY__SHIFT 0x0 27898 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY__SHIFT 0x4 27899 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY__SHIFT 0x8 27900 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY__SHIFT 0xc 27901 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY__SHIFT 0x10 27902 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY__SHIFT 0x14 27903 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY__SHIFT 0x18 27904 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY__SHIFT 0x1c 27905 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP0_PRIORITY_MASK 0x0000000FL 27906 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP1_PRIORITY_MASK 0x000000F0L 27907 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP2_PRIORITY_MASK 0x00000F00L 27908 #define MMEA5_SDP_IO_PRIORITY__RD_GROUP3_PRIORITY_MASK 0x0000F000L 27909 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP0_PRIORITY_MASK 0x000F0000L 27910 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP1_PRIORITY_MASK 0x00F00000L 27911 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP2_PRIORITY_MASK 0x0F000000L 27912 #define MMEA5_SDP_IO_PRIORITY__WR_GROUP3_PRIORITY_MASK 0xF0000000L 27913 //MMEA5_SDP_CREDITS 27914 #define MMEA5_SDP_CREDITS__TAG_LIMIT__SHIFT 0x0 27915 #define MMEA5_SDP_CREDITS__WR_RESP_CREDITS__SHIFT 0x8 27916 #define MMEA5_SDP_CREDITS__RD_RESP_CREDITS__SHIFT 0x10 27917 #define MMEA5_SDP_CREDITS__TAG_LIMIT_MASK 0x000000FFL 27918 #define MMEA5_SDP_CREDITS__WR_RESP_CREDITS_MASK 0x00007F00L 27919 #define MMEA5_SDP_CREDITS__RD_RESP_CREDITS_MASK 0x007F0000L 27920 //MMEA5_SDP_TAG_RESERVE0 27921 #define MMEA5_SDP_TAG_RESERVE0__VC0__SHIFT 0x0 27922 #define MMEA5_SDP_TAG_RESERVE0__VC1__SHIFT 0x8 27923 #define MMEA5_SDP_TAG_RESERVE0__VC2__SHIFT 0x10 27924 #define MMEA5_SDP_TAG_RESERVE0__VC3__SHIFT 0x18 27925 #define MMEA5_SDP_TAG_RESERVE0__VC0_MASK 0x000000FFL 27926 #define MMEA5_SDP_TAG_RESERVE0__VC1_MASK 0x0000FF00L 27927 #define MMEA5_SDP_TAG_RESERVE0__VC2_MASK 0x00FF0000L 27928 #define MMEA5_SDP_TAG_RESERVE0__VC3_MASK 0xFF000000L 27929 //MMEA5_SDP_TAG_RESERVE1 27930 #define MMEA5_SDP_TAG_RESERVE1__VC4__SHIFT 0x0 27931 #define MMEA5_SDP_TAG_RESERVE1__VC5__SHIFT 0x8 27932 #define MMEA5_SDP_TAG_RESERVE1__VC6__SHIFT 0x10 27933 #define MMEA5_SDP_TAG_RESERVE1__VC7__SHIFT 0x18 27934 #define MMEA5_SDP_TAG_RESERVE1__VC4_MASK 0x000000FFL 27935 #define MMEA5_SDP_TAG_RESERVE1__VC5_MASK 0x0000FF00L 27936 #define MMEA5_SDP_TAG_RESERVE1__VC6_MASK 0x00FF0000L 27937 #define MMEA5_SDP_TAG_RESERVE1__VC7_MASK 0xFF000000L 27938 //MMEA5_SDP_VCC_RESERVE0 27939 #define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS__SHIFT 0x0 27940 #define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS__SHIFT 0x6 27941 #define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS__SHIFT 0xc 27942 #define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS__SHIFT 0x12 27943 #define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS__SHIFT 0x18 27944 #define MMEA5_SDP_VCC_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 27945 #define MMEA5_SDP_VCC_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 27946 #define MMEA5_SDP_VCC_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 27947 #define MMEA5_SDP_VCC_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 27948 #define MMEA5_SDP_VCC_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 27949 //MMEA5_SDP_VCC_RESERVE1 27950 #define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS__SHIFT 0x0 27951 #define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS__SHIFT 0x6 27952 #define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS__SHIFT 0xc 27953 #define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 27954 #define MMEA5_SDP_VCC_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 27955 #define MMEA5_SDP_VCC_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 27956 #define MMEA5_SDP_VCC_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 27957 #define MMEA5_SDP_VCC_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 27958 //MMEA5_SDP_VCD_RESERVE0 27959 #define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS__SHIFT 0x0 27960 #define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS__SHIFT 0x6 27961 #define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS__SHIFT 0xc 27962 #define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS__SHIFT 0x12 27963 #define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS__SHIFT 0x18 27964 #define MMEA5_SDP_VCD_RESERVE0__VC0_CREDITS_MASK 0x0000003FL 27965 #define MMEA5_SDP_VCD_RESERVE0__VC1_CREDITS_MASK 0x00000FC0L 27966 #define MMEA5_SDP_VCD_RESERVE0__VC2_CREDITS_MASK 0x0003F000L 27967 #define MMEA5_SDP_VCD_RESERVE0__VC3_CREDITS_MASK 0x00FC0000L 27968 #define MMEA5_SDP_VCD_RESERVE0__VC4_CREDITS_MASK 0x3F000000L 27969 //MMEA5_SDP_VCD_RESERVE1 27970 #define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS__SHIFT 0x0 27971 #define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS__SHIFT 0x6 27972 #define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS__SHIFT 0xc 27973 #define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL__SHIFT 0x1f 27974 #define MMEA5_SDP_VCD_RESERVE1__VC5_CREDITS_MASK 0x0000003FL 27975 #define MMEA5_SDP_VCD_RESERVE1__VC6_CREDITS_MASK 0x00000FC0L 27976 #define MMEA5_SDP_VCD_RESERVE1__VC7_CREDITS_MASK 0x0003F000L 27977 #define MMEA5_SDP_VCD_RESERVE1__DISTRIBUTE_POOL_MASK 0x80000000L 27978 //MMEA5_SDP_REQ_CNTL 27979 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ__SHIFT 0x0 27980 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE__SHIFT 0x1 27981 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC__SHIFT 0x2 27982 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM__SHIFT 0x3 27983 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI__SHIFT 0x4 27984 #define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE__SHIFT 0x5 27985 #define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ__SHIFT 0x6 27986 #define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE__SHIFT 0x8 27987 #define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC__SHIFT 0xa 27988 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_READ_MASK 0x00000001L 27989 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_WRITE_MASK 0x00000002L 27990 #define MMEA5_SDP_REQ_CNTL__REQ_PASS_PW_OVERRIDE_ATOMIC_MASK 0x00000004L 27991 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_DRAM_MASK 0x00000008L 27992 #define MMEA5_SDP_REQ_CNTL__REQ_CHAIN_OVERRIDE_GMI_MASK 0x00000010L 27993 #define MMEA5_SDP_REQ_CNTL__INNER_DOMAIN_MODE_MASK 0x00000020L 27994 #define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_READ_MASK 0x000000C0L 27995 #define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_WRITE_MASK 0x00000300L 27996 #define MMEA5_SDP_REQ_CNTL__REQ_BLOCK_LEVEL_ATOMIC_MASK 0x00000C00L 27997 //MMEA5_MISC 27998 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB__SHIFT 0x0 27999 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB__SHIFT 0x1 28000 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB__SHIFT 0x2 28001 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB__SHIFT 0x3 28002 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB__SHIFT 0x4 28003 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB__SHIFT 0x5 28004 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC0__SHIFT 0x6 28005 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC1__SHIFT 0x7 28006 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC2__SHIFT 0x8 28007 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC3__SHIFT 0x9 28008 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC4__SHIFT 0xa 28009 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC5__SHIFT 0xb 28010 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC6__SHIFT 0xc 28011 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC7__SHIFT 0xd 28012 #define MMEA5_MISC__EARLY_SDP_ORIGDATA__SHIFT 0xe 28013 #define MMEA5_MISC__LINKMGR_DYNAMIC_MODE__SHIFT 0xf 28014 #define MMEA5_MISC__LINKMGR_HALT_THRESHOLD__SHIFT 0x11 28015 #define MMEA5_MISC__LINKMGR_RECONNECT_DELAY__SHIFT 0x13 28016 #define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD__SHIFT 0x15 28017 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB__SHIFT 0x1a 28018 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB__SHIFT 0x1b 28019 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB__SHIFT 0x1c 28020 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB__SHIFT 0x1d 28021 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB__SHIFT 0x1e 28022 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB__SHIFT 0x1f 28023 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_RD_ARB_MASK 0x00000001L 28024 #define MMEA5_MISC__RELATIVE_PRI_IN_DRAM_WR_ARB_MASK 0x00000002L 28025 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_RD_ARB_MASK 0x00000004L 28026 #define MMEA5_MISC__RELATIVE_PRI_IN_GMI_WR_ARB_MASK 0x00000008L 28027 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_RD_ARB_MASK 0x00000010L 28028 #define MMEA5_MISC__RELATIVE_PRI_IN_IO_WR_ARB_MASK 0x00000020L 28029 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC0_MASK 0x00000040L 28030 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC1_MASK 0x00000080L 28031 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC2_MASK 0x00000100L 28032 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC3_MASK 0x00000200L 28033 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC4_MASK 0x00000400L 28034 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC5_MASK 0x00000800L 28035 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC6_MASK 0x00001000L 28036 #define MMEA5_MISC__EARLYWRRET_ENABLE_VC7_MASK 0x00002000L 28037 #define MMEA5_MISC__EARLY_SDP_ORIGDATA_MASK 0x00004000L 28038 #define MMEA5_MISC__LINKMGR_DYNAMIC_MODE_MASK 0x00018000L 28039 #define MMEA5_MISC__LINKMGR_HALT_THRESHOLD_MASK 0x00060000L 28040 #define MMEA5_MISC__LINKMGR_RECONNECT_DELAY_MASK 0x00180000L 28041 #define MMEA5_MISC__LINKMGR_IDLE_THRESHOLD_MASK 0x03E00000L 28042 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_DRAM_ARB_MASK 0x04000000L 28043 #define MMEA5_MISC__FAVOUR_MIDCHAIN_CS_IN_GMI_ARB_MASK 0x08000000L 28044 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_DRAM_ARB_MASK 0x10000000L 28045 #define MMEA5_MISC__FAVOUR_LAST_CS_IN_GMI_ARB_MASK 0x20000000L 28046 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_DRAM_ARB_MASK 0x40000000L 28047 #define MMEA5_MISC__SWITCH_CS_ON_W2R_IN_GMI_ARB_MASK 0x80000000L 28048 //MMEA5_LATENCY_SAMPLING 28049 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM__SHIFT 0x0 28050 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM__SHIFT 0x1 28051 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI__SHIFT 0x2 28052 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI__SHIFT 0x3 28053 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO__SHIFT 0x4 28054 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO__SHIFT 0x5 28055 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ__SHIFT 0x6 28056 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ__SHIFT 0x7 28057 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE__SHIFT 0x8 28058 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE__SHIFT 0x9 28059 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET__SHIFT 0xa 28060 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET__SHIFT 0xb 28061 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET__SHIFT 0xc 28062 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET__SHIFT 0xd 28063 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC__SHIFT 0xe 28064 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC__SHIFT 0x16 28065 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_DRAM_MASK 0x00000001L 28066 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_DRAM_MASK 0x00000002L 28067 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_GMI_MASK 0x00000004L 28068 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_GMI_MASK 0x00000008L 28069 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_IO_MASK 0x00000010L 28070 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_IO_MASK 0x00000020L 28071 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_READ_MASK 0x00000040L 28072 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_READ_MASK 0x00000080L 28073 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_WRITE_MASK 0x00000100L 28074 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_WRITE_MASK 0x00000200L 28075 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_RET_MASK 0x00000400L 28076 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_RET_MASK 0x00000800L 28077 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_ATOMIC_NORET_MASK 0x00001000L 28078 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_ATOMIC_NORET_MASK 0x00002000L 28079 #define MMEA5_LATENCY_SAMPLING__SAMPLER0_VC_MASK 0x003FC000L 28080 #define MMEA5_LATENCY_SAMPLING__SAMPLER1_VC_MASK 0x3FC00000L 28081 //MMEA5_PERFCOUNTER_LO 28082 #define MMEA5_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 28083 #define MMEA5_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 28084 //MMEA5_PERFCOUNTER_HI 28085 #define MMEA5_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 28086 #define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 28087 #define MMEA5_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 28088 #define MMEA5_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 28089 //MMEA5_PERFCOUNTER0_CFG 28090 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 28091 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 28092 #define MMEA5_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 28093 #define MMEA5_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 28094 #define MMEA5_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 28095 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 28096 #define MMEA5_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 28097 #define MMEA5_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 28098 #define MMEA5_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 28099 #define MMEA5_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 28100 //MMEA5_PERFCOUNTER1_CFG 28101 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 28102 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 28103 #define MMEA5_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 28104 #define MMEA5_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 28105 #define MMEA5_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 28106 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 28107 #define MMEA5_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 28108 #define MMEA5_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 28109 #define MMEA5_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 28110 #define MMEA5_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 28111 //MMEA5_PERFCOUNTER_RSLT_CNTL 28112 #define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 28113 #define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 28114 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 28115 #define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 28116 #define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 28117 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 28118 #define MMEA5_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 28119 #define MMEA5_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 28120 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 28121 #define MMEA5_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 28122 #define MMEA5_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 28123 #define MMEA5_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 28124 //MMEA5_EDC_CNT 28125 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT__SHIFT 0x0 28126 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT__SHIFT 0x2 28127 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT__SHIFT 0x4 28128 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT__SHIFT 0x6 28129 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT__SHIFT 0x8 28130 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT__SHIFT 0xa 28131 #define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT__SHIFT 0xc 28132 #define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT__SHIFT 0xe 28133 #define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT__SHIFT 0x10 28134 #define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT__SHIFT 0x12 28135 #define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT__SHIFT 0x14 28136 #define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT__SHIFT 0x16 28137 #define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT__SHIFT 0x18 28138 #define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT__SHIFT 0x1a 28139 #define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT__SHIFT 0x1c 28140 #define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT__SHIFT 0x1e 28141 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 28142 #define MMEA5_EDC_CNT__DRAMRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 28143 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 28144 #define MMEA5_EDC_CNT__DRAMWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 28145 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 28146 #define MMEA5_EDC_CNT__DRAMWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 28147 #define MMEA5_EDC_CNT__RRET_TAGMEM_SEC_COUNT_MASK 0x00003000L 28148 #define MMEA5_EDC_CNT__RRET_TAGMEM_DED_COUNT_MASK 0x0000C000L 28149 #define MMEA5_EDC_CNT__WRET_TAGMEM_SEC_COUNT_MASK 0x00030000L 28150 #define MMEA5_EDC_CNT__WRET_TAGMEM_DED_COUNT_MASK 0x000C0000L 28151 #define MMEA5_EDC_CNT__IOWR_DATAMEM_SEC_COUNT_MASK 0x00300000L 28152 #define MMEA5_EDC_CNT__IOWR_DATAMEM_DED_COUNT_MASK 0x00C00000L 28153 #define MMEA5_EDC_CNT__DRAMRD_PAGEMEM_SED_COUNT_MASK 0x03000000L 28154 #define MMEA5_EDC_CNT__DRAMWR_PAGEMEM_SED_COUNT_MASK 0x0C000000L 28155 #define MMEA5_EDC_CNT__IORD_CMDMEM_SED_COUNT_MASK 0x30000000L 28156 #define MMEA5_EDC_CNT__IOWR_CMDMEM_SED_COUNT_MASK 0xC0000000L 28157 //MMEA5_EDC_CNT2 28158 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT__SHIFT 0x0 28159 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT__SHIFT 0x2 28160 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT__SHIFT 0x4 28161 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT__SHIFT 0x6 28162 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT__SHIFT 0x8 28163 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT__SHIFT 0xa 28164 #define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT__SHIFT 0xc 28165 #define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT__SHIFT 0xe 28166 #define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT__SHIFT 0x10 28167 #define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT__SHIFT 0x12 28168 #define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT__SHIFT 0x14 28169 #define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT__SHIFT 0x16 28170 #define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT__SHIFT 0x18 28171 #define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT__SHIFT 0x1a 28172 #define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT__SHIFT 0x1c 28173 #define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT__SHIFT 0x1e 28174 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_SEC_COUNT_MASK 0x00000003L 28175 #define MMEA5_EDC_CNT2__GMIRD_CMDMEM_DED_COUNT_MASK 0x0000000CL 28176 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_SEC_COUNT_MASK 0x00000030L 28177 #define MMEA5_EDC_CNT2__GMIWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 28178 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_SEC_COUNT_MASK 0x00000300L 28179 #define MMEA5_EDC_CNT2__GMIWR_DATAMEM_DED_COUNT_MASK 0x00000C00L 28180 #define MMEA5_EDC_CNT2__GMIRD_PAGEMEM_SED_COUNT_MASK 0x00003000L 28181 #define MMEA5_EDC_CNT2__GMIWR_PAGEMEM_SED_COUNT_MASK 0x0000C000L 28182 #define MMEA5_EDC_CNT2__MAM_D0MEM_SED_COUNT_MASK 0x00030000L 28183 #define MMEA5_EDC_CNT2__MAM_D1MEM_SED_COUNT_MASK 0x000C0000L 28184 #define MMEA5_EDC_CNT2__MAM_D2MEM_SED_COUNT_MASK 0x00300000L 28185 #define MMEA5_EDC_CNT2__MAM_D3MEM_SED_COUNT_MASK 0x00C00000L 28186 #define MMEA5_EDC_CNT2__MAM_D0MEM_DED_COUNT_MASK 0x03000000L 28187 #define MMEA5_EDC_CNT2__MAM_D1MEM_DED_COUNT_MASK 0x0C000000L 28188 #define MMEA5_EDC_CNT2__MAM_D2MEM_DED_COUNT_MASK 0x30000000L 28189 #define MMEA5_EDC_CNT2__MAM_D3MEM_DED_COUNT_MASK 0xC0000000L 28190 //MMEA5_DSM_CNTL 28191 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 28192 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 28193 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 28194 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 28195 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 28196 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 28197 #define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 28198 #define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 28199 #define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 28200 #define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 28201 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 28202 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 28203 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 28204 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 28205 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0x15 28206 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0x17 28207 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 28208 #define MMEA5_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 28209 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 28210 #define MMEA5_DSM_CNTL__DRAMWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 28211 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 28212 #define MMEA5_DSM_CNTL__DRAMWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 28213 #define MMEA5_DSM_CNTL__RRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 28214 #define MMEA5_DSM_CNTL__RRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 28215 #define MMEA5_DSM_CNTL__WRET_TAGMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 28216 #define MMEA5_DSM_CNTL__WRET_TAGMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 28217 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 28218 #define MMEA5_DSM_CNTL__GMIRD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 28219 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 28220 #define MMEA5_DSM_CNTL__GMIWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 28221 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00600000L 28222 #define MMEA5_DSM_CNTL__GMIWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00800000L 28223 //MMEA5_DSM_CNTLA 28224 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 28225 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 28226 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x3 28227 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x5 28228 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x6 28229 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x8 28230 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x9 28231 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0xb 28232 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA__SHIFT 0xc 28233 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE__SHIFT 0xe 28234 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0xf 28235 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x11 28236 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA__SHIFT 0x12 28237 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE__SHIFT 0x14 28238 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000003L 28239 #define MMEA5_DSM_CNTLA__DRAMRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000004L 28240 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00000018L 28241 #define MMEA5_DSM_CNTLA__DRAMWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00000020L 28242 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x000000C0L 28243 #define MMEA5_DSM_CNTLA__IORD_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000100L 28244 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_DSM_IRRITATOR_DATA_MASK 0x00000600L 28245 #define MMEA5_DSM_CNTLA__IOWR_CMDMEM_ENABLE_SINGLE_WRITE_MASK 0x00000800L 28246 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_DSM_IRRITATOR_DATA_MASK 0x00003000L 28247 #define MMEA5_DSM_CNTLA__IOWR_DATAMEM_ENABLE_SINGLE_WRITE_MASK 0x00004000L 28248 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x00018000L 28249 #define MMEA5_DSM_CNTLA__GMIRD_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00020000L 28250 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_DSM_IRRITATOR_DATA_MASK 0x000C0000L 28251 #define MMEA5_DSM_CNTLA__GMIWR_PAGEMEM_ENABLE_SINGLE_WRITE_MASK 0x00100000L 28252 //MMEA5_DSM_CNTLB 28253 //MMEA5_DSM_CNTL2 28254 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 28255 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x2 28256 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 28257 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x5 28258 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 28259 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x8 28260 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 28261 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xb 28262 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 28263 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY__SHIFT 0xe 28264 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 28265 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x11 28266 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 28267 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x14 28268 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0x15 28269 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0x17 28270 #define MMEA5_DSM_CNTL2__INJECT_DELAY__SHIFT 0x1a 28271 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 28272 #define MMEA5_DSM_CNTL2__DRAMRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 28273 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 28274 #define MMEA5_DSM_CNTL2__DRAMWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 28275 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 28276 #define MMEA5_DSM_CNTL2__DRAMWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 28277 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 28278 #define MMEA5_DSM_CNTL2__RRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 28279 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 28280 #define MMEA5_DSM_CNTL2__WRET_TAGMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 28281 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 28282 #define MMEA5_DSM_CNTL2__GMIRD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 28283 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 28284 #define MMEA5_DSM_CNTL2__GMIWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 28285 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00600000L 28286 #define MMEA5_DSM_CNTL2__GMIWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00800000L 28287 #define MMEA5_DSM_CNTL2__INJECT_DELAY_MASK 0xFC000000L 28288 //MMEA5_DSM_CNTL2A 28289 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x0 28290 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x2 28291 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x3 28292 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x5 28293 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x6 28294 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0x8 28295 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT__SHIFT 0x9 28296 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY__SHIFT 0xb 28297 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT__SHIFT 0xc 28298 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY__SHIFT 0xe 28299 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0xf 28300 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x11 28301 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT__SHIFT 0x12 28302 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY__SHIFT 0x14 28303 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000003L 28304 #define MMEA5_DSM_CNTL2A__DRAMRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000004L 28305 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00000018L 28306 #define MMEA5_DSM_CNTL2A__DRAMWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00000020L 28307 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x000000C0L 28308 #define MMEA5_DSM_CNTL2A__IORD_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000100L 28309 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_ENABLE_ERROR_INJECT_MASK 0x00000600L 28310 #define MMEA5_DSM_CNTL2A__IOWR_CMDMEM_SELECT_INJECT_DELAY_MASK 0x00000800L 28311 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_ENABLE_ERROR_INJECT_MASK 0x00003000L 28312 #define MMEA5_DSM_CNTL2A__IOWR_DATAMEM_SELECT_INJECT_DELAY_MASK 0x00004000L 28313 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x00018000L 28314 #define MMEA5_DSM_CNTL2A__GMIRD_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00020000L 28315 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_ENABLE_ERROR_INJECT_MASK 0x000C0000L 28316 #define MMEA5_DSM_CNTL2A__GMIWR_PAGEMEM_SELECT_INJECT_DELAY_MASK 0x00100000L 28317 //MMEA5_DSM_CNTL2B 28318 //MMEA5_CGTT_CLK_CTRL 28319 #define MMEA5_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 28320 #define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 28321 #define MMEA5_CGTT_CLK_CTRL__SPARE0__SHIFT 0xc 28322 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE__SHIFT 0x14 28323 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ__SHIFT 0x15 28324 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN__SHIFT 0x16 28325 #define MMEA5_CGTT_CLK_CTRL__SPARE1__SHIFT 0x17 28326 #define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE__SHIFT 0x1b 28327 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE__SHIFT 0x1c 28328 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ__SHIFT 0x1d 28329 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN__SHIFT 0x1e 28330 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x1f 28331 #define MMEA5_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 28332 #define MMEA5_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 28333 #define MMEA5_CGTT_CLK_CTRL__SPARE0_MASK 0x000FF000L 28334 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_WRITE_MASK 0x00100000L 28335 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_READ_MASK 0x00200000L 28336 #define MMEA5_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_RETURN_MASK 0x00400000L 28337 #define MMEA5_CGTT_CLK_CTRL__SPARE1_MASK 0x07800000L 28338 #define MMEA5_CGTT_CLK_CTRL__LS_OVERRIDE_MASK 0x08000000L 28339 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_WRITE_MASK 0x10000000L 28340 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_READ_MASK 0x20000000L 28341 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_RETURN_MASK 0x40000000L 28342 #define MMEA5_CGTT_CLK_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x80000000L 28343 //MMEA5_EDC_MODE 28344 #define MMEA5_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 28345 #define MMEA5_EDC_MODE__GATE_FUE__SHIFT 0x11 28346 #define MMEA5_EDC_MODE__DED_MODE__SHIFT 0x14 28347 #define MMEA5_EDC_MODE__PROP_FED__SHIFT 0x1d 28348 #define MMEA5_EDC_MODE__BYPASS__SHIFT 0x1f 28349 #define MMEA5_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 28350 #define MMEA5_EDC_MODE__GATE_FUE_MASK 0x00020000L 28351 #define MMEA5_EDC_MODE__DED_MODE_MASK 0x00300000L 28352 #define MMEA5_EDC_MODE__PROP_FED_MASK 0x20000000L 28353 #define MMEA5_EDC_MODE__BYPASS_MASK 0x80000000L 28354 //MMEA5_ERR_STATUS 28355 #define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS__SHIFT 0x0 28356 #define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS__SHIFT 0x4 28357 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS__SHIFT 0x8 28358 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR__SHIFT 0xa 28359 #define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xb 28360 #define MMEA5_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xc 28361 #define MMEA5_ERR_STATUS__FUE_FLAG__SHIFT 0xd 28362 #define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED__SHIFT 0xe 28363 #define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0xf 28364 #define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL__SHIFT 0x10 28365 #define MMEA5_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x11 28366 #define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR__SHIFT 0x12 28367 #define MMEA5_ERR_STATUS__SDP_RDRSP_STATUS_MASK 0x0000000FL 28368 #define MMEA5_ERR_STATUS__SDP_WRRSP_STATUS_MASK 0x000000F0L 28369 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATASTATUS_MASK 0x00000300L 28370 #define MMEA5_ERR_STATUS__SDP_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L 28371 #define MMEA5_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00000800L 28372 #define MMEA5_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00001000L 28373 #define MMEA5_ERR_STATUS__FUE_FLAG_MASK 0x00002000L 28374 #define MMEA5_ERR_STATUS__IGNORE_RDRSP_FED_MASK 0x00004000L 28375 #define MMEA5_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00008000L 28376 #define MMEA5_ERR_STATUS__INTERRUPT_IGNORE_CLI_FATAL_MASK 0x00010000L 28377 #define MMEA5_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00020000L 28378 #define MMEA5_ERR_STATUS__BUSY_ON_CMPL_FATAL_ERROR_MASK 0x00040000L 28379 //MMEA5_MISC2 28380 #define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB__SHIFT 0x0 28381 #define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB__SHIFT 0x1 28382 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM__SHIFT 0x2 28383 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI__SHIFT 0x7 28384 #define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE__SHIFT 0xc 28385 #define MMEA5_MISC2__RRET_SWAP_MODE__SHIFT 0xd 28386 #define MMEA5_MISC2__BLOCK_REQUESTS__SHIFT 0xe 28387 #define MMEA5_MISC2__REQUESTS_BLOCKED__SHIFT 0xf 28388 #define MMEA5_MISC2__CSGROUP_SWAP_IN_DRAM_ARB_MASK 0x00000001L 28389 #define MMEA5_MISC2__CSGROUP_SWAP_IN_GMI_ARB_MASK 0x00000002L 28390 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_DRAM_MASK 0x0000007CL 28391 #define MMEA5_MISC2__CSGRP_BURST_LIMIT_DATA_GMI_MASK 0x00000F80L 28392 #define MMEA5_MISC2__IO_RDWR_PRIORITY_ENABLE_MASK 0x00001000L 28393 #define MMEA5_MISC2__RRET_SWAP_MODE_MASK 0x00002000L 28394 #define MMEA5_MISC2__BLOCK_REQUESTS_MASK 0x00004000L 28395 #define MMEA5_MISC2__REQUESTS_BLOCKED_MASK 0x00008000L 28396 //MMEA5_ADDRDEC_SELECT 28397 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START__SHIFT 0x0 28398 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END__SHIFT 0x5 28399 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START__SHIFT 0xa 28400 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END__SHIFT 0xf 28401 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_START_MASK 0x0000001FL 28402 #define MMEA5_ADDRDEC_SELECT__DRAM_ADDRDEC_CHANNEL_END_MASK 0x000003E0L 28403 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_START_MASK 0x00007C00L 28404 #define MMEA5_ADDRDEC_SELECT__GMI_ADDRDEC_CHANNEL_END_MASK 0x000F8000L 28405 //MMEA5_EDC_CNT3 28406 #define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT__SHIFT 0x0 28407 #define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT__SHIFT 0x2 28408 #define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT__SHIFT 0x4 28409 #define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT__SHIFT 0x6 28410 #define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT__SHIFT 0x8 28411 #define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT__SHIFT 0xa 28412 #define MMEA5_EDC_CNT3__DRAMRD_PAGEMEM_DED_COUNT_MASK 0x00000003L 28413 #define MMEA5_EDC_CNT3__DRAMWR_PAGEMEM_DED_COUNT_MASK 0x0000000CL 28414 #define MMEA5_EDC_CNT3__IORD_CMDMEM_DED_COUNT_MASK 0x00000030L 28415 #define MMEA5_EDC_CNT3__IOWR_CMDMEM_DED_COUNT_MASK 0x000000C0L 28416 #define MMEA5_EDC_CNT3__GMIRD_PAGEMEM_DED_COUNT_MASK 0x00000300L 28417 #define MMEA5_EDC_CNT3__GMIWR_PAGEMEM_DED_COUNT_MASK 0x00000C00L 28418 //MMEA5_MISC_AON 28419 #define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 28420 #define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 28421 #define MMEA5_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L 28422 #define MMEA5_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L 28423 28424 28425 // addressBlock: mmhub_l1tlb_vml1dec 28426 //MC_VM_MX_L1_TLB0_STATUS 28427 #define MC_VM_MX_L1_TLB0_STATUS__BUSY__SHIFT 0x0 28428 #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28429 #define MC_VM_MX_L1_TLB0_STATUS__BUSY_MASK 0x00000001L 28430 #define MC_VM_MX_L1_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28431 //MC_VM_MX_L1_TLB1_STATUS 28432 #define MC_VM_MX_L1_TLB1_STATUS__BUSY__SHIFT 0x0 28433 #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28434 #define MC_VM_MX_L1_TLB1_STATUS__BUSY_MASK 0x00000001L 28435 #define MC_VM_MX_L1_TLB1_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28436 //MC_VM_MX_L1_TLB2_STATUS 28437 #define MC_VM_MX_L1_TLB2_STATUS__BUSY__SHIFT 0x0 28438 #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28439 #define MC_VM_MX_L1_TLB2_STATUS__BUSY_MASK 0x00000001L 28440 #define MC_VM_MX_L1_TLB2_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28441 //MC_VM_MX_L1_TLB3_STATUS 28442 #define MC_VM_MX_L1_TLB3_STATUS__BUSY__SHIFT 0x0 28443 #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28444 #define MC_VM_MX_L1_TLB3_STATUS__BUSY_MASK 0x00000001L 28445 #define MC_VM_MX_L1_TLB3_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28446 //MC_VM_MX_L1_TLB4_STATUS 28447 #define MC_VM_MX_L1_TLB4_STATUS__BUSY__SHIFT 0x0 28448 #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28449 #define MC_VM_MX_L1_TLB4_STATUS__BUSY_MASK 0x00000001L 28450 #define MC_VM_MX_L1_TLB4_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28451 //MC_VM_MX_L1_TLB5_STATUS 28452 #define MC_VM_MX_L1_TLB5_STATUS__BUSY__SHIFT 0x0 28453 #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28454 #define MC_VM_MX_L1_TLB5_STATUS__BUSY_MASK 0x00000001L 28455 #define MC_VM_MX_L1_TLB5_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28456 //MC_VM_MX_L1_TLB6_STATUS 28457 #define MC_VM_MX_L1_TLB6_STATUS__BUSY__SHIFT 0x0 28458 #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28459 #define MC_VM_MX_L1_TLB6_STATUS__BUSY_MASK 0x00000001L 28460 #define MC_VM_MX_L1_TLB6_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28461 //MC_VM_MX_L1_TLB7_STATUS 28462 #define MC_VM_MX_L1_TLB7_STATUS__BUSY__SHIFT 0x0 28463 #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 28464 #define MC_VM_MX_L1_TLB7_STATUS__BUSY_MASK 0x00000001L 28465 #define MC_VM_MX_L1_TLB7_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 28466 28467 28468 // addressBlock: mmhub_l1tlb_vml1pldec 28469 //MC_VM_MX_L1_PERFCOUNTER0_CFG 28470 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 28471 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 28472 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 28473 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 28474 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 28475 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 28476 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 28477 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 28478 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 28479 #define MC_VM_MX_L1_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 28480 //MC_VM_MX_L1_PERFCOUNTER1_CFG 28481 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 28482 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 28483 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 28484 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 28485 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 28486 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 28487 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 28488 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 28489 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 28490 #define MC_VM_MX_L1_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 28491 //MC_VM_MX_L1_PERFCOUNTER2_CFG 28492 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 28493 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 28494 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 28495 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 28496 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 28497 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 28498 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 28499 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 28500 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 28501 #define MC_VM_MX_L1_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 28502 //MC_VM_MX_L1_PERFCOUNTER3_CFG 28503 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 28504 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 28505 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 28506 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 28507 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 28508 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 28509 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 28510 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 28511 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 28512 #define MC_VM_MX_L1_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 28513 //MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL 28514 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 28515 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 28516 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 28517 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 28518 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 28519 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 28520 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 28521 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 28522 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 28523 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 28524 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 28525 #define MC_VM_MX_L1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 28526 28527 28528 // addressBlock: mmhub_l1tlb_vml1prdec 28529 //MC_VM_MX_L1_PERFCOUNTER_LO 28530 #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 28531 #define MC_VM_MX_L1_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 28532 //MC_VM_MX_L1_PERFCOUNTER_HI 28533 #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 28534 #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 28535 #define MC_VM_MX_L1_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 28536 #define MC_VM_MX_L1_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 28537 28538 28539 // addressBlock: mmhub_pctldec0 28540 //PCTL0_CTRL 28541 #define PCTL0_CTRL__PG_ENABLE__SHIFT 0x0 28542 #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE__SHIFT 0x1 28543 #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD__SHIFT 0xb 28544 #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT__SHIFT 0x10 28545 #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK__SHIFT 0x11 28546 #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK__SHIFT 0x12 28547 #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK__SHIFT 0x13 28548 #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK__SHIFT 0x14 28549 #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK__SHIFT 0x15 28550 #define PCTL0_CTRL__OVR_EA5_SDP_PARTACK__SHIFT 0x16 28551 #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK__SHIFT 0x17 28552 #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK__SHIFT 0x18 28553 #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK__SHIFT 0x19 28554 #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK__SHIFT 0x1a 28555 #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK__SHIFT 0x1b 28556 #define PCTL0_CTRL__OVR_EA5_SDP_FULLACK__SHIFT 0x1c 28557 #define PCTL0_CTRL__PG_ENABLE_MASK 0x00000001L 28558 #define PCTL0_CTRL__ALLOW_DEEP_SLEEP_MODE_MASK 0x0000000EL 28559 #define PCTL0_CTRL__STCTRL_DAGB_IDLE_THRESHOLD_MASK 0x0000F800L 28560 #define PCTL0_CTRL__STCTRL_IGNORE_PROTECTION_FAULT_MASK 0x00010000L 28561 #define PCTL0_CTRL__OVR_EA0_SDP_PARTACK_MASK 0x00020000L 28562 #define PCTL0_CTRL__OVR_EA1_SDP_PARTACK_MASK 0x00040000L 28563 #define PCTL0_CTRL__OVR_EA2_SDP_PARTACK_MASK 0x00080000L 28564 #define PCTL0_CTRL__OVR_EA3_SDP_PARTACK_MASK 0x00100000L 28565 #define PCTL0_CTRL__OVR_EA4_SDP_PARTACK_MASK 0x00200000L 28566 #define PCTL0_CTRL__OVR_EA5_SDP_PARTACK_MASK 0x00400000L 28567 #define PCTL0_CTRL__OVR_EA0_SDP_FULLACK_MASK 0x00800000L 28568 #define PCTL0_CTRL__OVR_EA1_SDP_FULLACK_MASK 0x01000000L 28569 #define PCTL0_CTRL__OVR_EA2_SDP_FULLACK_MASK 0x02000000L 28570 #define PCTL0_CTRL__OVR_EA3_SDP_FULLACK_MASK 0x04000000L 28571 #define PCTL0_CTRL__OVR_EA4_SDP_FULLACK_MASK 0x08000000L 28572 #define PCTL0_CTRL__OVR_EA5_SDP_FULLACK_MASK 0x10000000L 28573 //PCTL0_MMHUB_DEEPSLEEP_IB 28574 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0__SHIFT 0x0 28575 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1__SHIFT 0x1 28576 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2__SHIFT 0x2 28577 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3__SHIFT 0x3 28578 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4__SHIFT 0x4 28579 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5__SHIFT 0x5 28580 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6__SHIFT 0x6 28581 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7__SHIFT 0x7 28582 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8__SHIFT 0x8 28583 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9__SHIFT 0x9 28584 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10__SHIFT 0xa 28585 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11__SHIFT 0xb 28586 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12__SHIFT 0xc 28587 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13__SHIFT 0xd 28588 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14__SHIFT 0xe 28589 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15__SHIFT 0xf 28590 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16__SHIFT 0x10 28591 #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR__SHIFT 0x1f 28592 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS0_MASK 0x00000001L 28593 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS1_MASK 0x00000002L 28594 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS2_MASK 0x00000004L 28595 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS3_MASK 0x00000008L 28596 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS4_MASK 0x00000010L 28597 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS5_MASK 0x00000020L 28598 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS6_MASK 0x00000040L 28599 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS7_MASK 0x00000080L 28600 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS8_MASK 0x00000100L 28601 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS9_MASK 0x00000200L 28602 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS10_MASK 0x00000400L 28603 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS11_MASK 0x00000800L 28604 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS12_MASK 0x00001000L 28605 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS13_MASK 0x00002000L 28606 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS14_MASK 0x00004000L 28607 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS15_MASK 0x00008000L 28608 #define PCTL0_MMHUB_DEEPSLEEP_IB__DS16_MASK 0x00010000L 28609 #define PCTL0_MMHUB_DEEPSLEEP_IB__SETCLEAR_MASK 0x80000000L 28610 //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE 28611 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0__SHIFT 0x0 28612 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1__SHIFT 0x1 28613 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2__SHIFT 0x2 28614 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3__SHIFT 0x3 28615 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4__SHIFT 0x4 28616 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5__SHIFT 0x5 28617 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6__SHIFT 0x6 28618 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7__SHIFT 0x7 28619 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8__SHIFT 0x8 28620 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9__SHIFT 0x9 28621 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10__SHIFT 0xa 28622 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11__SHIFT 0xb 28623 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12__SHIFT 0xc 28624 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13__SHIFT 0xd 28625 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14__SHIFT 0xe 28626 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15__SHIFT 0xf 28627 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16__SHIFT 0x10 28628 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB__SHIFT 0x11 28629 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS0_MASK 0x00000001L 28630 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS1_MASK 0x00000002L 28631 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS2_MASK 0x00000004L 28632 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS3_MASK 0x00000008L 28633 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS4_MASK 0x00000010L 28634 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS5_MASK 0x00000020L 28635 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS6_MASK 0x00000040L 28636 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS7_MASK 0x00000080L 28637 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS8_MASK 0x00000100L 28638 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS9_MASK 0x00000200L 28639 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS10_MASK 0x00000400L 28640 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS11_MASK 0x00000800L 28641 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS12_MASK 0x00001000L 28642 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS13_MASK 0x00002000L 28643 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS14_MASK 0x00004000L 28644 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS15_MASK 0x00008000L 28645 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS16_MASK 0x00010000L 28646 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE__DS_ATHUB_MASK 0x00020000L 28647 //PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB 28648 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0__SHIFT 0x0 28649 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1__SHIFT 0x1 28650 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2__SHIFT 0x2 28651 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3__SHIFT 0x3 28652 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4__SHIFT 0x4 28653 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5__SHIFT 0x5 28654 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6__SHIFT 0x6 28655 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7__SHIFT 0x7 28656 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8__SHIFT 0x8 28657 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9__SHIFT 0x9 28658 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10__SHIFT 0xa 28659 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11__SHIFT 0xb 28660 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12__SHIFT 0xc 28661 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13__SHIFT 0xd 28662 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14__SHIFT 0xe 28663 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15__SHIFT 0xf 28664 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16__SHIFT 0x10 28665 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS0_MASK 0x00000001L 28666 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS1_MASK 0x00000002L 28667 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS2_MASK 0x00000004L 28668 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS3_MASK 0x00000008L 28669 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS4_MASK 0x00000010L 28670 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS5_MASK 0x00000020L 28671 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS6_MASK 0x00000040L 28672 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS7_MASK 0x00000080L 28673 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS8_MASK 0x00000100L 28674 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS9_MASK 0x00000200L 28675 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS10_MASK 0x00000400L 28676 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS11_MASK 0x00000800L 28677 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS12_MASK 0x00001000L 28678 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS13_MASK 0x00002000L 28679 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS14_MASK 0x00004000L 28680 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS15_MASK 0x00008000L 28681 #define PCTL0_MMHUB_DEEPSLEEP_OVERRIDE_IB__DS16_MASK 0x00010000L 28682 //PCTL0_PG_IGNORE_DEEPSLEEP 28683 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0__SHIFT 0x0 28684 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1__SHIFT 0x1 28685 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2__SHIFT 0x2 28686 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3__SHIFT 0x3 28687 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4__SHIFT 0x4 28688 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5__SHIFT 0x5 28689 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6__SHIFT 0x6 28690 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7__SHIFT 0x7 28691 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8__SHIFT 0x8 28692 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9__SHIFT 0x9 28693 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10__SHIFT 0xa 28694 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11__SHIFT 0xb 28695 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12__SHIFT 0xc 28696 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13__SHIFT 0xd 28697 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14__SHIFT 0xe 28698 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15__SHIFT 0xf 28699 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16__SHIFT 0x10 28700 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB__SHIFT 0x11 28701 #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS__SHIFT 0x12 28702 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS0_MASK 0x00000001L 28703 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS1_MASK 0x00000002L 28704 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS2_MASK 0x00000004L 28705 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS3_MASK 0x00000008L 28706 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS4_MASK 0x00000010L 28707 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS5_MASK 0x00000020L 28708 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS6_MASK 0x00000040L 28709 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS7_MASK 0x00000080L 28710 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS8_MASK 0x00000100L 28711 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS9_MASK 0x00000200L 28712 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS10_MASK 0x00000400L 28713 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS11_MASK 0x00000800L 28714 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS12_MASK 0x00001000L 28715 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS13_MASK 0x00002000L 28716 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS14_MASK 0x00004000L 28717 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS15_MASK 0x00008000L 28718 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS16_MASK 0x00010000L 28719 #define PCTL0_PG_IGNORE_DEEPSLEEP__DS_ATHUB_MASK 0x00020000L 28720 #define PCTL0_PG_IGNORE_DEEPSLEEP__ALLIPS_MASK 0x00040000L 28721 //PCTL0_PG_IGNORE_DEEPSLEEP_IB 28722 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0__SHIFT 0x0 28723 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1__SHIFT 0x1 28724 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2__SHIFT 0x2 28725 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3__SHIFT 0x3 28726 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4__SHIFT 0x4 28727 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5__SHIFT 0x5 28728 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6__SHIFT 0x6 28729 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7__SHIFT 0x7 28730 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8__SHIFT 0x8 28731 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9__SHIFT 0x9 28732 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10__SHIFT 0xa 28733 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11__SHIFT 0xb 28734 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12__SHIFT 0xc 28735 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13__SHIFT 0xd 28736 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14__SHIFT 0xe 28737 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15__SHIFT 0xf 28738 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16__SHIFT 0x10 28739 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS__SHIFT 0x11 28740 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS0_MASK 0x00000001L 28741 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS1_MASK 0x00000002L 28742 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS2_MASK 0x00000004L 28743 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS3_MASK 0x00000008L 28744 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS4_MASK 0x00000010L 28745 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS5_MASK 0x00000020L 28746 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS6_MASK 0x00000040L 28747 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS7_MASK 0x00000080L 28748 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS8_MASK 0x00000100L 28749 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS9_MASK 0x00000200L 28750 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS10_MASK 0x00000400L 28751 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS11_MASK 0x00000800L 28752 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS12_MASK 0x00001000L 28753 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS13_MASK 0x00002000L 28754 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS14_MASK 0x00004000L 28755 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS15_MASK 0x00008000L 28756 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__DS16_MASK 0x00010000L 28757 #define PCTL0_PG_IGNORE_DEEPSLEEP_IB__ALLIPS_MASK 0x00020000L 28758 //PCTL0_SLICE0_CFG_DAGB_BUSY 28759 #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 28760 #define PCTL0_SLICE0_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 28761 //PCTL0_SLICE0_CFG_DS_ALLOW 28762 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0__SHIFT 0x0 28763 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1__SHIFT 0x1 28764 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2__SHIFT 0x2 28765 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3__SHIFT 0x3 28766 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4__SHIFT 0x4 28767 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5__SHIFT 0x5 28768 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6__SHIFT 0x6 28769 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7__SHIFT 0x7 28770 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8__SHIFT 0x8 28771 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9__SHIFT 0x9 28772 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10__SHIFT 0xa 28773 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11__SHIFT 0xb 28774 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12__SHIFT 0xc 28775 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13__SHIFT 0xd 28776 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14__SHIFT 0xe 28777 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15__SHIFT 0xf 28778 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16__SHIFT 0x10 28779 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS0_MASK 0x00000001L 28780 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS1_MASK 0x00000002L 28781 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS2_MASK 0x00000004L 28782 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS3_MASK 0x00000008L 28783 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS4_MASK 0x00000010L 28784 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS5_MASK 0x00000020L 28785 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS6_MASK 0x00000040L 28786 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS7_MASK 0x00000080L 28787 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS8_MASK 0x00000100L 28788 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS9_MASK 0x00000200L 28789 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS10_MASK 0x00000400L 28790 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS11_MASK 0x00000800L 28791 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS12_MASK 0x00001000L 28792 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS13_MASK 0x00002000L 28793 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS14_MASK 0x00004000L 28794 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS15_MASK 0x00008000L 28795 #define PCTL0_SLICE0_CFG_DS_ALLOW__DS16_MASK 0x00010000L 28796 //PCTL0_SLICE0_CFG_DS_ALLOW_IB 28797 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 28798 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 28799 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 28800 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 28801 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 28802 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 28803 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 28804 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 28805 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 28806 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 28807 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 28808 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 28809 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 28810 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 28811 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 28812 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 28813 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 28814 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 28815 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 28816 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 28817 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 28818 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 28819 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 28820 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 28821 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 28822 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 28823 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 28824 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 28825 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 28826 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 28827 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 28828 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 28829 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 28830 #define PCTL0_SLICE0_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 28831 //PCTL0_SLICE1_CFG_DAGB_BUSY 28832 #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 28833 #define PCTL0_SLICE1_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 28834 //PCTL0_SLICE1_CFG_DS_ALLOW 28835 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0__SHIFT 0x0 28836 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1__SHIFT 0x1 28837 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2__SHIFT 0x2 28838 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3__SHIFT 0x3 28839 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4__SHIFT 0x4 28840 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5__SHIFT 0x5 28841 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6__SHIFT 0x6 28842 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7__SHIFT 0x7 28843 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8__SHIFT 0x8 28844 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9__SHIFT 0x9 28845 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10__SHIFT 0xa 28846 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11__SHIFT 0xb 28847 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12__SHIFT 0xc 28848 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13__SHIFT 0xd 28849 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14__SHIFT 0xe 28850 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15__SHIFT 0xf 28851 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16__SHIFT 0x10 28852 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS0_MASK 0x00000001L 28853 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS1_MASK 0x00000002L 28854 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS2_MASK 0x00000004L 28855 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS3_MASK 0x00000008L 28856 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS4_MASK 0x00000010L 28857 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS5_MASK 0x00000020L 28858 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS6_MASK 0x00000040L 28859 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS7_MASK 0x00000080L 28860 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS8_MASK 0x00000100L 28861 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS9_MASK 0x00000200L 28862 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS10_MASK 0x00000400L 28863 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS11_MASK 0x00000800L 28864 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS12_MASK 0x00001000L 28865 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS13_MASK 0x00002000L 28866 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS14_MASK 0x00004000L 28867 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS15_MASK 0x00008000L 28868 #define PCTL0_SLICE1_CFG_DS_ALLOW__DS16_MASK 0x00010000L 28869 //PCTL0_SLICE1_CFG_DS_ALLOW_IB 28870 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 28871 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 28872 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 28873 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 28874 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 28875 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 28876 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 28877 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 28878 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 28879 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 28880 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 28881 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 28882 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 28883 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 28884 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 28885 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 28886 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 28887 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 28888 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 28889 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 28890 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 28891 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 28892 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 28893 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 28894 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 28895 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 28896 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 28897 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 28898 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 28899 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 28900 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 28901 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 28902 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 28903 #define PCTL0_SLICE1_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 28904 //PCTL0_SLICE2_CFG_DAGB_BUSY 28905 #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 28906 #define PCTL0_SLICE2_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 28907 //PCTL0_SLICE2_CFG_DS_ALLOW 28908 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0__SHIFT 0x0 28909 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1__SHIFT 0x1 28910 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2__SHIFT 0x2 28911 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3__SHIFT 0x3 28912 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4__SHIFT 0x4 28913 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5__SHIFT 0x5 28914 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6__SHIFT 0x6 28915 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7__SHIFT 0x7 28916 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8__SHIFT 0x8 28917 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9__SHIFT 0x9 28918 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10__SHIFT 0xa 28919 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11__SHIFT 0xb 28920 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12__SHIFT 0xc 28921 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13__SHIFT 0xd 28922 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14__SHIFT 0xe 28923 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15__SHIFT 0xf 28924 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16__SHIFT 0x10 28925 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS0_MASK 0x00000001L 28926 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS1_MASK 0x00000002L 28927 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS2_MASK 0x00000004L 28928 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS3_MASK 0x00000008L 28929 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS4_MASK 0x00000010L 28930 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS5_MASK 0x00000020L 28931 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS6_MASK 0x00000040L 28932 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS7_MASK 0x00000080L 28933 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS8_MASK 0x00000100L 28934 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS9_MASK 0x00000200L 28935 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS10_MASK 0x00000400L 28936 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS11_MASK 0x00000800L 28937 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS12_MASK 0x00001000L 28938 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS13_MASK 0x00002000L 28939 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS14_MASK 0x00004000L 28940 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS15_MASK 0x00008000L 28941 #define PCTL0_SLICE2_CFG_DS_ALLOW__DS16_MASK 0x00010000L 28942 //PCTL0_SLICE2_CFG_DS_ALLOW_IB 28943 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 28944 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 28945 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 28946 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 28947 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 28948 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 28949 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 28950 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 28951 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 28952 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 28953 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 28954 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 28955 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 28956 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 28957 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 28958 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 28959 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 28960 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 28961 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 28962 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 28963 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 28964 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 28965 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 28966 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 28967 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 28968 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 28969 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 28970 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 28971 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 28972 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 28973 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 28974 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 28975 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 28976 #define PCTL0_SLICE2_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 28977 //PCTL0_SLICE3_CFG_DAGB_BUSY 28978 #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 28979 #define PCTL0_SLICE3_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 28980 //PCTL0_SLICE3_CFG_DS_ALLOW 28981 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0__SHIFT 0x0 28982 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1__SHIFT 0x1 28983 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2__SHIFT 0x2 28984 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3__SHIFT 0x3 28985 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4__SHIFT 0x4 28986 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5__SHIFT 0x5 28987 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6__SHIFT 0x6 28988 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7__SHIFT 0x7 28989 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8__SHIFT 0x8 28990 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9__SHIFT 0x9 28991 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10__SHIFT 0xa 28992 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11__SHIFT 0xb 28993 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12__SHIFT 0xc 28994 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13__SHIFT 0xd 28995 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14__SHIFT 0xe 28996 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15__SHIFT 0xf 28997 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16__SHIFT 0x10 28998 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS0_MASK 0x00000001L 28999 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS1_MASK 0x00000002L 29000 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS2_MASK 0x00000004L 29001 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS3_MASK 0x00000008L 29002 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS4_MASK 0x00000010L 29003 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS5_MASK 0x00000020L 29004 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS6_MASK 0x00000040L 29005 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS7_MASK 0x00000080L 29006 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS8_MASK 0x00000100L 29007 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS9_MASK 0x00000200L 29008 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS10_MASK 0x00000400L 29009 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS11_MASK 0x00000800L 29010 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS12_MASK 0x00001000L 29011 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS13_MASK 0x00002000L 29012 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS14_MASK 0x00004000L 29013 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS15_MASK 0x00008000L 29014 #define PCTL0_SLICE3_CFG_DS_ALLOW__DS16_MASK 0x00010000L 29015 //PCTL0_SLICE3_CFG_DS_ALLOW_IB 29016 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 29017 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 29018 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 29019 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 29020 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 29021 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 29022 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 29023 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 29024 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 29025 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 29026 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 29027 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 29028 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 29029 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 29030 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 29031 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 29032 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 29033 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 29034 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 29035 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 29036 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 29037 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 29038 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 29039 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 29040 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 29041 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 29042 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 29043 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 29044 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 29045 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 29046 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 29047 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 29048 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 29049 #define PCTL0_SLICE3_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 29050 //PCTL0_SLICE4_CFG_DAGB_BUSY 29051 #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 29052 #define PCTL0_SLICE4_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 29053 //PCTL0_SLICE4_CFG_DS_ALLOW 29054 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0__SHIFT 0x0 29055 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1__SHIFT 0x1 29056 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2__SHIFT 0x2 29057 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3__SHIFT 0x3 29058 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4__SHIFT 0x4 29059 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5__SHIFT 0x5 29060 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6__SHIFT 0x6 29061 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7__SHIFT 0x7 29062 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8__SHIFT 0x8 29063 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9__SHIFT 0x9 29064 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10__SHIFT 0xa 29065 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11__SHIFT 0xb 29066 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12__SHIFT 0xc 29067 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13__SHIFT 0xd 29068 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14__SHIFT 0xe 29069 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15__SHIFT 0xf 29070 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16__SHIFT 0x10 29071 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS0_MASK 0x00000001L 29072 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS1_MASK 0x00000002L 29073 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS2_MASK 0x00000004L 29074 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS3_MASK 0x00000008L 29075 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS4_MASK 0x00000010L 29076 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS5_MASK 0x00000020L 29077 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS6_MASK 0x00000040L 29078 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS7_MASK 0x00000080L 29079 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS8_MASK 0x00000100L 29080 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS9_MASK 0x00000200L 29081 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS10_MASK 0x00000400L 29082 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS11_MASK 0x00000800L 29083 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS12_MASK 0x00001000L 29084 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS13_MASK 0x00002000L 29085 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS14_MASK 0x00004000L 29086 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS15_MASK 0x00008000L 29087 #define PCTL0_SLICE4_CFG_DS_ALLOW__DS16_MASK 0x00010000L 29088 //PCTL0_SLICE4_CFG_DS_ALLOW_IB 29089 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 29090 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 29091 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 29092 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 29093 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 29094 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 29095 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 29096 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 29097 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 29098 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 29099 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 29100 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 29101 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 29102 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 29103 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 29104 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 29105 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 29106 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 29107 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 29108 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 29109 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 29110 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 29111 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 29112 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 29113 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 29114 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 29115 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 29116 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 29117 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 29118 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 29119 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 29120 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 29121 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 29122 #define PCTL0_SLICE4_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 29123 //PCTL0_SLICE5_CFG_DAGB_BUSY 29124 #define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG__SHIFT 0x0 29125 #define PCTL0_SLICE5_CFG_DAGB_BUSY__DB_LNCFG_MASK 0xFFFFFFFFL 29126 //PCTL0_SLICE5_CFG_DS_ALLOW 29127 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS0__SHIFT 0x0 29128 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS1__SHIFT 0x1 29129 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS2__SHIFT 0x2 29130 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS3__SHIFT 0x3 29131 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS4__SHIFT 0x4 29132 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS5__SHIFT 0x5 29133 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS6__SHIFT 0x6 29134 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS7__SHIFT 0x7 29135 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS8__SHIFT 0x8 29136 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS9__SHIFT 0x9 29137 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS10__SHIFT 0xa 29138 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS11__SHIFT 0xb 29139 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS12__SHIFT 0xc 29140 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS13__SHIFT 0xd 29141 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS14__SHIFT 0xe 29142 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS15__SHIFT 0xf 29143 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS16__SHIFT 0x10 29144 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS0_MASK 0x00000001L 29145 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS1_MASK 0x00000002L 29146 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS2_MASK 0x00000004L 29147 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS3_MASK 0x00000008L 29148 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS4_MASK 0x00000010L 29149 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS5_MASK 0x00000020L 29150 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS6_MASK 0x00000040L 29151 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS7_MASK 0x00000080L 29152 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS8_MASK 0x00000100L 29153 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS9_MASK 0x00000200L 29154 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS10_MASK 0x00000400L 29155 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS11_MASK 0x00000800L 29156 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS12_MASK 0x00001000L 29157 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS13_MASK 0x00002000L 29158 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS14_MASK 0x00004000L 29159 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS15_MASK 0x00008000L 29160 #define PCTL0_SLICE5_CFG_DS_ALLOW__DS16_MASK 0x00010000L 29161 //PCTL0_SLICE5_CFG_DS_ALLOW_IB 29162 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0__SHIFT 0x0 29163 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1__SHIFT 0x1 29164 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2__SHIFT 0x2 29165 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3__SHIFT 0x3 29166 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4__SHIFT 0x4 29167 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5__SHIFT 0x5 29168 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6__SHIFT 0x6 29169 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7__SHIFT 0x7 29170 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8__SHIFT 0x8 29171 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9__SHIFT 0x9 29172 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10__SHIFT 0xa 29173 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11__SHIFT 0xb 29174 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12__SHIFT 0xc 29175 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13__SHIFT 0xd 29176 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14__SHIFT 0xe 29177 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15__SHIFT 0xf 29178 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16__SHIFT 0x10 29179 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS0_MASK 0x00000001L 29180 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS1_MASK 0x00000002L 29181 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS2_MASK 0x00000004L 29182 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS3_MASK 0x00000008L 29183 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS4_MASK 0x00000010L 29184 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS5_MASK 0x00000020L 29185 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS6_MASK 0x00000040L 29186 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS7_MASK 0x00000080L 29187 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS8_MASK 0x00000100L 29188 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS9_MASK 0x00000200L 29189 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS10_MASK 0x00000400L 29190 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS11_MASK 0x00000800L 29191 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS12_MASK 0x00001000L 29192 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS13_MASK 0x00002000L 29193 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS14_MASK 0x00004000L 29194 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS15_MASK 0x00008000L 29195 #define PCTL0_SLICE5_CFG_DS_ALLOW_IB__DS16_MASK 0x00010000L 29196 //PCTL0_UTCL2_MISC 29197 #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xb 29198 #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xc 29199 #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xf 29200 #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0x10 29201 #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 29202 #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 29203 #define PCTL0_UTCL2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000800L 29204 #define PCTL0_UTCL2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00007000L 29205 #define PCTL0_UTCL2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00008000L 29206 #define PCTL0_UTCL2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00010000L 29207 #define PCTL0_UTCL2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 29208 #define PCTL0_UTCL2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 29209 //PCTL0_SLICE0_MISC 29210 #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 29211 #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 29212 #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 29213 #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 29214 #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 29215 #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 29216 #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE__SHIFT 0x12 29217 #define PCTL0_SLICE0_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 29218 #define PCTL0_SLICE0_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 29219 #define PCTL0_SLICE0_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 29220 #define PCTL0_SLICE0_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 29221 #define PCTL0_SLICE0_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 29222 #define PCTL0_SLICE0_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 29223 #define PCTL0_SLICE0_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 29224 //PCTL0_SLICE1_MISC 29225 #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 29226 #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 29227 #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 29228 #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 29229 #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 29230 #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 29231 #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE__SHIFT 0x12 29232 #define PCTL0_SLICE1_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 29233 #define PCTL0_SLICE1_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 29234 #define PCTL0_SLICE1_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 29235 #define PCTL0_SLICE1_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 29236 #define PCTL0_SLICE1_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 29237 #define PCTL0_SLICE1_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 29238 #define PCTL0_SLICE1_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 29239 //PCTL0_SLICE2_MISC 29240 #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 29241 #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 29242 #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 29243 #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 29244 #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 29245 #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 29246 #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE__SHIFT 0x12 29247 #define PCTL0_SLICE2_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 29248 #define PCTL0_SLICE2_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 29249 #define PCTL0_SLICE2_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 29250 #define PCTL0_SLICE2_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 29251 #define PCTL0_SLICE2_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 29252 #define PCTL0_SLICE2_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 29253 #define PCTL0_SLICE2_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 29254 //PCTL0_SLICE3_MISC 29255 #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 29256 #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 29257 #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 29258 #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 29259 #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 29260 #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 29261 #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE__SHIFT 0x12 29262 #define PCTL0_SLICE3_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 29263 #define PCTL0_SLICE3_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 29264 #define PCTL0_SLICE3_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 29265 #define PCTL0_SLICE3_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 29266 #define PCTL0_SLICE3_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 29267 #define PCTL0_SLICE3_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 29268 #define PCTL0_SLICE3_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 29269 //PCTL0_SLICE4_MISC 29270 #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 29271 #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 29272 #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 29273 #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 29274 #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 29275 #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 29276 #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE__SHIFT 0x12 29277 #define PCTL0_SLICE4_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 29278 #define PCTL0_SLICE4_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 29279 #define PCTL0_SLICE4_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 29280 #define PCTL0_SLICE4_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 29281 #define PCTL0_SLICE4_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 29282 #define PCTL0_SLICE4_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 29283 #define PCTL0_SLICE4_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 29284 //PCTL0_SLICE5_MISC 29285 #define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK__SHIFT 0xa 29286 #define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD__SHIFT 0xb 29287 #define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE__SHIFT 0xe 29288 #define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE__SHIFT 0xf 29289 #define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP__SHIFT 0x10 29290 #define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE__SHIFT 0x11 29291 #define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE__SHIFT 0x12 29292 #define PCTL0_SLICE5_MISC__CRITICAL_REGS_LOCK_MASK 0x00000400L 29293 #define PCTL0_SLICE5_MISC__TILE_IDLE_THRESHOLD_MASK 0x00003800L 29294 #define PCTL0_SLICE5_MISC__RENG_MEM_LS_ENABLE_MASK 0x00004000L 29295 #define PCTL0_SLICE5_MISC__STCTRL_FORCE_PGFSM_CMD_DONE_MASK 0x00008000L 29296 #define PCTL0_SLICE5_MISC__DEEPSLEEP_DISCSDP_MASK 0x00010000L 29297 #define PCTL0_SLICE5_MISC__RENG_EXECUTE_ON_REG_UPDATE_MASK 0x00020000L 29298 #define PCTL0_SLICE5_MISC__RD_TIMER_ENABLE_MASK 0x00040000L 29299 29300 29301 // addressBlock: mmhub_utcl2_atcl2dec 29302 //ATC_L2_CNTL 29303 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS__SHIFT 0x0 29304 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS__SHIFT 0x3 29305 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0x6 29306 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0x7 29307 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS__SHIFT 0x8 29308 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS__SHIFT 0xb 29309 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD__SHIFT 0xe 29310 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD__SHIFT 0xf 29311 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE__SHIFT 0x10 29312 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0x13 29313 #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE__SHIFT 0x14 29314 #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE__SHIFT 0x16 29315 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READ_REQUESTS_MASK 0x00000003L 29316 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITE_REQUESTS_MASK 0x00000018L 29317 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00000040L 29318 #define ATC_L2_CNTL__NUMBER_OF_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00000080L 29319 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READ_REQUESTS_MASK 0x00000300L 29320 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITE_REQUESTS_MASK 0x00001800L 29321 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_READS_DEPENDS_ON_ADDR_MOD_MASK 0x00004000L 29322 #define ATC_L2_CNTL__NUMBER_OF_HOST_TRANSLATION_WRITES_DEPENDS_ON_ADDR_MOD_MASK 0x00008000L 29323 #define ATC_L2_CNTL__CACHE_INVALIDATE_MODE_MASK 0x00070000L 29324 #define ATC_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00080000L 29325 #define ATC_L2_CNTL__FRAG_APT_INTXN_MODE_MASK 0x00300000L 29326 #define ATC_L2_CNTL__CLI_GPA_REQ_FRAG_SIZE_MASK 0x0FC00000L 29327 //ATC_L2_CNTL2 29328 #define ATC_L2_CNTL2__BANK_SELECT__SHIFT 0x0 29329 #define ATC_L2_CNTL2__NUM_BANKS_LOG2__SHIFT 0x6 29330 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE__SHIFT 0x9 29331 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xb 29332 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS__SHIFT 0xc 29333 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE__SHIFT 0xf 29334 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x12 29335 #define ATC_L2_CNTL2__BANK_SELECT_MASK 0x0000003FL 29336 #define ATC_L2_CNTL2__NUM_BANKS_LOG2_MASK 0x000001C0L 29337 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_MODE_MASK 0x00000600L 29338 #define ATC_L2_CNTL2__ENABLE_L2_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000800L 29339 #define ATC_L2_CNTL2__L2_CACHE_SWAP_TAG_INDEX_LSBS_MASK 0x00007000L 29340 #define ATC_L2_CNTL2__L2_CACHE_VMID_MODE_MASK 0x00038000L 29341 #define ATC_L2_CNTL2__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00FC0000L 29342 //ATC_L2_CACHE_DATA0 29343 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID__SHIFT 0x0 29344 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID__SHIFT 0x1 29345 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES__SHIFT 0x2 29346 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH__SHIFT 0x17 29347 #define ATC_L2_CACHE_DATA0__DATA_REGISTER_VALID_MASK 0x00000001L 29348 #define ATC_L2_CACHE_DATA0__CACHE_ENTRY_VALID_MASK 0x00000002L 29349 #define ATC_L2_CACHE_DATA0__CACHED_ATTRIBUTES_MASK 0x007FFFFCL 29350 #define ATC_L2_CACHE_DATA0__VIRTUAL_PAGE_ADDRESS_HIGH_MASK 0x07800000L 29351 //ATC_L2_CACHE_DATA1 29352 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW__SHIFT 0x0 29353 #define ATC_L2_CACHE_DATA1__VIRTUAL_PAGE_ADDRESS_LOW_MASK 0xFFFFFFFFL 29354 //ATC_L2_CACHE_DATA2 29355 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 29356 #define ATC_L2_CACHE_DATA2__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 29357 //ATC_L2_CACHE_DATA3 29358 #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS__SHIFT 0x0 29359 #define ATC_L2_CACHE_DATA3__PHYSICAL_PAGE_ADDRESS_MASK 0xFFFFFFFFL 29360 //ATC_L2_CNTL3 29361 #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE__SHIFT 0x0 29362 #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE__SHIFT 0x6 29363 #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE__SHIFT 0xc 29364 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST__SHIFT 0x12 29365 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1__SHIFT 0x15 29366 #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS__SHIFT 0x1b 29367 #define ATC_L2_CNTL3__REPEATER_FGCG_OFF__SHIFT 0x1e 29368 #define ATC_L2_CNTL3__L2_SMALLK_FRAGMENT_SIZE_MASK 0x0000003FL 29369 #define ATC_L2_CNTL3__L2_MIDK_FRAGMENT_SIZE_MASK 0x00000FC0L 29370 #define ATC_L2_CNTL3__L2_BIGK_FRAGMENT_SIZE_MASK 0x0003F000L 29371 #define ATC_L2_CNTL3__DELAY_SEND_INVALIDATION_REQUEST_MASK 0x001C0000L 29372 #define ATC_L2_CNTL3__ATS_REQUEST_CREDIT_MINUS1_MASK 0x07E00000L 29373 #define ATC_L2_CNTL3__COMPCLKREQ_OFF_HYSTERESIS_MASK 0x38000000L 29374 #define ATC_L2_CNTL3__REPEATER_FGCG_OFF_MASK 0x40000000L 29375 //ATC_L2_STATUS 29376 #define ATC_L2_STATUS__BUSY__SHIFT 0x0 29377 #define ATC_L2_STATUS__BUSY_MASK 0x00000001L 29378 //ATC_L2_STATUS2 29379 #define ATC_L2_STATUS2__UCE_MEM_ADDR__SHIFT 0x0 29380 #define ATC_L2_STATUS2__UCE_MEM_INST__SHIFT 0xc 29381 #define ATC_L2_STATUS2__UCE_SRT_CACHE__SHIFT 0x12 29382 #define ATC_L2_STATUS2__UCE__SHIFT 0x13 29383 #define ATC_L2_STATUS2__UCE_MEM_ADDR_MASK 0x00000FFFL 29384 #define ATC_L2_STATUS2__UCE_MEM_INST_MASK 0x0003F000L 29385 #define ATC_L2_STATUS2__UCE_SRT_CACHE_MASK 0x00040000L 29386 #define ATC_L2_STATUS2__UCE_MASK 0x00080000L 29387 //ATC_L2_MISC_CG 29388 #define ATC_L2_MISC_CG__OFFDLY__SHIFT 0x6 29389 #define ATC_L2_MISC_CG__ENABLE__SHIFT 0x12 29390 #define ATC_L2_MISC_CG__MEM_LS_ENABLE__SHIFT 0x13 29391 #define ATC_L2_MISC_CG__OFFDLY_MASK 0x00000FC0L 29392 #define ATC_L2_MISC_CG__ENABLE_MASK 0x00040000L 29393 #define ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK 0x00080000L 29394 //ATC_L2_MEM_POWER_LS 29395 #define ATC_L2_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 29396 #define ATC_L2_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 29397 #define ATC_L2_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 29398 #define ATC_L2_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 29399 //ATC_L2_CGTT_CLK_CTRL 29400 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 29401 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 29402 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 29403 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 29404 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 29405 #define ATC_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 29406 #define ATC_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 29407 #define ATC_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 29408 #define ATC_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 29409 #define ATC_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 29410 //ATC_L2_CACHE_4K_DSM_INDEX 29411 #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX__SHIFT 0x0 29412 #define ATC_L2_CACHE_4K_DSM_INDEX__INDEX_MASK 0x000000FFL 29413 //ATC_L2_CACHE_32K_DSM_INDEX 29414 #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX__SHIFT 0x0 29415 #define ATC_L2_CACHE_32K_DSM_INDEX__INDEX_MASK 0x000000FFL 29416 //ATC_L2_CACHE_2M_DSM_INDEX 29417 #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX__SHIFT 0x0 29418 #define ATC_L2_CACHE_2M_DSM_INDEX__INDEX_MASK 0x000000FFL 29419 //ATC_L2_CACHE_4K_DSM_CNTL 29420 #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 29421 #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 29422 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 29423 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 29424 #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 29425 #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc 29426 #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT__SHIFT 0xd 29427 #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT__SHIFT 0xf 29428 #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE__SHIFT 0x11 29429 #define ATC_L2_CACHE_4K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL 29430 #define ATC_L2_CACHE_4K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 29431 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 29432 #define ATC_L2_CACHE_4K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 29433 #define ATC_L2_CACHE_4K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 29434 #define ATC_L2_CACHE_4K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L 29435 #define ATC_L2_CACHE_4K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 29436 #define ATC_L2_CACHE_4K_DSM_CNTL__DED_COUNT_MASK 0x00018000L 29437 #define ATC_L2_CACHE_4K_DSM_CNTL__TEST_FUE_MASK 0x00020000L 29438 //ATC_L2_CACHE_32K_DSM_CNTL 29439 #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 29440 #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 29441 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 29442 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 29443 #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 29444 #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc 29445 #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT__SHIFT 0xd 29446 #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT__SHIFT 0xf 29447 #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE__SHIFT 0x11 29448 #define ATC_L2_CACHE_32K_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL 29449 #define ATC_L2_CACHE_32K_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 29450 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 29451 #define ATC_L2_CACHE_32K_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 29452 #define ATC_L2_CACHE_32K_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 29453 #define ATC_L2_CACHE_32K_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L 29454 #define ATC_L2_CACHE_32K_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 29455 #define ATC_L2_CACHE_32K_DSM_CNTL__DED_COUNT_MASK 0x00018000L 29456 #define ATC_L2_CACHE_32K_DSM_CNTL__TEST_FUE_MASK 0x00020000L 29457 //ATC_L2_CACHE_2M_DSM_CNTL 29458 #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY__SHIFT 0x0 29459 #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 29460 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 29461 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 29462 #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 29463 #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS__SHIFT 0xc 29464 #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT__SHIFT 0xd 29465 #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT__SHIFT 0xf 29466 #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE__SHIFT 0x11 29467 #define ATC_L2_CACHE_2M_DSM_CNTL__INJECT_DELAY_MASK 0x0000003FL 29468 #define ATC_L2_CACHE_2M_DSM_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 29469 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 29470 #define ATC_L2_CACHE_2M_DSM_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 29471 #define ATC_L2_CACHE_2M_DSM_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 29472 #define ATC_L2_CACHE_2M_DSM_CNTL__WRITE_COUNTERS_MASK 0x00001000L 29473 #define ATC_L2_CACHE_2M_DSM_CNTL__SEC_COUNT_MASK 0x00006000L 29474 #define ATC_L2_CACHE_2M_DSM_CNTL__DED_COUNT_MASK 0x00018000L 29475 #define ATC_L2_CACHE_2M_DSM_CNTL__TEST_FUE_MASK 0x00020000L 29476 //ATC_L2_CNTL4 29477 #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x0 29478 #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0xa 29479 #define ATC_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000003FFL 29480 #define ATC_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x000FFC00L 29481 //ATC_L2_MM_GROUP_RT_CLASSES 29482 #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS__SHIFT 0x0 29483 #define ATC_L2_MM_GROUP_RT_CLASSES__GROUP_RT_CLASS_MASK 0xFFFFFFFFL 29484 29485 29486 // addressBlock: mmhub_utcl2_atcl2pfcntldec 29487 //ATC_L2_PERFCOUNTER0_CFG 29488 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 29489 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 29490 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 29491 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 29492 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 29493 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 29494 #define ATC_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 29495 #define ATC_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 29496 #define ATC_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 29497 #define ATC_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 29498 //ATC_L2_PERFCOUNTER1_CFG 29499 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 29500 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 29501 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 29502 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 29503 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 29504 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 29505 #define ATC_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 29506 #define ATC_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 29507 #define ATC_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 29508 #define ATC_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 29509 //ATC_L2_PERFCOUNTER_RSLT_CNTL 29510 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 29511 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 29512 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 29513 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 29514 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 29515 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 29516 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 29517 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 29518 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 29519 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 29520 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 29521 #define ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 29522 29523 29524 // addressBlock: mmhub_utcl2_atcl2pfcntrdec 29525 //ATC_L2_PERFCOUNTER_LO 29526 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 29527 #define ATC_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 29528 //ATC_L2_PERFCOUNTER_HI 29529 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 29530 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 29531 #define ATC_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 29532 #define ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 29533 29534 29535 // addressBlock: mmhub_utcl2_l2tlbdec 29536 //L2TLB_TLB0_STATUS 29537 #define L2TLB_TLB0_STATUS__BUSY__SHIFT 0x0 29538 #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS__SHIFT 0x1 29539 #define L2TLB_TLB0_STATUS__BUSY_MASK 0x00000001L 29540 #define L2TLB_TLB0_STATUS__FOUND_PARITY_ERRORS_MASK 0x00000002L 29541 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO 29542 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR__SHIFT 0x0 29543 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_LO__ADDR_MASK 0xFFFFFFFFL 29544 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI 29545 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR__SHIFT 0x0 29546 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID__SHIFT 0x4 29547 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID__SHIFT 0x9 29548 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF__SHIFT 0xd 29549 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA__SHIFT 0xe 29550 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM__SHIFT 0x10 29551 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM__SHIFT 0x11 29552 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM__SHIFT 0x12 29553 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID__SHIFT 0x13 29554 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ__SHIFT 0x1f 29555 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__ADDR_MASK 0x0000000FL 29556 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VMID_MASK 0x000000F0L 29557 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VFID_MASK 0x00001E00L 29558 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__VF_MASK 0x00002000L 29559 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__GPA_MASK 0x0000C000L 29560 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__RD_PERM_MASK 0x00010000L 29561 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__WR_PERM_MASK 0x00020000L 29562 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__EX_PERM_MASK 0x00040000L 29563 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__CLIENT_ID_MASK 0x0FF80000L 29564 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_REQUEST_HI__REQ_MASK 0x80000000L 29565 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO 29566 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR__SHIFT 0x0 29567 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_LO__ADDR_MASK 0xFFFFFFFFL 29568 //UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI 29569 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR__SHIFT 0x0 29570 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS__SHIFT 0x4 29571 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE__SHIFT 0x7 29572 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP__SHIFT 0xd 29573 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA__SHIFT 0xe 29574 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO__SHIFT 0xf 29575 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ__SHIFT 0x10 29576 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE__SHIFT 0x11 29577 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE__SHIFT 0x12 29578 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG__SHIFT 0x14 29579 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK__SHIFT 0x15 29580 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK__SHIFT 0x1e 29581 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ADDR_MASK 0x0000000FL 29582 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PERMS_MASK 0x00000070L 29583 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__FRAGMENT_SIZE_MASK 0x00001F80L 29584 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SNOOP_MASK 0x00002000L 29585 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__SPA_MASK 0x00004000L 29586 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__IO_MASK 0x00008000L 29587 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__PTE_TMZ_MASK 0x00010000L 29588 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NO_PTE_MASK 0x00020000L 29589 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MTYPE_MASK 0x000C0000L 29590 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__MEMLOG_MASK 0x00100000L 29591 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__NACK_MASK 0x00600000L 29592 #define UTC_GPUVA_VMID_TRANSLATION_ASSIST_RESPONSE_HI__ACK_MASK 0x40000000L 29593 29594 29595 // addressBlock: mmhub_utcl2_l2tlbpldec 29596 //L2TLB_PERFCOUNTER0_CFG 29597 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 29598 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 29599 #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 29600 #define L2TLB_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 29601 #define L2TLB_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 29602 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 29603 #define L2TLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 29604 #define L2TLB_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 29605 #define L2TLB_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 29606 #define L2TLB_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 29607 //L2TLB_PERFCOUNTER1_CFG 29608 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 29609 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 29610 #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 29611 #define L2TLB_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 29612 #define L2TLB_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 29613 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 29614 #define L2TLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 29615 #define L2TLB_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 29616 #define L2TLB_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 29617 #define L2TLB_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 29618 //L2TLB_PERFCOUNTER2_CFG 29619 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 29620 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 29621 #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 29622 #define L2TLB_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 29623 #define L2TLB_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 29624 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 29625 #define L2TLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 29626 #define L2TLB_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 29627 #define L2TLB_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 29628 #define L2TLB_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 29629 //L2TLB_PERFCOUNTER3_CFG 29630 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 29631 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 29632 #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 29633 #define L2TLB_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 29634 #define L2TLB_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 29635 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 29636 #define L2TLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 29637 #define L2TLB_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 29638 #define L2TLB_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 29639 #define L2TLB_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 29640 //L2TLB_PERFCOUNTER_RSLT_CNTL 29641 #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 29642 #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 29643 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 29644 #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 29645 #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 29646 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 29647 #define L2TLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 29648 #define L2TLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 29649 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 29650 #define L2TLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 29651 #define L2TLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 29652 #define L2TLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 29653 29654 29655 // addressBlock: mmhub_utcl2_l2tlbprdec 29656 //L2TLB_PERFCOUNTER_LO 29657 #define L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 29658 #define L2TLB_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 29659 //L2TLB_PERFCOUNTER_HI 29660 #define L2TLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 29661 #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 29662 #define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 29663 #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 29664 29665 29666 // addressBlock: mmhub_utcl2_vml2pfdec 29667 //VM_L2_CNTL 29668 #define VM_L2_CNTL__ENABLE_L2_CACHE__SHIFT 0x0 29669 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING__SHIFT 0x1 29670 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE__SHIFT 0x2 29671 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE__SHIFT 0x4 29672 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE__SHIFT 0x8 29673 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0x9 29674 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE__SHIFT 0xa 29675 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY__SHIFT 0xb 29676 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE__SHIFT 0xc 29677 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE__SHIFT 0xf 29678 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION__SHIFT 0x12 29679 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE__SHIFT 0x13 29680 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE__SHIFT 0x15 29681 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE__SHIFT 0x1a 29682 #define VM_L2_CNTL__ENABLE_L2_CACHE_MASK 0x00000001L 29683 #define VM_L2_CNTL__ENABLE_L2_FRAGMENT_PROCESSING_MASK 0x00000002L 29684 #define VM_L2_CNTL__L2_CACHE_PTE_ENDIAN_SWAP_MODE_MASK 0x0000000CL 29685 #define VM_L2_CNTL__L2_CACHE_PDE_ENDIAN_SWAP_MODE_MASK 0x00000030L 29686 #define VM_L2_CNTL__L2_PDE0_CACHE_TAG_GENERATION_MODE_MASK 0x00000100L 29687 #define VM_L2_CNTL__ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000200L 29688 #define VM_L2_CNTL__ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE_MASK 0x00000400L 29689 #define VM_L2_CNTL__ENABLE_DEFAULT_PAGE_OUT_TO_SYSTEM_MEMORY_MASK 0x00000800L 29690 #define VM_L2_CNTL__L2_PDE0_CACHE_SPLIT_MODE_MASK 0x00007000L 29691 #define VM_L2_CNTL__EFFECTIVE_L2_QUEUE_SIZE_MASK 0x00038000L 29692 #define VM_L2_CNTL__PDE_FAULT_CLASSIFICATION_MASK 0x00040000L 29693 #define VM_L2_CNTL__CONTEXT1_IDENTITY_ACCESS_MODE_MASK 0x00180000L 29694 #define VM_L2_CNTL__IDENTITY_MODE_FRAGMENT_SIZE_MASK 0x03E00000L 29695 #define VM_L2_CNTL__L2_PTE_CACHE_ADDR_MODE_MASK 0x0C000000L 29696 //VM_L2_CNTL2 29697 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS__SHIFT 0x0 29698 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE__SHIFT 0x1 29699 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN__SHIFT 0x15 29700 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION__SHIFT 0x16 29701 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE__SHIFT 0x17 29702 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE__SHIFT 0x1a 29703 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE__SHIFT 0x1c 29704 #define VM_L2_CNTL2__INVALIDATE_ALL_L1_TLBS_MASK 0x00000001L 29705 #define VM_L2_CNTL2__INVALIDATE_L2_CACHE_MASK 0x00000002L 29706 #define VM_L2_CNTL2__DISABLE_INVALIDATE_PER_DOMAIN_MASK 0x00200000L 29707 #define VM_L2_CNTL2__DISABLE_BIGK_CACHE_OPTIMIZATION_MASK 0x00400000L 29708 #define VM_L2_CNTL2__L2_PTE_CACHE_VMID_MODE_MASK 0x03800000L 29709 #define VM_L2_CNTL2__INVALIDATE_CACHE_MODE_MASK 0x0C000000L 29710 #define VM_L2_CNTL2__PDE_CACHE_EFFECTIVE_SIZE_MASK 0x70000000L 29711 //VM_L2_CNTL3 29712 #define VM_L2_CNTL3__BANK_SELECT__SHIFT 0x0 29713 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE__SHIFT 0x6 29714 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE__SHIFT 0x8 29715 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE__SHIFT 0xf 29716 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY__SHIFT 0x14 29717 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE__SHIFT 0x15 29718 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE__SHIFT 0x18 29719 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS__SHIFT 0x1c 29720 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS__SHIFT 0x1d 29721 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS__SHIFT 0x1e 29722 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY__SHIFT 0x1f 29723 #define VM_L2_CNTL3__BANK_SELECT_MASK 0x0000003FL 29724 #define VM_L2_CNTL3__L2_CACHE_UPDATE_MODE_MASK 0x000000C0L 29725 #define VM_L2_CNTL3__L2_CACHE_UPDATE_WILDCARD_REFERENCE_VALUE_MASK 0x00001F00L 29726 #define VM_L2_CNTL3__L2_CACHE_BIGK_FRAGMENT_SIZE_MASK 0x000F8000L 29727 #define VM_L2_CNTL3__L2_CACHE_BIGK_ASSOCIATIVITY_MASK 0x00100000L 29728 #define VM_L2_CNTL3__L2_CACHE_4K_EFFECTIVE_SIZE_MASK 0x00E00000L 29729 #define VM_L2_CNTL3__L2_CACHE_BIGK_EFFECTIVE_SIZE_MASK 0x0F000000L 29730 #define VM_L2_CNTL3__L2_CACHE_4K_FORCE_MISS_MASK 0x10000000L 29731 #define VM_L2_CNTL3__L2_CACHE_BIGK_FORCE_MISS_MASK 0x20000000L 29732 #define VM_L2_CNTL3__PDE_CACHE_FORCE_MISS_MASK 0x40000000L 29733 #define VM_L2_CNTL3__L2_CACHE_4K_ASSOCIATIVITY_MASK 0x80000000L 29734 //VM_L2_STATUS 29735 #define VM_L2_STATUS__L2_BUSY__SHIFT 0x0 29736 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY__SHIFT 0x1 29737 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS__SHIFT 0x11 29738 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS__SHIFT 0x12 29739 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS__SHIFT 0x13 29740 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS__SHIFT 0x14 29741 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS__SHIFT 0x15 29742 #define VM_L2_STATUS__L2_BUSY_MASK 0x00000001L 29743 #define VM_L2_STATUS__CONTEXT_DOMAIN_BUSY_MASK 0x0001FFFEL 29744 #define VM_L2_STATUS__FOUND_4K_PTE_CACHE_PARITY_ERRORS_MASK 0x00020000L 29745 #define VM_L2_STATUS__FOUND_BIGK_PTE_CACHE_PARITY_ERRORS_MASK 0x00040000L 29746 #define VM_L2_STATUS__FOUND_PDE0_CACHE_PARITY_ERRORS_MASK 0x00080000L 29747 #define VM_L2_STATUS__FOUND_PDE1_CACHE_PARITY_ERRORS_MASK 0x00100000L 29748 #define VM_L2_STATUS__FOUND_PDE2_CACHE_PARITY_ERRORS_MASK 0x00200000L 29749 //VM_DUMMY_PAGE_FAULT_CNTL 29750 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE__SHIFT 0x0 29751 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL__SHIFT 0x1 29752 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS__SHIFT 0x2 29753 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_FAULT_ENABLE_MASK 0x00000001L 29754 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_ADDRESS_LOGICAL_MASK 0x00000002L 29755 #define VM_DUMMY_PAGE_FAULT_CNTL__DUMMY_PAGE_COMPARE_MSBS_MASK 0x000000FCL 29756 //VM_DUMMY_PAGE_FAULT_ADDR_LO32 29757 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32__SHIFT 0x0 29758 #define VM_DUMMY_PAGE_FAULT_ADDR_LO32__DUMMY_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 29759 //VM_DUMMY_PAGE_FAULT_ADDR_HI32 29760 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4__SHIFT 0x0 29761 #define VM_DUMMY_PAGE_FAULT_ADDR_HI32__DUMMY_PAGE_ADDR_HI4_MASK 0x0000000FL 29762 //VM_L2_PROTECTION_FAULT_CNTL 29763 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x0 29764 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES__SHIFT 0x1 29765 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x2 29766 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x3 29767 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x4 29768 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x5 29769 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x6 29770 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x7 29771 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x8 29772 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x9 29773 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 29774 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xb 29775 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 29776 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0xd 29777 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x1d 29778 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT__SHIFT 0x1e 29779 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT__SHIFT 0x1f 29780 #define VM_L2_PROTECTION_FAULT_CNTL__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00000001L 29781 #define VM_L2_PROTECTION_FAULT_CNTL__ALLOW_SUBSEQUENT_PROTECTION_FAULT_STATUS_ADDR_UPDATES_MASK 0x00000002L 29782 #define VM_L2_PROTECTION_FAULT_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000004L 29783 #define VM_L2_PROTECTION_FAULT_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000008L 29784 #define VM_L2_PROTECTION_FAULT_CNTL__PDE1_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000010L 29785 #define VM_L2_PROTECTION_FAULT_CNTL__PDE2_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000020L 29786 #define VM_L2_PROTECTION_FAULT_CNTL__TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000040L 29787 #define VM_L2_PROTECTION_FAULT_CNTL__NACK_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000080L 29788 #define VM_L2_PROTECTION_FAULT_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000100L 29789 #define VM_L2_PROTECTION_FAULT_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000200L 29790 #define VM_L2_PROTECTION_FAULT_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 29791 #define VM_L2_PROTECTION_FAULT_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000800L 29792 #define VM_L2_PROTECTION_FAULT_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 29793 #define VM_L2_PROTECTION_FAULT_CNTL__CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x1FFFE000L 29794 #define VM_L2_PROTECTION_FAULT_CNTL__OTHER_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0x20000000L 29795 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_NO_RETRY_FAULT_MASK 0x40000000L 29796 #define VM_L2_PROTECTION_FAULT_CNTL__CRASH_ON_RETRY_FAULT_MASK 0x80000000L 29797 //VM_L2_PROTECTION_FAULT_CNTL2 29798 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x0 29799 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT__SHIFT 0x10 29800 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE__SHIFT 0x11 29801 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY__SHIFT 0x12 29802 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT__SHIFT 0x13 29803 #define VM_L2_PROTECTION_FAULT_CNTL2__CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x0000FFFFL 29804 #define VM_L2_PROTECTION_FAULT_CNTL2__OTHER_CLIENT_ID_PRT_FAULT_INTERRUPT_MASK 0x00010000L 29805 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_MASK 0x00020000L 29806 #define VM_L2_PROTECTION_FAULT_CNTL2__ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY_MASK 0x00040000L 29807 #define VM_L2_PROTECTION_FAULT_CNTL2__ENABLE_RETRY_FAULT_INTERRUPT_MASK 0x00080000L 29808 //VM_L2_PROTECTION_FAULT_MM_CNTL3 29809 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 29810 #define VM_L2_PROTECTION_FAULT_MM_CNTL3__VML1_READ_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 29811 //VM_L2_PROTECTION_FAULT_MM_CNTL4 29812 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT__SHIFT 0x0 29813 #define VM_L2_PROTECTION_FAULT_MM_CNTL4__VML1_WRITE_CLIENT_ID_NO_RETRY_FAULT_INTERRUPT_MASK 0xFFFFFFFFL 29814 //VM_L2_PROTECTION_FAULT_STATUS 29815 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS__SHIFT 0x0 29816 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR__SHIFT 0x1 29817 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS__SHIFT 0x4 29818 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR__SHIFT 0x8 29819 #define VM_L2_PROTECTION_FAULT_STATUS__CID__SHIFT 0x9 29820 #define VM_L2_PROTECTION_FAULT_STATUS__RW__SHIFT 0x12 29821 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC__SHIFT 0x13 29822 #define VM_L2_PROTECTION_FAULT_STATUS__VMID__SHIFT 0x14 29823 #define VM_L2_PROTECTION_FAULT_STATUS__VF__SHIFT 0x18 29824 #define VM_L2_PROTECTION_FAULT_STATUS__VFID__SHIFT 0x19 29825 #define VM_L2_PROTECTION_FAULT_STATUS__UCE__SHIFT 0x1d 29826 #define VM_L2_PROTECTION_FAULT_STATUS__FED__SHIFT 0x1e 29827 #define VM_L2_PROTECTION_FAULT_STATUS__MORE_FAULTS_MASK 0x00000001L 29828 #define VM_L2_PROTECTION_FAULT_STATUS__WALKER_ERROR_MASK 0x0000000EL 29829 #define VM_L2_PROTECTION_FAULT_STATUS__PERMISSION_FAULTS_MASK 0x000000F0L 29830 #define VM_L2_PROTECTION_FAULT_STATUS__MAPPING_ERROR_MASK 0x00000100L 29831 #define VM_L2_PROTECTION_FAULT_STATUS__CID_MASK 0x0003FE00L 29832 #define VM_L2_PROTECTION_FAULT_STATUS__RW_MASK 0x00040000L 29833 #define VM_L2_PROTECTION_FAULT_STATUS__ATOMIC_MASK 0x00080000L 29834 #define VM_L2_PROTECTION_FAULT_STATUS__VMID_MASK 0x00F00000L 29835 #define VM_L2_PROTECTION_FAULT_STATUS__VF_MASK 0x01000000L 29836 #define VM_L2_PROTECTION_FAULT_STATUS__VFID_MASK 0x1E000000L 29837 #define VM_L2_PROTECTION_FAULT_STATUS__UCE_MASK 0x20000000L 29838 #define VM_L2_PROTECTION_FAULT_STATUS__FED_MASK 0x40000000L 29839 //VM_L2_PROTECTION_FAULT_ADDR_LO32 29840 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32__SHIFT 0x0 29841 #define VM_L2_PROTECTION_FAULT_ADDR_LO32__LOGICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 29842 //VM_L2_PROTECTION_FAULT_ADDR_HI32 29843 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4__SHIFT 0x0 29844 #define VM_L2_PROTECTION_FAULT_ADDR_HI32__LOGICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 29845 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32 29846 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32__SHIFT 0x0 29847 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32__PHYSICAL_PAGE_ADDR_LO32_MASK 0xFFFFFFFFL 29848 //VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32 29849 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4__SHIFT 0x0 29850 #define VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32__PHYSICAL_PAGE_ADDR_HI4_MASK 0x0000000FL 29851 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32 29852 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 29853 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 29854 //VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32 29855 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 29856 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 29857 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32 29858 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 29859 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 29860 //VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32 29861 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 29862 #define VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 29863 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32 29864 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32__SHIFT 0x0 29865 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32__PHYSICAL_PAGE_OFFSET_LO32_MASK 0xFFFFFFFFL 29866 //VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32 29867 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4__SHIFT 0x0 29868 #define VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32__PHYSICAL_PAGE_OFFSET_HI4_MASK 0x0000000FL 29869 //VM_L2_CNTL4 29870 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT__SHIFT 0x0 29871 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL__SHIFT 0x6 29872 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL__SHIFT 0x7 29873 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x8 29874 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT__SHIFT 0x12 29875 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE__SHIFT 0x1c 29876 #define VM_L2_CNTL4__GC_CH_FGCG_OFF__SHIFT 0x1d 29877 #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE__SHIFT 0x1e 29878 #define VM_L2_CNTL4__L2_CACHE_4K_PARTITION_COUNT_MASK 0x0000003FL 29879 #define VM_L2_CNTL4__VMC_TAP_PDE_REQUEST_PHYSICAL_MASK 0x00000040L 29880 #define VM_L2_CNTL4__VMC_TAP_PTE_REQUEST_PHYSICAL_MASK 0x00000080L 29881 #define VM_L2_CNTL4__MM_NONRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0003FF00L 29882 #define VM_L2_CNTL4__MM_SOFTRT_IFIFO_ACTIVE_TRANSACTION_LIMIT_MASK 0x0FFC0000L 29883 #define VM_L2_CNTL4__BPM_CGCGLS_OVERRIDE_MASK 0x10000000L 29884 #define VM_L2_CNTL4__GC_CH_FGCG_OFF_MASK 0x20000000L 29885 #define VM_L2_CNTL4__VFIFO_HEAD_OF_QUEUE_MASK 0x40000000L 29886 //VM_L2_MM_GROUP_RT_CLASSES 29887 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS__SHIFT 0x0 29888 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS__SHIFT 0x1 29889 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS__SHIFT 0x2 29890 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS__SHIFT 0x3 29891 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS__SHIFT 0x4 29892 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS__SHIFT 0x5 29893 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS__SHIFT 0x6 29894 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS__SHIFT 0x7 29895 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS__SHIFT 0x8 29896 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS__SHIFT 0x9 29897 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS__SHIFT 0xa 29898 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS__SHIFT 0xb 29899 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS__SHIFT 0xc 29900 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS__SHIFT 0xd 29901 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS__SHIFT 0xe 29902 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS__SHIFT 0xf 29903 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS__SHIFT 0x10 29904 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS__SHIFT 0x11 29905 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS__SHIFT 0x12 29906 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS__SHIFT 0x13 29907 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS__SHIFT 0x14 29908 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS__SHIFT 0x15 29909 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS__SHIFT 0x16 29910 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS__SHIFT 0x17 29911 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS__SHIFT 0x18 29912 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS__SHIFT 0x19 29913 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS__SHIFT 0x1a 29914 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS__SHIFT 0x1b 29915 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS__SHIFT 0x1c 29916 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS__SHIFT 0x1d 29917 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS__SHIFT 0x1e 29918 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS__SHIFT 0x1f 29919 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_0_RT_CLASS_MASK 0x00000001L 29920 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_1_RT_CLASS_MASK 0x00000002L 29921 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_2_RT_CLASS_MASK 0x00000004L 29922 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_3_RT_CLASS_MASK 0x00000008L 29923 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_4_RT_CLASS_MASK 0x00000010L 29924 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_5_RT_CLASS_MASK 0x00000020L 29925 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_6_RT_CLASS_MASK 0x00000040L 29926 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_7_RT_CLASS_MASK 0x00000080L 29927 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_8_RT_CLASS_MASK 0x00000100L 29928 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_9_RT_CLASS_MASK 0x00000200L 29929 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_10_RT_CLASS_MASK 0x00000400L 29930 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_11_RT_CLASS_MASK 0x00000800L 29931 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_12_RT_CLASS_MASK 0x00001000L 29932 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_13_RT_CLASS_MASK 0x00002000L 29933 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_14_RT_CLASS_MASK 0x00004000L 29934 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_15_RT_CLASS_MASK 0x00008000L 29935 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_16_RT_CLASS_MASK 0x00010000L 29936 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_17_RT_CLASS_MASK 0x00020000L 29937 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_18_RT_CLASS_MASK 0x00040000L 29938 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_19_RT_CLASS_MASK 0x00080000L 29939 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_20_RT_CLASS_MASK 0x00100000L 29940 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_21_RT_CLASS_MASK 0x00200000L 29941 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_22_RT_CLASS_MASK 0x00400000L 29942 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_23_RT_CLASS_MASK 0x00800000L 29943 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_24_RT_CLASS_MASK 0x01000000L 29944 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_25_RT_CLASS_MASK 0x02000000L 29945 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_26_RT_CLASS_MASK 0x04000000L 29946 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_27_RT_CLASS_MASK 0x08000000L 29947 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_28_RT_CLASS_MASK 0x10000000L 29948 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_29_RT_CLASS_MASK 0x20000000L 29949 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_30_RT_CLASS_MASK 0x40000000L 29950 #define VM_L2_MM_GROUP_RT_CLASSES__GROUP_31_RT_CLASS_MASK 0x80000000L 29951 //VM_L2_BANK_SELECT_RESERVED_CID 29952 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID__SHIFT 0x0 29953 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 29954 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE__SHIFT 0x14 29955 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 29956 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 29957 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 29958 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 29959 #define VM_L2_BANK_SELECT_RESERVED_CID__ENABLE_MASK 0x00100000L 29960 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 29961 #define VM_L2_BANK_SELECT_RESERVED_CID__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 29962 //VM_L2_BANK_SELECT_RESERVED_CID2 29963 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID__SHIFT 0x0 29964 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID__SHIFT 0xa 29965 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE__SHIFT 0x14 29966 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE__SHIFT 0x18 29967 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION__SHIFT 0x19 29968 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_READ_CLIENT_ID_MASK 0x000001FFL 29969 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_WRITE_CLIENT_ID_MASK 0x0007FC00L 29970 #define VM_L2_BANK_SELECT_RESERVED_CID2__ENABLE_MASK 0x00100000L 29971 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_INVALIDATION_MODE_MASK 0x01000000L 29972 #define VM_L2_BANK_SELECT_RESERVED_CID2__RESERVED_CACHE_PRIVATE_INVALIDATION_MASK 0x02000000L 29973 //VM_L2_CACHE_PARITY_CNTL 29974 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES__SHIFT 0x0 29975 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES__SHIFT 0x1 29976 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES__SHIFT 0x2 29977 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE__SHIFT 0x3 29978 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE__SHIFT 0x4 29979 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE__SHIFT 0x5 29980 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK__SHIFT 0x6 29981 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER__SHIFT 0x9 29982 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC__SHIFT 0xc 29983 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_4K_PTE_CACHES_MASK 0x00000001L 29984 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_BIGK_PTE_CACHES_MASK 0x00000002L 29985 #define VM_L2_CACHE_PARITY_CNTL__ENABLE_PARITY_CHECKS_IN_PDE_CACHES_MASK 0x00000004L 29986 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_4K_PTE_CACHE_MASK 0x00000008L 29987 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_BIGK_PTE_CACHE_MASK 0x00000010L 29988 #define VM_L2_CACHE_PARITY_CNTL__FORCE_PARITY_MISMATCH_IN_PDE_CACHE_MASK 0x00000020L 29989 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_BANK_MASK 0x000001C0L 29990 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_NUMBER_MASK 0x00000E00L 29991 #define VM_L2_CACHE_PARITY_CNTL__FORCE_CACHE_ASSOC_MASK 0x0000F000L 29992 //VM_L2_CGTT_CLK_CTRL 29993 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 29994 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 29995 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 29996 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 29997 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 29998 #define VM_L2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 29999 #define VM_L2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 30000 #define VM_L2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 30001 #define VM_L2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 30002 #define VM_L2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 30003 //VM_L2_CGTT_BUSY_CTRL 30004 #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY__SHIFT 0x0 30005 #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY__SHIFT 0x4 30006 #define VM_L2_CGTT_BUSY_CTRL__READ_DELAY_MASK 0x0000000FL 30007 #define VM_L2_CGTT_BUSY_CTRL__ALWAYS_BUSY_MASK 0x00000010L 30008 //VML2_MEM_ECC_INDEX 30009 #define VML2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 30010 #define VML2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 30011 //VML2_WALKER_MEM_ECC_INDEX 30012 #define VML2_WALKER_MEM_ECC_INDEX__INDEX__SHIFT 0x0 30013 #define VML2_WALKER_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 30014 //UTCL2_MEM_ECC_INDEX 30015 #define UTCL2_MEM_ECC_INDEX__INDEX__SHIFT 0x0 30016 #define UTCL2_MEM_ECC_INDEX__INDEX_MASK 0x000000FFL 30017 //VML2_MEM_ECC_CNTL 30018 #define VML2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 30019 #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 30020 #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 30021 #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 30022 #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 30023 #define VML2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 30024 #define VML2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 30025 #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 30026 #define VML2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 30027 #define VML2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL 30028 #define VML2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 30029 #define VML2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 30030 #define VML2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 30031 #define VML2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 30032 #define VML2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 30033 #define VML2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 30034 #define VML2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L 30035 #define VML2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L 30036 //VML2_WALKER_MEM_ECC_CNTL 30037 #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 30038 #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 30039 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 30040 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 30041 #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 30042 #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 30043 #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 30044 #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 30045 #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 30046 #define VML2_WALKER_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL 30047 #define VML2_WALKER_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 30048 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 30049 #define VML2_WALKER_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 30050 #define VML2_WALKER_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 30051 #define VML2_WALKER_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 30052 #define VML2_WALKER_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 30053 #define VML2_WALKER_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L 30054 #define VML2_WALKER_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L 30055 //UTCL2_MEM_ECC_CNTL 30056 #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY__SHIFT 0x0 30057 #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA__SHIFT 0x6 30058 #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE__SHIFT 0x8 30059 #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT__SHIFT 0x9 30060 #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY__SHIFT 0xb 30061 #define UTCL2_MEM_ECC_CNTL__SEC_COUNT__SHIFT 0xc 30062 #define UTCL2_MEM_ECC_CNTL__DED_COUNT__SHIFT 0xe 30063 #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS__SHIFT 0x10 30064 #define UTCL2_MEM_ECC_CNTL__TEST_FUE__SHIFT 0x11 30065 #define UTCL2_MEM_ECC_CNTL__INJECT_DELAY_MASK 0x0000003FL 30066 #define UTCL2_MEM_ECC_CNTL__DSM_IRRITATOR_DATA_MASK 0x000000C0L 30067 #define UTCL2_MEM_ECC_CNTL__ENABLE_SINGLE_WRITE_MASK 0x00000100L 30068 #define UTCL2_MEM_ECC_CNTL__ENABLE_ERROR_INJECT_MASK 0x00000600L 30069 #define UTCL2_MEM_ECC_CNTL__SELECT_INJECT_DELAY_MASK 0x00000800L 30070 #define UTCL2_MEM_ECC_CNTL__SEC_COUNT_MASK 0x00003000L 30071 #define UTCL2_MEM_ECC_CNTL__DED_COUNT_MASK 0x0000C000L 30072 #define UTCL2_MEM_ECC_CNTL__WRITE_COUNTERS_MASK 0x00010000L 30073 #define UTCL2_MEM_ECC_CNTL__TEST_FUE_MASK 0x00020000L 30074 //VML2_MEM_ECC_STATUS 30075 #define VML2_MEM_ECC_STATUS__UCE__SHIFT 0x0 30076 #define VML2_MEM_ECC_STATUS__FED__SHIFT 0x1 30077 #define VML2_MEM_ECC_STATUS__UCE_MASK 0x00000001L 30078 #define VML2_MEM_ECC_STATUS__FED_MASK 0x00000002L 30079 //VML2_WALKER_MEM_ECC_STATUS 30080 #define VML2_WALKER_MEM_ECC_STATUS__UCE__SHIFT 0x0 30081 #define VML2_WALKER_MEM_ECC_STATUS__FED__SHIFT 0x1 30082 #define VML2_WALKER_MEM_ECC_STATUS__UCE_MASK 0x00000001L 30083 #define VML2_WALKER_MEM_ECC_STATUS__FED_MASK 0x00000002L 30084 //UTCL2_MEM_ECC_STATUS 30085 #define UTCL2_MEM_ECC_STATUS__UCE__SHIFT 0x0 30086 #define UTCL2_MEM_ECC_STATUS__FED__SHIFT 0x1 30087 #define UTCL2_MEM_ECC_STATUS__UCE_MASK 0x00000001L 30088 #define UTCL2_MEM_ECC_STATUS__FED_MASK 0x00000002L 30089 //UTCL2_EDC_MODE 30090 #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED__SHIFT 0xf 30091 #define UTCL2_EDC_MODE__COUNT_FED_OUT__SHIFT 0x10 30092 #define UTCL2_EDC_MODE__GATE_FUE__SHIFT 0x11 30093 #define UTCL2_EDC_MODE__DED_MODE__SHIFT 0x14 30094 #define UTCL2_EDC_MODE__PROP_FED__SHIFT 0x1d 30095 #define UTCL2_EDC_MODE__BYPASS__SHIFT 0x1f 30096 #define UTCL2_EDC_MODE__FORCE_SEC_ON_DED_MASK 0x00008000L 30097 #define UTCL2_EDC_MODE__COUNT_FED_OUT_MASK 0x00010000L 30098 #define UTCL2_EDC_MODE__GATE_FUE_MASK 0x00020000L 30099 #define UTCL2_EDC_MODE__DED_MODE_MASK 0x00300000L 30100 #define UTCL2_EDC_MODE__PROP_FED_MASK 0x20000000L 30101 #define UTCL2_EDC_MODE__BYPASS_MASK 0x80000000L 30102 //UTCL2_EDC_CONFIG 30103 #define UTCL2_EDC_CONFIG__DIS_EDC__SHIFT 0x1 30104 #define UTCL2_EDC_CONFIG__DIS_EDC_MASK 0x00000002L 30105 30106 30107 // addressBlock: mmhub_utcl2_vml2pldec 30108 //MC_VM_L2_PERFCOUNTER0_CFG 30109 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL__SHIFT 0x0 30110 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT 0x8 30111 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE__SHIFT 0x18 30112 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE__SHIFT 0x1c 30113 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR__SHIFT 0x1d 30114 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_MASK 0x000000FFL 30115 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_SEL_END_MASK 0x0000FF00L 30116 #define MC_VM_L2_PERFCOUNTER0_CFG__PERF_MODE_MASK 0x0F000000L 30117 #define MC_VM_L2_PERFCOUNTER0_CFG__ENABLE_MASK 0x10000000L 30118 #define MC_VM_L2_PERFCOUNTER0_CFG__CLEAR_MASK 0x20000000L 30119 //MC_VM_L2_PERFCOUNTER1_CFG 30120 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL__SHIFT 0x0 30121 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT 0x8 30122 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE__SHIFT 0x18 30123 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE__SHIFT 0x1c 30124 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR__SHIFT 0x1d 30125 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_MASK 0x000000FFL 30126 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_SEL_END_MASK 0x0000FF00L 30127 #define MC_VM_L2_PERFCOUNTER1_CFG__PERF_MODE_MASK 0x0F000000L 30128 #define MC_VM_L2_PERFCOUNTER1_CFG__ENABLE_MASK 0x10000000L 30129 #define MC_VM_L2_PERFCOUNTER1_CFG__CLEAR_MASK 0x20000000L 30130 //MC_VM_L2_PERFCOUNTER2_CFG 30131 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL__SHIFT 0x0 30132 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT 0x8 30133 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE__SHIFT 0x18 30134 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE__SHIFT 0x1c 30135 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR__SHIFT 0x1d 30136 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_MASK 0x000000FFL 30137 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_SEL_END_MASK 0x0000FF00L 30138 #define MC_VM_L2_PERFCOUNTER2_CFG__PERF_MODE_MASK 0x0F000000L 30139 #define MC_VM_L2_PERFCOUNTER2_CFG__ENABLE_MASK 0x10000000L 30140 #define MC_VM_L2_PERFCOUNTER2_CFG__CLEAR_MASK 0x20000000L 30141 //MC_VM_L2_PERFCOUNTER3_CFG 30142 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL__SHIFT 0x0 30143 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT 0x8 30144 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE__SHIFT 0x18 30145 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE__SHIFT 0x1c 30146 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR__SHIFT 0x1d 30147 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_MASK 0x000000FFL 30148 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_SEL_END_MASK 0x0000FF00L 30149 #define MC_VM_L2_PERFCOUNTER3_CFG__PERF_MODE_MASK 0x0F000000L 30150 #define MC_VM_L2_PERFCOUNTER3_CFG__ENABLE_MASK 0x10000000L 30151 #define MC_VM_L2_PERFCOUNTER3_CFG__CLEAR_MASK 0x20000000L 30152 //MC_VM_L2_PERFCOUNTER4_CFG 30153 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL__SHIFT 0x0 30154 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT 0x8 30155 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE__SHIFT 0x18 30156 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE__SHIFT 0x1c 30157 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR__SHIFT 0x1d 30158 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_MASK 0x000000FFL 30159 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_SEL_END_MASK 0x0000FF00L 30160 #define MC_VM_L2_PERFCOUNTER4_CFG__PERF_MODE_MASK 0x0F000000L 30161 #define MC_VM_L2_PERFCOUNTER4_CFG__ENABLE_MASK 0x10000000L 30162 #define MC_VM_L2_PERFCOUNTER4_CFG__CLEAR_MASK 0x20000000L 30163 //MC_VM_L2_PERFCOUNTER5_CFG 30164 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL__SHIFT 0x0 30165 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT 0x8 30166 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE__SHIFT 0x18 30167 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE__SHIFT 0x1c 30168 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR__SHIFT 0x1d 30169 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_MASK 0x000000FFL 30170 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_SEL_END_MASK 0x0000FF00L 30171 #define MC_VM_L2_PERFCOUNTER5_CFG__PERF_MODE_MASK 0x0F000000L 30172 #define MC_VM_L2_PERFCOUNTER5_CFG__ENABLE_MASK 0x10000000L 30173 #define MC_VM_L2_PERFCOUNTER5_CFG__CLEAR_MASK 0x20000000L 30174 //MC_VM_L2_PERFCOUNTER6_CFG 30175 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL__SHIFT 0x0 30176 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT 0x8 30177 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE__SHIFT 0x18 30178 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE__SHIFT 0x1c 30179 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR__SHIFT 0x1d 30180 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_MASK 0x000000FFL 30181 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_SEL_END_MASK 0x0000FF00L 30182 #define MC_VM_L2_PERFCOUNTER6_CFG__PERF_MODE_MASK 0x0F000000L 30183 #define MC_VM_L2_PERFCOUNTER6_CFG__ENABLE_MASK 0x10000000L 30184 #define MC_VM_L2_PERFCOUNTER6_CFG__CLEAR_MASK 0x20000000L 30185 //MC_VM_L2_PERFCOUNTER7_CFG 30186 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL__SHIFT 0x0 30187 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT 0x8 30188 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE__SHIFT 0x18 30189 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE__SHIFT 0x1c 30190 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR__SHIFT 0x1d 30191 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_MASK 0x000000FFL 30192 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_SEL_END_MASK 0x0000FF00L 30193 #define MC_VM_L2_PERFCOUNTER7_CFG__PERF_MODE_MASK 0x0F000000L 30194 #define MC_VM_L2_PERFCOUNTER7_CFG__ENABLE_MASK 0x10000000L 30195 #define MC_VM_L2_PERFCOUNTER7_CFG__CLEAR_MASK 0x20000000L 30196 //MC_VM_L2_PERFCOUNTER_RSLT_CNTL 30197 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT 0x0 30198 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT 0x8 30199 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT 0x10 30200 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT 0x18 30201 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT 0x19 30202 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT 0x1a 30203 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK 0x0000000FL 30204 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK 0x0000FF00L 30205 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK 0x00FF0000L 30206 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L 30207 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L 30208 #define MC_VM_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L 30209 30210 30211 // addressBlock: mmhub_utcl2_vml2prdec 30212 //MC_VM_L2_PERFCOUNTER_LO 30213 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO__SHIFT 0x0 30214 #define MC_VM_L2_PERFCOUNTER_LO__COUNTER_LO_MASK 0xFFFFFFFFL 30215 //MC_VM_L2_PERFCOUNTER_HI 30216 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI__SHIFT 0x0 30217 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT 0x10 30218 #define MC_VM_L2_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL 30219 #define MC_VM_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L 30220 30221 30222 // addressBlock: mmhub_utcl2_vml2vcdec 30223 //VM_CONTEXT0_CNTL 30224 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30225 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30226 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30227 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30228 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30229 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30230 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30231 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30232 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30233 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30234 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30235 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30236 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30237 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30238 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30239 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30240 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30241 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30242 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30243 #define VM_CONTEXT0_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30244 #define VM_CONTEXT0_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30245 #define VM_CONTEXT0_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30246 #define VM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30247 #define VM_CONTEXT0_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30248 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30249 #define VM_CONTEXT0_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30250 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30251 #define VM_CONTEXT0_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30252 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30253 #define VM_CONTEXT0_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30254 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30255 #define VM_CONTEXT0_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30256 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30257 #define VM_CONTEXT0_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30258 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30259 #define VM_CONTEXT0_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30260 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30261 #define VM_CONTEXT0_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30262 //VM_CONTEXT1_CNTL 30263 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30264 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30265 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30266 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30267 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30268 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30269 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30270 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30271 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30272 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30273 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30274 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30275 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30276 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30277 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30278 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30279 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30280 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30281 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30282 #define VM_CONTEXT1_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30283 #define VM_CONTEXT1_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30284 #define VM_CONTEXT1_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30285 #define VM_CONTEXT1_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30286 #define VM_CONTEXT1_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30287 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30288 #define VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30289 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30290 #define VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30291 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30292 #define VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30293 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30294 #define VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30295 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30296 #define VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30297 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30298 #define VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30299 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30300 #define VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30301 //VM_CONTEXT2_CNTL 30302 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30303 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30304 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30305 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30306 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30307 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30308 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30309 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30310 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30311 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30312 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30313 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30314 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30315 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30316 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30317 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30318 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30319 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30320 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30321 #define VM_CONTEXT2_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30322 #define VM_CONTEXT2_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30323 #define VM_CONTEXT2_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30324 #define VM_CONTEXT2_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30325 #define VM_CONTEXT2_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30326 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30327 #define VM_CONTEXT2_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30328 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30329 #define VM_CONTEXT2_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30330 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30331 #define VM_CONTEXT2_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30332 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30333 #define VM_CONTEXT2_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30334 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30335 #define VM_CONTEXT2_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30336 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30337 #define VM_CONTEXT2_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30338 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30339 #define VM_CONTEXT2_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30340 //VM_CONTEXT3_CNTL 30341 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30342 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30343 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30344 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30345 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30346 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30347 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30348 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30349 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30350 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30351 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30352 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30353 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30354 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30355 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30356 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30357 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30358 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30359 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30360 #define VM_CONTEXT3_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30361 #define VM_CONTEXT3_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30362 #define VM_CONTEXT3_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30363 #define VM_CONTEXT3_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30364 #define VM_CONTEXT3_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30365 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30366 #define VM_CONTEXT3_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30367 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30368 #define VM_CONTEXT3_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30369 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30370 #define VM_CONTEXT3_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30371 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30372 #define VM_CONTEXT3_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30373 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30374 #define VM_CONTEXT3_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30375 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30376 #define VM_CONTEXT3_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30377 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30378 #define VM_CONTEXT3_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30379 //VM_CONTEXT4_CNTL 30380 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30381 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30382 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30383 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30384 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30385 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30386 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30387 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30388 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30389 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30390 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30391 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30392 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30393 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30394 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30395 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30396 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30397 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30398 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30399 #define VM_CONTEXT4_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30400 #define VM_CONTEXT4_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30401 #define VM_CONTEXT4_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30402 #define VM_CONTEXT4_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30403 #define VM_CONTEXT4_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30404 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30405 #define VM_CONTEXT4_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30406 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30407 #define VM_CONTEXT4_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30408 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30409 #define VM_CONTEXT4_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30410 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30411 #define VM_CONTEXT4_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30412 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30413 #define VM_CONTEXT4_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30414 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30415 #define VM_CONTEXT4_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30416 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30417 #define VM_CONTEXT4_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30418 //VM_CONTEXT5_CNTL 30419 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30420 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30421 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30422 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30423 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30424 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30425 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30426 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30427 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30428 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30429 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30430 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30431 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30432 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30433 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30434 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30435 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30436 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30437 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30438 #define VM_CONTEXT5_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30439 #define VM_CONTEXT5_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30440 #define VM_CONTEXT5_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30441 #define VM_CONTEXT5_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30442 #define VM_CONTEXT5_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30443 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30444 #define VM_CONTEXT5_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30445 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30446 #define VM_CONTEXT5_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30447 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30448 #define VM_CONTEXT5_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30449 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30450 #define VM_CONTEXT5_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30451 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30452 #define VM_CONTEXT5_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30453 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30454 #define VM_CONTEXT5_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30455 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30456 #define VM_CONTEXT5_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30457 //VM_CONTEXT6_CNTL 30458 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30459 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30460 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30461 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30462 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30463 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30464 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30465 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30466 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30467 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30468 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30469 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30470 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30471 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30472 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30473 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30474 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30475 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30476 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30477 #define VM_CONTEXT6_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30478 #define VM_CONTEXT6_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30479 #define VM_CONTEXT6_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30480 #define VM_CONTEXT6_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30481 #define VM_CONTEXT6_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30482 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30483 #define VM_CONTEXT6_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30484 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30485 #define VM_CONTEXT6_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30486 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30487 #define VM_CONTEXT6_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30488 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30489 #define VM_CONTEXT6_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30490 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30491 #define VM_CONTEXT6_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30492 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30493 #define VM_CONTEXT6_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30494 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30495 #define VM_CONTEXT6_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30496 //VM_CONTEXT7_CNTL 30497 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30498 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30499 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30500 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30501 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30502 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30503 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30504 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30505 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30506 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30507 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30508 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30509 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30510 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30511 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30512 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30513 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30514 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30515 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30516 #define VM_CONTEXT7_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30517 #define VM_CONTEXT7_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30518 #define VM_CONTEXT7_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30519 #define VM_CONTEXT7_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30520 #define VM_CONTEXT7_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30521 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30522 #define VM_CONTEXT7_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30523 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30524 #define VM_CONTEXT7_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30525 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30526 #define VM_CONTEXT7_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30527 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30528 #define VM_CONTEXT7_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30529 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30530 #define VM_CONTEXT7_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30531 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30532 #define VM_CONTEXT7_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30533 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30534 #define VM_CONTEXT7_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30535 //VM_CONTEXT8_CNTL 30536 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30537 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30538 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30539 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30540 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30541 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30542 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30543 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30544 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30545 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30546 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30547 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30548 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30549 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30550 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30551 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30552 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30553 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30554 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30555 #define VM_CONTEXT8_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30556 #define VM_CONTEXT8_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30557 #define VM_CONTEXT8_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30558 #define VM_CONTEXT8_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30559 #define VM_CONTEXT8_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30560 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30561 #define VM_CONTEXT8_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30562 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30563 #define VM_CONTEXT8_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30564 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30565 #define VM_CONTEXT8_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30566 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30567 #define VM_CONTEXT8_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30568 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30569 #define VM_CONTEXT8_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30570 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30571 #define VM_CONTEXT8_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30572 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30573 #define VM_CONTEXT8_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30574 //VM_CONTEXT9_CNTL 30575 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30576 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30577 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30578 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30579 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30580 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30581 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30582 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30583 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30584 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30585 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30586 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30587 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30588 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30589 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30590 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30591 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30592 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30593 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30594 #define VM_CONTEXT9_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30595 #define VM_CONTEXT9_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30596 #define VM_CONTEXT9_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30597 #define VM_CONTEXT9_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30598 #define VM_CONTEXT9_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30599 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30600 #define VM_CONTEXT9_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30601 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30602 #define VM_CONTEXT9_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30603 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30604 #define VM_CONTEXT9_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30605 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30606 #define VM_CONTEXT9_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30607 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30608 #define VM_CONTEXT9_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30609 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30610 #define VM_CONTEXT9_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30611 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30612 #define VM_CONTEXT9_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30613 //VM_CONTEXT10_CNTL 30614 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30615 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30616 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30617 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30618 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30619 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30620 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30621 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30622 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30623 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30624 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30625 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30626 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30627 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30628 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30629 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30630 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30631 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30632 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30633 #define VM_CONTEXT10_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30634 #define VM_CONTEXT10_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30635 #define VM_CONTEXT10_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30636 #define VM_CONTEXT10_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30637 #define VM_CONTEXT10_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30638 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30639 #define VM_CONTEXT10_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30640 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30641 #define VM_CONTEXT10_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30642 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30643 #define VM_CONTEXT10_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30644 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30645 #define VM_CONTEXT10_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30646 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30647 #define VM_CONTEXT10_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30648 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30649 #define VM_CONTEXT10_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30650 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30651 #define VM_CONTEXT10_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30652 //VM_CONTEXT11_CNTL 30653 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30654 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30655 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30656 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30657 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30658 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30659 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30660 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30661 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30662 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30663 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30664 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30665 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30666 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30667 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30668 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30669 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30670 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30671 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30672 #define VM_CONTEXT11_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30673 #define VM_CONTEXT11_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30674 #define VM_CONTEXT11_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30675 #define VM_CONTEXT11_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30676 #define VM_CONTEXT11_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30677 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30678 #define VM_CONTEXT11_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30679 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30680 #define VM_CONTEXT11_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30681 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30682 #define VM_CONTEXT11_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30683 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30684 #define VM_CONTEXT11_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30685 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30686 #define VM_CONTEXT11_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30687 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30688 #define VM_CONTEXT11_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30689 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30690 #define VM_CONTEXT11_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30691 //VM_CONTEXT12_CNTL 30692 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30693 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30694 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30695 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30696 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30697 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30698 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30699 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30700 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30701 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30702 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30703 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30704 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30705 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30706 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30707 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30708 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30709 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30710 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30711 #define VM_CONTEXT12_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30712 #define VM_CONTEXT12_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30713 #define VM_CONTEXT12_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30714 #define VM_CONTEXT12_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30715 #define VM_CONTEXT12_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30716 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30717 #define VM_CONTEXT12_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30718 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30719 #define VM_CONTEXT12_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30720 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30721 #define VM_CONTEXT12_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30722 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30723 #define VM_CONTEXT12_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30724 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30725 #define VM_CONTEXT12_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30726 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30727 #define VM_CONTEXT12_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30728 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30729 #define VM_CONTEXT12_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30730 //VM_CONTEXT13_CNTL 30731 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30732 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30733 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30734 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30735 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30736 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30737 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30738 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30739 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30740 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30741 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30742 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30743 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30744 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30745 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30746 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30747 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30748 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30749 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30750 #define VM_CONTEXT13_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30751 #define VM_CONTEXT13_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30752 #define VM_CONTEXT13_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30753 #define VM_CONTEXT13_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30754 #define VM_CONTEXT13_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30755 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30756 #define VM_CONTEXT13_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30757 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30758 #define VM_CONTEXT13_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30759 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30760 #define VM_CONTEXT13_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30761 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30762 #define VM_CONTEXT13_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30763 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30764 #define VM_CONTEXT13_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30765 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30766 #define VM_CONTEXT13_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30767 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30768 #define VM_CONTEXT13_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30769 //VM_CONTEXT14_CNTL 30770 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30771 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30772 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30773 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30774 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30775 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30776 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30777 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30778 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30779 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30780 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30781 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30782 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30783 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30784 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30785 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30786 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30787 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30788 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30789 #define VM_CONTEXT14_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30790 #define VM_CONTEXT14_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30791 #define VM_CONTEXT14_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30792 #define VM_CONTEXT14_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30793 #define VM_CONTEXT14_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30794 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30795 #define VM_CONTEXT14_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30796 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30797 #define VM_CONTEXT14_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30798 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30799 #define VM_CONTEXT14_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30800 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30801 #define VM_CONTEXT14_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30802 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30803 #define VM_CONTEXT14_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30804 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30805 #define VM_CONTEXT14_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30806 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30807 #define VM_CONTEXT14_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30808 //VM_CONTEXT15_CNTL 30809 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT__SHIFT 0x0 30810 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH__SHIFT 0x1 30811 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE__SHIFT 0x3 30812 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT 0x7 30813 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT__SHIFT 0x8 30814 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x9 30815 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xa 30816 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xb 30817 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xc 30818 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xd 30819 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0xe 30820 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0xf 30821 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x10 30822 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x11 30823 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x12 30824 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x13 30825 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x14 30826 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT__SHIFT 0x15 30827 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT__SHIFT 0x16 30828 #define VM_CONTEXT15_CNTL__ENABLE_CONTEXT_MASK 0x00000001L 30829 #define VM_CONTEXT15_CNTL__PAGE_TABLE_DEPTH_MASK 0x00000006L 30830 #define VM_CONTEXT15_CNTL__PAGE_TABLE_BLOCK_SIZE_MASK 0x00000078L 30831 #define VM_CONTEXT15_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT_MASK 0x00000080L 30832 #define VM_CONTEXT15_CNTL__RETRY_OTHER_FAULT_MASK 0x00000100L 30833 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000200L 30834 #define VM_CONTEXT15_CNTL__RANGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00000400L 30835 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00000800L 30836 #define VM_CONTEXT15_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00001000L 30837 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00002000L 30838 #define VM_CONTEXT15_CNTL__PDE0_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00004000L 30839 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00008000L 30840 #define VM_CONTEXT15_CNTL__VALID_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00010000L 30841 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00020000L 30842 #define VM_CONTEXT15_CNTL__READ_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00040000L 30843 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00080000L 30844 #define VM_CONTEXT15_CNTL__WRITE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00100000L 30845 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK 0x00200000L 30846 #define VM_CONTEXT15_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT_MASK 0x00400000L 30847 //VM_CONTEXTS_DISABLE 30848 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0__SHIFT 0x0 30849 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1__SHIFT 0x1 30850 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2__SHIFT 0x2 30851 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3__SHIFT 0x3 30852 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4__SHIFT 0x4 30853 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5__SHIFT 0x5 30854 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6__SHIFT 0x6 30855 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7__SHIFT 0x7 30856 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8__SHIFT 0x8 30857 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9__SHIFT 0x9 30858 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10__SHIFT 0xa 30859 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11__SHIFT 0xb 30860 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12__SHIFT 0xc 30861 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13__SHIFT 0xd 30862 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14__SHIFT 0xe 30863 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15__SHIFT 0xf 30864 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_0_MASK 0x00000001L 30865 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_1_MASK 0x00000002L 30866 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_2_MASK 0x00000004L 30867 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_3_MASK 0x00000008L 30868 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_4_MASK 0x00000010L 30869 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_5_MASK 0x00000020L 30870 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_6_MASK 0x00000040L 30871 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_7_MASK 0x00000080L 30872 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_8_MASK 0x00000100L 30873 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_9_MASK 0x00000200L 30874 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_10_MASK 0x00000400L 30875 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_11_MASK 0x00000800L 30876 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_12_MASK 0x00001000L 30877 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_13_MASK 0x00002000L 30878 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_14_MASK 0x00004000L 30879 #define VM_CONTEXTS_DISABLE__DISABLE_CONTEXT_15_MASK 0x00008000L 30880 //VM_INVALIDATE_ENG0_SEM 30881 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE__SHIFT 0x0 30882 #define VM_INVALIDATE_ENG0_SEM__SEMAPHORE_MASK 0x00000001L 30883 //VM_INVALIDATE_ENG1_SEM 30884 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE__SHIFT 0x0 30885 #define VM_INVALIDATE_ENG1_SEM__SEMAPHORE_MASK 0x00000001L 30886 //VM_INVALIDATE_ENG2_SEM 30887 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE__SHIFT 0x0 30888 #define VM_INVALIDATE_ENG2_SEM__SEMAPHORE_MASK 0x00000001L 30889 //VM_INVALIDATE_ENG3_SEM 30890 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE__SHIFT 0x0 30891 #define VM_INVALIDATE_ENG3_SEM__SEMAPHORE_MASK 0x00000001L 30892 //VM_INVALIDATE_ENG4_SEM 30893 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE__SHIFT 0x0 30894 #define VM_INVALIDATE_ENG4_SEM__SEMAPHORE_MASK 0x00000001L 30895 //VM_INVALIDATE_ENG5_SEM 30896 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE__SHIFT 0x0 30897 #define VM_INVALIDATE_ENG5_SEM__SEMAPHORE_MASK 0x00000001L 30898 //VM_INVALIDATE_ENG6_SEM 30899 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE__SHIFT 0x0 30900 #define VM_INVALIDATE_ENG6_SEM__SEMAPHORE_MASK 0x00000001L 30901 //VM_INVALIDATE_ENG7_SEM 30902 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE__SHIFT 0x0 30903 #define VM_INVALIDATE_ENG7_SEM__SEMAPHORE_MASK 0x00000001L 30904 //VM_INVALIDATE_ENG8_SEM 30905 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE__SHIFT 0x0 30906 #define VM_INVALIDATE_ENG8_SEM__SEMAPHORE_MASK 0x00000001L 30907 //VM_INVALIDATE_ENG9_SEM 30908 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE__SHIFT 0x0 30909 #define VM_INVALIDATE_ENG9_SEM__SEMAPHORE_MASK 0x00000001L 30910 //VM_INVALIDATE_ENG10_SEM 30911 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE__SHIFT 0x0 30912 #define VM_INVALIDATE_ENG10_SEM__SEMAPHORE_MASK 0x00000001L 30913 //VM_INVALIDATE_ENG11_SEM 30914 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE__SHIFT 0x0 30915 #define VM_INVALIDATE_ENG11_SEM__SEMAPHORE_MASK 0x00000001L 30916 //VM_INVALIDATE_ENG12_SEM 30917 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE__SHIFT 0x0 30918 #define VM_INVALIDATE_ENG12_SEM__SEMAPHORE_MASK 0x00000001L 30919 //VM_INVALIDATE_ENG13_SEM 30920 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE__SHIFT 0x0 30921 #define VM_INVALIDATE_ENG13_SEM__SEMAPHORE_MASK 0x00000001L 30922 //VM_INVALIDATE_ENG14_SEM 30923 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE__SHIFT 0x0 30924 #define VM_INVALIDATE_ENG14_SEM__SEMAPHORE_MASK 0x00000001L 30925 //VM_INVALIDATE_ENG15_SEM 30926 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE__SHIFT 0x0 30927 #define VM_INVALIDATE_ENG15_SEM__SEMAPHORE_MASK 0x00000001L 30928 //VM_INVALIDATE_ENG16_SEM 30929 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE__SHIFT 0x0 30930 #define VM_INVALIDATE_ENG16_SEM__SEMAPHORE_MASK 0x00000001L 30931 //VM_INVALIDATE_ENG17_SEM 30932 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE__SHIFT 0x0 30933 #define VM_INVALIDATE_ENG17_SEM__SEMAPHORE_MASK 0x00000001L 30934 //VM_INVALIDATE_ENG0_REQ 30935 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 30936 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE__SHIFT 0x10 30937 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 30938 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 30939 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 30940 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 30941 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 30942 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 30943 #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST__SHIFT 0x18 30944 #define VM_INVALIDATE_ENG0_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 30945 #define VM_INVALIDATE_ENG0_REQ__FLUSH_TYPE_MASK 0x00030000L 30946 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 30947 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 30948 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 30949 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 30950 #define VM_INVALIDATE_ENG0_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 30951 #define VM_INVALIDATE_ENG0_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 30952 #define VM_INVALIDATE_ENG0_REQ__LOG_REQUEST_MASK 0x01000000L 30953 //VM_INVALIDATE_ENG1_REQ 30954 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 30955 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE__SHIFT 0x10 30956 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 30957 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 30958 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 30959 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 30960 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 30961 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 30962 #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST__SHIFT 0x18 30963 #define VM_INVALIDATE_ENG1_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 30964 #define VM_INVALIDATE_ENG1_REQ__FLUSH_TYPE_MASK 0x00030000L 30965 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 30966 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 30967 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 30968 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 30969 #define VM_INVALIDATE_ENG1_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 30970 #define VM_INVALIDATE_ENG1_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 30971 #define VM_INVALIDATE_ENG1_REQ__LOG_REQUEST_MASK 0x01000000L 30972 //VM_INVALIDATE_ENG2_REQ 30973 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 30974 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE__SHIFT 0x10 30975 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 30976 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 30977 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 30978 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 30979 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 30980 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 30981 #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST__SHIFT 0x18 30982 #define VM_INVALIDATE_ENG2_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 30983 #define VM_INVALIDATE_ENG2_REQ__FLUSH_TYPE_MASK 0x00030000L 30984 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 30985 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 30986 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 30987 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 30988 #define VM_INVALIDATE_ENG2_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 30989 #define VM_INVALIDATE_ENG2_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 30990 #define VM_INVALIDATE_ENG2_REQ__LOG_REQUEST_MASK 0x01000000L 30991 //VM_INVALIDATE_ENG3_REQ 30992 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 30993 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE__SHIFT 0x10 30994 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 30995 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 30996 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 30997 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 30998 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 30999 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31000 #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST__SHIFT 0x18 31001 #define VM_INVALIDATE_ENG3_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31002 #define VM_INVALIDATE_ENG3_REQ__FLUSH_TYPE_MASK 0x00030000L 31003 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31004 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31005 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31006 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31007 #define VM_INVALIDATE_ENG3_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31008 #define VM_INVALIDATE_ENG3_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31009 #define VM_INVALIDATE_ENG3_REQ__LOG_REQUEST_MASK 0x01000000L 31010 //VM_INVALIDATE_ENG4_REQ 31011 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31012 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE__SHIFT 0x10 31013 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31014 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31015 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31016 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31017 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31018 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31019 #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST__SHIFT 0x18 31020 #define VM_INVALIDATE_ENG4_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31021 #define VM_INVALIDATE_ENG4_REQ__FLUSH_TYPE_MASK 0x00030000L 31022 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31023 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31024 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31025 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31026 #define VM_INVALIDATE_ENG4_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31027 #define VM_INVALIDATE_ENG4_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31028 #define VM_INVALIDATE_ENG4_REQ__LOG_REQUEST_MASK 0x01000000L 31029 //VM_INVALIDATE_ENG5_REQ 31030 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31031 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE__SHIFT 0x10 31032 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31033 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31034 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31035 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31036 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31037 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31038 #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST__SHIFT 0x18 31039 #define VM_INVALIDATE_ENG5_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31040 #define VM_INVALIDATE_ENG5_REQ__FLUSH_TYPE_MASK 0x00030000L 31041 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31042 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31043 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31044 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31045 #define VM_INVALIDATE_ENG5_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31046 #define VM_INVALIDATE_ENG5_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31047 #define VM_INVALIDATE_ENG5_REQ__LOG_REQUEST_MASK 0x01000000L 31048 //VM_INVALIDATE_ENG6_REQ 31049 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31050 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE__SHIFT 0x10 31051 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31052 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31053 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31054 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31055 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31056 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31057 #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST__SHIFT 0x18 31058 #define VM_INVALIDATE_ENG6_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31059 #define VM_INVALIDATE_ENG6_REQ__FLUSH_TYPE_MASK 0x00030000L 31060 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31061 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31062 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31063 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31064 #define VM_INVALIDATE_ENG6_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31065 #define VM_INVALIDATE_ENG6_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31066 #define VM_INVALIDATE_ENG6_REQ__LOG_REQUEST_MASK 0x01000000L 31067 //VM_INVALIDATE_ENG7_REQ 31068 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31069 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE__SHIFT 0x10 31070 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31071 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31072 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31073 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31074 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31075 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31076 #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST__SHIFT 0x18 31077 #define VM_INVALIDATE_ENG7_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31078 #define VM_INVALIDATE_ENG7_REQ__FLUSH_TYPE_MASK 0x00030000L 31079 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31080 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31081 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31082 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31083 #define VM_INVALIDATE_ENG7_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31084 #define VM_INVALIDATE_ENG7_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31085 #define VM_INVALIDATE_ENG7_REQ__LOG_REQUEST_MASK 0x01000000L 31086 //VM_INVALIDATE_ENG8_REQ 31087 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31088 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE__SHIFT 0x10 31089 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31090 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31091 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31092 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31093 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31094 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31095 #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST__SHIFT 0x18 31096 #define VM_INVALIDATE_ENG8_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31097 #define VM_INVALIDATE_ENG8_REQ__FLUSH_TYPE_MASK 0x00030000L 31098 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31099 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31100 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31101 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31102 #define VM_INVALIDATE_ENG8_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31103 #define VM_INVALIDATE_ENG8_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31104 #define VM_INVALIDATE_ENG8_REQ__LOG_REQUEST_MASK 0x01000000L 31105 //VM_INVALIDATE_ENG9_REQ 31106 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31107 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE__SHIFT 0x10 31108 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31109 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31110 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31111 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31112 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31113 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31114 #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST__SHIFT 0x18 31115 #define VM_INVALIDATE_ENG9_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31116 #define VM_INVALIDATE_ENG9_REQ__FLUSH_TYPE_MASK 0x00030000L 31117 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31118 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31119 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31120 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31121 #define VM_INVALIDATE_ENG9_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31122 #define VM_INVALIDATE_ENG9_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31123 #define VM_INVALIDATE_ENG9_REQ__LOG_REQUEST_MASK 0x01000000L 31124 //VM_INVALIDATE_ENG10_REQ 31125 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31126 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE__SHIFT 0x10 31127 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31128 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31129 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31130 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31131 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31132 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31133 #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST__SHIFT 0x18 31134 #define VM_INVALIDATE_ENG10_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31135 #define VM_INVALIDATE_ENG10_REQ__FLUSH_TYPE_MASK 0x00030000L 31136 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31137 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31138 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31139 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31140 #define VM_INVALIDATE_ENG10_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31141 #define VM_INVALIDATE_ENG10_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31142 #define VM_INVALIDATE_ENG10_REQ__LOG_REQUEST_MASK 0x01000000L 31143 //VM_INVALIDATE_ENG11_REQ 31144 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31145 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE__SHIFT 0x10 31146 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31147 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31148 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31149 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31150 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31151 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31152 #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST__SHIFT 0x18 31153 #define VM_INVALIDATE_ENG11_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31154 #define VM_INVALIDATE_ENG11_REQ__FLUSH_TYPE_MASK 0x00030000L 31155 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31156 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31157 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31158 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31159 #define VM_INVALIDATE_ENG11_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31160 #define VM_INVALIDATE_ENG11_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31161 #define VM_INVALIDATE_ENG11_REQ__LOG_REQUEST_MASK 0x01000000L 31162 //VM_INVALIDATE_ENG12_REQ 31163 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31164 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE__SHIFT 0x10 31165 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31166 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31167 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31168 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31169 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31170 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31171 #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST__SHIFT 0x18 31172 #define VM_INVALIDATE_ENG12_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31173 #define VM_INVALIDATE_ENG12_REQ__FLUSH_TYPE_MASK 0x00030000L 31174 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31175 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31176 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31177 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31178 #define VM_INVALIDATE_ENG12_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31179 #define VM_INVALIDATE_ENG12_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31180 #define VM_INVALIDATE_ENG12_REQ__LOG_REQUEST_MASK 0x01000000L 31181 //VM_INVALIDATE_ENG13_REQ 31182 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31183 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE__SHIFT 0x10 31184 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31185 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31186 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31187 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31188 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31189 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31190 #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST__SHIFT 0x18 31191 #define VM_INVALIDATE_ENG13_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31192 #define VM_INVALIDATE_ENG13_REQ__FLUSH_TYPE_MASK 0x00030000L 31193 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31194 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31195 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31196 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31197 #define VM_INVALIDATE_ENG13_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31198 #define VM_INVALIDATE_ENG13_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31199 #define VM_INVALIDATE_ENG13_REQ__LOG_REQUEST_MASK 0x01000000L 31200 //VM_INVALIDATE_ENG14_REQ 31201 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31202 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE__SHIFT 0x10 31203 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31204 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31205 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31206 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31207 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31208 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31209 #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST__SHIFT 0x18 31210 #define VM_INVALIDATE_ENG14_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31211 #define VM_INVALIDATE_ENG14_REQ__FLUSH_TYPE_MASK 0x00030000L 31212 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31213 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31214 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31215 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31216 #define VM_INVALIDATE_ENG14_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31217 #define VM_INVALIDATE_ENG14_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31218 #define VM_INVALIDATE_ENG14_REQ__LOG_REQUEST_MASK 0x01000000L 31219 //VM_INVALIDATE_ENG15_REQ 31220 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31221 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE__SHIFT 0x10 31222 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31223 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31224 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31225 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31226 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31227 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31228 #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST__SHIFT 0x18 31229 #define VM_INVALIDATE_ENG15_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31230 #define VM_INVALIDATE_ENG15_REQ__FLUSH_TYPE_MASK 0x00030000L 31231 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31232 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31233 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31234 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31235 #define VM_INVALIDATE_ENG15_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31236 #define VM_INVALIDATE_ENG15_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31237 #define VM_INVALIDATE_ENG15_REQ__LOG_REQUEST_MASK 0x01000000L 31238 //VM_INVALIDATE_ENG16_REQ 31239 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31240 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE__SHIFT 0x10 31241 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31242 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31243 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31244 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31245 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31246 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31247 #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST__SHIFT 0x18 31248 #define VM_INVALIDATE_ENG16_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31249 #define VM_INVALIDATE_ENG16_REQ__FLUSH_TYPE_MASK 0x00030000L 31250 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31251 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31252 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31253 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31254 #define VM_INVALIDATE_ENG16_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31255 #define VM_INVALIDATE_ENG16_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31256 #define VM_INVALIDATE_ENG16_REQ__LOG_REQUEST_MASK 0x01000000L 31257 //VM_INVALIDATE_ENG17_REQ 31258 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ__SHIFT 0x0 31259 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE__SHIFT 0x10 31260 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES__SHIFT 0x12 31261 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0__SHIFT 0x13 31262 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1__SHIFT 0x14 31263 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2__SHIFT 0x15 31264 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES__SHIFT 0x16 31265 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR__SHIFT 0x17 31266 #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST__SHIFT 0x18 31267 #define VM_INVALIDATE_ENG17_REQ__PER_VMID_INVALIDATE_REQ_MASK 0x0000FFFFL 31268 #define VM_INVALIDATE_ENG17_REQ__FLUSH_TYPE_MASK 0x00030000L 31269 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PTES_MASK 0x00040000L 31270 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE0_MASK 0x00080000L 31271 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE1_MASK 0x00100000L 31272 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L2_PDE2_MASK 0x00200000L 31273 #define VM_INVALIDATE_ENG17_REQ__INVALIDATE_L1_PTES_MASK 0x00400000L 31274 #define VM_INVALIDATE_ENG17_REQ__CLEAR_PROTECTION_FAULT_STATUS_ADDR_MASK 0x00800000L 31275 #define VM_INVALIDATE_ENG17_REQ__LOG_REQUEST_MASK 0x01000000L 31276 //VM_INVALIDATE_ENG0_ACK 31277 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31278 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE__SHIFT 0x10 31279 #define VM_INVALIDATE_ENG0_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31280 #define VM_INVALIDATE_ENG0_ACK__SEMAPHORE_MASK 0x00010000L 31281 //VM_INVALIDATE_ENG1_ACK 31282 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31283 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE__SHIFT 0x10 31284 #define VM_INVALIDATE_ENG1_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31285 #define VM_INVALIDATE_ENG1_ACK__SEMAPHORE_MASK 0x00010000L 31286 //VM_INVALIDATE_ENG2_ACK 31287 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31288 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE__SHIFT 0x10 31289 #define VM_INVALIDATE_ENG2_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31290 #define VM_INVALIDATE_ENG2_ACK__SEMAPHORE_MASK 0x00010000L 31291 //VM_INVALIDATE_ENG3_ACK 31292 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31293 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE__SHIFT 0x10 31294 #define VM_INVALIDATE_ENG3_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31295 #define VM_INVALIDATE_ENG3_ACK__SEMAPHORE_MASK 0x00010000L 31296 //VM_INVALIDATE_ENG4_ACK 31297 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31298 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE__SHIFT 0x10 31299 #define VM_INVALIDATE_ENG4_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31300 #define VM_INVALIDATE_ENG4_ACK__SEMAPHORE_MASK 0x00010000L 31301 //VM_INVALIDATE_ENG5_ACK 31302 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31303 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE__SHIFT 0x10 31304 #define VM_INVALIDATE_ENG5_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31305 #define VM_INVALIDATE_ENG5_ACK__SEMAPHORE_MASK 0x00010000L 31306 //VM_INVALIDATE_ENG6_ACK 31307 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31308 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE__SHIFT 0x10 31309 #define VM_INVALIDATE_ENG6_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31310 #define VM_INVALIDATE_ENG6_ACK__SEMAPHORE_MASK 0x00010000L 31311 //VM_INVALIDATE_ENG7_ACK 31312 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31313 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE__SHIFT 0x10 31314 #define VM_INVALIDATE_ENG7_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31315 #define VM_INVALIDATE_ENG7_ACK__SEMAPHORE_MASK 0x00010000L 31316 //VM_INVALIDATE_ENG8_ACK 31317 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31318 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE__SHIFT 0x10 31319 #define VM_INVALIDATE_ENG8_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31320 #define VM_INVALIDATE_ENG8_ACK__SEMAPHORE_MASK 0x00010000L 31321 //VM_INVALIDATE_ENG9_ACK 31322 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31323 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE__SHIFT 0x10 31324 #define VM_INVALIDATE_ENG9_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31325 #define VM_INVALIDATE_ENG9_ACK__SEMAPHORE_MASK 0x00010000L 31326 //VM_INVALIDATE_ENG10_ACK 31327 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31328 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE__SHIFT 0x10 31329 #define VM_INVALIDATE_ENG10_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31330 #define VM_INVALIDATE_ENG10_ACK__SEMAPHORE_MASK 0x00010000L 31331 //VM_INVALIDATE_ENG11_ACK 31332 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31333 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE__SHIFT 0x10 31334 #define VM_INVALIDATE_ENG11_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31335 #define VM_INVALIDATE_ENG11_ACK__SEMAPHORE_MASK 0x00010000L 31336 //VM_INVALIDATE_ENG12_ACK 31337 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31338 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE__SHIFT 0x10 31339 #define VM_INVALIDATE_ENG12_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31340 #define VM_INVALIDATE_ENG12_ACK__SEMAPHORE_MASK 0x00010000L 31341 //VM_INVALIDATE_ENG13_ACK 31342 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31343 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE__SHIFT 0x10 31344 #define VM_INVALIDATE_ENG13_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31345 #define VM_INVALIDATE_ENG13_ACK__SEMAPHORE_MASK 0x00010000L 31346 //VM_INVALIDATE_ENG14_ACK 31347 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31348 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE__SHIFT 0x10 31349 #define VM_INVALIDATE_ENG14_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31350 #define VM_INVALIDATE_ENG14_ACK__SEMAPHORE_MASK 0x00010000L 31351 //VM_INVALIDATE_ENG15_ACK 31352 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31353 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE__SHIFT 0x10 31354 #define VM_INVALIDATE_ENG15_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31355 #define VM_INVALIDATE_ENG15_ACK__SEMAPHORE_MASK 0x00010000L 31356 //VM_INVALIDATE_ENG16_ACK 31357 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31358 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE__SHIFT 0x10 31359 #define VM_INVALIDATE_ENG16_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31360 #define VM_INVALIDATE_ENG16_ACK__SEMAPHORE_MASK 0x00010000L 31361 //VM_INVALIDATE_ENG17_ACK 31362 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK__SHIFT 0x0 31363 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE__SHIFT 0x10 31364 #define VM_INVALIDATE_ENG17_ACK__PER_VMID_INVALIDATE_ACK_MASK 0x0000FFFFL 31365 #define VM_INVALIDATE_ENG17_ACK__SEMAPHORE_MASK 0x00010000L 31366 //VM_INVALIDATE_ENG0_ADDR_RANGE_LO32 31367 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31368 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31369 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31370 #define VM_INVALIDATE_ENG0_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31371 //VM_INVALIDATE_ENG0_ADDR_RANGE_HI32 31372 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31373 #define VM_INVALIDATE_ENG0_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31374 //VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 31375 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31376 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31377 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31378 #define VM_INVALIDATE_ENG1_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31379 //VM_INVALIDATE_ENG1_ADDR_RANGE_HI32 31380 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31381 #define VM_INVALIDATE_ENG1_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31382 //VM_INVALIDATE_ENG2_ADDR_RANGE_LO32 31383 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31384 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31385 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31386 #define VM_INVALIDATE_ENG2_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31387 //VM_INVALIDATE_ENG2_ADDR_RANGE_HI32 31388 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31389 #define VM_INVALIDATE_ENG2_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31390 //VM_INVALIDATE_ENG3_ADDR_RANGE_LO32 31391 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31392 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31393 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31394 #define VM_INVALIDATE_ENG3_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31395 //VM_INVALIDATE_ENG3_ADDR_RANGE_HI32 31396 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31397 #define VM_INVALIDATE_ENG3_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31398 //VM_INVALIDATE_ENG4_ADDR_RANGE_LO32 31399 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31400 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31401 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31402 #define VM_INVALIDATE_ENG4_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31403 //VM_INVALIDATE_ENG4_ADDR_RANGE_HI32 31404 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31405 #define VM_INVALIDATE_ENG4_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31406 //VM_INVALIDATE_ENG5_ADDR_RANGE_LO32 31407 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31408 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31409 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31410 #define VM_INVALIDATE_ENG5_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31411 //VM_INVALIDATE_ENG5_ADDR_RANGE_HI32 31412 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31413 #define VM_INVALIDATE_ENG5_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31414 //VM_INVALIDATE_ENG6_ADDR_RANGE_LO32 31415 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31416 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31417 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31418 #define VM_INVALIDATE_ENG6_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31419 //VM_INVALIDATE_ENG6_ADDR_RANGE_HI32 31420 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31421 #define VM_INVALIDATE_ENG6_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31422 //VM_INVALIDATE_ENG7_ADDR_RANGE_LO32 31423 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31424 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31425 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31426 #define VM_INVALIDATE_ENG7_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31427 //VM_INVALIDATE_ENG7_ADDR_RANGE_HI32 31428 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31429 #define VM_INVALIDATE_ENG7_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31430 //VM_INVALIDATE_ENG8_ADDR_RANGE_LO32 31431 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31432 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31433 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31434 #define VM_INVALIDATE_ENG8_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31435 //VM_INVALIDATE_ENG8_ADDR_RANGE_HI32 31436 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31437 #define VM_INVALIDATE_ENG8_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31438 //VM_INVALIDATE_ENG9_ADDR_RANGE_LO32 31439 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31440 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31441 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31442 #define VM_INVALIDATE_ENG9_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31443 //VM_INVALIDATE_ENG9_ADDR_RANGE_HI32 31444 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31445 #define VM_INVALIDATE_ENG9_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31446 //VM_INVALIDATE_ENG10_ADDR_RANGE_LO32 31447 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31448 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31449 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31450 #define VM_INVALIDATE_ENG10_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31451 //VM_INVALIDATE_ENG10_ADDR_RANGE_HI32 31452 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31453 #define VM_INVALIDATE_ENG10_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31454 //VM_INVALIDATE_ENG11_ADDR_RANGE_LO32 31455 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31456 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31457 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31458 #define VM_INVALIDATE_ENG11_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31459 //VM_INVALIDATE_ENG11_ADDR_RANGE_HI32 31460 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31461 #define VM_INVALIDATE_ENG11_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31462 //VM_INVALIDATE_ENG12_ADDR_RANGE_LO32 31463 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31464 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31465 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31466 #define VM_INVALIDATE_ENG12_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31467 //VM_INVALIDATE_ENG12_ADDR_RANGE_HI32 31468 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31469 #define VM_INVALIDATE_ENG12_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31470 //VM_INVALIDATE_ENG13_ADDR_RANGE_LO32 31471 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31472 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31473 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31474 #define VM_INVALIDATE_ENG13_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31475 //VM_INVALIDATE_ENG13_ADDR_RANGE_HI32 31476 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31477 #define VM_INVALIDATE_ENG13_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31478 //VM_INVALIDATE_ENG14_ADDR_RANGE_LO32 31479 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31480 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31481 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31482 #define VM_INVALIDATE_ENG14_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31483 //VM_INVALIDATE_ENG14_ADDR_RANGE_HI32 31484 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31485 #define VM_INVALIDATE_ENG14_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31486 //VM_INVALIDATE_ENG15_ADDR_RANGE_LO32 31487 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31488 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31489 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31490 #define VM_INVALIDATE_ENG15_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31491 //VM_INVALIDATE_ENG15_ADDR_RANGE_HI32 31492 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31493 #define VM_INVALIDATE_ENG15_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31494 //VM_INVALIDATE_ENG16_ADDR_RANGE_LO32 31495 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31496 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31497 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31498 #define VM_INVALIDATE_ENG16_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31499 //VM_INVALIDATE_ENG16_ADDR_RANGE_HI32 31500 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31501 #define VM_INVALIDATE_ENG16_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31502 //VM_INVALIDATE_ENG17_ADDR_RANGE_LO32 31503 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT__SHIFT 0x0 31504 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31__SHIFT 0x1 31505 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__S_BIT_MASK 0x00000001L 31506 #define VM_INVALIDATE_ENG17_ADDR_RANGE_LO32__LOGI_PAGE_ADDR_RANGE_LO31_MASK 0xFFFFFFFEL 31507 //VM_INVALIDATE_ENG17_ADDR_RANGE_HI32 31508 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5__SHIFT 0x0 31509 #define VM_INVALIDATE_ENG17_ADDR_RANGE_HI32__LOGI_PAGE_ADDR_RANGE_HI5_MASK 0x0000001FL 31510 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32 31511 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31512 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31513 //VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32 31514 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31515 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31516 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 31517 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31518 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31519 //VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32 31520 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31521 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31522 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32 31523 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31524 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31525 //VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32 31526 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31527 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31528 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32 31529 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31530 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31531 //VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32 31532 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31533 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31534 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32 31535 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31536 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31537 //VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32 31538 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31539 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31540 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32 31541 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31542 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31543 //VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32 31544 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31545 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31546 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32 31547 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31548 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31549 //VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32 31550 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31551 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31552 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32 31553 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31554 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31555 //VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32 31556 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31557 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31558 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32 31559 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31560 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31561 //VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32 31562 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31563 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31564 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32 31565 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31566 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31567 //VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32 31568 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31569 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31570 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32 31571 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31572 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31573 //VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32 31574 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31575 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31576 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32 31577 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31578 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31579 //VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32 31580 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31581 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31582 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32 31583 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31584 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31585 //VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32 31586 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31587 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31588 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32 31589 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31590 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31591 //VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32 31592 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31593 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31594 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32 31595 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31596 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31597 //VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32 31598 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31599 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31600 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32 31601 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32__SHIFT 0x0 31602 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_LO32__PAGE_DIRECTORY_ENTRY_LO32_MASK 0xFFFFFFFFL 31603 //VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32 31604 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32__SHIFT 0x0 31605 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR_HI32__PAGE_DIRECTORY_ENTRY_HI32_MASK 0xFFFFFFFFL 31606 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32 31607 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31608 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31609 //VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32 31610 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31611 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31612 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32 31613 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31614 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31615 //VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32 31616 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31617 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31618 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32 31619 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31620 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31621 //VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32 31622 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31623 #define VM_CONTEXT2_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31624 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32 31625 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31626 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31627 //VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32 31628 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31629 #define VM_CONTEXT3_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31630 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32 31631 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31632 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31633 //VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32 31634 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31635 #define VM_CONTEXT4_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31636 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32 31637 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31638 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31639 //VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32 31640 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31641 #define VM_CONTEXT5_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31642 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32 31643 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31644 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31645 //VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32 31646 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31647 #define VM_CONTEXT6_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31648 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32 31649 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31650 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31651 //VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32 31652 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31653 #define VM_CONTEXT7_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31654 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32 31655 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31656 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31657 //VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32 31658 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31659 #define VM_CONTEXT8_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31660 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32 31661 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31662 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31663 //VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32 31664 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31665 #define VM_CONTEXT9_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31666 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32 31667 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31668 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31669 //VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32 31670 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31671 #define VM_CONTEXT10_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31672 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32 31673 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31674 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31675 //VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32 31676 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31677 #define VM_CONTEXT11_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31678 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32 31679 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31680 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31681 //VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32 31682 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31683 #define VM_CONTEXT12_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31684 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32 31685 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31686 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31687 //VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32 31688 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31689 #define VM_CONTEXT13_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31690 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32 31691 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31692 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31693 //VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32 31694 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31695 #define VM_CONTEXT14_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31696 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32 31697 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31698 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31699 //VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32 31700 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31701 #define VM_CONTEXT15_PAGE_TABLE_START_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31702 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32 31703 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31704 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31705 //VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32 31706 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31707 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31708 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32 31709 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31710 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31711 //VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32 31712 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31713 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31714 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32 31715 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31716 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31717 //VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32 31718 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31719 #define VM_CONTEXT2_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31720 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32 31721 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31722 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31723 //VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32 31724 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31725 #define VM_CONTEXT3_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31726 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32 31727 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31728 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31729 //VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32 31730 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31731 #define VM_CONTEXT4_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31732 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32 31733 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31734 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31735 //VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32 31736 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31737 #define VM_CONTEXT5_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31738 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32 31739 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31740 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31741 //VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32 31742 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31743 #define VM_CONTEXT6_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31744 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32 31745 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31746 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31747 //VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32 31748 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31749 #define VM_CONTEXT7_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31750 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32 31751 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31752 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31753 //VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32 31754 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31755 #define VM_CONTEXT8_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31756 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32 31757 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31758 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31759 //VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32 31760 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31761 #define VM_CONTEXT9_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31762 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32 31763 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31764 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31765 //VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32 31766 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31767 #define VM_CONTEXT10_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31768 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32 31769 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31770 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31771 //VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32 31772 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31773 #define VM_CONTEXT11_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31774 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32 31775 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31776 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31777 //VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32 31778 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31779 #define VM_CONTEXT12_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31780 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32 31781 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31782 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31783 //VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32 31784 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31785 #define VM_CONTEXT13_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31786 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32 31787 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31788 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31789 //VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32 31790 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31791 #define VM_CONTEXT14_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31792 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32 31793 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32__SHIFT 0x0 31794 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_LO32__LOGICAL_PAGE_NUMBER_LO32_MASK 0xFFFFFFFFL 31795 //VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32 31796 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4__SHIFT 0x0 31797 #define VM_CONTEXT15_PAGE_TABLE_END_ADDR_HI32__LOGICAL_PAGE_NUMBER_HI4_MASK 0x0000000FL 31798 31799 31800 // addressBlock: mmhub_utcl2_vmsharedhvdec 31801 //MC_VM_FB_SIZE_OFFSET_VF0 31802 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE__SHIFT 0x0 31803 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET__SHIFT 0x10 31804 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_SIZE_MASK 0x0000FFFFL 31805 #define MC_VM_FB_SIZE_OFFSET_VF0__VF_FB_OFFSET_MASK 0xFFFF0000L 31806 //MC_VM_FB_SIZE_OFFSET_VF1 31807 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE__SHIFT 0x0 31808 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET__SHIFT 0x10 31809 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_SIZE_MASK 0x0000FFFFL 31810 #define MC_VM_FB_SIZE_OFFSET_VF1__VF_FB_OFFSET_MASK 0xFFFF0000L 31811 //MC_VM_FB_SIZE_OFFSET_VF2 31812 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE__SHIFT 0x0 31813 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET__SHIFT 0x10 31814 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_SIZE_MASK 0x0000FFFFL 31815 #define MC_VM_FB_SIZE_OFFSET_VF2__VF_FB_OFFSET_MASK 0xFFFF0000L 31816 //MC_VM_FB_SIZE_OFFSET_VF3 31817 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE__SHIFT 0x0 31818 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET__SHIFT 0x10 31819 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_SIZE_MASK 0x0000FFFFL 31820 #define MC_VM_FB_SIZE_OFFSET_VF3__VF_FB_OFFSET_MASK 0xFFFF0000L 31821 //MC_VM_FB_SIZE_OFFSET_VF4 31822 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE__SHIFT 0x0 31823 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET__SHIFT 0x10 31824 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_SIZE_MASK 0x0000FFFFL 31825 #define MC_VM_FB_SIZE_OFFSET_VF4__VF_FB_OFFSET_MASK 0xFFFF0000L 31826 //MC_VM_FB_SIZE_OFFSET_VF5 31827 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE__SHIFT 0x0 31828 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET__SHIFT 0x10 31829 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_SIZE_MASK 0x0000FFFFL 31830 #define MC_VM_FB_SIZE_OFFSET_VF5__VF_FB_OFFSET_MASK 0xFFFF0000L 31831 //MC_VM_FB_SIZE_OFFSET_VF6 31832 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE__SHIFT 0x0 31833 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET__SHIFT 0x10 31834 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_SIZE_MASK 0x0000FFFFL 31835 #define MC_VM_FB_SIZE_OFFSET_VF6__VF_FB_OFFSET_MASK 0xFFFF0000L 31836 //MC_VM_FB_SIZE_OFFSET_VF7 31837 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE__SHIFT 0x0 31838 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET__SHIFT 0x10 31839 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_SIZE_MASK 0x0000FFFFL 31840 #define MC_VM_FB_SIZE_OFFSET_VF7__VF_FB_OFFSET_MASK 0xFFFF0000L 31841 //MC_VM_FB_SIZE_OFFSET_VF8 31842 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE__SHIFT 0x0 31843 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET__SHIFT 0x10 31844 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_SIZE_MASK 0x0000FFFFL 31845 #define MC_VM_FB_SIZE_OFFSET_VF8__VF_FB_OFFSET_MASK 0xFFFF0000L 31846 //MC_VM_FB_SIZE_OFFSET_VF9 31847 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE__SHIFT 0x0 31848 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET__SHIFT 0x10 31849 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_SIZE_MASK 0x0000FFFFL 31850 #define MC_VM_FB_SIZE_OFFSET_VF9__VF_FB_OFFSET_MASK 0xFFFF0000L 31851 //MC_VM_FB_SIZE_OFFSET_VF10 31852 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE__SHIFT 0x0 31853 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET__SHIFT 0x10 31854 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_SIZE_MASK 0x0000FFFFL 31855 #define MC_VM_FB_SIZE_OFFSET_VF10__VF_FB_OFFSET_MASK 0xFFFF0000L 31856 //MC_VM_FB_SIZE_OFFSET_VF11 31857 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE__SHIFT 0x0 31858 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET__SHIFT 0x10 31859 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_SIZE_MASK 0x0000FFFFL 31860 #define MC_VM_FB_SIZE_OFFSET_VF11__VF_FB_OFFSET_MASK 0xFFFF0000L 31861 //MC_VM_FB_SIZE_OFFSET_VF12 31862 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE__SHIFT 0x0 31863 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET__SHIFT 0x10 31864 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_SIZE_MASK 0x0000FFFFL 31865 #define MC_VM_FB_SIZE_OFFSET_VF12__VF_FB_OFFSET_MASK 0xFFFF0000L 31866 //MC_VM_FB_SIZE_OFFSET_VF13 31867 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE__SHIFT 0x0 31868 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET__SHIFT 0x10 31869 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_SIZE_MASK 0x0000FFFFL 31870 #define MC_VM_FB_SIZE_OFFSET_VF13__VF_FB_OFFSET_MASK 0xFFFF0000L 31871 //MC_VM_FB_SIZE_OFFSET_VF14 31872 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE__SHIFT 0x0 31873 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET__SHIFT 0x10 31874 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_SIZE_MASK 0x0000FFFFL 31875 #define MC_VM_FB_SIZE_OFFSET_VF14__VF_FB_OFFSET_MASK 0xFFFF0000L 31876 //MC_VM_FB_SIZE_OFFSET_VF15 31877 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE__SHIFT 0x0 31878 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET__SHIFT 0x10 31879 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_SIZE_MASK 0x0000FFFFL 31880 #define MC_VM_FB_SIZE_OFFSET_VF15__VF_FB_OFFSET_MASK 0xFFFF0000L 31881 //MC_VM_MARC_BASE_LO_0 31882 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0__SHIFT 0xc 31883 #define MC_VM_MARC_BASE_LO_0__MARC_BASE_LO_0_MASK 0xFFFFF000L 31884 //MC_VM_MARC_BASE_LO_1 31885 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1__SHIFT 0xc 31886 #define MC_VM_MARC_BASE_LO_1__MARC_BASE_LO_1_MASK 0xFFFFF000L 31887 //MC_VM_MARC_BASE_LO_2 31888 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2__SHIFT 0xc 31889 #define MC_VM_MARC_BASE_LO_2__MARC_BASE_LO_2_MASK 0xFFFFF000L 31890 //MC_VM_MARC_BASE_LO_3 31891 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3__SHIFT 0xc 31892 #define MC_VM_MARC_BASE_LO_3__MARC_BASE_LO_3_MASK 0xFFFFF000L 31893 //MC_VM_MARC_BASE_HI_0 31894 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0__SHIFT 0x0 31895 #define MC_VM_MARC_BASE_HI_0__MARC_BASE_HI_0_MASK 0x000FFFFFL 31896 //MC_VM_MARC_BASE_HI_1 31897 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1__SHIFT 0x0 31898 #define MC_VM_MARC_BASE_HI_1__MARC_BASE_HI_1_MASK 0x000FFFFFL 31899 //MC_VM_MARC_BASE_HI_2 31900 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2__SHIFT 0x0 31901 #define MC_VM_MARC_BASE_HI_2__MARC_BASE_HI_2_MASK 0x000FFFFFL 31902 //MC_VM_MARC_BASE_HI_3 31903 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3__SHIFT 0x0 31904 #define MC_VM_MARC_BASE_HI_3__MARC_BASE_HI_3_MASK 0x000FFFFFL 31905 //MC_VM_MARC_RELOC_LO_0 31906 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0__SHIFT 0x0 31907 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0__SHIFT 0x1 31908 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0__SHIFT 0xc 31909 #define MC_VM_MARC_RELOC_LO_0__MARC_ENABLE_0_MASK 0x00000001L 31910 #define MC_VM_MARC_RELOC_LO_0__MARC_READONLY_0_MASK 0x00000002L 31911 #define MC_VM_MARC_RELOC_LO_0__MARC_RELOC_LO_0_MASK 0xFFFFF000L 31912 //MC_VM_MARC_RELOC_LO_1 31913 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1__SHIFT 0x0 31914 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1__SHIFT 0x1 31915 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1__SHIFT 0xc 31916 #define MC_VM_MARC_RELOC_LO_1__MARC_ENABLE_1_MASK 0x00000001L 31917 #define MC_VM_MARC_RELOC_LO_1__MARC_READONLY_1_MASK 0x00000002L 31918 #define MC_VM_MARC_RELOC_LO_1__MARC_RELOC_LO_1_MASK 0xFFFFF000L 31919 //MC_VM_MARC_RELOC_LO_2 31920 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2__SHIFT 0x0 31921 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2__SHIFT 0x1 31922 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2__SHIFT 0xc 31923 #define MC_VM_MARC_RELOC_LO_2__MARC_ENABLE_2_MASK 0x00000001L 31924 #define MC_VM_MARC_RELOC_LO_2__MARC_READONLY_2_MASK 0x00000002L 31925 #define MC_VM_MARC_RELOC_LO_2__MARC_RELOC_LO_2_MASK 0xFFFFF000L 31926 //MC_VM_MARC_RELOC_LO_3 31927 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3__SHIFT 0x0 31928 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3__SHIFT 0x1 31929 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3__SHIFT 0xc 31930 #define MC_VM_MARC_RELOC_LO_3__MARC_ENABLE_3_MASK 0x00000001L 31931 #define MC_VM_MARC_RELOC_LO_3__MARC_READONLY_3_MASK 0x00000002L 31932 #define MC_VM_MARC_RELOC_LO_3__MARC_RELOC_LO_3_MASK 0xFFFFF000L 31933 //MC_VM_MARC_RELOC_HI_0 31934 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0__SHIFT 0x0 31935 #define MC_VM_MARC_RELOC_HI_0__MARC_RELOC_HI_0_MASK 0x000FFFFFL 31936 //MC_VM_MARC_RELOC_HI_1 31937 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1__SHIFT 0x0 31938 #define MC_VM_MARC_RELOC_HI_1__MARC_RELOC_HI_1_MASK 0x000FFFFFL 31939 //MC_VM_MARC_RELOC_HI_2 31940 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2__SHIFT 0x0 31941 #define MC_VM_MARC_RELOC_HI_2__MARC_RELOC_HI_2_MASK 0x000FFFFFL 31942 //MC_VM_MARC_RELOC_HI_3 31943 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3__SHIFT 0x0 31944 #define MC_VM_MARC_RELOC_HI_3__MARC_RELOC_HI_3_MASK 0x000FFFFFL 31945 //MC_VM_MARC_LEN_LO_0 31946 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0__SHIFT 0xc 31947 #define MC_VM_MARC_LEN_LO_0__MARC_LEN_LO_0_MASK 0xFFFFF000L 31948 //MC_VM_MARC_LEN_LO_1 31949 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1__SHIFT 0xc 31950 #define MC_VM_MARC_LEN_LO_1__MARC_LEN_LO_1_MASK 0xFFFFF000L 31951 //MC_VM_MARC_LEN_LO_2 31952 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2__SHIFT 0xc 31953 #define MC_VM_MARC_LEN_LO_2__MARC_LEN_LO_2_MASK 0xFFFFF000L 31954 //MC_VM_MARC_LEN_LO_3 31955 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3__SHIFT 0xc 31956 #define MC_VM_MARC_LEN_LO_3__MARC_LEN_LO_3_MASK 0xFFFFF000L 31957 //MC_VM_MARC_LEN_HI_0 31958 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0__SHIFT 0x0 31959 #define MC_VM_MARC_LEN_HI_0__MARC_LEN_HI_0_MASK 0x000FFFFFL 31960 //MC_VM_MARC_LEN_HI_1 31961 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1__SHIFT 0x0 31962 #define MC_VM_MARC_LEN_HI_1__MARC_LEN_HI_1_MASK 0x000FFFFFL 31963 //MC_VM_MARC_LEN_HI_2 31964 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2__SHIFT 0x0 31965 #define MC_VM_MARC_LEN_HI_2__MARC_LEN_HI_2_MASK 0x000FFFFFL 31966 //MC_VM_MARC_LEN_HI_3 31967 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3__SHIFT 0x0 31968 #define MC_VM_MARC_LEN_HI_3__MARC_LEN_HI_3_MASK 0x000FFFFFL 31969 //VM_PCIE_ATS_CNTL 31970 #define VM_PCIE_ATS_CNTL__STU__SHIFT 0x10 31971 #define VM_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT 0x1f 31972 #define VM_PCIE_ATS_CNTL__STU_MASK 0x001F0000L 31973 #define VM_PCIE_ATS_CNTL__ATC_ENABLE_MASK 0x80000000L 31974 //VM_PCIE_ATS_CNTL_VF_0 31975 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE__SHIFT 0x1f 31976 #define VM_PCIE_ATS_CNTL_VF_0__ATC_ENABLE_MASK 0x80000000L 31977 //VM_PCIE_ATS_CNTL_VF_1 31978 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE__SHIFT 0x1f 31979 #define VM_PCIE_ATS_CNTL_VF_1__ATC_ENABLE_MASK 0x80000000L 31980 //VM_PCIE_ATS_CNTL_VF_2 31981 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE__SHIFT 0x1f 31982 #define VM_PCIE_ATS_CNTL_VF_2__ATC_ENABLE_MASK 0x80000000L 31983 //VM_PCIE_ATS_CNTL_VF_3 31984 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE__SHIFT 0x1f 31985 #define VM_PCIE_ATS_CNTL_VF_3__ATC_ENABLE_MASK 0x80000000L 31986 //VM_PCIE_ATS_CNTL_VF_4 31987 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE__SHIFT 0x1f 31988 #define VM_PCIE_ATS_CNTL_VF_4__ATC_ENABLE_MASK 0x80000000L 31989 //VM_PCIE_ATS_CNTL_VF_5 31990 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE__SHIFT 0x1f 31991 #define VM_PCIE_ATS_CNTL_VF_5__ATC_ENABLE_MASK 0x80000000L 31992 //VM_PCIE_ATS_CNTL_VF_6 31993 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE__SHIFT 0x1f 31994 #define VM_PCIE_ATS_CNTL_VF_6__ATC_ENABLE_MASK 0x80000000L 31995 //VM_PCIE_ATS_CNTL_VF_7 31996 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE__SHIFT 0x1f 31997 #define VM_PCIE_ATS_CNTL_VF_7__ATC_ENABLE_MASK 0x80000000L 31998 //VM_PCIE_ATS_CNTL_VF_8 31999 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE__SHIFT 0x1f 32000 #define VM_PCIE_ATS_CNTL_VF_8__ATC_ENABLE_MASK 0x80000000L 32001 //VM_PCIE_ATS_CNTL_VF_9 32002 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE__SHIFT 0x1f 32003 #define VM_PCIE_ATS_CNTL_VF_9__ATC_ENABLE_MASK 0x80000000L 32004 //VM_PCIE_ATS_CNTL_VF_10 32005 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE__SHIFT 0x1f 32006 #define VM_PCIE_ATS_CNTL_VF_10__ATC_ENABLE_MASK 0x80000000L 32007 //VM_PCIE_ATS_CNTL_VF_11 32008 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE__SHIFT 0x1f 32009 #define VM_PCIE_ATS_CNTL_VF_11__ATC_ENABLE_MASK 0x80000000L 32010 //VM_PCIE_ATS_CNTL_VF_12 32011 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE__SHIFT 0x1f 32012 #define VM_PCIE_ATS_CNTL_VF_12__ATC_ENABLE_MASK 0x80000000L 32013 //VM_PCIE_ATS_CNTL_VF_13 32014 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE__SHIFT 0x1f 32015 #define VM_PCIE_ATS_CNTL_VF_13__ATC_ENABLE_MASK 0x80000000L 32016 //VM_PCIE_ATS_CNTL_VF_14 32017 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE__SHIFT 0x1f 32018 #define VM_PCIE_ATS_CNTL_VF_14__ATC_ENABLE_MASK 0x80000000L 32019 //VM_PCIE_ATS_CNTL_VF_15 32020 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE__SHIFT 0x1f 32021 #define VM_PCIE_ATS_CNTL_VF_15__ATC_ENABLE_MASK 0x80000000L 32022 //MC_SHARED_ACTIVE_FCN_ID 32023 #define MC_SHARED_ACTIVE_FCN_ID__VFID__SHIFT 0x0 32024 #define MC_SHARED_ACTIVE_FCN_ID__VF__SHIFT 0x1f 32025 #define MC_SHARED_ACTIVE_FCN_ID__VFID_MASK 0x0000000FL 32026 #define MC_SHARED_ACTIVE_FCN_ID__VF_MASK 0x80000000L 32027 //MC_VM_XGMI_GPUIOV_ENABLE 32028 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0__SHIFT 0x0 32029 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1__SHIFT 0x1 32030 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2__SHIFT 0x2 32031 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3__SHIFT 0x3 32032 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4__SHIFT 0x4 32033 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5__SHIFT 0x5 32034 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6__SHIFT 0x6 32035 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7__SHIFT 0x7 32036 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8__SHIFT 0x8 32037 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9__SHIFT 0x9 32038 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10__SHIFT 0xa 32039 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11__SHIFT 0xb 32040 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12__SHIFT 0xc 32041 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13__SHIFT 0xd 32042 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14__SHIFT 0xe 32043 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15__SHIFT 0xf 32044 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF__SHIFT 0x1f 32045 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF0_MASK 0x00000001L 32046 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF1_MASK 0x00000002L 32047 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF2_MASK 0x00000004L 32048 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF3_MASK 0x00000008L 32049 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF4_MASK 0x00000010L 32050 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF5_MASK 0x00000020L 32051 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF6_MASK 0x00000040L 32052 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF7_MASK 0x00000080L 32053 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF8_MASK 0x00000100L 32054 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF9_MASK 0x00000200L 32055 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF10_MASK 0x00000400L 32056 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF11_MASK 0x00000800L 32057 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF12_MASK 0x00001000L 32058 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF13_MASK 0x00002000L 32059 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF14_MASK 0x00004000L 32060 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_VF15_MASK 0x00008000L 32061 #define MC_VM_XGMI_GPUIOV_ENABLE__ENABLE_PF_MASK 0x80000000L 32062 32063 32064 // addressBlock: mmhub_utcl2_vmsharedpfdec 32065 //MC_VM_FB_OFFSET 32066 #define MC_VM_FB_OFFSET__FB_OFFSET__SHIFT 0x0 32067 #define MC_VM_FB_OFFSET__FB_OFFSET_MASK 0x00FFFFFFL 32068 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB 32069 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB__SHIFT 0x0 32070 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB__PHYSICAL_PAGE_NUMBER_LSB_MASK 0xFFFFFFFFL 32071 //MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB 32072 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB__SHIFT 0x0 32073 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB__PHYSICAL_PAGE_NUMBER_MSB_MASK 0x0000000FL 32074 //MC_VM_STEERING 32075 #define MC_VM_STEERING__DEFAULT_STEERING__SHIFT 0x0 32076 #define MC_VM_STEERING__DEFAULT_STEERING_MASK 0x00000003L 32077 //MC_SHARED_VIRT_RESET_REQ 32078 #define MC_SHARED_VIRT_RESET_REQ__VF__SHIFT 0x0 32079 #define MC_SHARED_VIRT_RESET_REQ__PF__SHIFT 0x1f 32080 #define MC_SHARED_VIRT_RESET_REQ__VF_MASK 0x0000FFFFL 32081 #define MC_SHARED_VIRT_RESET_REQ__PF_MASK 0x80000000L 32082 //MC_MEM_POWER_LS 32083 #define MC_MEM_POWER_LS__LS_SETUP__SHIFT 0x0 32084 #define MC_MEM_POWER_LS__LS_HOLD__SHIFT 0x6 32085 #define MC_MEM_POWER_LS__LS_SETUP_MASK 0x0000003FL 32086 #define MC_MEM_POWER_LS__LS_HOLD_MASK 0x00000FC0L 32087 //MC_VM_CACHEABLE_DRAM_ADDRESS_START 32088 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS__SHIFT 0x0 32089 #define MC_VM_CACHEABLE_DRAM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL 32090 //MC_VM_CACHEABLE_DRAM_ADDRESS_END 32091 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS__SHIFT 0x0 32092 #define MC_VM_CACHEABLE_DRAM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL 32093 //MC_VM_APT_CNTL 32094 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC__SHIFT 0x0 32095 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN__SHIFT 0x1 32096 #define MC_VM_APT_CNTL__CHECK_IS_LOCAL__SHIFT 0x2 32097 #define MC_VM_APT_CNTL__PERMS_GRANTED__SHIFT 0x3 32098 #define MC_VM_APT_CNTL__FORCE_MTYPE_UC_MASK 0x00000001L 32099 #define MC_VM_APT_CNTL__DIRECT_SYSTEM_EN_MASK 0x00000002L 32100 #define MC_VM_APT_CNTL__CHECK_IS_LOCAL_MASK 0x00000004L 32101 #define MC_VM_APT_CNTL__PERMS_GRANTED_MASK 0x00000008L 32102 //MC_VM_LOCAL_HBM_ADDRESS_START 32103 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS__SHIFT 0x0 32104 #define MC_VM_LOCAL_HBM_ADDRESS_START__ADDRESS_MASK 0x00FFFFFFL 32105 //MC_VM_LOCAL_HBM_ADDRESS_END 32106 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS__SHIFT 0x0 32107 #define MC_VM_LOCAL_HBM_ADDRESS_END__ADDRESS_MASK 0x00FFFFFFL 32108 //MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL 32109 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK__SHIFT 0x0 32110 #define MC_VM_LOCAL_HBM_ADDRESS_LOCK_CNTL__LOCK_MASK 0x00000001L 32111 //UTCL2_CGTT_CLK_CTRL 32112 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY__SHIFT 0x0 32113 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS__SHIFT 0x4 32114 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA__SHIFT 0xc 32115 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE__SHIFT 0xf 32116 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE__SHIFT 0x10 32117 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE__SHIFT 0x18 32118 #define UTCL2_CGTT_CLK_CTRL__ON_DELAY_MASK 0x0000000FL 32119 #define UTCL2_CGTT_CLK_CTRL__OFF_HYSTERESIS_MASK 0x00000FF0L 32120 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_EXTRA_MASK 0x00007000L 32121 #define UTCL2_CGTT_CLK_CTRL__MGLS_OVERRIDE_MASK 0x00008000L 32122 #define UTCL2_CGTT_CLK_CTRL__SOFT_STALL_OVERRIDE_MASK 0x00FF0000L 32123 #define UTCL2_CGTT_CLK_CTRL__SOFT_OVERRIDE_MASK 0xFF000000L 32124 //MC_VM_XGMI_LFB_CNTL 32125 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION__SHIFT 0x0 32126 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION__SHIFT 0x4 32127 #define MC_VM_XGMI_LFB_CNTL__PF_LFB_REGION_MASK 0x0000000FL 32128 #define MC_VM_XGMI_LFB_CNTL__PF_MAX_REGION_MASK 0x000000F0L 32129 //MC_VM_XGMI_LFB_SIZE 32130 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE__SHIFT 0x0 32131 #define MC_VM_XGMI_LFB_SIZE__PF_LFB_SIZE_MASK 0x0001FFFFL 32132 //MC_VM_CACHEABLE_DRAM_CNTL 32133 #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE__SHIFT 0x0 32134 #define MC_VM_CACHEABLE_DRAM_CNTL__ENABLE_CACHEABLE_DRAM_ADDRESS_APERTURE_MASK 0x00000001L 32135 //MC_VM_HOST_MAPPING 32136 #define MC_VM_HOST_MAPPING__MODE__SHIFT 0x0 32137 #define MC_VM_HOST_MAPPING__MODE_MASK 0x00000001L 32138 32139 32140 // addressBlock: mmhub_utcl2_vmsharedvcdec 32141 //MC_VM_FB_LOCATION_BASE 32142 #define MC_VM_FB_LOCATION_BASE__FB_BASE__SHIFT 0x0 32143 #define MC_VM_FB_LOCATION_BASE__FB_BASE_MASK 0x00FFFFFFL 32144 //MC_VM_FB_LOCATION_TOP 32145 #define MC_VM_FB_LOCATION_TOP__FB_TOP__SHIFT 0x0 32146 #define MC_VM_FB_LOCATION_TOP__FB_TOP_MASK 0x00FFFFFFL 32147 //MC_VM_AGP_TOP 32148 #define MC_VM_AGP_TOP__AGP_TOP__SHIFT 0x0 32149 #define MC_VM_AGP_TOP__AGP_TOP_MASK 0x00FFFFFFL 32150 //MC_VM_AGP_BOT 32151 #define MC_VM_AGP_BOT__AGP_BOT__SHIFT 0x0 32152 #define MC_VM_AGP_BOT__AGP_BOT_MASK 0x00FFFFFFL 32153 //MC_VM_AGP_BASE 32154 #define MC_VM_AGP_BASE__AGP_BASE__SHIFT 0x0 32155 #define MC_VM_AGP_BASE__AGP_BASE_MASK 0x00FFFFFFL 32156 //MC_VM_SYSTEM_APERTURE_LOW_ADDR 32157 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR__SHIFT 0x0 32158 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 32159 //MC_VM_SYSTEM_APERTURE_HIGH_ADDR 32160 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR__SHIFT 0x0 32161 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR__LOGICAL_ADDR_MASK 0x3FFFFFFFL 32162 //MC_VM_MX_L1_TLB_CNTL 32163 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB__SHIFT 0x0 32164 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE__SHIFT 0x3 32165 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS__SHIFT 0x5 32166 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL__SHIFT 0x6 32167 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS__SHIFT 0x7 32168 #define MC_VM_MX_L1_TLB_CNTL__MTYPE__SHIFT 0xb 32169 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN__SHIFT 0xd 32170 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_L1_TLB_MASK 0x00000001L 32171 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_ACCESS_MODE_MASK 0x00000018L 32172 #define MC_VM_MX_L1_TLB_CNTL__SYSTEM_APERTURE_UNMAPPED_ACCESS_MASK 0x00000020L 32173 #define MC_VM_MX_L1_TLB_CNTL__ENABLE_ADVANCED_DRIVER_MODEL_MASK 0x00000040L 32174 #define MC_VM_MX_L1_TLB_CNTL__ECO_BITS_MASK 0x00000780L 32175 #define MC_VM_MX_L1_TLB_CNTL__MTYPE_MASK 0x00001800L 32176 #define MC_VM_MX_L1_TLB_CNTL__ATC_EN_MASK 0x00002000L 32177 32178 #endif 32179